Note: Descriptions are shown in the official language in which they were submitted.
CA 02346136 2001-05-09
ENHANCED PHASE-LOCKED LOOP (PLL)
SYSTEM
The present invention relates to phase-locked loop (PLL) systems and circuits,
and in par-
ticular, to an enhanced phase-locked loop structure which exhibits global
stability within
an indefinitely wide dynamic range of operational amplitude, phase and
frequency, the
values of which are directly estimated by the system. The improvement to the
structure
of the conventional PLL systems is achieved by means of introducing a phase
detection
(PD) scheme into the loop which, while ensuring the stability of the loop for
any point of
operation, simplifies the structure of the loop filter (LF) to the extent that
a first order
filter is sufficient for most of the applications in which PLLs are currently
used. The range
of applications of the present invention encompasses those in which
conventional PLLs
are employed such as filtering of electrical signals, demodulation in
continuous-wave mod-
ulation systems, clock recovery in digital transmission systems as well as
those in which
detection and extraction of amplitude, phase and frequency of signals are
desired such as
phasor measurement in power systems.
BACKGROUND OF THE INVENTION
Phase-locked loop is a fundamental concept widely used in diverse areas of
electrical engi-
neering such as communications, instrumentation, systems control, radar, and
telemetry.
The main idea of phase lock is the ability to generate a sinusoidal signal
whose phase
coherently follows that of the main component of the input signal. PLLs have
been the
subject of research for several decades. Enormous amount of theoretical and
practical in-
formation is now available on this rather mature subject. Explosive
developments in the
area of electronic circuitry have had tremendous impact on the PLL technology.
Inven-
tions in PLL technology combined with advancement in integrated circuit (IC)
technology
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CA 02346136 2001-05-09
have rendered PLL circuits important system components. Examples of inventions
in this
area abound. To name a few, one is referred to the following United States of
America
patents:
6208182Mar. 27, 2001 Marbot,
et al.,
6104222Aug. 15, 2000 Embrec,
6049254Apr. 11, 2000 Knapp, et
al.,
6031428Feb. 29, 2000 Hill,
59784261~'ov. 02, Glover,
1999 et al.,
5909474Jun. O1, 1999 Yoshizawa.
Despite the abundance of theoretical information on PLL and its fascinating
technological
progress, the fundamental structure of PLL has remained almost unchanged since
its
introduction in 1930s. The phase difference between the input and output
signals is
measured using a phase detector and, having been passed through a loop filter,
is used as
the error signal driving a voltage controlled oscillator (VCO) which generates
the output
signal. PD constitutes the main part of the PLL structure so much so that very
often
PLL is thought of as solely consisting of the PD, the existence of which
presumes a closed
loop. PD may be implemented in digital or analog form, a crucial structural
feature which
is the turning point of ramification into digital and analog PLL technology.
The most intuitive structure for PD is a multiplier sometimes referred to as
mixer or
sinusoidal PD. The output of the loop filter which follows the PD, i.e. the
error signal,
is supposed to be a measure of the total phase difference of the two input
signals of
PD. Ideally, such an error signal is proportional to, or at least a monotonic
function of,
the total phase difference of the two input signals of PD. The fundamental
problem of
conventional PLL -of which all the complex theory and practical shortcomings
involving
PLL are consequences- is that such an ideal has never been realized. Such a
simple
structure of PLL consisting mainly of a means of generating an error signal
proportional
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CA 02346136 2001-05-09
to the total phase difference, which has remained the most obvious choice -and
as if the
only choice- ever since the phase lock concept was introduced, provides the
most intuitive
PLL structure; a simple and intuitive starting point which, by the very reason
of its non-
existence, was never accomplished. Such a concept of phase lock promised to
result the
simplest PLL, a promise which was never fulfilled and therefore hindered
development of
any alternative method by its fascinating enticement.
Conventional PLLs, although possess an intuitive structure comprising
conceptually easy
to understand components, are well-known for having loop stability problems
for input
signals whose parameters such as amplitude, phase and frequency may undergo
large
variations. There has been reported no PLL structure which is proved, both
theoretically
and practically, to be capable of locking into the desired component of the
input signal
whose parameters, especially frequency, may vary in an indefinitely wide range
of values.
SUMMARY OF THE INVENTION
The present invention offers a new structure for PLL based on an alternative
method
of phase detection. Unlike conventional PLL theory which despite its
hypertrophy of
mathematical proofs does not guarantee the desired performance of PLL in
general, the
desired performance of the present invention is theoretically proved in
general. The loop
filter in the introduced PLL has a very simple structure which nonetheless
provides an easy
yet powerful method of control and determination of the behavior of the loop.
Everything
is determined by the adjustment of few parameters so that the need for
sophisticated loop
filters is obviated.
It is an object of the present invention to provide a phase-locked loop system
which would
obviate aforementioned shortcomings of conventional PLLs, namely those
associated with
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CA 02346136 2001-05-09
loop stability problems and narrow range of permitted variations of parameters
of the
input signal. This is done through introduction of a new structure for PLL in
which the
phase detection mechanism is substantially improved and the structure of the
loop filter
is significantly simplified.
According to one aspect of the invention, the intuitive phase detection unit
is replaced
by a rather non-intuitive phase detection mechanism, the structure of which
comprises
simple arithmetic units easily realizable in the form of analog and digital
circuitry, or
alternatively, if the implementation is done in software form, in the form of
computational
procedures.
Advantageously, the need for complex loop filters, conventionally employed to
control
and improve operation of the loop, is obviated to the extent that a simple
gain unit,
or equivalently a P-controller, or alternatively a first order filter, or
equivalently a PI-
controller, may be employed to provide almost any desired performance. This
feature
drastically reduces structural complexity and simplifies the design procedure.
Accordingly, the first embodiment of the invention employs a simple gain unit,
a P-
controller, as the loop filter and shall hereinafter be referred to as P-type
PLL. The second
embodiment of the invention employs a PI-controller as the loop filter and
shall hereinafter
be referred to as PI-type PLL. All other embodiments of the invention
employing higher
order filters as the loop filter shall be called higher order PLLs.
Advantageously, performance of the loop in terms of speed of convergence and
permitted
error is fully controlled by means of adjustment of few parameters. This
provides the
designer with an easy yet powerful means of determination of the behavior of
the system
for different applications.
CA 02346136 2001-05-09
It is another object of the present invention to extend the functionality of
the conventional
PLL systems from capability of locking to the phase (and a limited range of
frequency) of
the input signal to capability of locking to amplitude, phase and frequency of
the input
signal thereby providing an amplitude-phase-frequency-locked loop system.
It is also another object. of the present invention to furnish the PLL system
with means of
direct estimation of the values of amplitude, phase and frequency of the
desired component
of the input signal instantly and with high speed and precision.
According to an aspect of the present invention, two controlling parameters in
the case
of the first embodiment of the invention, i.e. P-type PLL, provide full
control over the
speed/error trade-off in the estimated values of the amplitude and phase of
the desired
component of the input signal.
According to another aspect of the present invention, three controlling
parameters in the
case of the second embodiment of the invention, i.e. PI-type PLL, provide full
control over
the speed/error trade-off in the estimated values of the amplitude, phase and
frequency
of the desired component of the input signal.
It is yet another object of the present invention to equip the PLL system with
means of
providing a sinusoidal signal synchronized with the desired component of the
input signal
having the same amplitude, phase and frequency as that of such a desired
component of the
input signal which moreover follows the variations in the characteristics of
such a desired
component over time while being insensitive to external disturbances and
environmentally
imposed noise.
CA 02346136 2001-05-09
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings like reference numbers denote like components,
brief de-
scription of each of which is herewith given.
Figure 1 shows a general structural block diagram of the PLL system,
Figure 2 shows the block diagram of the preferred embodiment of the phase
detection
scheme wherein an amplitude adjustment unit described in Figure 3 is employed,
Figure 3 shows the structure of the amplitude adjustment unit used in the
preferred phase
detection unit of Figure 2,
Figure 4 shows one possible structure of the loop filter of Figure 1 employing
which results
the first embodiment of the present invention, namely P-type PLL,
Figure 5 shows another possible structure of the loop filter of Figure 1
employing which
results the second embodiment of the present invention, namely PI-type PLL,
Figure 6 illustrates, by way of example, performance of the first embodiment
of the present
PLL with respect to a pure sinusoidal input,
Figure 7 illustrates, by way of example, performance of the first embodiment
of the present
PLL with respect to a step change in the amplitude of the sinusoidal input
signal,
Figure 8 illustrates, by way of example, performance of the first embodiment
of the present
PLL with respect to a step change in the phase angle of the sinusoidal input
signal,
Figure 9 illustrates, by way of example, performance of the present PLL with
respect to a
step change in the frequency of the sinusoidal input signal. The performance
of the first
and the second embodiments of the invention are shown separately through two
separate
figures,
Figure 10 illustrates, by way of example, performance of the first embodiment
of the
present PLL with respect to noise immunity, and finally
Figure 11 shows, by way of example, typical fitter transfer functions of P-
type and PI-type
PLL systems.
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CA 02346136 2001-05-09
DETAILED DESCRIPTION OF THE INVENTION
With reference to the accompanying drawings and in particular with reference
to Figure
1, the enhanced phase-locked loop (PLL) system of the invention, like most
conventional
PLL systems, comprises a phase detection (PD) scheme 10, a loop filter (LF)
20, and a
voltage-controlled oscillator (VCO) 30.
The input signal usually has a strong component at a certain frequency. The
VCO 30
is commonly set to oscillate at such a frequency, thereby providing a
sinusoidal output
signal, the phase of which is intended to be coherent with that of the main
component of
the input signal.
Phase detection unit is probably the most important and at the same time the
most prob-
lematic component of conventional PLLs. Very often, a multiplication unit is
employed to
act as a phase detector. The output of such a unit is usually composed of two
signals whose
phases are the sum and difference of the phases of the two input signals. In
conventional
PLLs, it is hoped that the summation term would have a frequency much higher
than that
of the difference and would be easily filtered out and that the difference of
phases is so
small that a linear approximation is valid. In short, in conventional PLLs, it
is expected
that. the phase detection unit and subsequent filtering yield a signal
proportional to the
total phase difference of the two input signals. This is a valid expectation
if the loop is
already operating at or near lock frequency which, of course, is not a case to
be taken as
granted. Herein lies the root of all the complexity of conventional PLLs; the
output of a
multiplication unit is expected to be other that what it really is, an
expectation which is
valid only under the ideal condition of loop being already in its lock-in
range.
The main novelty in the structure of the present PLL as depicted in Figure 1.
is in the
introduction of a new phase detection scheme 20 which is shown in more detail
in Figure 2.
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CA 02346136 2001-05-09
The usual multiplication, or the like, process in most conventional PLLs is
replaced by a
subtraction 12 and a multiplication 14. More precisely, rather than
multiplying the input
signal by the output of VCO to generate a signal whose phase is hopefully the
difference
between the phases of these two signals as is normally done in a lot of
conventional
PLLs, a refined variant of the VCO signal, the one coming from amplitude
adjustment
unit 16, is subtracted from the input signal, using subtraction unit 12, to
produce an
intermediary signal. This intermediary signal is then multiplied by the output
of VCO 30
by multiplication unit 14 the same way as the input signal is multiplied by
the output of
VCO in conventional PLLs with the only difference that here the output is not
expected
to be something other than what it is. Such is the case with all other
arithmetics involved
with the present structure: all units have defined duties realizable under all
conditions.
The refinement of the output of VCO 30 involved in phase detection scheme 10
of Figure
2 is performed by the amplitude adjustment unit 16. Figure 3 shows the
amplitude
adjustment unit 16 in detail. It is observed that both the intermediary
signal, which is
the output signal of the subtraction unit 12, and the output signal of VCO 30
are used
for amplitude adjustment. The signal generated by VCO 30 is first shifted by
90° by
a phase shifter 162. Such a phase-shifted signal is then multiplied by the
intermediary
signal in the multiplication unit 164, the output of which is amplified and
integrated by
a gain/integration unit 166. The output of gain/integration unit 166, when
multiplied by
the output of the phase-shifter 162 in the multiplication unit 168, generates
the refined
variant of the output signal of VCO used in the phase detection unit 10.
The function of the amplitude adjustment unit 16 is basically adjustment of
the level of
the output of VCO 30 so that it follows the amplitude of the main component of
the
input signal. Its function may be termed amplitude-locking in a parallelism
with the
function of the rest of the present structure which should then be termed
phase-locking.
The speed of amplitude tracking is mostly controlled by the value of the
coefficient K in
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CA 02346136 2001-05-09
the gain/integration unit 166: large values of K force the loop to track the
variations in
the amplitude more rapidly. There is, however, a trade-off between speed and
the error
incurred in the estimated value of the amplitude. To improve such a trade-off,
one can
insert a low pass filter at the input or output of the gain/integration unit
166, or in general
within this unit, to smooth out the estimated value of the amplitude while not
introducing
significant delay into the loop. It may be clear by now that the intermediary
signal thus
generated is in fact the error between the input and the final amplitude-
adjusted output.
Phase detection mechanism in the present structure is smart enough to leave
the loop
filter 20 as simple as a constant gain or at most a first order filter for
most practical
applications. It is most convenient to think of the loop filter 20 as a simple
P- or PI-
controller as depicted in Figures 4 and 5.
In the loop filter structure of Figure 4; a simple gain (amplification) unit
22 provides the
filtering process. Accordingly, the PLL structure of Figure 1 employing the
loop filter 20
of Figure 4, i.e. a P-controller, constitutes the first embodiment of the
present invention
referred to as P-type PLL throughout this disclosure.
In the loop filter structure of Figure 5, a PI-controller provides the
filtering process. The
input signal in passed through a gain unit 28 with the gain of Kp and is added
to the
output of the gain/integration unit 24, having a gain of KI, by means of a
summation unit
26 to generate the output signal. Accordingly, the PLL structure of Figure 1
employing
the loop filter 20 of Figure 5, i.e. a PI-controller, constitutes the second
embodiment of
the present invention referred to as PI-type PLL throughout this disclosure.
Of course, one can use more sophisticated filters if one wills or if any
application demands
it, but it has been observed that a simple P- or PI-controller provides
sufficiently satisfac-
tory results for the majority of the problems encountered. Any such
embodiments of the
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CA 02346136 2001-05-09
PLL structure of Figure 1 that employ higher order loop filters are referred
to as higher
order PLL throughout this disclosure.
The value of Kp in the case of P-type PLL and the values of Kp and KI in the
case
of PI-type PLL primarily determine the performance of the present PLL in
tracking the
phase (and frequency in case of PI-type PLL) of the main component of the
input signal.
As with conventional PLLs, a frequency divider unit may be incorporated within
the loop
in order to move the frequency of operation of the VCO up to a harmonic of the
main
component of the input reference signal. Such a frequency divider unit,
inserted within
the feedback loop at the output of VCO 30, will then convert the output
frequency of a
VCO operating at a higher frequency than that of the main component of the
reference
signal back to the operating frequency of the loop.
The embodiments of the present invention easily provide all the necessary
information
about the main component of the input signal locking to which is desired. The
amplitude-
adjusted output of VCO, i.e. the output of the amplitude adjustment unit 16 of
Figure
3, is the synthesized output which is locked to the desired component of the
input signal.
The output of the gain/integrator block 166 of amplitude adjustment unit 16 of
Figure 3
is the estimated amplitude of such a synthesized output. The input of the VCO
30, or the
output of the loop filter 20, is the time derivative of the total phase. An
integrator may
be added to provide the total phase if needed. Finally, in case PI-controller
is used as the
loop filter, the output of the gain/integrator unit 24 of Figure 5 is the
frequency in rad/s.
Therefore, in the present invention, in addition to the fact that the
synthesized output
is in amplitude/phase/frequency lock with the desired component of its input,
the values
of amplitude, phase and frequency of the synthesized component are directly
available, a
fact which renders the structure an amplitude/phase/frequency estimator PLL.
CA 02346136 2001-05-09
The present structure of PLL may seem rather unusual and totally non-
intuitive. This
is true, however, it is shown that replacement of some very intuitive phase
detection
scheme by such a non-obvious structure resolves almost all the problems
associated with
conventional PLLs. One multiplication, usual with conventional PLLs, is
replaced by
three multiplications 14, 164, 168, one subtraction 12, and one
gain/integration 166.
With today's available technology of electronic circuitry; these extra units
add practically
no complexity. l~-loreover, the structure of the loop filter may remain as
simple as a P or PI
controller which substantially reduces the overall complexity of the system.
In exchange,
a structure of PLL is achieved which works almost ideally under any condition.
There
is no pull-in or lock-in range involved; no complex circuitry is needed to
bring the PLL
to its pull-in or lock-in range; the PLL works in a range of theoretically
infinitely large,
a statement which is mathematically proved once and forever with no
reservation. One
more feature of this PLL is that the output is locked in both phase (and
frequency) and
in amplitude. Moreover, unlike conventional PLLs which provide only the
synthesized
output signal, the introduced PLL directly provides the estimates of the
amplitude and
phase (and frequency) of the desired component of the input signal in addition
to the
synthesized output. One further feature of the present PLL is its immunity to
the noise
which may be present in its input. From this aspect, the structure is very
robust with
respect to external conditions which may be manifested as the degree of
pollution in the
input signal such as white noise, harmonic distortion, disturbances, etc. It
is also very
robust with respect to its internal structure; small variations of the
internal parameters
such as K, KP and KP are tolerated without tangible effect on the performance
of the
loop.
A number of graphs arc presented to aid the evaluation of the performance of
the present
PLL. The input signal u(t) is composed of a single sinusoidal signal ul(t) =
Asin(wt+B)
in most cases. The output signal y(t) is the sinusoidal signal synthesized by
VCO 30
meant to coherently follow ul(t). The parameters K, KP and KI determine the
speed of
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CA 02346136 2001-05-09
the PLL in tracking amplitude and phase of the input signal. In all of the
graphs, the
time scale is normalized so as to provide unbiased data.
Figure 6 shows, by way of example, performance of the present PLL in its most
basic mode
of operation. The loop filter is taken to be a simple constant gain Kp, thus
reducing the
structure to its simplest form, P-type PLL. P-type PLL is meant to find the
constant
value of the phase of the input signal and to produce a signal whose constant
phase is
equal to that of the input. In such embodiment of the present PLL, the
frequency is
more or less known and is almost fixed; the VCO is set to initially oscillate
at such a
frequency; small drifts from this nominal frequency are tolerated by the loop
without
incurring much error. If the frequency happens to be changing with time, the
filter has
to be a PI-controller, thus presenting a PI-type PLL. If the frequency of the
input signal
is more or less fixed and known, PI-type PLL behaves the same way as P-type
PLL does.
P-type PLL is a phase-locked loop, phase here meaning the constant phase, or
equivalently
the total phase provided frequency is known and almost fixed. The phase of the
output
signal is not simply coherent with that of the input, it is equal to that:
Similarly, the
amplitude of the output signal is equal to that of the input signal. In Figure
6, the phase
of the input signal is taken to be a random number between 0° to
180° and the signal is
taken to be of unit amplitude. Parameters K and Kp determine the speed of the
loop
in catching the amplitude and phase, almost respectively. The loop generates a
precise
copy of its input signal; therefore, the difference between the input signal
and the output
approaches zero in a certain number of cycles which is controllable by the
values of the
parameters. It is noteworthy that in conventional PLLs, such an error signal
does not
approach zero for two reasons: 1) the phases are not equal, but their
difference is ideally a
constant, and 2) the amplitudes need not be equal. The bottom graph in Figure
6 shows
the variations of the phase of the synthesized output in more clarity.
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Figure 7 shows the performance of the present PLL when a step change in
amplitude of
the input signal occurs. It is observed that the structure is sufficiently
robust to adapt
itself to the new value of the amplitude.
As was mentioned earlier, P-type PLL (and with all the more reason PI-type
PLL, of
course) is meant to track the variations of the phase under more or less fixed
frequency
condition. Figure 8 shows performance of the present PLL in locking to the
phase of the
input signal if it happens to undergo a step change.
Performance of P-type PLL is sufficiently satisfactory when the frequency of
the input
signal is known and fixed. However, if the frequency happens to be changing
with time,
it loses its accuracy and a steady state error will be introduced. The top
graph in Figure
9 shows such a scenario; the frequency of the input signal undergoes a step
change. The
phase of the output signal is not equal to that of the input although it is
more or less
coherent with it.
PI-type PLL may be used to eliminate the steady state error due to the step
change in
the frequency by employing a PI-controller in its loop filter. This type of
PLL is a more
general case than P-type PLL (it reduces to P-type by letting KI = 0) and is
capable
of locking the phase of its output to that of the input even if the frequency
undergoes
changes with time. The bottom graph in Figure 9 shows performance of PI-type
PLL
when the frequency undergoes a step change.
In cases where the frequency is constantly changing with time (such as a ramp
or a
sine function), the PI-type PLL may lose its feature of generating zero-
delayed output.
However, it has been observed that it more or less preserves the phase
coherence. The
degree of coherence is controllable by the values of parameters.
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CA 02346136 2001-05-09
The introduced PLL is very immune to the undesired pollution which may be
present in
its input. Figure 10 shows this feature. In this figure, the pollution is
modeled by a white
Gaussian noise which has reduced the signal to noise ratio (SNR) of the input
signal to
20 dB. It acts similar to an adaptive notch filter. It is observed that the
output signal is
ten times cleaner than the input signal.
One of the representative characteristics of PLL is its fitter transfer
function. It is a
measure of phase lock feature of the loop and is roughly defined as the
normalized value
of the magnitude of time-varying phase of the output signal as a function of
frequency
of time-variations of the phase of the input signal. Figure 11 shows examples
of fitter
function of the PLL structure of the present invention. Of course, the shape
of graphs are
dependent upon, and are controlled by, settings of the parameters K, Kp and
KI.
14
