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Patent 2379519 Summary

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Claims and Abstract availability

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(12) Patent Application: (11) CA 2379519
(54) English Title: REDUCED POWER LINE DRIVER
(54) French Title: CIRCUIT D'ATTAQUE DE LIGNE A PUISSANCE REDUITE
Status: Deemed Abandoned and Beyond the Period of Reinstatement - Pending Response to Notice of Disregarded Communication
Bibliographic Data
(51) International Patent Classification (IPC):
  • H04M 1/76 (2006.01)
  • H03H 11/28 (2006.01)
  • H04M 11/06 (2006.01)
  • H04M 19/00 (2006.01)
(72) Inventors :
  • BISSON, ROBERT (Canada)
  • TREMBLAY, FRANCOIS (Canada)
(73) Owners :
  • CATENA NETWORKS, INC.
(71) Applicants :
  • CATENA NETWORKS, INC. (United States of America)
(74) Agent: KIRBY EADES GALE BAKER
(74) Associate agent:
(45) Issued:
(86) PCT Filing Date: 2000-07-25
(87) Open to Public Inspection: 2001-02-01
Availability of licence: N/A
Dedicated to the Public: N/A
(25) Language of filing: English

Patent Cooperation Treaty (PCT): Yes
(86) PCT Filing Number: PCT/US2000/020265
(87) International Publication Number: WO 2001008388
(85) National Entry: 2002-01-16

(30) Application Priority Data:
Application No. Country/Territory Date
2,278,909 (Canada) 1999-07-26

Abstracts

English Abstract


A telephone line feed circuit for use with a telecommunication line includes a
transformer having a primary winding and a secondary winding wound with low
resistance conductors, the primary for direct connection to a tip terminal and
a ring terminal, and a driver circuit having an output connected to a
secondary winding of the transformer for driving the transformer secondary
winding directly with substantially no resistance therebetween while
maintaining an impedance match between the telecommunications line and the
telephone line feed circuit, to thereby reduce power consumption of the driver
circuit. The present invention seeks to provide a line interface circuit that
allows the significant reduction of driver power, namely up to about 50 %.


French Abstract

L'invention concerne un circuit d'alimentation de ligne téléphonique, utile dans une ligne de télécommunications et comprenant un transformateur doté d'un premier et d'un second enroulement, enroulés au moyen de conducteurs basse résistance; le premier enroulement est directement connecté à une borne de pointe et une borne de nuque; un circuit d'attaque comprenant une sortie connectée au second enroulement du transformateur sert à exciter ce second enroulement, directement, sans pratiquement de résistance entre eux, tout en maintenant une correspondance d'impédance entre la ligne de télécommunications et le circuit d'alimentation de la ligne téléphonique, de manière à réduire la consommation d'énergie du circuit d'attaque. L'invention porte notamment sur un circuit d'interface de ligne qui permet cette réduction importante de puissance d'attaque, laquelle réduction peut aller jusqu'à 50 % environ.

Claims

Note: Claims are shown in the official language in which they were submitted.


WHAT IS CLAIMED IS:
1. A telephone line feed circuit for use with a telecommunication line
having a tip terminal and a ring terminal, comprising:
a) a transformer having a primary winding and a secondary winding each
wound with low resistance conductors, the primary winding for direct
connection to the
tip terminal and the ring terminal of said telecommunication line; and
b) a driver circuit having an output coupled to the transformer secondary
winding, the driver circuit operative to drive the transformer secondary
winding directly
with substantially no resistance therebetween while maintaining an impedance
match
between the telecommunication line and the telephone line feed circuit.
2. A circuit as defined in claim 1, wherein said driver circuit is
operative to receive signals from an integrated POTS and xDSL(C1-C6) line
card.
3. A circuit as defined in claim 1, wherein said driver circuit includes
an active impedance synthesis circuit for generating said line impedance for
DSL signals.
4. A circuit as defined in claim 3, wherein said impedance synthesis
circuit is operative to synthesize matching impedance by sensing a current in
the
telecommunication line and driving a voltage source with a corresponding
voltage.
5. A circuit as defined in claim 4, wherein said current being sensed is
on the secondary side of said transformer.
6. A circuit as defined in claim 4, said current being sensed on the
primary side of said transformer.
7. A circuit as defined in claim 5, including a sense resistor coupled
in series in said line.
8. A circuit as defined in claim 6, including a sense resistor coupled
in series in said line.
9. A circuit as defined in claim 5, including a sense transformer
coupled in series in said line.

10. A circuit as defined in claim 6, including a sense transformer
coupled in series in said line.
11. A circuit as defined in claim 3, wherein said impedance synthesis
circuit is operative to synthesize matching impedance by sensing a voltage on
the
telecommunication line and driving a current source with a corresponding
current.
12. A circuit as defined in claim 11, wherein said voltage being sensed
is on the secondary winding side of said transformer.
13. A circuit as defined in claim 11, wherein said voltage being sensed
is on the primary winding side of said transformer.
11

Description

Note: Descriptions are shown in the official language in which they were submitted.


CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
REDUCED POWER LINE DRIVER
BACKGROUND OF THE INVENTION
This invention relates to a method and system for reducing power
consumption in a line driver.
With the increasing popularity of the Internet, there has been a
corresponding increase in the demand for high rate digital transmission over
the local
subscriber loops of telephone companies. A loop is a twisted-pair copper
telephone line
coupling a user or subscriber telephone to a central office (CO).
Traditional data communication equipment uses the voice band of the
subscriber loop. Such equipment includes voice band modems, which operate at
up to 56
kbps using compression techniques. On the other hand, Integrated Services
Digital
Network (ISDN) systems have boosted data rates over existing cooper phone
lines to 120
kbps. However traditional voice bands equipment is limited by the maximum data
rate of
the existing switching networks and PCM (Pulse Code Modulation) data highways.
By utilizing the frequency bandwidth of the loop outside the voiceband has
enabled other high-speed systems to evolve. However because loops can differ
in
distance, diameter, age and transmission characteristics depending on the
network, they
pose some limitations and challenges for designers of these high-speed
systems.
Current high-speed digital transmission systems of the above type include
asymmetric, symmetric, high-rate, and very high-rate digital subscriber loops,
conventionally known as ADSL, SDSL, HDSL and VDSL respectively. Normally these
and other similar protocols are known as xDSL protocols.
Of these flavors of xDSL, ADSL is intended to co-exist with traditional
voice services by using different frequency spectra on the loop. In the
future, it is
possible that multiple different transmission schemes may be employed in
different
frequency bands on the same loop, and that these transmission schemes may
include
traditional analog voice services as well as current and new forms of xDSL. In
today's
ADSL systems, the plain old telephone services (POTS) uses the frequency
spectrum
between 0 kHz and 4 kHz and the ADSL uses the frequency spectrum between 30
kHz
and 1.1 MHz for data over the telephone line. This is shown schematically in
Figure 1 a.
ADSL also partitions its frequency spectrum with upstream (subscriber to CO)
transmission in a lower frequency band, typically 30 kHz to 138 kHz, and with

CA 02379519 2002-O1-16
WO 01/08388 PCT/CJS00/20265
downstream transmission in a higher frequency band, typically 138 kHz to 550
kHz or 1.1
MHz. ADSL uses a discrete mufti-tone (DMT) mufti-carrier technique that
divides the
available bandwidth into approximately 4 kHz sub-channels.
Much effort is being expended by various xDSL hardware manufacturers
to reduce overall power dissipation of the xDSL equipment. Although overall
power
reduction improvements have been made, significant power improvements in the
area of
line drivers have not occurred. Minor improvements have been due to crest
factor
reductions that in turn precipitated a slight driver voltage rail reduction at
the expense of
DSP MIPS. For all of these applications the driver power is not significantly
improved.
To make xDSL technology attractive, the overall power dissipation must
be reduced beyond that of the presently offered solutions. This power
dissipation
manifests itself in the form of increased operation temperature of the
equipment. A
number of design constraints are introduced in order to maintain circuits at a
reasonable
operating temperature, including the inclusion of additional fans, air
conditioning, heat
sinks and space for thermal ventilation. These constraints significantly
increase the
material, labor and maintenance cost associated with the system. Furthermore,
excessive
heat may restrict the density of equipment, thereby increasing the size of the
facility
hosting the system and/or limiting the number of customers that can be served
by a fixed
size facility. Thus, reducing the power consumption in communications systems
can be a
key aspect of any system design.
The line driver is a component that consumes a significant amount of
power. Typically, the line driver includes an amplifier for receiving an
analog signal
from a preceding circuit, such as a digital to analog (DA) converter on the
xDSL line
card, to drive this signal through a source resistance and a line transformer
onto a twisted
pair telephone line or loop. The xDSL line drivers commonly in use include a
source or
feed resistance equal to the reference impedance of the loop, usually 100 ohms
implemented as a series resistance. Typical line drivers use two amplifiers
working
differentially.
Various forms of line interface circuits are known, and which are
particularly applicable to POTS system. For example U.S. Pat. No. 5,258,713
describes
an impedance generator for a telephone line interface circuit, which uses a
sensing circuit
coupled to the feed resistors in series with the tip and ring lines. The
sensing circuit
produces a feedback signal for use by an impedance generator circuit. In U.S.
Pat. No.
5,661,794 also describes a telephone line interface circuit, however loop
current and
2

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
common mode current are through the feed resistors are monitored and converted
to
digital signals for providing programmable control of the operating conditions
of the
circuit. Other exemplary line interface circuits are described in U.S. Pat.
No. 4,764,956,
U.S. Pat. No. 5,052,039 and U.S. Pat. No. 5,333,192. Thus it appears that
without
exception current line interface circuits, for use either with POST or xDSL
systems,
utilize a series feed resistance to match the impedance on the line, which is
relatively
wasteful of power.
Accordingly there is a need for a line driver circuit that exhibits lower
power consumption than current implementations and which is easily implemented
in
integrated circuit form.
SUMMARY OF THE INVENTION
In accordance with this invention, a telephone line feed circuit for use with
a telecommunication line includes a transformer having a primary winding and a
1 S secondary winding wound with low resistance conductors, the primary for
direct
connection to a tip terminal and a ring terminal, and a driver circuit having
an output
connected to a secondary winding of the transformer for driving the
transformer
secondary winding directly with substantially no resistance therebetween while
maintaining an impedance match between the telecommunications line and the
telephone
line feed circuit, to thereby reduce power consumption of the driver circuit.
The present
invention seeks to provide a line interface circuit that allows the
significant reduction of
driver power, namely up to about 50%.
In one embodiment the line feed circuit includes an active impedance
synthesis circuit for generating the line impedance for xDSL signals.
In another embodiment the line feed circuit includes an active impedance
synthesis circuit for generating the line impedance for POTS signals.
In a further embodiment the line feed circuit is coupled to an integrated
POTS/xDSL line card.
In a still further embodiment the line feed circuit includes an active
impedance synthesis circuit for generating line impedances for both xDSL and
POTS
signals.
3

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features of the preferred embodiments of the invention
will become more apparent in the following detailed description in which
reference is
made to the appended drawings.
Figure 1 is a schematic diagram of a line feed circuit according to the prior
art.
Figure 2 is a schematic diagram of a line feed circuit according to an
embodiment of the invention.
Figure 3 is a schematic diagram of a line feed circuit with a current sense
feedback.
Figure 4 is a schematic diagram of a line feed circuit with a current sense
feedback according to a further embodiment of the invention.
Figure 5 is a schematic diagram of a line feed circuit with a current sense
feedback using a transformer.
Figure 6 is a schematic diagram of a line feed circuit with a current sense
feedback using a transformer according to a further embodiment of the
invention.
Figure 7 is a schematic diagram of a line feed circuit with a voltage sense
feedback.
DESCRIPTION OF SPECIFIC EMBODIMENTS
In the following description like numerals refer to like structures in the
drawings.
Referring to Figure 1, a line feed circuit according to the prior art is shown
generally by numeral 10. The line feed circuit 10 includes driver stage 12,
feed resistors
18 and a line transformer 19. The driver stage normally comprises two driver
amplifier
circuits 14 and 16 (normally fixed-gain amplifiers) for supplying a subscriber
line
comprising tip T and ring R lines, via respective series feed resistors RF 18.
A load
resistance RL normally terminates the line. For xDSL signals the line is
normally
terminated by a load resistance RL of typically 100 ohms, thus the series feed
resistors RF
are chosen to equal the reference impedance of the loop, i.e. 50 ohms each.
Other values
of the feed resistors are chosen for different signals such as POTS signals.
Furthermore as
illustrated in Figure 1, the drive amplifiers 14 and 16 are each powered by
(+)VS"pp~y
voltage rails referenced to ground. Alternatively the drive amplifiers may be
powered by
(-)VS"pP~y~2 and (+)VS"pp~y~2 voltage rails.
4

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
For convenience the following definitions of specific terms that are used in
the following description are provided:
Vh = total voltage headroom required on side of the voltage rail for
allowing proper biasing of the drive amplifiers, typically 3V/2;
RS = total source resistance;
Rtr = tip and ring load resistance, 100 ohms for xDSL;
Vtr = tip and ring voltage, 2V rms;
ItT. "= tip and ring current, 20 mA rms (or 16.2 dBm into 100 ohms);
a = CF = crest factor, which is the ratio of the peak signal to the rms
signal ( typically 5.3 for the g.Lite standard);
R~ = load impedance;
RF = feed impedance;
n = transformer turns ratio;
VP/a = peak output voltage at one driver;
Pt = total power for two driver amplifiers;
Vp_p = total peak-to-peak voltage at output of drivers;
Ib = quiescent bias current per drive amplifier;
VsuPPiy = total driver amplifier supply voltage across supply rails; and
~2/~ _ (average DSL current)/(rms DSL current).
Referring back to the circuit of Figure l, the peak voltage at one driver
may be derived as follows:
Vp/a = (RF + RL)/(n*RL)*Vtr/2*6;
the supply voltage rails required, given the desired voltage headroom
above is then given by:
2S VsUppiy = (Vn + Vp/a)*2.
The total differential driver power consumption for xDSL signals can be
defined in terms of the driver supply voltage and the required current to be
driven onto
the line, as follows:
Pt = Vsupply *(~2/7L*n*Vtr/RL + 2*Ib)
par;~e = 2*(Vh + ((Rs+RtT)/(n*RtT)*Vt,/2 * 6)*(~2/~*nVtt/RL + 2*Ib) (1)
5

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
The supply voltage Vsupply is a function of the total resistance, the current
and the crest factor requirement. Power consumption can be calculated for the
circuit in
Figure 1 assuming
CF = 5.3;
Vh = 1.5V;
RF = 100 ; and
RL = 100
Then using equation (1) the driver power:
Pdr;,,e = 2*(1.SV + (2 * 2V,-n,5/2 * 5.3)) * 1~2/~t* 2/100 +2*7 mA = 557 mW
According to the present invention, a mechanism is provided for reducing
the nominal DSL driver power consumption (ideally by 50%) by driving the DSL
signal
directly onto the line and not through a source resistance. The source
resistance is
actively generated through feedback.
Accordingly, referring to Figure 2, a telephone line feed circuit 20 for use
with a telecommunication line, comprises a transformer 29 having a primary and
secondary winding wound with low resistance conductors; the primary for direct
connection to the tip T terminal and a ring terminal R of a telecommunication
line, a
driver circuit 22 having an output 23 connected to the secondary winding of
the
transformer for driving the transformer secondary winding directly with
substantially no
resistance therebetween, a sensing circuit 27 for producing a feedback signal
which is
combined in a summing circuit 21 with the signal from the preceding xDSL/POTS
circuit
(not shown) to the driver circuit 22, while maintaining an impedance match
between the
telecommunications line and the telephone line feed circuit, to thereby reduce
power
consumption of the driver circuit 22.
The feedback signal from the sensing circuit 27 represents either the loop
current Itt flowing differentially in the tip and ring lines or the voltage V~
between the tip
and ring lines. In a specific embodiment the drive stage 22 includes two drive
amplifiers
operating differentially.
Power consumption for the circuit of Figure 2 is calculated as follows,
assuming RF= 0--because the driver circuit 22 is coupled directly to the
transformer 29-
6

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
and R~ = 100 ; then from equation 1:
Par;ve = 2*(1.5V+ (1 * 2Vrms/2 * 5.3 * 2)) *~2/~c* 2/100 + 2*7 mA. = 313 mW.
Thus, the power consumption is reduced from 557 mW to 313 mW, a
reduction of 44%.
Referring to Figure 3 a line feed circuit according to a first
embodiment of the invention is shown by numeral 30. In the following
description the
following additional symbols are used:
Z°°t = the source impedance of the line. This impedance is
usually 100
ohms in the xDSL band.
Rsense = sense resistor resistance
Isense = current though sense resistor Rsense
K = gain of the sense amplifier.
Referring back to Figure 3, the line feed circuit 30 comprises two voltage
sources 32 and 34 , coupled via respective current sense resistors 36 and 38
to the
secondary winding of a line transformer 40. The current Isense through the
each sense
resistor Rsense generates a voltage Vsense~ which is sensed and applied to the
differential
inputs of a sense amplifier 42. The output of the sense amplifier is amplified
and fed
back as an input to the voltage sources 32 and 34. The gain K of the sense
amplifier 42 is
chosen so that the voltage feedback to drivers 32 and 34 causes the drivers to
drive a
voltage sufficient to maintain the output impedance at Z°"t.
The line feed circuit 30 provides a voltage source with a current sense.
Although the sensing circuit uses a sense resistor to sense the current, this
could be a
reduced value feed, which would reduce the overall power savings. In
operation, the
driver stage must drive a current of Iteea = 20 ma rms into a load Z°~t
of approximately 100
ohms. Thus the voltage at the output of the voltage source 32 and 34 is given
by
Vout = (tout - 2*Rfeed) * Ifeed
_ (100 -2*5 ) * Ifeed
= 90*Ifeed
The gain K of the feedback amplifier is thus chosen to be 90. Because a
separate drive is used to drive the tip and ring lines, the gain of these
voltage source
drivers 32 and 34 is chosen to be (+)0.5 and (-)0.5 respectively. These
amplifiers may be
easily implemented by one of many known circuits as is well known in the art
and will
not be discussed further. Furthermore the summing circuit in the illustrated
embodiment
7

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
is implemented using a simple series connected resistors as shown. However,
other
summing circuits known in the art may equally well be used.
A variation of the circuit of Figure 3 is shown in Figure 4. In this second
embodiment the current sensing is on the tip and ring side (primary) of the
transformer.
The sense resistors are indicated as 36' and 38' respectively. Once again the
gain of the
feedback amplifier K is 90, based on the computation as for the circuit of
Figure 3.
Referring to Figure 5, a third embodiment of the invention is indicated
generally by numeral 50. In this embodiment using a sense transformer 52
performs the
current sense. An advantage of this configuration is that there is no power
loss by using a
sense resistor. The operation of the circuit is similar to that of Figure 3,
however the
output voltage of the voltage sources 32 and 34 is given by:
Vout - Ifeed*~Zout~
- Ifeed*(100)
Thus the gain K of the feedback amplifier 42 is chosen to be 100. Current
sense transformers are well known in the art and will not be discussed
further.
A variation of the circuit of Figure 5 is shown in Figure 6. In this
embodiment the current sensing is performed on the tip and ring side of the
line
transformer 40.
Refernng to Figure 7, a fifth embodiment of the active source resistance
generation circuit 70 for the driver stage comprises two current sources 72
and 74,
coupled directly to the secondary winding of a line transformer 40. A voltage
sense
amplifier 76 is coupled to receive the voltage across the transformer primary
Vtr i.e. at
the line side, which is amplified by the gain K' of the amplifier 76 and fed
back as an
input to the current sources 72 and 74.
The gain K' of the sense amplifier 76 is chosen so that the current feed
back to drivers 72 and 74 causes the drivers to drive a current into the
secondary of the
transformer 40 sufficient to match the output impedance to Zout. The current
Io"t driven
by the current sources may be given by
lout - Ut/r*~l~zout~
3 0 - V,,r~ 100
= 0.01 * VUr
Thus the gain K' of the amplifier 76 is 0.01
Although the invention has been described with reference to certain
specific embodiments, various modifications thereof will be apparent to those
skilled in
8

CA 02379519 2002-O1-16
WO 01/08388 PCT/US00/20265
the art without departing from the spirit and scope of the invention as
outlined in the
claims appended hereto. For example the turns ratio of the line transformer
used for
illustration purposes is 1:1. Other turns ratios may equally well be used,
such as 1:2, 2:1,
etc.
9

Representative Drawing

Sorry, the representative drawing for patent document number 2379519 was not found.

Administrative Status

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Event History

Description Date
Inactive: IPC assigned 2014-10-27
Inactive: IPC removed 2014-10-27
Inactive: IPC removed 2014-10-27
Inactive: IPC assigned 2014-10-27
Inactive: IPC assigned 2014-10-27
Appointment of Agent Request 2004-12-14
Revocation of Agent Request 2004-12-14
Time Limit for Reversal Expired 2004-07-26
Application Not Reinstated by Deadline 2004-07-26
Deemed Abandoned - Failure to Respond to Maintenance Fee Notice 2003-07-25
Revocation of Agent Requirements Determined Compliant 2003-06-02
Inactive: Office letter 2003-06-02
Inactive: Office letter 2003-06-02
Inactive: Delete abandonment 2003-06-02
Appointment of Agent Requirements Determined Compliant 2003-06-02
Letter Sent 2003-05-30
Letter Sent 2003-05-30
Appointment of Agent Request 2003-04-22
Inactive: Single transfer 2003-04-22
Revocation of Agent Request 2003-04-22
Inactive: Abandoned - No reply to Office letter 2003-04-22
Inactive: Office letter 2003-04-10
Inactive: Office letter 2003-04-10
Inactive: Adhoc Request Documented 2003-04-10
Appointment of Agent Request 2003-02-27
Revocation of Agent Request 2003-02-27
Revocation of Agent Requirements Determined Compliant 2003-01-29
Inactive: Office letter 2003-01-29
Inactive: Office letter 2003-01-29
Appointment of Agent Requirements Determined Compliant 2003-01-29
Revocation of Agent Request 2003-01-13
Appointment of Agent Request 2003-01-13
Inactive: Courtesy letter - Evidence 2002-07-16
Inactive: Cover page published 2002-07-11
Inactive: Notice - National entry - No RFE 2002-07-09
Inactive: First IPC assigned 2002-07-09
Application Received - PCT 2002-05-06
National Entry Requirements Determined Compliant 2002-01-16
Application Published (Open to Public Inspection) 2001-02-01

Abandonment History

Abandonment Date Reason Reinstatement Date
2003-07-25

Maintenance Fee

The last payment was received on 2002-01-16

Note : If the full payment has not been received on or before the date indicated, a further fee may be required which may be one of the following

  • the reinstatement fee;
  • the late payment fee; or
  • additional fee to reverse deemed expiry.

Please refer to the CIPO Patent Fees web page to see all current fee amounts.

Fee History

Fee Type Anniversary Year Due Date Paid Date
Basic national fee - standard 2002-01-16
MF (application, 2nd anniv.) - standard 02 2002-07-25 2002-01-16
Registration of a document 2003-04-22
Owners on Record

Note: Records showing the ownership history in alphabetical order.

Current Owners on Record
CATENA NETWORKS, INC.
Past Owners on Record
FRANCOIS TREMBLAY
ROBERT BISSON
Past Owners that do not appear in the "Owners on Record" listing will appear in other documentation within the application.
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Document
Description 
Date
(yyyy-mm-dd) 
Number of pages   Size of Image (KB) 
Cover Page 2002-07-11 1 34
Description 2002-01-16 9 396
Drawings 2002-01-16 4 57
Claims 2002-01-16 2 55
Abstract 2002-01-16 1 59
Notice of National Entry 2002-07-09 1 208
Request for evidence or missing transfer 2003-01-20 1 102
Courtesy - Certificate of registration (related document(s)) 2003-05-30 1 105
Courtesy - Abandonment Letter (Maintenance Fee) 2003-08-25 1 176
PCT 2002-01-16 4 117
Correspondence 2002-07-09 1 24
PCT 2002-01-17 5 265
Correspondence 2003-01-13 2 48
Correspondence 2003-01-29 1 14
Correspondence 2003-01-29 1 18
Correspondence 2003-02-27 8 134
Correspondence 2003-04-10 1 16
Correspondence 2003-04-10 1 20
Correspondence 2003-04-22 3 84
Correspondence 2003-06-02 1 15
Correspondence 2003-06-02 1 17
Correspondence 2004-12-14 3 103
Correspondence 2005-02-01 2 30