Note: Descriptions are shown in the official language in which they were submitted.
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PACKET VIDEO SIGNAL INVERSE TRANSPORT PROCESSOR MEMORY
ADDRESS CIRCUITRY
This application is a division of Canadian Serial No. 2,146,472 filed April 6,
1995.
This invention relates to apparatus for processing packets of program
component
data from a packet video signal and extracting corresponding payloads of
different
program signal components. It encompasses apparatus for addressing a transport
buffer
memory and the concept of utilizing a common transport buffer memory.
BACKGROUND OF THE INVENTION
It is known from, for example, United States Patent No. 5,168,356 and United
States Patent No. 5,289,276, that it is advantageous to transmit compressed
video signal
in packets, with respective packets affording a measure of error
protection/correction.
The systems in the foregoing patents transmit and process a single television
program,
albeit with a plurality of program components, from respective transmission
channels.
These systems utilize inverse transport processors to extract the video signal
component
of respective programs for further processing to condition the video component
for
reproduction. The 5,289,276 patent only discusses processing the video signal
component. The 5,168,356 patent describes an inverse transport processor which
separates other program components with a simple demultiplexer responsive to
packet
header data for distinguishing respective signal components. The separated
video
component is coupled to a buffer memory, while the remaining signal components
are
shown coupled directly to their respective processing circuitry.
It is known from United States Patent 5,233,654, that code may be transmitted
with
television signals in order to provide interactive programming. This code will
typically be
operated upon, or executed by, a computer associated with a television
receiver.
In applications where most of the program components are
compressed, some buffering is needed between the transmission channel and
most of the respective component processing (decompression) apparatus,
thus it is desirable to couple most, if not all components to buffer memory.
The data rates of different program components may vary widely between
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respective components as well as within respective components.
Thus it is advantageous to buffer each component separately.
Buffer memory for buffering compressed program component
data and for processing interactive programs in general is not
insignificant. In fact it can contribute significantly to the cost of a
receiver system.
If the inverse transport processor resides in, for
example, a set top box, the memory size and management
circuitry should be kept to a minimum to keep consumer costs as
low as possible. Thus it is economically desirable to utilize the
same memory and memory management circuitry for program
component buffering, processor house keeping, and interactive
functions.
SUMMARY OF THE INVENTION
The present invention is an inverse transport
processor system for a TDM packet signal receiver. The system
includes apparatus for selectively extracting desired payloads of
program component data and coupling this data to a common
buffer memory data input port. A microprocessor generates data
which is also applied to the comnion buffer memory data input
port. The respective component payloads and data generated by
the microprocessor are stored in respective blocks of the common
buffer memory in response to associated memory addresses
wtiich are applied to a memory address input port by a address
2 5 multiplexer.
In a particular embodiment the program component
packet payloads of respective program components are
multiplexed to a memory data input port and directed to select
areas of random access memory (RAM) in accordance with a
plurality of start and end pointers. The start and end pointers are
stored in a first plurality of registers, one for each program
component. Addresses are generated, in part, by a plurality of
read pointer registers multiplexed with an adder to successively
increment the pointers for respective program components. The
3 5 start pointers are associated with read pointers for memory
addresses that scroll through designated memory blocks
selectively assigned to respective program components.
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In a further embodiment, a decryption device is included to decrypt
payload data according to packet specific decryption keys.
In a still further embodiment, a detector is included to detect payloads
including entitlement data. Payloads containing entitlement data are directed
via the common buffer memory to a smart card which generates the packet
specific decryption keys.
A data output from the memory is coupled to a bus interconnected
with the respective program component processors. Responsive to data
requests from the respective program component processors, and data write
requests from the component payload source, memory access for read and write
functions is arbitrated so that no incoming program data is lost, and all
component processors are serviced.
In accordance with the invention, there is provided apparatus in an
audio/video signal transport processor for processing signal including time
division multiplexed packets of program components with respective packets
including a payload of component data and a header with a component
identifier, SCID, and wherein respective payloads of predetermined
components are extracted from respective packets and stored in buffer memory.
The apparatus includes direct memory access circuits, responsive to detected
the identifiers for generating mutually exclusive direct memory access address
sequences to write payloads of component data in mutually exclusive blocks of
the buffer memory.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described with reference to the drawings,
wherein:
FIGURE I is a pictorial representation of a time division multiplexed
packet television signal;
FIGURE 2 is a pictorial representation of respective signal packets;
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FIGURE 3 is a block diagram of a receiver for selecting and
processing packets of multiplexed component signals embodying the present
invention;
FIGURE 4 is a block diagram of exemplary memory management
circuitry which may be implemented for element 17 of FIGURE 3;
FIGURE 5 is a pictorial representation showing memory address
formation for service channel data.
FIGURE 6 is a pictorial representation showing memory address
formation for auxiliary packet data.
FIGURE 7 is a block diagram of exemplary circuitry for generating
auxiliary packet memory addresses.
FIGURE 8 is a block diagram of alternative register circuitry for
incrementing memory addresses.
FIGURE 9 is a flow chart of operation of the memory address
control.
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FIGURE 10 is a block diagram of a conditional access
filter/start code detector.
DETAILED DESCRIPTION
FIGURE 1 shows a signal stream consisting of a string
of boxes which represent signal packets which are components of
a plurality of different television or interactive television
programs. These program components are assumed to be formed
of compressed data and as such the quantity of video data for
respective images is variable. The packets are of fixed length.
packets with letters having like subscripts represent components
of a single program. For example, V;, Ai, Di represent video, audio
and data packets and packets designated Vi, AI, DI, represent
video, audio and data components for program 1, and V3, A31, A32,
D3, represent video, audio 1, audio 2 and data components of
program 3. The data packets Di may contain e.g. control data to
initiate certain action within a receiver, or they may include
executable code forming an application to be executed by e.g., a
microprocessor located within or associated with a receiver.
In the upper line of the string of packets the
respective components of a particular program are shown grouped
together. However there is no necessity of packets from the sarne
program being grouped as is indicated by the entire string of
packets. Nor is there any particular order for the sequence of
2 5 occurrence of respective components.
The respective packets are arranged to include a
prefix and a payload as shown in FIGURE 2. The prefix of this
exaniple includes two 8-bit bytes comprising five fields, four (P,
BB, CF, CS) of which are 1-bit fields, and one (SCID) of which is a
12-bit field. The SCID field is the signal coniponent identifier.
The field CF contains a flag to indicate whether the payload of the
packet is scrambled, and the field CS contains a flag which
indicates which of two alternative unscrambling keys is to be
utilized to unscramble scrambled packets. The prefix of every
3 5 packet is packet aligned, thus the location of the respective fields
are easily identifiable.
Within every payload is a header which contains a
continuity count, CC, modulo 16, and a TOGGLE flag bit which are
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program component specific. The continuity count is simply a
successive numbering of successive packets of the same program
component. The TOGGLE flag bit is a one bit signal which, for the
video component, changes logic level or toggles in packets defining
the beginning of a new picture (frame), i.e., packets which contain
a picture layer header.
FIGURE 3 illustrates in block form, a portion of digital
television signal receiver including elements of an inverse
transport processor. Signal is detected by an antenna 10 and
applied to a tuner detector4 11, which extracts a particular
frequency band of received signals, and provides baseband
compressed signal in a binary format. The frequency band is
selected by the user through a microprocessor 19 by conventional
methods. Nominally broadcast digital signals will have been error
encoded using, for example, Reed-Solomon forward error
correcting (FEC) coding. The baseband signals will thus be applied
to a FEC decoder, 12. The FEC decoder 12 synchronizes the
received video and provides a stream of signal packets of the type
illustrated in FIGURE 1. The FEC 12 may provide packets at
regular intervals, or on demand, by for example, memory
controller 17. In either case a packet framing or synchronizing
signal is provided by the FEC circuit, which indicates the times
that respective packet inforrnation is transferred from the FEC 12.
The detected frequency band may contain a plurality
2 5 of time division multiplexed programs in packet form. To be
useful, only packets from a single program should be passed to
the further circuit elements. In this example it is assumed that
the user has no knowledge of which packets to select. This
information is contained in a program guide, which in itself is a
program consisting of data which interrelates program signal
components through SCID's, and may include information relating
to, for example, subscriber entitlements. The program guide is a
listing for each program, of the SCID's for the audio, video, and
data components of respective programs. The program guide
3 5 (packets D4 in FIGURE 1) is assigned a fixed SCID. When power is
applied to the receiver, the microprocessor 19 is programmed to
load the SCID associated with the program guide into one of a
bank of similar programmable SCID registers 13. The SCID fields
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of the prefix portion of respective detected packets of signal from
the FEC 12 are successively loaded in a further SCID register 14.
The programmable registers and the received SCID register are
coupled to respective input ports of a comparator circuit 15, and
the received SCID is compared with the program guide SCID. If the
SCID for a packet matches the program guide SCID, the comparator
conditions a memory controller 17 to route that packet to a
predetermined location in the memory 18 for use by the
microprocessor. If the received SCID does not match the program
10 guide SCID, the corresponding packet is simply dumped.
The microprocessor waits for a programming
command from the user via an interface 20, which is shown as a
computer keyboard, but which rnay be a conventional remote
control, or receiver front panel switches. The user may request to
1 5 view a program provided on channel 4 (in the vernacular of
analog TV systems). The microprocessor 19 is programmed to
scan the program guide list that was loaded in the memory 18 for
the respective SCID's of the channel 4 program components, and to
load these SCID's in respective other ones of the programmable
registers of the bank of registers 13 which are associated with
corresponding component signal processing paths.
Received packets of audio, video or data program
components, for a desired program, must ultimately be routed to
the respective audio 23, video 22, or auxiliary data 21, (24) signal
2 5 processors respectively. Tlie data is received at a relatively
constant rate, but the signal processors nominally require input
data in bursts (according to the respective types of decompression
for example). Ttie exemplary system of FIGURE 3, first routes the
respective packets to predetermined memory locations in the
memory 18. Thereafter the respective processors 21-24 request
the component packets from the rnemory .18. Routing the
components ttirough the memory provides a measure of desired
signal data rate buffering or throttling.
The audio, video and data packets are loaded into
3 5 respective predetermined memory locations to enable the signal
processors convenient buffered access to the component data. In
order that the payloads of respective component packets get
loaded in the appropriate memory areas, the respective SCID
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comparators are associated with those memory areas. This
association may be hardwired in the memory controller 17, or the
association may be programmable. If the former, specific ones of
the programmable registers 13 will always be assigned the audio,
video and data SCID's respectively. If the latter the audio, video
and data SCID's may be loaded in any of the programmable
registers 13, and the appropriate association will be programmed
in the memory controller 17 when the respective SCID's are
loaded in the programmable registers.
In the steady state, after the program SCID's have
been stored in the programmable registers 13, the SCID's of
received signal packets are compared with all of the SCID's in the
programmable SCID registers. If a match is made with either a
stored audio, video or data SCID, the corresponding packet
1 5 payload will be stored in the audio, video or data niemory area or
block respectively.
The respective signal packets are coupled from the FEC
12 to the memory controller 17 via a signal decryptor 16. Only
the signal payloads are scrambled and the packet headers are
passed by the decryptor unaltered. Whether or not a packed is to
be descrambled is determined by the CF flag in the packet prefix,
and how it is to be descrambled is deterrnined by the CS flag. If
no SCID match is had for a respective packet, the decryptor may
simply be disabled frorn passing any data. Alternatively, if there
is no SCID match for a packet the decryptor may be allowed to
decrypt according to its last settings and the memory write
control may be disabled to dump the respective packet.
The decryptor is programmed with decryption keys
provided by the smart card apparatus 31. "I'he smart card is
responsive to entitlement information contained in particular
packets of the program guide to generate appropriate decryption
keys. The system of ttie present example incorporates two levels
of encryption or program access, entitlement control messages,
ECM's, and entitlement management messages, EMM's. Program
entitlement control and management information is regularly
transmitted in packets identifiable with specific SCID's included in
the packet stream cotnprising the prograrn guide. The ECM
information contained in these packets is used by the smart card
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to generate the decryption keys used by the decryptor. The EMM
information included in these packets is used by the subscriber
specific smart card to determine program material to which the
subscriber is entitled. EMM entitlement information within these
packets may be made geographically specific, or group specific or
subscriber specific. For example, the present system will include
a modem (not shown) for communicating billing information from
the smart card to the prograrn provider, e.g., the satellite
broadcaster. The smart card may be programmed with, for
example, the area code and telephone exchange of the receiver
location. The EMM may include data, which when processed by
the smart card, will entitle or deny reception of particular
programs in particular area codes.
The program provider may want the ability to black
out particular areas or groups with very short lead time. For
example, a broadcaster may be required to black out a football
game in the area local to ttie stadium, if the tickets for the game
are not sold out. This information is not available until
immediately before game time. With such short lead time it may
not be possible to program EMM's to black out the local area. A
further coding of the entitlement information is included within
payloads of entitlement data to allow instant blackout.
Packets containing the entitlement data include a
payload header of 128 bits arranged in specially coded 4 groups
2 5 of 32 bits. A matched filter or E-code decoder 30, is arranged to
detect certain combinations of bit patterns within the 128 bit
header. If a match is detected the decoder communicates with the
memory controller 17 and the srnart card 31 to make the
remainder of the entitlement payload available to the smart card
(via the memory 18). If a rnatch is not detected, the payload is
not accepted by the specific receiver. 'The special codes may be
periodically changed if ttie matched filter 30 is made
programmable. These codes may be periodically provided by the
smart card. For more specific details on smart card operation as
3 5 related to viewer entitlements the reader is invited to review
Section 25 of THE SATELLITE BOOK, A COMPLETE GUIDE TO
SATELLITE TV THEORY AND PRACTICE, Swift Television
Publications, 17 Pittsfield, Cricklade, Wilts, England.
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The matched filter or E-code decoder is arranged to
perform a second function, which is to detect particular MPEG
video headers. 'These headers or start codes are 32 bits in length,
(which is the reason the headers of entitlement payloads are
coded in 32-bit groups). If video data is lost, an MPEG video
decoder can only restart decompressing video data at particular
data entry points. These entry points coincide with MPEG start
codes. The decoder may be arranged to communicate with the
memory controller 17 to inhibit the flow of video data to memory
after video packet losses, and to resume writing video payloads to
memory only after the next MPEG start code is detected by the
decoder 30.
FIGURE 4 illustrates exemplary apparatus for the
memory controller 17 shown in FIGURE 3. Each program
component is stored in a different contiguous block of the memory
18. In addition other data, such as data generated by the
microprocessor 19 or a Smart Card (not shown) may be stored in
the memory 18.
Addresses are applied to the memory 18 by a
multiplexor 105, and input data is applied to the memory 18 by a
multiplexor 99. Output data from the rriemory management
circuitry is provided to the signal processors by a further
multiplexor 104. Output data provided by the multiplexor 104 is
derived from the microprocessor 19, the memory 18 or directly
from the multiplexor 99. Program data is presumed to be of
standard picture resolution and quality, and occurring at a
particular data rate. On the other hand high definition television
signals, HDTV, which may be provided by this receiver, occur at a
significantly higher data rate. Practically all data provided by the
FEC will be routed through the memory 18 via the multiplexor 99
and memory I/O circuit 102, except for ttie higher rate HDTV
signals which may be routed directly from the multiplexer 99 to
the multiplexor 104. Data is provided to the multiplexer 99 from
the decryptor 16, the smart card circuitry, the microprocessor 19,
and a source of a media error codes 100. The term "media error
codes as used herein, means special codewords to be inserted in a
data stream, to condition the respective signal processor
(decompressor) to suspend processing until detection of a
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predetermined codeword such as a start code, and then to resume
processing in accordance with the e.g. start code.
Meniory addresses are provided to the multiplexor
105, from program addressing circuitry 79-97, from the
microprocessor 19, from the Smart Card apparatus 31 and from
the auxiliary packet address counter 78. Selection of the particular
address at any particular time period is controlled by a direct
memory access DMA, circuit 98. The SCID control signals from the
comparator 15 and "data needed" signals from respective signal
processors are applied to the DMA 98, and responsive thereto,
memory access contention is arbitrated. The DMA 98 cooperates
with a Service Pointer Controller 93, to provide the appropriate
read or write addresses for respective program signal
components.
The respective addresses for the various signal
component memory blocks are generated by four groups of
program component or service pointer registers 83, 87, 88, and
92. The starting pointers for respective blocks of memory, into
which respective signal cornponents are stored, are contained in
2 0 registers 87 for the respective signal components. The start
pointers may be fixed values, or they may be calculated by
conventional memory rnanagement methods in the microprocessor
19.
The last address pointers for respective blocks are
stored in the bank of service registers 88, one for each potential
program component. Similar to the start addresses, the end
addresses may be fixed values or they rnay be calculated values
provided by the microprocessor 19. Using calculated values for
starting and end pointers is preferred because it provides a more
3 0 versatile system with less rnemory.
The rnemory write pointers or head pointers are
generated by the adder 80 and the service head registers 83.
There is a service head register for each potential program
component. A write or head pointer value is stored in a register
3 5 83, and provided to the address multiplexor 105 during a memory
write cycle. The head pointer is also coupled to the adder 80,
wherein it is incremented by one unit, and the incremented
pointer is stored in the appropriate register 83 for the next write
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cycle. The registers 83 are selected by the service pointer
controller, 93, for the appropriate program component currently
being serviced.
In this example it is assumed that the start and end
pointers are 16-bit pointers. The registers 83 provides 16 bit
write or head pointers. 16-bit pointers were selected to facilitate
use of 16-bit or 8-bit busses for loading the start and end pointers
in the registers 87 and 88. The memory 18, on the other hand,
has 18-bit addresses. The 18-bit write addresses are formed by
concatenating the two most significant bits of the start pointers to
the 16-bit head pointers, with the start pointer bits in the most
significant bit positions of the combined 18-bit write address. The
start pointers are provided by the respective registers 87 to the
service pointer controller 93. The service pointer controller
parses the more significant start pointer bits from the start
pointers stored in registers 87, and associates these bits with the
16-bit head pointer bus. This is illustrated by the bus 96 shown
being combined with the head pointer bus exiting the multiplexor
85, and by FIGURE 5 with reference to the bold arrows.
In FIGURE 5, the top middle and bottom rows of boxes
represent the bits of a start pointer, an address and a head or tail
pointer respectively. The higher numbered boxes represent more
significant bit positions. The arrows indicate froni which bit
positions of the start or head/tail pointers the respective bits of
2 5 an address are derived. In this derivation ttie bold arrows
represent steady state operation.
Similarly, memory read pointers or tail pointers are
generated by the adder 79 and the service tail registers 92. There
is a service tail register for each potential program component. A
3 0 read or tail pointer value is stored in a register 92, and provided
to the address multiplexor 105 during a memory read cycle. The
tail pointer is also coupled to the adder 79, wherein it is
incremented by one unit, and the incremented pointer is stored in
the appropriate register 92 for the next read cycle. The registers
3 5 92 are selected by the service pointer controller, 93, for the
appropriate program component currently being serviced.
The registers 92 provides 16 bit tail pointers. 18-bit
read addresses are formed by concatenating the two most
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significant bits of the start pointers to the 16-bit tail pointers,
with the start pointer bits in the most significant bit positions of
the combined 18-bit write address. The service pointer controller
parses the more significant start pointer bits from the start
pointers stored in registers 87, and associates these bits with the
16-bit tail pointer bus. This is illustrated by the bus 94 shown
being combined with the tail pointer bus exiting the multiplexor
90.
Data is stored in the memory 18 at the calculated
address. After storing a byte of data, the head pointer is
incremented by one and compared to the end pointer for this
program component, and if they are equal the more significant
bits of the head pointer are replaced with the lower 14 bits of the
start pointer and zeros are placed in the lower two bit positions of
the head pointer portion of the address. This is illustrated in
FIGURE 5 with reference to the hatched arrows between the start
pointers and the address. This operation is illustrated by the
arrow 97 pointing from the service pointer controller 93 to the
head pointer bus from the multiplexor 85. It is presumed that
application of the lower 14 start pointer bits override the head
pointer bits. Replacing the head pointer bits with the lower start
pointer bits in the address for this one write cycle, causes the
memory to scroll through the memory block designated by the
upper two start pointer bits, thus obviating reprogramming write
2 5 addresses at the start of each packet to a uriique memory location
within a block.
If the head pointer ever equals the tail pointer (used
to indicate where to read data from the memory 18) a signal is
sent to the interrupt section of the microprocessor to indicate ttiat
a head tail crash has occurred. Further writing to the memory 18
from this program channel is disabled until the niicroprocessor re-
enables the channel. This case is very rare and should not occur
in normal operation.
Data is retrieved from the memory 18 at the request
3 5 of the respective signal processors, at addresses calculated by the
adder 79 and registers 92. After reading a byte of stored data,
the tail pointer is incremented by one unit and compared to the
end pointer for this logical channel in ttie service pointer
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controller 93. If the tail and end pointers are equal then the more
significant bits of the tail pointer are replaced with the lower 14
bits of the start pointer and zeros are placed in the lower two bit
positions of the tail pointer portion of the address. This is
illustrated by the arrow 95 emanating f'rom controller 93 and
pointing to ttie tail pointer bus from the multiplexor 90. If the tail
pointer is now equal to the head pointer, then the respective
memory block is defined as enipty and no rnore bytes will be sent
to the associated signal processor until rriore data is received from
the FEC for this program channel. T'he actual replacement of the
head or tail pointer portions of the respective write or read
addresses by the lower 14 bits of the start pointer may be
accomplished by appropriate multiplexing, or the use of three
state interconnects .
1 5 Data transmitted in auxiliary packets is typically
directory, header or control information and thus is processed
slightly differently from program component data. Data in the
auxiliary packets include information necessary to establish the
requisite tnemory storage areas for the respective program
components and any included applications. As such auxiliary
packets are given preference. Two service blocks are provided for
each component. Each block has an eight bit sequential address or
storage locations for 256 bytes of data. Each block has an
eighteen bit total address which is illustrated in FIGURE 6. The
2 5 eight LSB's of the address are provided by a sequential counter.
"I'he ninth bit is provided by the CS or scramble key bit from the
transport prefix. The tenth through twelfth bits are generated
responsive to ttie particular SCID's assigned for program detection.
T'his example assurnes that the system has provision for
3 0 processing and detecting five prograni componerrts (including
program guide) or services. There are thus five SCID's
programmed in the respective programmable SCID registers 13
and five SCID comparators, 15. "I'he five comparators each have
an output terminal, which tertninal is assigned a program
3 5 component. The five possible programs that are associated with
the five comparator output terminals are assigned respective
three bit codes, three bits being ttie fewest number of bits that
can represent five states. 'T'he ttiree bit codes are inserted as the
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tenth through twelfth bits of the auxiliary packet addresses.
Assume that SCID's for five respective program components are
assigned to programmable registers arbitrarily numbered 1-5.
The three bit codes assigned to the components assigned to the
programmable registers 1-5 are 000, 001, 010, 011, and 100
respectively. Depending upon which program component is
currently being detected, the three bit code associated with the
programmable register containing the current program component
SCID, will be inserted into the tenth through twelfth bit positions
in the memory write address.
The six most significant bits of the 18 bit auxiliary
addresses are provided by the microprocessor according to
conventional memory management techniques.
FIGURE 7 illustrates exemplary auxiliary memory
address generating circuitry. FIGURE 7 includes a prefix register
125 used for capturing the prefix bit CS, which is applied to the
microprocessor 19. The five control lines from the SCID detector
15 are applied to a five control line to three bit converter 126,
which may be a simple Boolean logic operator. The three bits
generated by the converter 126 are applied to the microprocessor
19 which composes respective 10 most significant bit (MSB)
portions of auxiliary addresses. On detection of an auxiliary
packet, the 10-MSB address portion is applied to the MSB portion
of one of a bank of registers 128. The 8-LSB portion of the
2 5 respective register 128 is set to a predetermined value, typically
zero, at the beginning of each auxiliary packet . The 8-LSB portion
is appended to the 10-MSB portion and applied to an input port of
a 10-to-1 multiplexer 129. The 8-LSB portion of respective
addresses provided by the rnultiplexer 129 are coupled to an
adder 130, wherein the 8-LSB address value is incremented by
one unit and coupled back into the 8-LSB portion of the register
128 via a further multiplexer 127. The incremented LSB portion
(with its MSB portion) serves as the next successive address for
the respective auxiliary packet. The multiplexers 127 and 129
3 5 are controlled by the DMA controller 98 for selecting the current
memory block to be addresses. Note, in an alternative
arrangement the PC 19 may be arranged to establish at least a
portion of the auxiliary addresses.
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Auxiliary packets are typically processed
independently and an entire auxiliary packet payload is typically
loaded in memory before it can be utilized. As such, the block of
memory being addressed for writing a current auxiliary packet
thereto, will not normally be addressed concurrently for read and
write purposes. "I'herefor the same registers may be used for read
and write addressing. Once an auxiliary packet is stored in a
respective block of memory, the 8-LSB portion is reset to the
predetermined starting address in preparation for data readout.
In an alternative arrangement, a parallel bank of registers,
multiplexers and an adder similar to elements 127--130 may be
configured for generating read addresses. These read addresses
may be time division multiplexed with a further multiplexer in
cascaded connection with the multiplexer 129.
Memory read/write control is performed by the
service pointer controller and direct memory access, DMA,
elements 93 and 94. The DMA is programmed to schedule read
and write cycles. Scheduling is dependent upon whether the FEC
12 is providing data to be written to memory or not. FEC data
write operations take precedence so that no incoming signal
component data is lost. In the exemplary apparatus illustrated in
FIGURE 4, there are four types of apparatus which may access the
memory. These are Smart Card (not shown), the FEC 12 (more
precisely the decryptor 16), the microprocessor 19 and the
2 5 application devices such as the audio and video processors.
Memory contention is handled in the following manner. The DMA,
responsive to data requests frorn the various processing elements
listed above, allocates blocks of inemory for respective program
components. Access to the mernory is provided in 95 nS time
3 0 slots during which a byte of data is rea(i from or written to the
memory 18. There are two major niodes of access allocation,
defined by "FEC Providing Data", or "FEC Not Providing Data"
respectively. For each of these modes the time slots are allocated
and prioritized as follows, assuming a maximum FEC data rate of 5
3 5 Mbytes/second, or one byte for each 200 nS. These are:
FEC Providing Data
1) FEC data write;
2) Applicatiori device read/Microprocessor read/write;
RCA 87,602A CA 02387110 2002-06-20
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3) FEC data write;
4) Microprocessor read/write;
and for
FEC Not Providing Data
1) Smart Card read/write;
2) Application device read/Microprocessor read/write;
3 )Smart Card read/write;
4) Microprocessor read/write.
Because FEC data writes cannot be deferred, the FEC (or more
correctly the decryptor), when providing data must be guaranteed
memory access during each 200 nS interval. Alternate time slots
are shared by the application devices and the microprocessor.
When there is no data available for the requesting devices, the
microprocessor is provided use of the application time slots.
The Controller 93 cotnmunicates with the SCID
detector to determine which of the respective Start, head and end
pointer registers to access for memory write operations. The
controller 93 communicates with the DMA to determine which of
the start, end and tail registers to access for memory read
operations. The DMA 98 controls selection of the corresponding
addresses and data by the multiplexers 99, 104 and 105.
Preferred alternative circuitry for incrementing
meniory addresses is shown in FIGURE 8, which circuitry may be
utilized in either the FIGURE 4 or FIGURE 7 apparatus. FIGURE 8
2 5 illustrates its implementation as for tail pointer incrementing
according to FIGURE 4. At the beginning of a packet., the pointer
in the associated register 92A is coupled to the adder 79A,
wherein it is incremented by 1. Rather than storing intermediate
incremented tail pointers in the registers 92A of FIGURE 8 (92 of
FIGURE 4), intermediate incremented pointer values are
successively stored in a working register 107. After the last
pointer value is generated for a packet of signal, ttie updated
pointer in register 107 is transferred to the register 92A
associated with the packet SCID.
3 5 It is not uncommon that data in a memory buffer may
need to be omitted. For exarnple a partial packet may have been
stored when a system error or a data interrupt occurred. To
conserve memory space, the data ornissiorr is perforrned simply
RCA 87,602A CA 02387110 2002-06-20
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by overwriting the partial packet of data. Overwriting this data is
effected by resetting the appropriate pointer to the value it
exhibited at the beginning of the packet. Such resetting is
accomplished by not transferring the value in register 107 to the
pointer register, that is by doing nothing.
It is advantageous to insert media error codes into the
video component signal stream when packets are lost, to condition
ttie video signal decompressor to suspend decompression until a
particular signal entry poirrt occurs in the data stream. It is not
practical to predict where and in which video packet the next
entry point may occur. In order to find the next entry point as
fast as possible, it is necessary to include a media error code at
the beginning of the first video packet after detection that a
packet is lost. The circuitry of FIGURE 4 places a media error code
at the beginning of every video packet and then excises the media
error code in respective packets if there is no loss of a preceding
packet. The media error code is inserted in the first M memory
address locations reserved for the current video packet payload,
by writing to mernory 18 for M write cycles prior to the video
payload arriving from the decrypter. Concurrently the multiplexor
99 is conditioned by the DMA 98, to apply the media error code
from the source 100 to the mernory 18 1/0. M is simply the
integer number of memory locations required to store the media
error code. Assuming the memory to store 8-bit bytes, and the
2 5 media error code to be 32 bits, M will equal 4.
The addresses for loading the media error code in
niemory are provided by the respective video component service
register 83 via the multiplexer 82 and multiplexer 85. It will be
appreciated that the first M addresses provided from the pointer
register 83 for loading the media error code into the memory
locations that would otherwise be loaded with video component
data, will simply be the next M sequential addresses that would
normally be produced by the video head pointer. These same
addresses are coupled into an M-stage delay element 84, so that
3 5 immediately after the last byte of the media error code is stored
in ttie rnemory 18, the first of the M addresses is available at the
output of the delay element 84.
RCA 87,602A CA 02387110 2002-06-20
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The timing of the loading of the media error code into
memory coincides with the determination of a lost packet.
Loading the media error code while packet loss determination is
performed places no additional timing constraints on signal flow
processing.
If a packet loss is detected, the video component of the
current packet is stored in memory 18, starting at the next or
(M+l)th address location of the memory block established for that
component. This is accomplished by conditioning the multiplexer
85 to continue to pass undelayed head pointers from the
appropriate register 83. Alternatively, if a packet loss is not
detected, the first M bytes of' the video component in the current
packet are stored in the memory locations in which the media
error code was immediately previously stored. This is
accomplished by the service pointer controller conditioning the
multiplexer 85 to pass the delayed head pointers from the delay
element 84, for M write cycles. At the end of the M write cycles
the service pointer controiler 93 will condition the multiplexer to
again pass undelayed head pointers. When the niultiplexer
switches back to non delayed pointers, the next non delayed
pointer will correspond to the M+l ih address.
Packet error or loss detection is performed by an error
detector 101 which is responsive to the CC and HD data of the
current packet. The detector 101 examines the continuity count
2 5 CC in ttie current packet to determine if it differs from the CC of
ttie previous packet by one unit. In addition the TOGGLE bit in the
current packet is examined to determine if it has undergone a
change from the previous packet. If the CC value is incorrect, the
state of the TOGGLE bit is exatnined. Depending if one or both of
the CC and TOGGLE bit are in error or changed respectively, first
or second modes of error remediation are instituted. In the
second mode, ihitiated by the CC being in error and the TOGGLE bit
having changed, the system is conditioned to reset to a packet
containing a picture layer header. In the first mode, where only
3 5 the CC is erroneous, the system is conditioned to reset to a packet
containing a slice start code. (A slice layer is a subset of
compressed data within a frame.) In both the first and second
rnodes, the media error code written to memory is retained in the
RCA 87,602A CA 02387110 2002-06-20
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respective payload to alert the decompressor to institute remedial
action.
Depending upon the particular designs of a given
receiver, it may or may not be conducive to include media error
codes in different ones of the signal components when respective
component transport packets are lost. In addition it may be
advantageous to utilize different media error codes for different
signal component formats or compression processes. Thus one or
more media error code sources may be required.
FIGURE 9 illustrates an exemplary flow chart of the
DMA 98 memory access process. The DMA responds (200) to
detection or non detection of a received packet via detection of
SCID's. If a SCID has been detected indicating the presence of data
from the decryptor 16 to be written to rneniory, one byte of
program data from the decryptor is written {201) to the buffer
memory 18. The block of memory to which it is written is
determined by the processor 93 responsive to the current SCID.
Next the DMA determines (202) if any of the program component
processors, including the smart card and PC are requesting data
or read/write (R/W) access to the memory 18. If no data requests
are made on the DMA the process returns to step (200). If a data
R/W request has been made, the DMA determines 1203) the
priority of the request. This will be accomplished by a
conventional interrupt routine or alternatively sequential one
byte service in an arbitrary order of those program processors
requesting data. For example, assume that an arbitrary order of
access priority is video, audio I, audio II. smart card, and PC.
Assume also that only the video, audio 11 and PC are requesting
memory access. During the current operation of step (2031 a byte
of video will be read from memory. During the next operation of
step (2031 a byte of audio Il will be read from memory, and
During the next subsequent occurrence of step (203) a byte of P C
data will be written to- or read from memory 18 and so forth.
Note that address for smart card and PC access are provided by
the smart card and PC respectively, but addresses for video,
audio and program guide are available from the address pointer
arrangement (80-93).
RCA 87,602A CA 02387110 2002-06-20
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Once priority access has been established [2031, the
requisite progranl processor is serviced (204) with one byte of
data written to- or read from memory 18. Next a byte of data
from the decryptor 16 is written (205) to memory. A check 1206)
is made to determine if the PC is requesting access. If the PC is
requesting access, it is serviced (207) with one byte of data. lf
the PC is not requesting access the process jumps to step (202) to
determine if any of the program processors are requesting access.
In this manner the incoming data is always guaranteed access to
every other memory access period, and the intervening memory
access periods are spread amongst the program processors.
If data is not presently available from the decryptor
16, i.e. an SCID is not currently detected, the process (208-216) is
followed. First (208) the smart card is examined to determine if it
1 5 is requesting memory access. If it is, it is given a one byte
memory access [2091, else a check is made (210) to determine if
any of the program processors is requesting memory access. If a
data R/W request has been made, the DMA determines 1211) the
priority of the request. The appropriate processor is serviced
(212) with a one byte mernory read or write access. If a data
R/W request has not been made by the program processors, the
process jumps to step [213) where a test is performed to
determine if the smart card is requesting memory access. If it is
it is serviced (216) with a one byte rneniory access, else the
2 5 process jumps to step (200).
It should be recognized that in the present preferred
example, when in the "FEC Not Providing Data" mode, the smart
card is provided a two-to-one access precedence over all other
program processors. This priority is programmed into a
programmable state machine within the DMA apparatus and is
subject to being changed by the PC. As mentioned earlier, the
system is intended to provide interactive services, and the PC 19
will be responsive to interactive data to perform at least in part
ttie interactive operation. In this role, the PC 19 will use the
3 5 memory 18 both for application storage and working memory. In
these instances, the systeni operator may change the rnemory
access priority to provide the PC 19 with memory access of
RCA 87,602A CA 02387110 2002-06-20
-21 -
greater frequency. The reprogramming of memory access priority
may be included as a subset of interactive application instructions.
It is advantageous to insert media error codes into the
video component signal stream when packets are lost, to condition
the video signal decompressor to suspend decompression until a
particular signal entry point occurs in the data stream. It is not
practical to predict where and in which video packet the next
entry point may occur. In order to find the next entry point as
fast as possible, it is necessary to include a media error code at
the beginning of the first video packet after detection that a
packet is lost. The circuitry of FIGURE 4 places a media error code
at the beginning of every video packet and then excises the media
error code in respective packets if there is no loss of a preceding
packet. The. media error code is inserted in the first M memory
1 5 address locations reserved for the current video packet payload,
by writing to memory 18 for M write cycles prior to the video
payload arriving from the decryptor. Concurrently the multiplexor
99 is conditioned by the DMA 98, to apply the media error code
from the source 100 to the memory 18 1/0. M is simply the
integer number of memory locations required to store the media
error code. Assuming the memory to store 8-bit bytes, and the
rnedia error code to be 32 bits, M will equal 4.
The addresses for loading the media error code in
memory are provided by the respective video component service
2 5 register 83 via the multiplexer 82 and multiplexer 85. It will be
appreciated that the first M addresses provided from the pointer
register 83 for loading the media error code into the memory
locations that would otherwise be loaded with video component
data, will simply be the next M sequential addresses that would
normally be produced by the video head pointer. These same
addresses are coupled into an M-stage delay element 84, so that
immediately after the last byte of the media error code is stored
in the memory 18, the first of the M addresses is available at the
output of the delay element 84.
3 5 Packet error or loss detection is performed by an error
detector 101 which is responsive to the CC and HD data of the
current packet. The detector 101 examines the continuity count
CC in the current packet to deterrnirie if it differs from the CC of
RCA 87,602A CA 02387110 2002-06-20
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the previous packet by one unit. In addition the TOGGLE bit in the
current packet is examined to determine if it exhibits the proper
state for the respective video frame. If the CC value is incorrect,
ttie state of the TOGGLE bit is examined. Depending if one or both
of the CC and TOGGLE bit are in error, first or second modes of
error remediation are instituted. In the first mode, where only
the CC is erroneous, the system is conditioned to reset to a packet
containing a slice layer header. (A slice layer is a subset of
compressed data within a frame.) In the second mode, initiated
by both CC and TOGGLE bits being erroneous, the system is
conditioned to reset to a packet containing a picture layer header.
In both the first and second modes, the media error code written
to memory is retained in the respective payload to alert the
decompressor to institute remedial action.
1 5 If a packet loss is detected, the video component of the
current packet is stored in memory 18, starting at the next or
(M+l)rh address location. This is accomplished by conditioning
the multiplexer 85 to continue to pass undelayed head pointers
from the appropriate register 83. Alterriatively, if a packet loss is
not detected, the first M bytes of the video component in the
current packet are stored in the memory locations in which the
media error code was immediately previously stored. 'I'his is
accomplished by the service pointer controller conditioning the
multiplexer 85 to pass the delayed head pointers from the delay
2 5 element 84, for M write cycles. At the end of the M write cycles
the service pointer controller 93 will condition the multiplexer to
again pass undelayed head pointers. When the multiplexer
switches back to non delayed pointers, the next non delayed
pointer will correspond to the M+lth address.
3 0 Depending upon the particular designs of a given
receiver, it may or may riot be conducive to include media error
codes in different ones of the signal components when respective
component transport packets are lost. In addition it may be
advantageous to utilize different media error codes for different
3 5 signal component formats or compression processes. Thus one or
more rnedia error code sources niay be required.
FIGURE 10 illustrates exemplary apparatus for
detecting packets which include conditional access information or
RCA 87,602A CA 02387110 2002-06-20
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MPEG start codes (decoder 30 of FIGURE 3). Whether the decoder
30 is conditioned to detect entitlement payloads or MPEG start
codes is a function of the SCID currently being received. In
FIGURE 10, it is assumed that data provided from the decryptor
16 is in 8-bit bytes and packet aligned. That is, the first byte of
an entitlement payload or the first byte of an MPEG start code is
aligned precisely with the beginning of a packet payload, such
that for detecting specific header or start codewords, their
position in the bit/byte stream is precisely known. Data from the
decryptor 16 is applied to an 8-bit register 250, which has an 8-
bit parallel output port coupled to respective first input
connections of a comparator 254 which may be configured of, for
example, a bank of eight exclusive NOR (XNOR) circuits having
respective output connections coupled to an AND gate and a latch.
1 5 The latch may be a data latch arranged to latch the results of the
AND gate at each byte interval.
A 32-bit MPEG start code is stored as four bytes in an
8-bit register bank 265. Entitlement header codes are stored as
8-bit bytes in a bank of 16 8-bit registers 257. Loading of the
register banks 251 and 265 is controlled by the microprocessor 19
and/or by the smart card. The start code registers 265 are
coupled to a four to one multiplexer 266, and the entitlement
header registers are coupled to sixteen to one multiplexer 257.
Output ports of the multiplexers 257 and 266 are coupled to a two
to one multiplexer 249. Respective output connections of the
multiplexer 249 are coupled to respective corresponding second
input terminals of the comparator 254. Note the input and output
connections of the multiplexers 249, 257 and 266 are 8-bit
busses. If the respective values exhibited at the respective output
connections of the register 250 are correspondingly the same as
the output values exhibited by the respective output connections
of the multiplexer 249, a true signal is generated by the
comparator 254 circuit for the corresponcling data byte.
For start code detection, the multiplexer 266 is
scanned by the counter 258 to sequentially couple the four
different registers 265 to the XNOR in synchronism with the
occurrence of the first four data bytes from the decryptor 16.
Alternatively, for entitlement payload header detection, the
RCA 87,602A CA 02387110 2002-06-20
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multiplexer 257 is scanned by the counter 258 to sequentially
couple different ones of the registers 265 to the comparator
circuit.
The output of the cotnparator circuit is applied to an
accumulate and test circuit 255. The circuit 255 determines if any
of a predetermined number of byte matching conditions have
occurred, and if they have, it generates a write enable signal for
the entitlement data in a portion of the particular payload under
examination. In the present system the entitlement payload
header contains 128 bits arranged in four 32-bit segments.
Different subscribers will be arranged to look for different
combinations of bytes of the 128 bits. For example one subscriber
apparatus may be arranged to match the first four bytes of the
entitlement payload header. Another subscriber apparatus may
be arranged to match the second four bytes of the entitlement
payload header and so forth. In either of these exemplary
situations the circuitry 255 will determine if a match has occurred
for the appropriate four consecutive bytes.
The FIGURE 10 apparatus also includes circuitry
(elements 261-263) for detecting an all zero entitlement payload
header condition. 'The bits of respective arriving bytes of data are
coupled to respective terminals of the 8-bit OR gate 263. If any
one of the bits is a logic one the OR gate 263 generates a logic one
output. The output of the OR gate 263 is coupled to one input of a
2 5 two-input OR gate 262, which has an output and second input
coupled respectively to the data-input and Q-output terminals of a
D-type latch 261. The D-type latch is clocked by the timing circuit
259 synchronously with the arrival of incoming data bytes. If any
bit in any of the data bytes which occurs after the latch is reset is
3 0 a logic one, the latch 261 will exhibit a logic one at its Q-output
until the next reset pulse. The Q-output of latch 261 is coupled to
an inverter which exhibits a zero output level whenever the latch
exhibits a one output level. Thus, if after the 128 bits (16 bytes)
of the header have been passed through register 250, the output
3 5 of the inverter is high, then the 128 bits are zero valued.
Responsive to detection of a high output level from the inverter
after passage of the entitletnent payload header, the circuitry 255
will generate a data write enable signal.
RCA 87,602A CA 02387110 2002-06-20
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It has been found to be particularly efficient to
partition the system such that the SCID detector, the decryptor,
the addressing circuitry, the conditional access filter, and the
smart card interface are all included on a single integrated circuit.
This limits the number of external paths which may lead to
critical timing constraints.
