Note: Descriptions are shown in the official language in which they were submitted.
CA 02392386 2002-11-19
SPECIFICATION
SYNCHRONOUS PROCESSOR CIRCUIT
TECHNICAL FIELD
The present invention relates to synchronous,processor
circuits-in a color receiver and, more. specifically, to a
synchronous processor circuit for reproducing a synchronizing
signal externally provided by a video signal source to a color
receiver, and supplying the synchronizing signal to each circuit
block in the color receiver.
BACKGROUND ART
FIG. 14 is a block diagram showing the structure of a
conventional synchronous processor circuit. In FIG. 14, the
synchronous processor circuit includes an LPF 1'to which a
composite signal 5 is externally provided, and a vertical
synchronization separating signal 6 is separated therefrom and
outputted; a phase delay part 2 for receiving the composite signal
. 5 and outputting a plurality of horizontal synchronizing signals
19 to 24 each differently delayed in phase; and a vertical
synchronizing signal reproduction circuit 3 for receiving the
plurality of horizontal. synchronizing signals 19 to 24 each
differently delayed in phase and the vertical synchronization
separating signal 6 and outputting a vertical synchronizing
CA 02392386 2002-08-13
H
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signal 8. The phase delay part 2 includes first to sixth phase
delay circuits 201 to 206. The LPF is a low pass filter. The
operation of this synchronous processor circuit is described next
below.
FIG. 15 is a time chart which explains the operation of the
conventional synchronous processor circuit. In the upper part
of the drawing, t1 to t13 indicate time at a regular interval.
To be specific, time t1 to time t13 indicate timing for a horizontal
synchronizing signal to rise. As shown in FIG. 15, the composite
signal 5 externally provided to a display is a synchronizing
signal onto which a vertical synchronizing signal and a horizontal
synchronizing signal are superimposed.
In FIG. 15, the horizontal synchronizing signal is a pulse
signal which rises e~rery time at times t1 to time t13. The
vertical synchronizing signal is a pulse signal which rises at
time t4 and falls at time t8 . Once inputted into the LPF 1, such
composite signal 5 is cut off with any horizontal synchronizing
frequency component which is high in frequency. Therefore, the
LPF-1 is capable of reproducing the vertical synchronization
separating signal 6 with any horizontal synchronizing frequency
component subtracted from the-composite signal 5.
The composite signal 5 is also provided to each of the first
to sixth phase delay circuits 201 to 206 in the phase delay part
2. Those inputted composite signals 5 each generate a pulse
corresponding to a period of the horizontal synchronizing signal .
2
CA 02392386 2002-11-19
By using the pulses corresponding to the period of the horizontal
synchronizing signal, the first to sixth phase delay circuits 201
to 206-output horizontal synchronizing signals 19 to 24 varied
in phase with a predetermined interval in the corresponding phase
delay circuit, respectively. T'he horizontal synchronizing
signals I9.to 24 phase-delayed as such and the vertical
synchronization separating signal 6 are provided to the vertical
synchronizingv signal reproduction circuit 3. The vertical
synchronizing signal reproduction circuit3 outputs the vertical
synchronizing signal 8 having the phase relationship with the
horizontal synchronizing signal determined.
Next, the vertical synchronizing signal reproduction
circuit 3 is described for its structure and operation in detail.
FIG. 16 is a diagram showing an exemplary detailed structure of
the verticalsynahronizingsignalreproduction circuit3. In FIG.
i6, the vertical synchronizing signal reproduction circuit 3
includes flip-flops 10-to 13, each of which receives the
phase-delayed horizontal synchronizing signal 19, 21, 22, or 24
and the vertical synchronization separating signal 6 ; a NAND gate
15 which receives signals from the flip-flops 10 and 11; a NAND
gate 16 which receives signals from the flip-flops 12 and 13; a
set-reset flip-flop 17 in which a signal frofi the NAND gate 15
goes to the set and a signal from the NAND gate -16 to the reset;
a multiplexes 18 which receives a signal from the set-reset
flip-flop 17 as' a control signal and the phase-delayed horizontal
3
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Y 7
synchronizing signals 20 and 23, and outputs a signal 27 which
is either one of the horizontal synchronizing signals; and a
flip-flop 10 which receives the vertical synchronization
separating. signal 6 and the output signal 27 from the multiplexer
18, and outputs the vertical synchronizing.signal 8.
In FIG. 16, the flip-flop 10 plays a role as latch means
for latching a vertical synchronization separating signal, and
outputting a synchronizing signal having the phase relationship
with the horizontal synchronizing signal determined. The
.i0 multiplexer 18 plays a role. as signal selection means for
selecting, for output, a signal for latching the vertical
synchronization separating signal from among a plurality. of
phase-delayed signals. The flip-flops 10 to 13, the NAND gates
and 16, and the set-reset flip-flop 17 play a role as signal
15 selection control means for outputting a signal to control the
multiplexer 1.8 which phase-delayed signal is selected therein.
The operation of such structured vertical synchronizing signal
reproduction circuit 3 is described next below by referring to
FIGS. 16 and 17.
FIG. 17 is a time chart showing the operation of the vertical
synchronizing signal reproduction circuit 3 from time t4 to time
t5 in FIG. 15. In FIG. 1,7, a timing (denoted by time tA in the
drawing) which coincides with a threshold value between a high
.. level and a low level of the vertical synchronization separating
signal 6 is observed between timings for the phase-delayed
4
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,
s
synchronizing signals 19 and 21 to rise. In such case, as shown
in FIG. 17; the output signal from the HAND gate 15 changes in
level from high to low with the timing when the phase-delayed
horizontal synchronizing signal 21 rises. The signal i~s a set
incoming signal 25 which is inputted into the set terminal of the
set-reset flip-flop 17.
Further, in FIG. 17, the timing which coincides with the
threshold value between the high level and the low level of the
vertical synchronization separating signal 6 is not observed
between timings for the phase-delayed horizontal synchronizing
signals 22 and 24 to rise. Therefore, as shown in FTG. 17, an
output signal 26 from the NAND gate 16 remains in the high level.
The signal is a reset incoming signal 26 which is inputted into
the reset terminal of the set-reset flip-flop 17.
Once such set incoming signal 25 and reset incoming signal
26 are provided to the set-re et flip-flop 17, as shown in FIG.
17, . an output signal 33 from the set-reset flip-flop 17 is fixed
in the low level. The output signal 33 from the set-reset
flip-flop 17 is provided to a control terminal of the multiplexer
18.
When receiving a signal high' in level in the control
terminal, the multiplexer' 18 selects the phase-delayed
horizontal synchronizing.signal 20 for output. When a signal low
in level is inputted thereto, the multiplexer 18 selects the
phase-delayed horizontal synchronizing signal 23 for output.
5
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Accordingly, the multiplexer 18 having the signal low in level
provided to its control germinal selects and outputs the
phase-delayed horizontal synchronizing signal 23.
The phase-delayed horizontal synchronizing signal 23 can-
assuredly be latched with the verticalsynchronization separating
signal .6 with the timing Which coincides with the threshold value
between the high Level and low level thereof. This is because,
as described in the foregoing, the timing which coincides with
the threshold value between the high level and the low level of
the vertical synchronization separating signal 6 is observed
between the timings for the phase-delayed horizontal
synchronizing signals l9 and 21 to rise. Therefore, it is not
certain whether the phase-delayed horizontal synchronizing
signal 20 between the phase-delayed horizontal synchronizing
signals 19 and 21 is capable for latching. Accordingly, the
flip=flop 14 can assuredly latch the vertical synchronization
separating signal 6 with the help of the phase-delayed horizontal
synchronizing signal 23.
In the foregoing, by referring to FIG. 17, it has been .
exemplarily described the case where the timing which coincides
With the threshold value between the high level and the low level
of the -vertical synchronization separating signal 6 is observed
between the phase-delayed-ho-rizontal synchronizing signals 19 and
21. Herein, the timing which coincides with the threshold value
between the high level and the low level of the vertical
6
CA 02392386 2002-08-13
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''
synchronization separating signal 6 may be observed between the
timings for the phase-delayed horizontal synchronizing signals
22 and 24 to rise. In such case, the multiplexer 18 selects, for
output, not the phase-delayed horizontal synchronizing signal 23
but the phase-delayed horizontal synchronizing signal 20.
Accordingly, similar to the above-described case, the flip-flop
14 can assuredly latch .the vertical synchronization separating
signal 6.
In such manner, by receiving the phase-delayed horizontal
synchronizing signals l9 to 24 fxom the, phase delay part 2 as
signals for detecting the timing which coincides with the
threshold value between the high level and the low level of the
vertical synchronization separating signal 6, the vertical
synchronizing signal reproduction circuit 3 can determine the
phase relationship between the,vertical synchronizing signal and
the horizontal synchronization signals. As such, the vertical
synchronizing signal reproduction circuit 3 can assuredly latch
the vertical synchronization separating signal 6, and thus can
supply, to each digital signal processor circuit arranged in the
display, the vertical synchronizing signal 8 which has been
accurately reproduced.
According to the conventional synchronous processor
circuit structured as such, however,- a stabilized vertical
synchronizing signal cannot be assuredly obtained if,-as shown
in FIG. 15, the timings which coincide with the threshold value
7
CA 0239238 6 2002-08-13
7
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between the high level and the low level. of the .vertical
synchronization separating signal 6 separated and reproduced by
the hPF 1 approximately coincide with both pulse timings of the
phase-delayed horizontal synchronizing signals 20 and 23. This
is because the phase relationship between the vertical
synchronization separating signal 6 and the horizontal
synchronizing. signal is not determined.,
FIGS. 18 are diagrams schematically showing a
partially-enlarged waveform of the vertical synchronization
separating signal 6. A dotted line laterally drawn in the
drawings indicates. the threshold value between the high level and
the low level of the vertical synchronization separating signal
6. To be specific, the threshold value is used by the flip-flops
10 to 14 which receive the vertical synchronization separating
signal & to distinguish the level thereof between high and low.
FIG. 18(a) is the diagram schematically showing the
waveform at a front part of the vertical synchronization
separating signal 6 in the range between time t4 and time t5 in
FIG. 11. In the drawing; tA indicates a time when the vertical
synchronization separating signal 6 reaches the threshold value
as in FIG. 17. In the drawing, Ts indicates a period between time
t4 and time tA. FIG. 18 (b) is the diagram schematically showing
the waveform at a rear part of the vertical synchronization
separating signal & in the range between time t8 and time t9 in
FIG. 11. In the drawing, tB.indicates a time when the vertical
8
CA 02392386 2002-08-13
i
synchronization separating signal 6 reaches the threshold value.
In the drawing, Te indicates a period between time t8 and time
tB.
As shown in FI'G. 18, the waveform of the vertical
synchronization separating :signal 6 often differs in shape
between the front part and the rear part, and the timings tA and
tB which coincide with the threshold value between the high level
and the low level of the vertical synchronization separating
signal 6 often differ between the front part and the rear part
thereof. Therefore, at the rear part of the vertical
synchronization separating signal 6; unlike the above-described
case in FIG. 1?, the.timing which coincides with the threshold
value between the high level and the low level of the. vertical
synchronization separating signal 6 may be observed between the
timings for the phase-delayed horizontal synchronizing signals
22 and 24 to rise. If this is the case, the multiplexer 18 may
select, for output,. the phase-delayed horizontal synchronizing
signal 20, or. the phase-delayed horizontal synchronizing signal,
23. Consequently, the output signal 27 from the multiplexer 18
fails to be constant in horizontal synchronizing freguency.as
shown in FIG. 15. As. such, according to the conventional
structure, the phase relationship between the vertical
synchronization separating__signal 6 and the horizontal
synchronizing signal is not determined. Therefore, the vertical .
synchronization signal provided therefrom cannot be stabilized
9
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~j ~ )
,,
enough.
Further, in such case as shown in FIG. 15; as to the vertical
synchronizing signal provided by the vertical synchronizing
signal reproduction circuit 3,-a pulse width thereof does not
become integral multiple of that of the frequency of the
horizontal synchronizing signal. Consequently, the synchronous
processor circuit in the display becomes complicatedin structure,
thereby rendering the cost increased.
Especially, such phenomenon often occurs in a multiscan
monitor, which receives incoming signals varied in scanning
frequency from a video signal source. Generally, the LPF 1 is
fixed in cutoff frequency. Therefore, the cutoff frequency of
the LPF 1 maybe too heavy (too low) for the vertical synchronizing
signal component superimposed on the composite signal 5 depending
on its pulse width. If this is the case, the vertical
synchronization separating signal 6 provided by the LPF 1 may get
very blunt. As exemplarily shown in FIG. 18, the vertical
synchronization separating signal 6 provided by the LPF 1 shows
a gradual change from time t4 to time t5, or from time t4 and time
t5. As a result, as described in the foregoing, the timings which
coincide with the threshold value between the high level and the
low level of the vertical synchronization separating signal 6
approximately coincide with both pulse timings of the above-
described phase-delayed horizontal synchronizing signals 20 and
23, thereby causing such problem a-s above-described.
CA 02392386 2002-08-13
.. ~
Therefore, an object of the present invention is to provide
a synchronous processor circuit capable of improving a display's
synchronization stability by determining a phase relationship
between a vertical synchronizing signal and horizontal
synchronizing signals, and circuitry structure of which can be
simplified by setting a pulse width of the vertical synchronizing
signal to be the integral multiple of the frequency of the
horizontal synchronizing signal:
DISCLOSURE OF THE INVENTION
A first aspect of the:present invention is directed to a
synchronous processor circuit arranged in a display for
reproducing a synchronizing signal from a composite signal
provided by a video signal source for stabilizing synchronization
in the display, the circuit comprising:
a low pass filter-for outputting a vertical synchronization
separating signal by separating a vertical synchronizing signal
from the composite signal;
a frequency divider circuit for outputting a vertical phase
detection signal obtained by frequency-dividing a cycle of the
vertical synchronization separating signal into 1/n (where.n is
multiple of 2);
a plurality of phase delay circuits for outputting
phase-delayed signals each differently delayed in phase with
respect to a horizontal synchronizing signal included in the
11
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, ,
composite signal; and
a vertical synchronizing signal reproduction circuit for
outputting the synchronizing signal. having a phase relationship
with the horizontal synchronizing signal determined by receiving
5~ the vertical synchronization separating signal, the vertical
phase detection signal, and the plurality .of phase-delayed
signals .
As described above, in the first aspect of the present
invention, it becomes possible to determine the phase
relationship between.the vertical synchronizing signal and the
horizontal synchronizing signal. Accordingly, the stabilized
vertical synchronizing signal can be supplied to each circuit
arranged in the display.
According to a second aspect of the present invention; in
the first aspect of the present invention,
the frequency divider, circuit outputs the vertical phase
detection signal obtained by dividing the cycle of the vertical
synchronizing signal into l/2.
As described above, in the, second aspect of the present
invention, it becomes possible to swiftly respond to any minute
change in phase of the incoming composite signal by having the
1/2 frequency divider circuit provided. Accordingly, the
stabilized vertical synchronizing signal can be supplied to each
circuit arranged in the display.
According to a third aspect of the present invention, in
12
CA 02392386 2002-08-13
,~
the first aspect.of the present invention,
the vertical synchronizing signal reproduction circuit
comprises:
latch means for latching the vertical synchronization
separating signal, and outputting the synchronizing signal having
the phase relationship with the horizontal synchronizing signal
determined;
signal selection means for selecting a signal to be used
by the latch means to latch the vertical synchronization
separating signal from among the plurality of phase-delayed
signals for output to the latch means; and
signal selection control means for receiving the vertical
phase detectionsignaland the plurality of phase-delayedsignals,
and outputting, to the signal selection means, a signal for
15. controlling the signal selection control means which of the
phase-delayed signals is selected therein.
As described above, according to the third aspect of the
present invention, the phase relationship between the vertical
synchronizing signal and the horizontal synchronizing signal can
be determined with the help of a plurality of phase-delayed
signals inputted as signals for detecting a timing which coincides
with the threshold value between the high level and the low level
of the vertical synchronization separating signal.
According to a fourth aspect of the present invention, in
the first aspect of the present invention,
13
- CA 02392386 2002-08-13
. >~ ~ . ...,
thesynchronousprocessor circuit further comprises a pulse
width reproduction circuit for receiving the signal from the
vertical synchronizing signal reproduction circuit, and
reproducing the synchronizing signal having a predetermined pulse
width.
As described above, according to the fourth aspect of the
present invention; as long as the reference timing is stabilized,
regardless of the other timing's stability, the stabilized
vertical synchronizing signal can be outputted with the counting
operation carried out according to the set pulse width.
According to a fifth aspect.of the present invention, in
the fourth aspect of the present invention,
the pulse width reproduction circuit comprises:
a counter, in which a counter value is set to 0 when the
signalprovided by the vertical synchronizingsignal reproduction
circuit rises, for incrementing the counter value according to
an incoming. clock signal; and
a comparator for con3paring pulse width setting data
provided to set the pulse width and tha counter value, and
outputting a signal. who se pulse width is based on the pulse width
setting data.
As described above, in the 'fifth aspect of the present
invention, the pulse width reproduction circuit can,output~the
stabilized signal according to the pulse width which is previously
set or calculated by operation.
14
CA 0239238 6 2002-08-13
v _.,
A sixth aspect of the present invention is directed to a
synchronous processor circuit arranged in a display for
reproducing a synchronizing signal from a composite signal
provided by a video signal source for stabilizing synchronization
in the display, the circuit comprising:
a low pass filter for outputting a vertical synchronization
separating signal by separating a vertical synchronizing signal
from the composite signal;
a plurality of phase delay circuits for outputting
phase=delayed signals each differently delayed in phase with
respect to a horizontal synchronizing signal included in the
composite signal; and
a vertical synchronizing signal reproduction circuit for
outputting a signal having the phase relationship with the
horizontal synchronizing signal determined by receiving the
vertical synchronization separating signal, and the plurality of
phase-delayed signals; and
a flip-flop for latching the signal provided by the vertical
synchronizing signal reproduction circuit, and outputting the
synchronizing signal whose period is an integral multiple of the
horizontal synchronizing signal:
As described above, in the sixth aspect of the present
invention, it is possible to obtain the vertical synchronizing
signal having the pulse width of the integral multiple of that
of, the frequency of the horizontal 'synchronizing signal with a
CA 02392386 2002-08-13
'~ -3 _.
r
structurally simplified circuit. Accordingly, the synchronous
processor circuit in the display can be simplified in structure.
According to a seventh aspect of the present invention, in
the sixth aspect of the present invention,
the vertical synchronizing signal reproduction circuit
comprises:
latch means for;latching, and outputting the synchronizing
signal having the phase relationship with the horizontal
synchronizing signal determined;
10. signal selection means for selecting a signal to be used
by the latch means to latch the vertical synchronization
separating signal from among the plurality of phase-delayed
signals for output to the latch means; and ..
signal~selection control means for receiving the vertical
phase detectionsignaland the plurality of phase-delayedsignals,
and outputting, to the signal selection means, a signal. for
controlling the signal selection control means which of the
phase-delayed signals is selected therein.
As described above, in the seventh aspect of the present
invention, the phase relationship between the .vertical
synchronizing signal and the horizontal synchronizing signal can
be determined with the help of a plurality of phase-delayed
signals inputted as signals for detecting a timing which coincides
with the threshold value between the high level and the low level
of the vertical synchronization separating signal.
16
CA 02392386 2002-08-13
. . .1. ) . ~ .?
a 1
According to an eighth aspect of the present invention, in
the sixth aspect of the present invention,
the synchronousprocessor circuit further comprises a pulse
width reproduction circuit for receiving the signal from the
flip-flop, and reproducing the synchronizing signal having a
predetermined pulse width.
As described above, in the eighth aspect of. the present
invention, as long as the reference timing is stabilized,
regardless of the other timing's stability, the stabilized
vertical synchronizing signal can be outputted with the counting
operation carried out according to the set pulse width. Therefore,
with a structurally simplified circuit, even with respect to the
interlace signal, the vertical synchronizing signal can have the
pulse width of the integral multiple of the frequency of the
horizontal synchronizingsignal. Therefore, it becomes possible
to simplify the synchronous processor circuit in the display.
According to a ninth aspect of the present invention, in
the eighth aspect of the present invention,
the, pulse width reproduction circuit comprises:
a counter, in which a counter value is set to 0 when the
signal provided by the flip-flop rises, for incrementing the
counter value according to an incoming clock signal; and
a. comparator f-or , comparing pulse s~ridth setting data
provided to set the pulse width and the counter value, and
outputting a signal whose pulse width is based on the pulse width
17
CA 02392386 2002-08-13
_~ )
setting data. w
As described above, iri the ninth aspect of the present
invention, the pulse width reproduction circuit can output the
stabilized signal according to the pulse width which is previously
set or calculated by operation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the structure of a
synchronous processor circuit in a first embodiment of the present
invention.
FIG. 2 is a time chart which explains the operation of a
vertical synchronizing signal reproduction circuit in the first
embodiment of the piesent invention.
FIG. 3 is a block diagram showing the structure of the
vertical synchronizing signal reproduction circuit in the first
embodiment of the present invention:
FIG. 4 is a time chart which explains the operation of the
synchronous processor circuit in the first embodiment of the
present invention.
FIG. 5 is a block' diagram showing the structure of a
synchronous processor circuit in a second embodiment of the
present invention.
FIG. 6 is a time chart which explains the operation of the
synchronous processor circuit in the second embodiment of the
present invention:
18
CA 02392386 2002-08-13
? .. y ___: ~ )
FIG. 7 is a block diagram showing an exemplary structure
of a pulse width reproduction circuit in the second embodiment
of the present invention.
FIG. 8 is a time chart which explains the operation of the
- pulse width reproduction circuit in the second embodiment of the
present invention.
FIG. 9 is a block diagram showing an exempJ_ary structure
of the pulse width reproduction: circuit in the second embodiment
of the present~invention.
FIG. 10 is a time chart which explains the operation of the
pulse width reproduction circuit in FIG. 9.
FIG. 11 is' a block diagram showing the structure' of a.
synchronous processor circuit in a third embodiment of the present
invention.
FIG. 12 is a time chart which explains the operation of the
synchronous processor circuit in the third embodiment of the
present invention
FIG. 13 is a block diagram showing the structure of a
synchronous processor circuit im a fourth embodiment of the
20' present invention.
FIG. 14 is a block diagram showing the:structure of a
conventional synchronous: processor circuit.
FIG . 15 is a time -chart vxhich explains the operation of the
conventional synchronous processor circuit.
FIG. 16 is a block diagramwshowing the structure of a
19
CA 02392386 2002-08-13
conventional vertical synchronizing signal reproduction
circuit.
FIG. 17 is a time chart which explains the operation of the
conventional vertical synchronizing signal reproduction
circuit.
FIGS. l8 are diagrams schematically showing a partial-
enlarged waveform of a vertical synchronizationseparatingsignal
6.
BEST MODE FOR CARRYTNG OUT THE LNVENTLON
(First Embodiment)
FIG. 1 is a block diagram showing the structure of a
synchronous processor circuit .according to a first embodiment of
the present invention. In FIG: 1, the synchronous processor
circuit includes the LPF l to which the composite signal 5 is
externally provided, and the vertical synchronization separating
signal 6 is separated therefrom for output; a 1/2 frequency
divider circuit 4 for receiving the vertical synchronization
separating signal 6 and subjecting the signal to 1/2 frequency
division to output a vertical phase detection signal 9; the phase
delay part 2 for receiving the composite signal 5 and outputting
the plurality of horizontal synchronizing signals 19 to 24 each
differently delayed in phase; and'the vertical synchronizing
signal reproduction circuit 3.for receiving the plurality of
phase-delayed horizontal synchronizing signals 19 to 24, the
CA 02392386 2002-08-13
, .. ) ..) ,) .t
vertical synchronization separating signal 6, and the vertical
phase detection signal 9, and outputting the vertical
synchroni zing signal $. The phase delay part 2.includes the fixst
to sixth phase delay circuits 201 to 206. The operation of the
synchronous processor circuit is described next below.
FIG. 2 is a time chart which explains the operation of they
synchronous processor circuit according to the first embodiment
of the present invention. In the upper part of the drawing, tI
to t19 indicate time. at a regular interval. To be specific, time
t3 to time t19 indicate timings for a horizontal synchronizing
signal to rise.
In FIG. 2; similarly in FIG. 15, the horizontal
synchronizing signal is a pulse signal which rises every. time at
times t1 to t19. The vertical synchronizing signal is a pulse
signal which rises at times t4 and t13 and falls at times t8 and
t16.
As shown in FIG. 2,. the composite signal 5 externally
provided'to a display is a synchronizing signal onto which. the
vertical synchronizing si.gnaland the horizontal synchronizing
signal are superimposed. Once provided to the LPF 1, such
composite signal 5 is cut off with any horizontal frequency
component high in frequency. Therefore; the LPF l is capable of
reproducing the vertical synchronization separatingsignal6with
any horizontal synchronizing frequency component subtracted from
the composite signal 5. The vertical synchronization separating
21
CA 02392386 2002-08-13
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v
signal 6 then is provided to the 1/2 frequency divider circuit
4 to be divided into 1/2, and is outputted as the vertical phase
detection signal 9.
The composite signal 5 is also provided to each of the first
to sixth phase delay circuits 2'01 to 206 in the phase delay part
2. Those inputted composite signals 5 each generate a pulse
corresponding to a period of the horizontal synchronizing signal .
By using the pulses corresponding to the period of the horizontal
synchronizing signal, the first to sixth phase delay circuits 201
to 206 output the horizontal synchronizing signals 19 to 24 each
varied in phase with a predetermined interval, respectively.
The horizontalsynchronizing signalsl9to24phase-delayed
as such, the vertical synchronization separating signal 6, and
the vertical phase detection signal 9 are all provided to the
vertical synchronizing signal reproduction circuit 3. The
ver.tical~synchronizing signal reproduction circuit 3 outputs the.
vertical synchronizing signal 8 having the phase relationship
with the horizontal synchronizing signal determined.
Next, the vertical synchronizing signal reproduction
circuit 3 is described for its structure and operation in detail.
FIG. 3 is. a diagram showing an exemplary detailed structure of
the vertical synchronizing signal reproduction circuit 3 of the
first embodiment. In FIG: 3, the vertical synchronizing signal
reproduction circuit 3 has almost the same structure as the
vertical synchronizing signal reproduction circuit 3 in FIG. 16.
22
CA 02392386 2002-08-13
. ,~._~
Accordingly, also for the vertical synchronizing signal
reproduction circuit 3 in FIG: 3; the flip-flop 10 plays a role
as latch means for latching a vertical synchronization separating
signal, and outputting a synchronizing signal having the phase
relationship with a horizontal synchronizing signal determined.
The multiplexes 18 plays a role as signal selection means for
selecting, for output, a signal for latching the vertical
synchronization separating signal from among a plurality of
phase-delayed signals. The; flip-flops 10 to 13, the NAND gates
15 and 16, and the set-reset flip-flop 17 play a .role as signal
selection control means fox outputting.a signal to control the
multiplexes 18 which phase-delayed signal is selected therein.
Note herein that,. the vertical synchronizingv signal
reproduction circuit 3 in FIG: 3 is different from the one in FTG.
16 in that the flip-flops 10 to 13 are not provided with the
vertical synchronization eparating signal.6 but the vertical
phase detection signal 9.
The operation of such structured vertical synchronizing
signal reproduction circuit 3 is described by referring to FIG.
4. The operation of any component in FIG. 3 identica l to that
in the vertical synchronizing signal reproduction circuit 3 is
not described again.
In FIG. 4, the composite signal 5 onto which the horizontal
synchronizing signal and the vertical synchronizing signal are
superimposed is provided to the ZPF 1. The LPF 1 outputs the
23
CA 02392386 2002-08-13
~j ~j
.~
vertical synchronization separating signal 6,as shown in FIG. 4
through separation. Thzs vertical synchronization separating
signal 6 is provided to the 1%2 frequency divider circuit 4. The
1/2 frequency divider circuit 4 outputs the vertical phase
detection signal 9 whose level shows change only with either one
of the timings which coincide with the threshold value between
the high level and the low level of the vertical synchronization
separating signal 6 as shown in FIG. 4.
The vertical phase detection signal 9 is provided to th.e
flip-flops 10 to 13. arranged. in the vertical synchronizing signal
reproduction circuit 3 in FIG. 3. As shown in FIG. 1$, as above
described., the timings which ..coincide with the threshold value
between the high level and ;the low level of the vertical
synchronization separating signal 6 may differ between.at the
front part and the rear part thereof .- With the above-described
structure, however,.the vertical phase detection signal 9 only
shows change in level with either timing which coincides with the
fxont part or the rear part of the vertical synchronization
separating signal 6. Accordingly, as shown in FIG. 2, the output
signal 27 from the multiplexes l8 is fixed to either the
phase-delayed horizontal synchronizing signal 20 or 23, thereby
becoming always constant.
In order to achieve such structure in which the output
signal 27 from the rnultiplexer 18 is fixed to either the
phase-delayed horizontal ynchronizing signal 20 or 23 to be
24
CA 02392386 2002-08-13
, )
always constant, for example, either the set incoming signal or
reset incoming signal to the flip-flop l7 in FIG. 3 may be put
invalid. Although being fired to the ph.as~-delayed horizontal
synchronizing signal ~23 in FIG. 2, the output signal 27 from the
multiplexer 18 is surely fixable to the phase-delayed horizontal
synchronizing signal 20 depending on the-waveform or the threshold
value of the vertical synchronization separating signal 6.
Therefore, setting the set incoming signal or the reset incoming
signal to the flip-flop l7 in FTG. 17 invalid is not enough to
output the vertical~synchrori~izing_signal 8 whose phase can be
determined with respect to the horizontal synchronizing signal.:
As is known from the above, according to the structure of
the synchronous processor circuit of this embodiment, the phase
of the vertical synchronizing signal can be determined by the
horizontal synchronizing signals; whereby the stabilized
vertical synchronizing signal can be supplied to each circuit
arranged in the display.
Herein, in this embodiment, the 1/2 frequency divider
circuit is included in the structure: to generate the vertical
phase detection signal which varies in level with either one of
the timings which coincide with the threshold value between the
high level and the low level of the vertical synchronization
separating signal 6. However, instead of the 1/2 frequency
divider circuit, a 1/n (where nis multiple of-2) frequency divider
circuit.such as 1/4 frequency divider circuit leads to similar
CA 02392386 2002-08-13
n f
effects. Therefore, the frequency divider circuit in this
embodiment is not limited to the 1/2 ~frequer~cy divider circuit.
Note herein that, if n is set too large, it becomes difficult to
respond to any minute change, in phase of the composite signal 5.
Accordingly, needless to say:, n has its own limitation in value.
(Second Embodiment)
FIG. 5 is a .block diagram showing the structure of a
synchronous processor circuit according to a second embodiment
of the present invention.. The synchronous processor circuit i,n
FIG. 5 is structurally almost the same as the above-described
synchronous processor circuit in FIG. 1. Note herein that, only
difference between the synchronous processor circuit in FIG. 5
and the one im FIG. 1 is that a pulse width reproduction circuit
28 which receives the output signal from the vertical
synchronizing reproduction circuit 3 is additionally provided.
Therefore, any identical constituent is under the same reference
numeral, and is not described again:
Herein, the pulse width reproduction circuit 28 newly
provided in this embodiment is described. In the synchronous
. 20 processor circuit according tothe first embodiment of the~present
invention, the vertical synchronizing signal reproduction
circuit 3 uses the vertical phase detection signal 9 to obtain
the vertical synchronizing signal 8- with reference only to one
timing coinciding with the hreshold value between the high level:
and the low level of the vertical synchronization separating
26
CA 02392386 2002-08-13
. ...~
s
signal 6. In FIG. 2, the timing referred to for obtaining the
vertical synchronizing signal 8 is the one coinciding with the
threshold value at the front part of the vertical synchronization
separating signal 6.
With such structure, if the output signal 27 from the
multiplexer 18 is used to hatch not with the referred timing but
with the timing on the other side (at the rear part of the vertical
synchronizing separating signal 6 in FIG.. 2) which coincides with
the threshold value between' the high level and the low level, a
latch miss may be occurred. FIG. 6 is a timing chart showing a
case where such~latch miss is occurred.
As shown in FIG. 6, in the synchronous processor circuit
of the first embodiment, latching can be assuredly carried out
at the front part of the vertical synchronization separating
signal 6 but is. not assured for the rear part thereof . Buch latch
miss may degrade the display's synchronization stability.
Therefore; the synchronous processor circuit of this
embodiment, as shown in FIG'. 5, is so structured that the output
from the vertical synchronizing signal reproduction circuit 3
goes to the pulse width reproduction Circuit 28. This pulse width'
reproduction circuit 28 is structured by such counter circuit as
will be later described: With this structure., as long as the
reference~timing is stabi~.ized, regardless of the timing
stability on the other side; the pulse width reproduction circuit
28 can output the stabilized vertical synchronizing signal 8 by
27
CA 02392386 2002-08-13
i
a
taking place counting operation according to the set pulse width.
Such pulse width reproduction circuit 28 is structurally
described in detail with two examples next below. In a first
example, the pulse width reproduction circuit 28 is structured
as shown in FIG. 7. In FIG. 7, the pulse width reproduction
circuit 28 includes a differentiating circuit 501 for receiving
a reference pulse; a first counter 502 for receiving an output
signal 51 from the differentiating circuit 501; and a comparator
503 for receiving an output ignal 52 from the first counter 502
and pulse width setting data.
The first counter 502 resets its output signal to 0 when
the signal 51 provided to a reset erminal, which is denoted by
R in the drawing, is in the high level, and then outputs .a value
obtained by incrementing from 0 on the basis of an incoming clock.
The comparator 503 compares in value between a value A provided
by the first counter 502 and the pulse width setting data B: After
the comparison, if A is smaller than B, the comparator 503 outputs
a signal high .in level. On the other hand, if A is B or larger, .
the comparator 503 outputs a 'signal low in level.
~ FIG. 8 shows a iming chart. which explains the operation
of such pulse width reproduction circuit 28. In FIG. 8, the pulse
width data is fixed to 2. Once the reference pulse is inputted,
the differentiating circwit 501 outputs the signal 51 obtained
by differentiating the inputted signal. After the signal 51 is
inputted, the first counter 502 resets its counter value to 0,
'2 8
CA 02392386 2002-08-13
.:
,1 ~
and then outputs the counter vale obtained by incrementing from
0 in sync with an incoming clock. The comparator 503 monitors
the value provided by the first counter 502, and keeps outputting
a signal high in level until the value reaches 2 which is the pulse
width setting data. When the value.provided by the first counter
502 reached 2, the comparator 503 outputs a signal low in level.
Thereafter, until the value provided from the first counter 502
returns to 0, the comparator 5Q3 keeps. outputting the signal low
in level. By repeating such operation,~the.pulse width
reproduction circuit 28 becomes capable of outputting 'a
stabilized signal according to the set pulse width.
In a second example, the pulse width reproduction circuit
28 is structured as shown in FIG. 9 . In FLG. 9 , the pulse width
reproduction circuit 28 includes the differentiating circuit 501
for receiving the reference pulse; the first counter 502 for
receiving an output signal 6l from the differentiating circuit
501; a second counter 504 for receiving the output signal 61 from
the differentiating circui 501 and the reference pulse; an
operation circuit 505 for receiving an output signal from the
second counter 504 and outputting the pulse width setting data;
and the comparator 503 for receiving an output signal 62 from the
first counter 502 and the pulse width setting data.
The pulse width reproductian circuit 28 in FIG. 9 is,
compared with the one in FIG . '7 ; additionally provided with the
second counter 504 and the operation circuit 505 to generate the
29
CA 02392386 2002-08-13
~~
s
pulse width setting data. Since he differentiating circuit 501,
the first counter 502 , and the comparator 503 in FIG . 9 are
identical to those in'FIG. 7, the same reference numerals are
provided, and the structureand the operation thereof are not
described again.
In FIG . 9 , if the signal 61 provided to the reset terminal ;
which is denoted by R in the drawing, is high in level, the second
counter 504 resets its output signal to 0. The second counter
504 outputs a counter value counted up from 0 on the basis of the
incoming clock when the reference pulse provided to its enable
teiminal denoted by E in the drawing.is high in level. If the
reference pulse. is low in level, the second counter 504 outputs
the current counter value as it is without counting up.
FIG. 10 shows a timing chart which explains the operation
of such second counter 504. In FIG. 10, the differentiating
circuit 501 outputs the signal 61 obtained by differentiating the
inputted reference pulse. Once the signal 61 is provided, the
second counter 502 resets its counter value to 0. At this time;
since the 'reference pulse provided to the enable terminal of the
second counter 502 is high in level, the second counter 502 outputs
an signal 63 indicating the counter value incremented from O.~in
sync with the incoming clock.' Thereafter, when the reference
pulse provided to the enable terminal becomes low in level , the
second counter 502 outputs'the signal 63 without changing its
current counter value (2 in FIG. 10).
CA 02392386 2002-08-13
i
t
The operatiowcircuit 505 performs operation with respect
to the maximum value or most-frequent value: of the counter value
inputted from the second counter' 504, and outputsa value obtained
by the operation as the pulse width setting data. In FIG. 10,
the maximum value of the counter value is 2 as is the most-frequent
value. Accordingly, the operation circuit 505 sets the pulse
width setting data to 2 for output . The comparator~ 503 operates
similarly to the case in FIG. 7. By repeating such operation',
the pulse width reproduction, circuit 28 can output the stabilized
signal according to the pulse width calculated based on the
reference pulse.
Herein, the pulse width reproduction circuit 28 may take
any . structure as long as the pulse width .to be outputted is
changeable- by arbitrarily setting the pulse width setting data,
and thus above structure is not restrictive . Although the clock
used in this pulse width reproduction circuit 28 is the horizontal
synchronizing signal (or composite signal:) , it is not restrictive
and the clock may be the one which is generated from the horizontal
synchronizing signal in a PLL circuit.
As is known from the above, according to the synchronous
processor circuit of the second, embodiment which is additionally
provided with the pulse widthre;production circuit 28 compared
with the synchronous processor circuit of the first embodiment;
the vertical synchronizing signal to be, outputted therefrom can
be more stabilized than the one from the synchronous processor
31
CA 02392386 2002-08-13
. 1 ..~~
a t
circuit of the first embodiment.
(Third Embodiment)
FIG. I1 is a block diagram showing the- structure of a
synchronous processor circuit according to a third embodiment of
the present invention. The synchronous processor circuit in FIG.
11 is structurally almost the same as the above-described w
synchronous processor circuit in FIG: 1. Note herein that, the
synchronous processor circuit in FIG. 11 is not provided with the
1/2 frequency divider c-ircuit.but is additionally provided with
a flip-flop 29 for receiving the output signal from the vertical
synchronizing signal reproduction circuit 3 and the phase-delayed
horizontal synchronizing signal 20. This is the only difference
between the synchronous processor circuit in FIG: 11 ,and the
above-described one in FIG. 1. Thus, any identical constituent
is under the same reference numeral, and is not described again.
Next ; the f 1 ip-f lop 2 9 newly provided. in this embodiment
is described. In the synchronous processor circuit of this
embodiment, a signal 30 provided by the vertical synchronizing
signal.reproduction circuit 3 may not have a pulse width of the
integral- multiple of the frequency of the horizontal
synchronizing signal as is described next below. Therefore, the
synchronous processor circuit of this embodiment is additionally
provided with the flip-flop 29, and is so.structured that the
signal 30 provided by the vertical synchronizing signal
reproduction circuit 3 goes to a data terminal of the flip-flop
32
CA 02392386 2002-08-13
r ,
29. Further, the synchronous processor circuit is so structured
that the phase-delayed horizontal synchronizing signal 20
provided to either of multiplexes 18 arranged in the vertical
synchronizing signal reproduction circuit 3 goes to a clock
terminal of the flip-flop 29. With such structured synchronous
processor circuit, the vertical synchronizing signal 8 can be a
signal whose pulse width i the integral multiple of that of the
frequency of the horizontal synchronizing signal.
FIG. 12 is~ a timing chart showing the case that the pulse
width of the signal 30 provided by the vertical synchronizing
signal reproduction circuit 3 does not become the integral
multiple of that of the frequency of the horizontal synchronizing
signal. With reference to FIG: 12, it is now described why the
pulse width of the output signal from the flip-flop 29, i.e. , the
vertical synchronizing signal 8 becomes the integral multiple of
that of the frequency of the horizontal synchronizing signal.
In FIG. 12, the signal 30 provided by the vertical
synchronizing signal reproduction circuit 3 does not become
constant in horizontal synchronization frequency a.s described by
referring to FIG. 15. In FIG. 12; the phase-delayed horizontal
synchronizing signals 20 and 23 presumably show a phase shift of
0.5H therebetween. If so, the signal 30 outputted from the
vertical synchronizing signal reproduction circuit 3 has the
pulse width of 3.5H. Herein, the flip-flop 29 has already
received the phase-delayed horizontal synchronizing signal 20 in
33
CA 02392386 2002-08-13
1 T
,
the clock terminal: Accordingly, the vertical synchronizing
signal 8 is outputted from the flip-flop 29 with the same timing
asthe phase-delayed horizontalsynchronizingsigna120. Assuch;
. the pulse width of the vertical synchronizing signal 8 outputted
from the flip-flop 29 becomes the integral multiple of the pulse
width of the phase-delayed horizontal synchronizing signal 20.
In FIG. 12 , the pulse width of the vertical synchronizing signal
8 is 4H.
In this embodiment; the clock for the~flip-flop 29 where
the pulse width reproduction is carried out is the phase-delayed
horizontal synchronizing signal 20.. However, other phase-
delayed horizontal synchronizing signals 19. and 21 to 24 lead to
the similar effects. By taking this into consideration, the clock
for the flip-flop 29 where pulse width reproduction is carried
out may be a signal whose frequency is equal to that of the
horizontal synchronizing signal, and is not restrictive to the
phase-delayed horizontal synchronizing.signal 20.
With such. structured synchronous processor circuit
according to the third. embodiFnent of the present invention, the
vertical synchronizing signal outputted therefrom can have the
pulse width of the integral multiple of that of the frequency of
the horizontal synchronizing ignal with a simplified circuit,
thereby rendering the synchronous processor circuit in the
display simplified.
(Fourth Embodimerit)~
34
CA 02392386 2002-08-13
j
f
FIG. 13 is a block diagram showing the structure of a
synchronous processor circuit~according to a fourth embodiment
of the present invention: The synchronous processor circuit in
FIG. 13 is structurally almost he same as the above-described
synchronous processor circuit in FIG. 11. The only difference
between the synchronous processor circuit in FIG. 13 and the one
in FIG. 11 is that a pulse width reproduction circuit 32 for
receiving the output signal from the flip-flop 29 is additionally
provided. Therefore, any identical constituent is under the same
reference numeral, and-is not described again.
Next, the reason why the pulse width reproduction circuit
32 is provided to the synchronous processor circuit of this
embodiment is described. Hexein, it is assumed .that the' display
is applicable to interlace, and an interlace signal is provided
to the synchronous processor circuit. In such case; the clock
provided to the f3ip-flop 29: is in a 1/2 period, that is, a pulse
signal of O.SH. Accordingly, the pulse width of the vertical
synchronizing signal provided by the flip--flop 29 does not become
the integral multiple of tha of the frequency of the horizontal
synchronizing signal.
In this respect, in order to have the display applicable
to interlace, it is conventionally known that a double-speed
horizontal synchronizingwsignal generation circuit in which the
frequency of the horizontal synchronizing signal is doubly
multiplied so as to stabilize the phase relationship between the
CA 02392386 2002-08-13
vertical synchronizing signal and the horizontal synchronizing
signals : However, even if the interlace sigwal is handled in such
conventional structure, the;period of the clock to be provided
to the flip-flop 29 remains 1/2-of the cycle of the horizontal
synchronizing ,signal. Consequently, the pulse width of the
vertical synchronizing signal from the flip-flop 29 does not
become the integral multiple of the frequency of the horizontal
synchronizing signal.
Therefore, as shown in FIG. 13; the synchronous processor
circuit of this embodiment i so structured that the output from
the flip-flop 29 goes to the pulse w'idth.reproduction circuit 32.
InyFIG. 13, by arbitrarily setting the pulse width setting data,
the pulse width reproduction circuit 32 can set the pulse width
to be outputted to 'an even mul iple - of the clock to be provided
to the flip-flop 29 . In such. manner, it becomes possible to always
set the pulse width of the vertical synchronizing signal to be
the integral multiple of that of the frequency of the horizontal
synchronizing signal while retaining the. phase relationship
between the horizontal synchronizing signals and the vertical
synchronizing signal.
The structure of thepulse width reproduction circuit 28
is already described in detail by referring to FIGS . 7 and 9 . As
already described, as long -as the pulse width to be outputted is
changeable by arbitrarily setting the pulse width setting data,
the pulse width reproduction circuit 28 may take any structure
36
CA 02392386 2002-08-13
y , ~
With such structured synchronous processor circuit of this
embodiment, even with respect also to the interlace signal, the
VertlCal synchronizing signal can have.the pulse width of the
integral multiple of the frequency of the horizontal
synchronizing signal with a simplified circuit: Therefore, it
becomes possible to simplify the synchronous processor circuit
in the display.
Lastly, those above-described synchronous processor
circuits of the first to fourth embodiments_are arranged in a
display, and so structured as to reproduce a synchronizing signal
from a composite signal provided by a video signal source for the
display's synchronization stability. Such structure, however,
is made for clarity of description, and thus the synchronous
processor circuit is not restricted to the case that the composite
1S signal is provided from the video signal source. As an example,
the synchronous processor circuit may be used for a case where
a polarized synchronizing signal is provided in combination with
an amplifier where voltage is pumped up.
INDUSTRIAL APPLICABILITY
With the present invention, a display's synchronization
stability can be improved by determining the phase relationship
between a vertical synchronizing signal and horizontal
synchronizing signals, and a synchronous processor circuit
arranged in the display can be simplified by setting a pulse width
CA 02392386 2002-08-13
f
"~
y
of the vertical synchronizing signal to be the integral multiple
of that of the frequency of the horizontal synchronizing signal.
3g
