METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS

PROCEDE ET APPAREIL RELATIFS A LA SYNCHRONISATION D'ACCES A DES RANGEES ET A DES COLONNES

English Abstract

A circuit for synchronizing row and column access operations in a
semiconductor memory having an array of bit lines pairs, word lines, memory
cells, sense amplifiers, and a sense amplifier power supply circuit for
powering the sense amplifiers, the circuit comprising, a first delay circuit
for delaying a word line timing pulse by a first predetermined period, a first
logic circuit for logically combining the word line timing pulse and the
delayed word line timing pulse to produce a sense amplifier enable signal, for
enabling a sense amplifier power supply circuit, a second delay circuit for
delaying the word line timing pulse by a second predetermined period, and a
second logic circuit for logically combining the word line timing pulse and
the second delayed word line timing pulse to produce a column select enable
signal, for enabling selected ones of a plurality of column access devices
wherein the second predetermined time period is selected so that ones of a
plurality of column access devices are activated after the sense amplifier
power supply circuit is enabled.

French Abstract

Cette invention a trait à un circuit permettant de synchroniser des accès à des rangées et à des colonnes dans une mémoire à semi-conducteurs possédant un réseau de paires de lignes de bits, des lignes de mots, des cellules de mémoire, des amplificateurs de détection et un circuit d'alimentation d'amplificateur de détection les alimentant. Le circuit, qui comporte un premier circuit de retard destiné à retarder une impulsion de synchronisation de ligne de mots pendant une première période prédéterminée, un premier circuit logique combinant logiquement l'impulsion de synchronisation de ligne de mots et l'impulsion de synchronisation de ligne de mots retardée afin de produire un signal de validation d'amplificateur de détection afin de mettre en service le circuit d'alimentation d'amplificateur de détection, comporte également un second circuit de retard destiné à retarder une impulsion de synchronisation de ligne de mots pendant une seconde période prédéterminée, un second circuit logique combinant logiquement l'impulsion de synchronisation de ligne de mots et la seconde impulsion de synchronisation de ligne de mots retardée afin de produire un signal de validation de sélection de colonne et ce, pour mettre en service les dispositifs d'accès aux colonnes sélectionnées. La seconde période de temps prédéterminée est sélectionnée de telle sorte que les dispositifs d'accès aux colonnes soient activés après la validation du circuit d'alimentation de l'amplificateur de détection.

Claims

CLAIMS:
1. A circuit for synchronizing row and column access operations in a
semiconductor
memory having an array of bit lines pairs, word lines, memory cells, sense
amplifiers, and a
sense amplifier power supply circuit for powering said sense amplifiers, said
circuit comprising:
(a) a first delay circuit for delaying a word line timing pulse by a first
predetermined
period;
(b) a first logic circuit for logically combining said word line timing
pulse and said
delayed word line timing pulse to produce a sense amplifier enable signal, for
enabling a sense
amplifier power supply circuit;
(c) a second delay circuit for delaying said word line timing pulse by a
second
predetermined period; and
(d) a second logic circuit for logically combining said word line timing
pulse and said
second delayed word line timing pulse to produce a column select enable
signal, for enabling
selected ones of a plurality of column access devices wherein said second
predetermined time
period is selected so that ones of a plurality of column access devices are
activated after said
sense amplifier power supply circuit is enabled.
2. The circuit as defined in claim 1, wherein said first delay circuit is a
first delay element.
3. The circuit as defined in claim 1, wherein said second delay circuit is
a second delay
element.
4. The circuit as defined in claim 3, wherein said second delay element is
coupled with said
word line timing pulse via said first delay element.
5. The circuit as defined in claim 4, wherein said circuit further
comprises a plurality of
logic circuits for logically combining said column select enable signal with a
plurality of column
address signals for enabling said selected ones of a plurality of column
access devices.
6. The circuit as defined in claim 3, wherein said second predetermined
time is longer than
said first predetermined time.
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7. The circuit as defined in claim 6, wherein said circuit further
comprises a third delay
element for delaying said word line timing pulse before said word line timing
pulse is input to
said first logic circuit.
8. The circuit as defined in claim 6, wherein said circuit further
comprises a third delay
element for delaying said word line timing pulse before said word line timing
pulse is input to
said second logic circuit.
9. The circuit as defined in claim 2, wherein said second delay circuit is
a comparator
having a first input coupled to a power signal of said sense amplifier power
supply circuit and a
second input coupled to a predetermined threshold voltage, said comparator
having an output
that is asserted depending on a comparison between said first and second
inputs.
10. The circuit as defined in claim 9, wherein said first input is coupled
to a p-channel power
signal of said sense amplifier power supply circuit and said output of said
comparator is asserted
if said p-channel power signal is greater than said threshold.
11. The circuit as defined in claim 10, wherein a third delay circuit is
coupled between said
output of said comparator and said second logic circuit.
12. The circuit as denied in claim 9, wherein said first input is coupled
to an n-channel
power signal of said sense amplifier power supply circuit and said output of
said comparator is
asserted if said n-channel power signal is less than said threshold.
13. The circuit as defined in claim 12, wherein a third delay circuit is
coupled between said
output of said comparator and said second logic circuit.
14. A method for synchronizing row and column access operations in a
semiconductor
memory having an array of bit lines pairs, word lines, memory cells, sense
amplifiers, and a
sense amplifier power supply circuit for powering said sense amplifiers, said
method comprising
the steps of:
(a) generating a word line timing pulse for activating of at least one of
said word
lines;
(b) delaying said word line timing pulse by a first predetermined time;
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(c) logically combining said word line timing pulse and said first delayed
word line
timing pulse for providing a sense amplifier enable signal, said sense enable
signal for enabling
said sense amplifier power supply circuit;
(d) delaying said word line timing pulse by a second predetermined time;
and
(e) logically combining said word line timing pulse and said second delayed
word
line timing pulse for providing a column select enable signal, said column
select enable signal
for enabling selected ones of a plurality of column access devices wherein
said selected ones of a
plurality of column access devices are activated a predetermined time period
after said sense
amplifier power supply circuit is enabled.
15. The method as defined in claim 14, wherein said column select enable
signal is logically
combined with a plurality of column address signals for enabling said selected
ones of a plurality
of column access devices.
16. The method as defined in claim 14, wherein said second predetermined
time is longer
than said first predetermined time.
I 7. The method as defined in claim 14, wherein said word line timing pulse
is delayed before
being logically combined with said first delayed world line timing pulse.
18. The method as defined in claim 14, wherein said word line timing pulse
is delayed before
being logically combined with said second delayed world line timing pulse.
19. The method as defined in claim 14, wherein said word line timing pulse
is delayed by a
first predetermined time by coupling said word line timing pulse with a first
delay circuit.
20. The method as defined in claim 19, wherein said word line timing pulse
is delayed by a
second predetermined time by coupling said word line timing pulse with a
second delay circuit.
21. The method as defined in claim 20, wherein said word line timing pulse
is delayed by a
second predetermined time by coupling said word line timing pulse with both
said first and said
second delay circuits.
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22. The method as defined in claim 21, wherein said second delay circuit is
a comparator
having a first input coupled to a power signal of said sense amplifier power
supply circuit and a
second input coupled to a predetermined threshold voltage, said comparator
having an output
that is asserted depending on a comparison between said first and second
inputs.
23. The method as defined in claim 22, wherein said first input of said
comparator is coupled
to a p channel power signal of said sense amplifier power supply circuit and
said output of said
comparator is asserted if said p-channel power signal is greater than said
threshold.
24. The method as defined in claim 23, wherein a third delay circuit is
coupled between said
output of said comparator and said second logic circuit.
25. The method as defined in claim 22, wherein said first input of said
comparator is coupled
to an n-channel power signal of said sense amplifier power supply circuit and
said output of said
comparator is asserted if said n-channel power signal is less than said
threshold.
26. The method as defined in claim 25, wherein a third delay circuit is
coupled between said
output of said comparator and said second logic circuit.
27. A Random Access Memory_(RAM) comprising:
(a) at least one memory array comprising plurality of bit line pairs,
plurality of word lines
and plurality of memory cells for storing and retrieving binary data;
(b) a set of bit line sense amplifiers for sensing and enhancing differential
signals
between bit lines of said bit line pairs;
(c) a set of column access devices for coupling said bit line pairs to data
lines;
(d) a bit line sense amplifier power supply circuit for powering said bit line
sense
amplifiers;
(e) first and second delay circuits for delaying a word line timing pulse by
predetermined
periods of time, the first and second delay circuits being coupled in series
so that the first delay
circuit delays the word line timing pulse by a first period of time and the
second delay circuit
adds to the first delay, thus providing a further delayed version of the word
line timing pulse;

(f) a first logic circuit for logically combining said word line timing pulse
and the delayed
version of the word line timing pulse to produce a bit line sense amplifier
enable signal, for
enabling the bit line sense amplifier power supply circuit; and
(g) a second logic circuit far logically combining said word line timing pulse
and the
further delayed version of the word line timing pulse to produce a column
select enable signal.
28. The Random Access Memory (RAM) as claimed in claim 27, wherein said
memory cells
are Dynamic Random Access Memory (DRAM) cells.
29. The Random Access Memory (RAM) as claimed in claim 27, wherein said
word line
timing pulse is logically combined with a pre-decoded row address by a third
logic circuit in
order to raise one of the said word lines selected by the row address.
30. The Random Access Memory (RAM) as claimed in claim 27, wherein said
column select
enable signal is logically combined with a plurality of pre-decoded y-
addresses by a plurality of
fourth logic circuits in order to enable selected ones of a plurality of
column access devices.
31. The Random Access Memory (RAM) as defined in claim 27, wherein the time
delay
introduced by said second delay circuit is longer than the time delay time
introduced by said first
delay circuit.
32. The Random Access Memory (RAM) as defined in claim 31, wherein the time
delay
introduced by said first and second delay circuits is controlled with
precision.
33. The Random Access Memory (RAM) as defined in claim 27, wherein said
word line
timing pulse, bit line sense amplifier enabling signal and column select
enable signal are all local
with respect to said memory array.
34. The Random Access Memory (RAM) as claimed in claim 30, wherein said
first, second,
third and fourth logic circuits are all local with respect to said memory
array.
35. The Random Access Memory (RAM) as claimed in claim 27, wherein said
first and
second delay circuits are both local with respect to said memory array.
36. A semiconductor memory device comprising:
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a memory array including a plurality of memory cells, a plurality of bit
lines, and a
plurality of word lines;
a plurality of sense amplifiers for sensing and amplifying signals from said
bit lines;
a plurality of column access devices for coupling said bit lines to a data
line of the
memory device;
first and second circuits for delaying a word line timing pulse, the first and
second
circuits being coupled to each other such that the first circuit delays the
word line timing pulse to
provide a delayed word line timing pulse and the second circuit further delays
the word line
timing pulse to provide a further delayed word line timing pulse;
a third circuit for enabling the sense amplifier at a first time corresponding
to said
delayed word line timing pulse; and
a fourth circuit for enabling the column access device at a second time
corresponding to
the said further delayed word line timing pulse.
37. The memory device as claimed in claim 36, wherein the third circuit
includes a logic
circuit for using said delayed word line timing pulse and generating a sense
amplifier enable
signal to activate the sense amplifier.
38. The memory device as claimed in claim 36, wherein the fourth circuit
includes a logic
circuit for using said further delayed word line timing pulse and generating a
column access
enable signal to activate the column access device.
39. An apparatus for operating a semiconductor memory device having a
plurality of memory
cells arranged in rows and columns, and a plurality of word lines and bit
lines, said apparatus
comprising:
a first circuit for delaying a word line timing signal;
a second circuit for activating a sense amplifier at a first time
corresponding to the
delayed word line timing signal, the sense amplifier sensing and amplifying a
signal from a
selected memory cell;
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a third circuit for further delaying the word line timing signal; and
a fourth circuit for activating a column access device at a second time
corresponding to
the further delayed word line timing signal, the column access device
connecting the selected
memory cell to a data line of the memory device.
40. The apparatus as claimed in claim 39, wherein the second circuit
includes a logic circuit
for generating a sense amplifier enable signal for activating the sense
amplifier, in response to
the delayed word line timing signal.
41. The apparatus as claimed in claim 39, wherein the fourth circuit
includes a logic circuit
for generating a column access enable signal for activating the column access
device, in response
to the delayed word line timing signal.
42. A semiconductor memory device comprising:
a plurality of memory cells,
a plurality of bitlines and word lines coupled to the plurality of memory
cells;
a plurality of sense amplifiers for sensing and amplifying signals from the
bit lines;
a plurality of column access devices for coupling the bit lines to a data
line;
delay circuitry for providing a delayed word line timing pulse and a further
delayed word
line timing pulse in response to a word line timing pulse, the further delayed
word line timing
pulse being provided in response to the delayed word line timing pulse; and
enable circuitry for enabling the sense amplifier in response to the delayed
word line
timing pulse and for enabling the column access devices in response to the
further delayed word
line timing pulse.
43. The semiconductor memory device of claim 42, wherein the delay
circuitry comprising:
first delay circuitry for delaying the word line timing pulse to provide the
delayed word line
timing pulse; and
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second delay circuitry for delaying the delayed word line timing pulse to
provide the
further delayed word line timing pulse.
44. The semiconductor memory device of claim 43, wherein the enable
circuitry is
configured to enable the sense amplifier at a time corresponding to the
delayed word line timing
pulse and to enable the column access device at a time corresponding to the
further delayed word
line timing pulse.
45. An apparatus for operating a semiconductor memory device having a
plurality of memory
cells, a plurality of bit and word lines, the apparatus comprising:
a plurality of sense amplifiers for sensing and amplifying signals from the
bit lines;
a plurality of column access devices for coupling the bit lines to a data
line;
delay circuitry for providing a delayed word line timing pulse and a further
delayed word
line timing pulse in response to a word line timing pulse, the further delayed
word line timing
pulse being provided in response to the delayed word line timing pulse; and
enable circuitry for enabling the sense amplifier in response to the delayed
word line
timing pulse and for enabling the column access device in response to the
further delayed word
line timing pulse.
46. The apparatus of claim 45, wherein the delay circuitry of the
semiconductor memory
device comprises:
first delay circuitry for delaying the word line timing pulse to provide the
delayed word
line timing pulse; and
second delay circuitry for delaying the delayed word line timing pulse to
provide the
further delayed word line timing pulse.
47. The apparatus of claim 45, wherein the enable circuitry of the
semiconductor memory
device is configured to enable the sense amplifier at a time corresponding to
the delayed word
line timing pulse and to enable the column access device at a time
corresponding the further
delayed word line timing pulse.
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48. A method for operating a semiconductor memory device having a plurality
of memory
cells, a plurality of bit and word lines, the method comprising:
providing a delayed word line timing pulse in response to a word line timing
pulse;
providing a further delayed word line timing pulse in response to the delayed
word line
timing pulse;
enabling the sense amplifier for sensing and amplifying signals from the bit
lines in
response to the delayed word line timing pulse; and,
enabling the column access device for coupling the bit lines to a data line of
the memory
device in response to the further delayed word line timing pulses.
49. The method of claim 48, wherein the step of providing comprises:
delaying a word line timing pulse to provide the delayed word line timing
pulse; and
delaying the delayed word line timing pulse to provide the further delayed
word line
timing pulse.
50. The method of claim 49, wherein the step of enabling comprises:
enabling the sense amplifier at a time corresponding to the delayed word line
timing
pulse and
enabling the column access device at a time corresponding to the further
delayed word
line timing pulse.
51. The method of claim 49, wherein the step of enabling comprises:
activating the sense amplifier in synchronization with the delayed word line
timing pulse and
activating the column access device in synchronization with the further
delayed word line timing
pulse.
52. A semiconductor memory device, comprising:
an array of memory cells; and

a memory array interface circuit coupled to the array of memory cells, the
memory
array interface comprising:
a first delay means for delaying a wordline timing pulse by a first
predetermined
delay amount to provide a first delayed wordline timing pulse;
a first logic circuit, coupled to the first delay means, for logically
combining the
wordline timing pulse and the first delayed wordline timing pulse to provide a
sense
amplifier enable signal;
a second delay means for delaying the wordline timing pulse by a second
predetermined delay amount, that is greater than the first predetermined delay
amount, to
provide a second delayed wordline timing pulse;
a second logic circuit, coupled to the second delay means, for logically
combining
the wordline timing pulse and the second delayed wordline timing pulse to
provide a
column select enable signal; and
enabling circuitry, coupled to the first and second logic circuits and to a
sense
amplifier power supply circuit of the memory array arid a plurality of column
access
devices of the memory array, the enabling circuitry being configured to
enable:
the sense amplifier power supply circuit in response to the sense amplifier
enable signal, and
selected ones of the plurality of column access devices in response to the
column select enable signal, after the sense amplifier power supply circuit is
enabled.
53. The semiconductor memory device of claim 52, wherein the memory cells
are Dynamic
Random Access Memory (DRAM) cells.
54. The semiconductor memory device of claim 52, wherein the memory array
interface
circuit is a Static Random Access Memory (SRAM) interface.
21

55. The semiconductor memory, device of claim 52, wherein the wordline
timing pulse, the
sense amplifier enable signal and column select enable signal are all local
with respect to said
memory, array.
56. The semiconductor memory, device of claim 52, wherein the first delay
means is a first
delay element.
57. The semiconductor memory, device of claim 56, wherein the second delay
means
comprises a comparator having a first input coupled to a power signal of the
sense amplifier
power supply circuit and a second input coupled to a predetermined threshold
voltage, the
comparator having an output that is asserted in response to a comparison
between the first and
second inputs.
58. The semiconductor memory, device of claim 57, wherein the output of the
comparator is
asserted if the power signal is greater than the predetermined threshold
voltage.
59. The semiconductor memory, device of claim 58, wherein the power signal
is a p-channel
power signal.
60. The semiconductor memory, device of claim 57, wherein the output of
the comparator is
asserted if the power signal is less than the predetermined threshold voltage.
61. The semiconductor memory, device of claim 60, wherein the power signal
is an n-
channel power signal.
62. The semiconductor memory, device of claim 52, wherein the second delay
means is a
second delay element.
63. The semiconductor memory, device of claim 62, wherein the second delay
element is
coupled with the wordline timing pulse via a first delay element.
64. The semiconductor memory device of claim 62, wherein the second delay
element is
directly coupled to the wordline timing pulse.
22

65. The
semiconductor memory device of claim 52, further comprising a plurality of
logic
circuits for logically combining the column select enable signal with a
plurality of column
address signals for enabling the selected ones of a plurality of column access
devices.
23

Description

CA 02415218 2003-O1-06
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METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND
COLUMN ACCESS OPERATIONS
The present invention relates generally to synchronization of row and column
access
operations in semiconductor memory devices, and specifically to row and column
access operations in a high-speed dynamic random access memory.
BACKGROUND OF THE INVENTION
Semiconductor memory integrated circuits have traditionally utilized an
internal
architecture defined in an array having rows and columns, with the row-column
address intersections defining individual data storage locations or memory
cells.
Typically, these intersections are addressed through an internal address bus,
and the
data to be stored or read from the locations is transferred to an internal
input/output
bus. Groups of data storage locations are normally coupled together along word
lines.
Semiconductor configurations utilizing tlus basic architecture include dynamic
random access memory (DRAM), static random access memory (SRAM), electrically
programmable read only memory (EPROM), erasable EPROM (EEPROM), as well as
"flash" memory.
One of the more important measures of performance for such memory devices is
the
total usable data bandwidth . The main type of timing delay affecting the data
bandwidth is referred to as access time. Access time is defined as the delay
between
the arrival of new address information at the address bus and the availability
of the
accessed data on the input/output bus.
In order to either read data from or write data to a DRAM memory array, a
number of
sequential operations are performed. Initially, bit line pairs are equalized
and pre-
charged. Next, a selected word line is asserted in order to read out the
charge state of
an addressed memory cell onto the bit lines. Bit line sense amplifiers are
then
activated for amplifying a voltage difference across the bit line pairs to
full logic
levels. Column access transistors, which are typically n-channel pass
transistors, are
then enabled to either couple the bit line state to DRAM read data amplifiers
and
SUBSTITUTE SHEET (RULE 26)

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outputs, or to over-write the bit line state with new values from DRAM write
data
inputs.
In nearly all DRAM architectures, the two dimensional nature of the memory
array
addressing is directly accessible to the external memory controller. In
asynchronous
DRAM architectures, separate control signals are used for controlling the row
(or x-
address) and column (or y-address) access operations. In synchronous DRAM
arclutectures, it is also possible to use separate row and column control
signals as
described above. Furthermore, for synchronous DRAM architectures it is
possible to
employ a single command path for both row and column control signals.
In these cases, bit line sense amplifier activation is usually performed as
the last stage
of a self timed sequence of DRAM operations initiated by a row activation
command.
Column access transistors are controlled by the y-address decoding logic and
are
enabled by the control signals associated with individual read and write
commands.
However, for both asynchronous and synchronous DRAM architectures, the ability
to
minimize the timing margin between bit line sensing and the enabling of the
column
access transistors is limited by the timing variability between the separate
control
paths for row access and column access operations. Even in synchronous
designs, the
x-address and y-address decoding logic paths are quite distinct. The timing
variability
between the completion of bit line sensing and the commencement of column
access
transistor activation comprises the sum of the variability between the x and y
address
decoding paths, the variability of the self timed chain that activates the bit
line sense
amplifiers, and the time of flight differences in control signals. That is,
the control
signals arrive at a given memory array from row and column control logic
located in
separate regions of the memory device and therefore may have different
activation
timing.
In order to reduce DRAM access times and increase the rate at which read and
write
operations can be performed it is important to attempt to reduce the time
needed for
each of the previously mentioned sequential operations necessary for the
fmctioning
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of a DRAM. Furthermore, equally important is the need to initiate each
successive
DRAM access function as soon as possible after the previous operation.
Specifically, the delay between bit line restoration and the enabling of the
column
activation device is critical for both correct DRAM operation and achieving
low
access latency. If the column access transistor is enabled too soon, the
memory cell
a
read out on to the bit lines may be corrupted. The corruption can occur
directly from
noise on the bit lines coupled through the column access transistors or
indirectly
through capacitive coupling between a bit line driven through the column
access
transistor and an adj acent unselected bit line. Since the data is read
destructively, if it
is corrupted, it cannot be retrieved. On the other hand, if the column access
transistor
is enabled too late, unnecessary delay is added to memory access latency.
Furthermore, the equalization and pre-charge of the bit lines in preparation
for a
subsequent access operation may effectively be unable to proceed until the
column
access transistors are turned off.
Therefore, there is a need for a memory device that can initiate successive
DRAM
access functions with little or no unnecessary delay without corrupting memory
cell
data. Accordingly, it is an object of the present invention to obviate or
mitigate at
least some of the above mentioned disadvantages.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention there is provided
circuit
for synchronizing row and column access operations in a semiconductor memory
having an array of bit lines pairs, word lines, memory cells, sense
amplifiers, and a
sense amplifier power supply circuit for powering the sense amplifiers. The
circuit
comprises a word line timing pulse for activating of at least one of the word
lines, a
first delay circuit coupled with the word line timing pulse for delaying the
word line
timing pulse by a first predetermined period, and a first logic circuit for
logically
combining the word line timing pulse and the word line timing pulse delayed by
the
first delay circuit. The output of the first logic circuit provides a sense
amplifier
enable signal for enabling the sense amplifier power supply circuit. The
circuit
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further comprises a second delay circuit coupled with the word line timing
pulse for
delaying the word line timing pulse by a second predetermined period. The
circuit
further comprises a second logic circuit for logically combining the word line
timing
pulse and the word line timing pulse delayed by the second delay circuit for
providing
a column select enable signal. The column select enable signal enables
selected ones
of a plurality of column access devices, which are activated a predetermined
time
period after the sense amplifier power supply circuit is enabled.
There is also provided a method for synchronizing row and column access
operations
in a semiconductor memory having an array of bit lines pairs, word lines,
memory
cells, sense amplifiers, and a sense amplifier power supply circuit for
powering the
sense amplifiers. The method comprising the steps of generating a word line
timing
pulse for activating of at least one of the word lines, delaying the word line
timing
pulse by a first predetermined time, and logically combining the word line
timing
pulse and the first delayed word line timing pulse fox providing a sense
amplifier
enable signal. The sense enable signal enables the sense amplifier power
supply
circuit. The method ftirther comprises the steps of delaying the word line
timing
pulse by a second predetermined time and logically combining the word line
timing
pulse and the second delayed word line timing pulse for providing a column
select
enable signal. The column select enable signal enables selected ones of a
plurality of
column access devices wherein the selected ones of a plurality of column
access
devices are activated a predetermined time period after the sense amplifier
power
supply circuit is enabled.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described by way of example only with
reference
to the following drawings in which:
Figure 1 is a schematic drawing of an asynchronous DRAM architecture (prior
Figure 2 is a schematic drawing of a synchronous DRAM architecture with a
common command and address path (prior art);
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Figure 3 is a schematic drawing of a DRAM architecture according to an
embodiment of the present invention;
Figure 4 is a timing diagram for the DRAM architecture illustrated in the
figure 3;
Figure 5 is an alternative embodiment of the schematic diagram illustrated in
figure 3; and
Figure 6 is yet an alternate embodiment of the schematic diagram illustrated
in
figure 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
For convenience, like numerals in the description refer to like structures in
the
drawings. Referring to figure 1, a prior art implementation of an asynchronous
DRAM architecture using separate control signals for controlling the row and
column
access operations is shown generally by numeral 100. All bit line pairs are
precharged and equalized prior to an active cycle. An external memory
controller 102
transmits row control signals 104 to a row control logic device 106. The
external
memory controller 102 sends column control signals 108 to a column control
logic
device 110. The external memory controller 102 also sends an address signal
112 to
both the row control logic device 106 and the column control logic device 110.
In response to an activation signal, the row control logic device 106 asserts
word line
114 in accordance with decoding of the address signal 112. The charge state of
memory cell 113 is read on to a pair of complementary bit lines 116. A sense
amplifier 115 amplifies the voltage across the bit lines 116. The column
control logic
110 then asserts column select signal 117 in accordance with decoding of the
address
signal 112. The column select signal enables the column access transistors
119. The
intersection of word line 114 and bit lines 116 is an address specified by the
address
signal 112. The address is to be read from the memory array via a data bus
sense
amplifier 118a and subsequently an output buffer 118b or written to the memory
array
via an input buffer 118c and subsequently a write driver 118d.
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Referring to figure 2, a prior art implementation of a synchronous DRAM
architecture
having a single command path for both row and column access operations is
illustrated generally by muneral 200. The external memory controller 102 sends
an
address signal 112 and a command signal 202 to a synchronous front end 204.
The
synchronous front end 204 provides the address signal 112 to a row control
logic
device 106 as well as a column control logic device 110. Further, the
synchronous
front end 204 provides row control signals) 104 to the row control logic
device 106
and column control signals) 108 to the column control logic device 110.
The row control logic device 106 and the column control logic device 110
assert word
line 114 and column select signal 117 in a similar fashion to that described
above with
reference to figure 1. An input/output path 206 functions similarly to the
input/output
path 118 illustrated in figure 1 with the exception that input/output path 206
also
contains input and output data latches 208a and 208b respectively for
providing
synchronous transfer of data. Both of the synchronous front end 204 and the
latches
208 are clocked by the same clock 210.
Both the implementations described with reference to figure 1 and figure 2
suffer
from the timing uncertainty and variability between bit line sensing and
column
access transistor activation. One method for reducing timing uncertainty and
variability between bit line sensing and column access transistor activation
comprises
synchronzing the two operations locally within the peripheral region of the
selected
memory array. By combining the activation of column access transistors with a
control signal generated based on bit line sense amplifier activation, it is
possible to
greatly reduce the unnecessary delay between bit line sensing and column
access.
This allows memory access latency to be reduced and memory operations to be
performed at a faster rate.
Referring to figure 3, a DRAM architecture in accordance with an embodiment of
the
present invention is illustrated generally by numeral 300. A word line timing
pulse
signal WTP is coupled to the input of a first delay element D1. The output of
the first
delay element D1 is coupled to the input of an AND gate A1. The word line
timing
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pulse WTP is a second input to the AND gate Al . The output of AND gate A1 is
a
sense amplifier enable signal SAEN, which is the input to a bit line sense
amplifier
power supply circuit 302. The bit line sense amplifier power supply circuit
302
powers the sense amplifiers 304 for amplifying the voltage across bit line
pairs 306.
Power is provided by selectively coupling p-channel supply signal SAP and n-
channel
supply signal SAN to the positive supply voltage VDD and ground supply voltage
Vss
respectively during an active sensing cycle, and to bit line precharge voltage
VBLP
during a precharge cycle.
The output of the first delay element D1 is fizrther coupled to the input of a
second
delay element D2. The output of the second delay element D2 is coupled to the
input
of a second AND gate A2. The word line timing pulse WTP is a second input to
the
AND gate A2. The output of the AND gate A2 is a column select enable signal
CSE.
The CSE signal is combined with global column select signals GCSLJ comprised
of
predecoded column address signals via AND gates 312 (only two of which are
shown
for simplicity) wluch generate local column select signals LCSLJ. Local column
select signals LCSLJ in turn enable the appropriate column to be accessed. The
word
line timing pulse WTP is also coupled to an associated word line 30~ via a
plurality of
AND gates 314 (only one of which is shown for simplicity) for enabling the
appropriate word line as selected by a pre-decoded x-address.
Referring to figure 4, a timing diagram for the above-described circuit is
shown. The
operation of the circuit will be described with reference to figures 3 and 4
and will
refer to a read operation although a write operation will be apparent to a
person
skilled in the art once the read operation has been described. In response to
a rising
edge of the word line timing pulse WTP, a selected word line rises, turning on
the
access transistor for that memory cell. The data stored in the selected cell
is dumped
on to the bit line and charge sharing between the cell and bit line
capacitance occurs.
After a delay T1 (generated by delay element D1) from receiving a rising edge
of the
word line timing pulse WTP, the bit line sense amplifiers 304 are enabled by
the
assertion of the sense amplifier enable signal SAEN. Asserting the sense
amplifier
enable signal SAEN causes the sense amplifier power supply circuit 302 to
drive the
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voltage on the sense amplifier power supply rails SAP and SAN from the bit
line pre-
charged voltage VBLP to the positive supply voltage VDD and ground supply
voltage
Vss respectively. Once the sense amplifier has been enabled, the data on the
bit line is
amplified to full swing levels.
After a delay of T2 (generated by the delay element D2) from the assertion of
the
sense amplifier enable signal, the column select enable signal CSE is
asserted. The
column select enable signal CSE is used to qualify a set of global coluxml
select
signals GCSLJ generated by the y-address decode logic for local column
selection.
Column select signals LCSLJ local to the individual DRAM array, are generated
by
AND-ing the column select enable CSE signal with the global column select
signals
GCSLJ. Therefore, when the column select enable signal CSE is asserted and a
global
column select signal GCSLJ is asserted, a corresponding local column select
signal
LCSLJ is enabled. The local column select signal LCSLJ, in turn, enables the
column
access transistor 310 which couples the local bit lines to the data buses.
Thus,
referring again to figure 4, a local column select signal LCSLi is generated
after a
delay of T1 and T2. The local column select signal LCSLI enables a first
column
access transistor 310a. During a second read cycle initiated by the next
rising edge of
the of the word line timing pulse WTP, a second local control signal LCSLZ is
enabled
after a delay of T1 and T2. The second local column select signal LCSLZ
enables a
second column access transistor 310b. In the present embodiment, LCSLZ is
implied
to be different to LCSLI for illustrative purposes although this need not be
the case.
The local column select enable signal LCSLJ is activated after a delay of T1
and T2
from the rising edge of the word line timing pulse WTP and is deactivated by
the
falling edge of the column select enable signal CSE. The sense amplifiers are
powered
by the bit line sense amplifier power supply circuit 302 after a delay of T1
from the
rising edge of the word line timing pulse WTP and are deactivated by the
falling edge
of the SAEN signal. The AND gates A1 and A2 ensure that both the sense
amplifier
enable signal SAEN and the column select enable signal CSE are disabled
immediately in response to the falling edge of the word line timing pulse WTP.
The
word line 308 is enabled as long as the word line timing pulse WTP is active.

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Therefore, synchronization of the enabling of column access transistors within
an
individual DRAM array to a predetermined time period after the activation of
the bit
line sense amplifiers associated with that array is achieved. It should be
noted that the
predetermined delay between the sense amplifiers can be selectively programmed
to
achieve optimum read and write performance. .
Referring to figure 5, an alternate embodiment to that described in figure 3
is
illustrated generally by numeral 500. The bit line sense amplifier power
supply
circuit 302 is enabled by AND-ing the timing control signal WTP with a delayed
version of the timing control signal WTP, as was described in the previous
embodiment. However, in the present embodiment, the column select enable
signal
CSE is a result of AND-ing the timing control signal WTP with the output of a
comparator 502.
The comparator 502 compares the level of either one of the p-channel or n-
channel
supply signals SAP and SAN respectively with a predetermined threshold voltage
VsW. In figure 5, the comparator compares the p-channel supply signal SAP with
the
threshold voltage VsW, which is set to have a value between VB~ and VDD. As
soon
as SAP rises above the threshold voltage VsW, the comparator asserts a
corresponding
output, thereby enabling the column select enable signal CSE via and gate A2.
The
column select enable signal CSE is used for enabling the column select signals
(not
shown) as described in the previous embodiment.
In yet an alternate embodiment, instead of receiving the p-channel supply
signal SAP,
the cornparator receives the n-channel supply signal SAN and the threshold
voltage
Vsw is set to a value between VBLP and Vss. Therefore, once the n-channel
supply
signal SAN voltage is below the predefined threshold value VsW, the output of
the
comparator will be such that the column select enable signal CSE is enabled.
The
column select enable signal CSE is used for enabling the column select signals
as
described in the first embodiment.
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Optionally, for either of the above-mentioned embodiments, a further delay
element
504 may be added for providing a delay before enabling the column select
enabling
signal CSE.
Yet an alternate embodiment is illustrated in figure 6 and represented
generally by
numeral 600. As in the previous embodiments, the sense amplifier enable signal
SAEN is generated as a result of AND-ing the word Line timing pulse WTP with a
delayed version of the word line timing pulse WTP. However, in the present
embodiment the column select enable signal is a result of AND-ing the word
line
timing pulse WTP with a delayed version of the word line timing pulse WTP. A
second delay element D3 delays the word line timing pulse WTP by a combined
time
delay of T1 and T2. Therefore, unlike the first embodiment, the word line
timing
pulse WTP is presented directly at the input of the second delay element D3.
The time between the negation of the word line timing pulse WTP and the
disabling
of the bit line sense amplification power supply circuit 302 can be adjusted
by
inserting a delay element between the word line timing pulse WTP and the input
of
the AND gate Al . Similarly, the time between the negation of the word Iine
timing
pulse WTP and the negation of the column select enable signal CSE can be
adjusted
by inserting a delay element between the word line timing pulse WTP and the
input of
AND gate A2.
Since more precise control of the timing between bit line sensing and column
access
is achieved by all of the previous embodiments, it is also possible to
initiate column
access while bit line sensing is only partially complete for further
accelerating read
and write operations.
Although the invention has been described with reference to certain specific
embodiments, various modifications thereof will be apparent to those skilled
in the art
without departing from the spirit and scope of the invention as outlined in
the claims
appended hereto. Furthermore, the invention may be applicable to any type of
electronic memory organized in array and addressed using distinct and
sequential x

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and y addressing phases. These include SRAM and various non-volatile memories
such EPROM, EEPROM, flash EPROM, and FRAM.
11

Representative Drawing