CA 02441159 2003-09-19
OPTO-ELECTRONIC HYBRID INTEGRATION PLATFORM, OPTICAL SUB
MODULE, OPTO-ELECTRONIC HYBRTD INTEGRATION CIRCTJIT, AND
PROCESS FOR FABRICATING PLATFORM
The present invention relates to a hybrid optical
integration platform capable of incorporating an optical
device or optical sub-module used for optical
communication and optical signal processing in addition
to optical waveguides and electrical wirings, an optical
sub-module which can be equipped on the board, and a
10 hybrid optical integrated circuit equipped with the
optical device or optical sub-module, and to a process
for fabricating the hybrid optical integration platform.
With recent advance in optical communications and
optical information processing, development of an opto-
electronic integration circuit is in demand, in which
active devices are incorporated in low-loss optical
waveguides and the like to be driven by a high-frequency
electrical circuit.
To achieve a circuit incorporated with active
20 devices on the optical waveguide and high-frequency
driven, three conditions are required f_or the opto-
electronic board, which are (1) a low-loss optical
waveguide function, (2) an optical bench function to
incorporate an optical device on the same substrate and
prevent axis deviation, and {3) a high-frequency
electrical wiring function required to drive the optical
device.
However, a circuit that satisfies the above three
conditions has not been obtained with the prior art.
30 As a prior art example, Fig. Z is a schematic
",_ perspective view showing canstruction called "Sil9_con
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CA 02441159 2003-09-19
optical bench'q in which, using a guide groove 2 and
positioning reference surfaces 3a, 3b, and 3c formed on a
silicon substrate 1, an optical fiber 4 and a semiconductor
laser (LD) 5 are integrated on.the silicon substrate. In
this construction, since the guide groove can be formed
with a good precision utilizing good processability of the
silicon substrate, integration of the optical fiber 4 with
optical devices such as the semiconductor laser (LD) 5 and
a photo-detector (PD) can be easily achieved. Further,
10 siwce the silicon substrate is superior in thermal
conductivity, it also functions as a good heat sink for
optical devices.
Further, the electrical wiring 6 is formed directly on
the surface of the silicon substrate 1, or through a very
thin oxide film of less than 0.5~,cn in thickness, but this
structure has a problem of considerably deteriorating the
high-frequency characteristics of the electrical wiring 6.
That is, to form the electrical wiring 6 with superior
high-frequency characteristics, the electrical wiring layer
20 must have a sufficient thickness and be formed on an
c
insulator with small dielectric loss. However, the silicon
substrate 1 is very thin in thickness, the resistance is
not high enough to ensure the high-frequency
characteristics, and has a specific resistivity of about 1
k-ohm. cm.
Fig. 2 shows high-frequency characteristics of a 0.6 mm
long coplanar wiring formed directly on the silicon
substrate (T. 5uzuki et al.: Microwave Workshop Digest
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(1993) p95). The axis of ordinates indicates transmission
characteristics S21 of S parameter and the axis of
abscissas indicates a frequency (GHz). Loss of the 0..6 mm
long wiring is about 0.4 dB (2 GHz) and about 0.8 dB (10
GHz), which are converted to 1 cm as 7 dB (2 GHz) and 13 dB
(10 GHz), thus showing a substantial loss.
On the other hand, an optical packaged circuit having
an optical waveguide function, application of silica-based
optical waveguide formed on the silicon substrate is
10 expected. Prior art optical waveguides include (1) a
"ridge type optical waveguide" in which the core is
protected with a thin over-cladding layer as shown in Figs.
3A and 3B, and (2) an '°embedded optical waveguide" in which
the core is embedded in a sufficiently thick over-cladding
layer as shown in Figs. 3C and 3D.
Fig. 4 is a schematic perspective view showing an
example of the ridge type optical waveguide which is
described in a document. This document is '°Hybrid-
Integrated 4 X 4 Optical Gate Matrix Switch Using Silica-
20 Based Optical Waveguides and LD Array Chips", IEEE J.
Lightwave Technol., voI.lO, pp. 383-390, 1992, by Y. Yamada
et al. This example shows a hybrid optical integrated
circuit including a silica-based optical waveguide ? formed
on the silicon substrate 1 and a semiconductor. optical
device 8. In Lhis example, a semiconductor-laser amplifier
represents as SLA. The optical waveguide 7 has a structure
of ridge type optical waveguide, in which a core 7a formed
on a thick under-cladding layer ?c formed on the silicon
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,r"w.
substrate 1 is protected with very thin cladding layers 7b
and 7c. The SLA 8 is surface packaged in an upside-down
construction in which an active layer 8a is facing down in
the vicinity of the waveguide end, and a heat sink 9 for
heat dissipation is provided on the backside. Since, in
such a structure, the core is only covered with very thin
cladding layers 7b and 7c, it has problems that (1) the'
optical waveguide has a large loss, (2) it is liable ~to be
affected by external disturbance, and (3) formation of a
20 directional coupler circuit is difficult. In particular,
the directive coupler is an indispensable circuit element
to fabricate a high--performance optical circuit, and the
impossibility of the formation means that application of
the ridge type optical waveguide is limited to a narrow
area. Thus, the ridge type optical waveguide does not
sufficiently satisfy the optical waveguide function.
Further, electrical wiring function is not investigated
here.
Fig. 5 shows an example of "optical waveguide circuit
20 with terrace" (Yamada, Kawachi, Kobayashi: Japanese Patent
Application Laying-open 63--131104 "E~ybrid Optical
Integrated Circuit") in which an optical waveguide is
formed in a recess 1a on a silicon substrate 1 having
irregularities and a device is equipped on a protruded part
1b. In Fig. 5, an under-cladding layer 10c of a silica-
based optical waveguide 10 is formed in the recess la of
the silicon substrate 1, and a core layer 10b is formed on
top, and finally an embedding cladding layer 10a is formed.
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The upper surface of the under-cladding layer lOc and the
upper surface of the protruded part 1b of the silicon
substrate are in line in height, and the protruded part 1b
can be used as a height reference surface of the optical
device 8. In such a substrate 1, low-loss op~tioal
waveguide function and optical bench function are
satisfied, but a function to provide high-frequency wirings
is not considered quite at all. When an electrical wiring
is equipped, it is formed on the protruded part 1b of the
10 silicon substrate 1, which does not satisfy the
requirements for high-frequency characteristics. Tn Fig.
5, the reference numeral 8a indicates an active layer, and
11 indicates a reference surface for device positioning.
Fig. 6 is a schematic perspective view showing
construction of a hybrid optical integrated circuit
disclosed in Japanese Patent Application haying-open No.
62-242362. This circuit almost comprises a buffer layer 12
provided on a silicon substrate 1, a silica-based optical
waveguide 13 provided thereon, a device holding table 19
20 having the same height from the upper surface of the
silicon substrate 1 as the buffer layer 12, a semiconductor
laser 15 held in upside-down construction on the holding
table 14, and an electrical wiring table 16 having a
conductive film 16a electrically connected with a gold wire
to the upper electrodewof~the-~emiconductor laser 15 and
protrudingly provided on the upper surface of the silicon
substrate 1. The reference numeral 17 indicates a heat
sink.
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_,..,. -~s
l
In such a circuit construction, since a difference in
height from the upper surface of the buffer layer 12 to the
core of the waveguide 13 is set equal to the difference in
height from the upper surface of the device holding table
14 to the active layer 15a of the semiconductor laser 15,
it has an advantage that optical devices such as a
semiconductor laser can be equipped with a very high
positioning precision.
However, even with this circuit, the optical waveguide
10 13 is limited to the ridge type, tends to be affected by
external disturbance, and cannot provide a low loss optical
waveguide function.
Fig. 7 is a schematic perspective view showing
construction of a hybrid optical integrated circuit
disclosed in Japanese Patent Application Publication 5-
2748. This circuit mainly comprises an optical waveguide
18 protrudingly disposed with nearly the same height on the
silicon substrate, an optical fiber guide 19, an optical
device guide 20, an electrical wiring holding table 21, a
20 first conductive film (common electrode) 22 disposed on the
silicon substrate l, a second conductive film 23 disposed
on the upper surface of the electrical wiring holding 21
and insulated from the first conductive film 22, an optical
fiber 24 disposed along the optical fiber guide 19, and a
laser diode 25 as an optical device disposed long the
optical device guide 20.
The circuit of this construction, since the optical
device is equipped directly on the silicon substrate, has
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! 1
i.;.
an advantage that the silicon substrate can be functioned
as a heat sink.
However, even with this circuit, the optical Paaveguide
18 is limited to the ridge type, tends to be affected by
external disturbance, and cannot provide a low loss optical
waveguide function.
Pig. 8 is a schematic cross sectional view showing
construction of an optical waveguide device disclosed in
Japanese Patent Application Laying--open 5-60952. This
1g device mainly comprises a silicon substrate 1, an optical
waveguide formed on the substrate 1, and a semiconductor
device 27 equipped in an upside-down construction in a
recess of the silicon substrate 1.
In the device of this construction, since the optical
waveguide 26 is formed on a convex region of the silicon
substrate 1, an under-clad of a sufficient thickness cannot
be formed. Therefore, it has a large transmission loss,
tends to be affected by external disturbance, and does not
satisfy a sufficient optical waveguide function.
20 Further, in the above device, since the electrical
wiring 28 is provided on the silicon substrate 1,
requirements for high-frequency characteristics are not
satisfied.
As described above, the prior art hybrid optical
integration technology 'does 'not 'satisfy the above 'three
requirements. In particular, the high-frequency electrical
wiring function has not been considered.
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r;., .:,
An object of the present invention is to provide an
opto-electronic hybrid packaged platform which satisfy a
low-loss optical waveguide function, an optical bench
function, and a high-frequency electrical wiring function.
A further object of the present invention is to provide
a process far fabricating an opto-electronic hybrid
packaged platform which satisfy the three functions as
described above.
A still further object of the present invention is to
10 provide an opto-electronic hybrid integration circuit which
satisfy the three functions as described above.
Another object of the present invention is to provide
an optical sub-module which satisfy the three functions as
described above.
According to an aspect of the present invention, one of
the foregoing objects can be achieved by providing an opto-
electronic hybrid packaged platform, having an optical
waveguide part, an optical device mounting part, and an
electrical wiring part provided on a same substrate,
20 wherein the optical device mounting part has a terrace
a
provided as a protrusion on the substrates and the
electrical wiring part has a dielectric layer formed an the
substrate and a conductor pattern formed on the surface or
inside.
The terrace may be made of silicon material. The
substrate may have a silicon terrace far electronic circuit
formation in addition to the silicon terrace for optical
device mounting. An upper surface of the conductor pattern
g
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y
_ ;~Jj
a on the dielectric layer may be set lower than an upper
surface of the silicon terrace in the optical device
mounting part and at least in the vicinity of silicon
terrace of the electrical wiring part.
The silicon terrace may have a side surface having an
inclination angle; and a thin film electrode may be formed
on the surface and the s7~de surface of the silicon terrace,
and the thin film electrode may be electrically connected
to the conductor pattern formed on an upper surface or
inside of the dielectric layer in the periphery of the
silicon terrace.
The silicon terrace for optical device may be divided
into two or more sections, a space between the divided
silicon terrace may be filled with the dielectric Layer,
and a conductor pattern may be provided on the dielectric
layer between the silicon terraces far optical device. The
optical waveguide part may include a positioning groove
formed on the silicon terrace, and an optical fiber fixed
in the positioning groove.
The optical waveguide part may have an under-cladding
layer formed on the substrate, a care, and an over-cladding
layer, and a height of a core bottom surface of the optical
waveguide may be set higher than the upper surface of the
silicon terrace.
The optical waveguide may include at least one signal
optical waveguide and at least one monitor optical
waveguide.
The optical waveguide may be a dielectric optical
_ g _
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/..__,.
waveguide, and the dielectric layer of the electrical
wiring part may have an under-cladding layer of the
dielectric optical waveguide.
A second dielectric layer may be stacked on a part of a
first dielectric layer, the first dielectric layer
including the under-cladding layer of the optical
waveguide, the second dielectric layer including a material
different from the optical waveguide, and a conductor
pattern may be formed inside or on the surface of the
10 second dielectric layer.
The substrate may be a sila~con substrate, the optical
waveguide and the electrical wiring part dielectric layer
are formed of silica-based optical waveguide, a conductor
pattern formed on the electrical wiring part dielectric
layer may be a coplanar wiring having a central conductor
and a ground conductor, and the dielectric layer may have a
thickness of 50~,tm or more.
The silicon substrate may have an average resistivity
of 50 ohm-cm or more, the optical waveguide and the
20 dielectric layer are formed on silica-based optical
waveguide, a conductor pattern provided on the electrical
wiring part dielectric layer may be a coplanar wiring
comprising a central conductor and a ground conductor, and
the dielectric layer may have a thickness of 20~t.m or more.
According to another aspect of the present invention,
one of the foregoing objects can be achieved by providing
an opto-electronic hybrid packaged platform, raaving a
silica-based optical waveguide including an under-clad, a
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core and an over-clad which are formed on a silicon
substrate: and an electrical wiring layer including a
coplanar wiring, the coplanar wiring having a central
conductor and a grounding conductor which are formed on any
one of the under-clad and the over-clad of the silica-based
optical wavegu ide, wherein the silica-based optical
waveguide defined between the electrical wiring layer and
the silicon substrate may have a thickness of SO~Im or more.
According to another aspect of the ~aresent invention,
10 one of the foregoing objects can be achieved by providing
an opto-electronic hybrid packaged platform, having a
silica-based optical waveguide including an under-clad, a
core and an over-clad which are formed on a silicon
substrate; and an electrical wiring' layer including a.
coplanar wiring, the coplanar wiring having a central
conductor and a grounding conductor which are formed an any
one of the under-clad and the aver-clad of the silica-based
optical waveguide, wherein the silicon substrate may have
an average rev~istivity of SO ohm-cm or more, and the
20 silica-based csptical waveguide defined between the
a
electrical wiring layer and the silicon substrate may have
a thickness of 20~tm or more.
The silica-based optical waveguide rnay have a total
thickness of 120Nm or less. The substrate may be a silicon
substrate having awrecess and a protrusion formed on the
surface, the silicon substrate protrusion functions as the
silicon terrace, the optical waveguide may have an under-
cladding layer, a core, and an over-cladding Layer formed
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on the recess, and the electrical wiring part may have a
dielectric layer formed on the silicon substrate recess and a
conductor pattern provided on the surface or inside of the
dielectric layer.
A conductor pattern may be formed within the substrate,
and the conductor pattern in the substrate and the conductor
pattern in or on the dielectric layer are electrically
connected.
The optical waveguide part may include an under-clad, a
10 core and an over-clad which are formed. on the silicon
substrate, wherein the height of the bottom surface of the
core of the optical waveguide part may be higher than that of
the upper surface of the silicon terrace, and wherein the
conductor pattern of the electrical wiring part may be formed
on a surface of the dielectric layer, the dielectric layer
having a height which may be substantially equal to a surface
of the over-clad of the optical wavegu.ide.
According to another aspect of the present invention, one
of the foregoing objects can be achieved by providing a method
20 for producing a platform, having the steps of: providing a
protruding silicon terrace on a substrate; providing an
electrical wiring part on said substrate adjacent to said
silicon terrac4a forming an optical wa.veguide under-cladding
layer on the substrate, and flattening' the surface; forming a
core pattern a:nd an over-cladding layer on said silicon
terrace; removing an over-cladding layer of the silicon
terrace and tYae electrical wiring part., all of the core and
part of an
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under-cladding layer to form a device mounting part, whereby
exposing a silicon terrace upper surface, and setting the
under-
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r ~.
,i
' cladding layer of the electrical wiring part lower by a
desired size than the silicon terrace surface; and forming
a conductor pattern on the electrical wiring paste
According to another aspect of the present inventions
one of the foregoing ob~eCts can be achieved by providing
an opto-electronic hybrid integrated circuit, having a
packaged platform, the platform including: an optical
waveguide hava:ng an under-cladding layer, a core, and an
over-cladding layer provided on a ~~ubstrate; a silicon
terrace funct~.oning as a device moL~nting part provided as a
protrusion adjacent to the optical waveguide; and an
electrical wiring part provided adjacent to the silicon
terrace and including a dielectric layer and a conductor
pattern provided on the surface or inside of the dielectric
layer, wherein on the platform, an optical functional
device may be mounted on the optical device silicon
terrace, with an optical device surface facing down and at
least part of the optical device surface contacted with the
silicon terrace upper surface, and maintaining optical
coupling with the optical waveguide and electrical
connection with a conductor pattern of the electrical
wiring part.
According to another aspect of the present invention,
one of the foregoing objects can be achieved by providing
an opto-electronic hybrid integrated circuit, having a
platform, the platform including: an optical waveguide
including. an under-cladding layer, a core, and an over-
cladding layer provided on a substrate; a silicon terrace
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,,% ' :.
''_..f
functioning as a device mounting part provided as a
protrusion ad_~acent to the optical waveguide; an electrical
wiring part provided adjacent to tree silicon terrace and
including a d3_electric layer and a conductor pattern
provided on the surface or inside of the dielectric layer;
and an electronic circuit silicon terrace provided as a
protrusion on the substrate in the electrical wiring part
and functioning as an electronic circuit mounting part;
wherein on the platform, an optical functional device may
10 be mounted on the optical device silicon terrace, with an
optical device: surface facing down and at least part of the
optical device: surface contacted with the silicon terrace
upper surface, and maintaining optical coupling with the
optical waveguide and electrical connection with a
conductor pattern of the electrical wiring part, and an
electronic circuit may be mounted on the silicon terrace
while maintaining thermal connection with the silicon
terrace.
Height of conductor pattern upper surface on the
20 dielectric layer in the vicinity of the electronic circuit
silicon terrace may be set lower than the electronic d
circuit silicon terrace upper surface, the electronic
circuit may be held with part thereof contacted with the
electronic circuit silicon terrace, and at least part of
electrode~on the electronic circuit surface may be fixed
while maintaining electrical connection with a conductor
pattern on the dielectric layer corresponding to the
electrode through electroconductive material.
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The optical functional device may be contacted and fixed
with a backside electrode electrically contacted with a
thermal conductive material provided on a sub-carrier, the
sub-carrier including an outer side surface and an inner side
surface, the inner side surface including a recess surface,
the thermal coxlductive material being provided on the inner
side surface for electrically connecting the recess surface to
the silicon terrace upper surface; the silicon terrace may be
divided into two or more sections, and. a spacing between the
divided silicon terrace may be filled with the dielectric
layer; a first conductor pattern to th.e elecarode provided on
the active layer side surface of the optical. functional device
and a second conductor pattern corresponding to the optical
functional device backside electrode a.re prcavided on the
dielectric layer in the periphery of the silicon terrace;
height of upper surfaces of the first and second conductor
patterns may be set lower than the sii.icon terrace upper
surface; the optical functional device mounted on the
sub-carrier may be mounted on the platform vaith the device
surface facing down and while the periphery of the optical
device surface maintaining connection and thermal connection
with the silicon terrace surface; the optical functional
device surface electrode and the first conductor pattern are
electrically connected through an electroconductive bonding
material; and the optical functional device backside electrode
may be electrically connected with the second conductor
pattern through the conductor pattern on the sub-carrier
protrusion and an
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electroconducti_ve bonding material.
The optical functional device may be contacted and fixed
with a backside electrode electrically contacted with a
thermal conductive material provided an a sub-carrier, the
sub-carrier including an outer side surface and an inner side
surface, the inner side surface including a recess surface,
the thermal conductive material being provided on the inner
side surface for electrically connecting the recess surface to
the silicon terrace upper surface; the silicon terrace may be
divided into tsao or more sections, and may have an inclination
angle; the per:ephery of the divided silicon terrace may be
filled with the dielectric layer; on the dielectric layer in
the periphery of the silicon terrace, a first conductor
pattern corresponding to the electrode provided on the active
layer side sur'~ace of the optical functional device, and
height of the first conductor pattern may be set lower than
the silicon te:=race upper surface; a thin film electrode
corresponding to the optical functional device backside
electrode may be formed on part of the silicon terrace upper
surface and the inclined side surface, and the thin film
electrode may be electrically connected. with a second
conductor pattern provided on the dielectric layer; wherein
the optical functional device mounted on the sub-carrier ma.y
be mounted on the packaged substrate with the device surface
facing down and while the periphery of the optical device
surface maintaining connection and thermal connection with the
silicon terrace surface; wherein the optical functional device
surface electrode and the first
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E
I
conductor pattern are electrically connected through an
electroconductive bonding materials and wherein the optical
functional device backside electrode may be electrically
contacted with the second conductor pattern through the
conductor pattern on the sub-carrier protrusion and the
thin film electrode on the silicon terrace.
Distance I:rom the sub--carrier outer side surface to the
optical functional device active layer may be set to a
desired setting value D in the optical functional device
10 fixed on the sub-carrier; a guide structure formed of the
optical waveguide material may be provided in the vicinity
of the silicon terrace: distance from the guide structure
inner side surface to the optical wavegu3.de core center rnay
be set to the setting value D; and the optical functional
device may be :mounted on the silicon terrace while the sub-
carrier outer side surface maintains contact with the guide
structure inner side surface.
The optical waveguide may inclLide at least one signal
line optical waveguide and at least monitor optical
20 waveguide;
the optical functional device may have a signal port
and a monitor ;port formed at positions individually
corresponding 'to the signal optical waveguide and the
monitor optical waveguide on the platform~ and the monitor
optical waveguide~ 'of -thw p~laWform and the monitor port of '
the optical functional device are optically coupled and, at
the same time, the optical functional device may be
disposed on tha_ silicon terrace on the platform with the
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' .."
signal optical waveguide and the signal port optically
coupled.
According to another aspect of the present invention~
one of the foregoing objects can be achieved by providing
an opto-electronic hybrid integrated circuit, having: an
optical wavegu ide part including at least one signal
optical waveguide and at,l.east one monitor optical
waveguide which are formed on a substrate; an optical
device mounting part disposed at an end or a way of the
optical waveguide; arid an optical functional device
including a signal port for optically connecting the signal
optical wavegui.de of the optical waveguide part and a
monitor port for optically connecting the monitor optical
waveguide of the optical waveguide part, wherein the
monitor optical waveguide of the platform and the monitor
port of the optical functional device are optically coupled
and the signal optical waveguide of the optical waveguide
part and the signal port of the optical functional device
are optically coupled, and the optical functional device
may be disposed on the optical device mounting part with
optical couples are performed at the same time.
The other end of the waveguide of the individual
monitor optical waveguides optically coupled with the
optical functional device may be conducted to an end of the
opto-electrorizc-hybrid platform.
Two or more optical functional devices are mounted on
the opto-electronic hybrid packaged substrate, and the
monitor port of each optical functional device may be
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optically coupled with the monitor optical waveguide
connecting the optical functional device monitor port and
an end of the opto°electronic hybrid platform or the
monitor optical waveguide connecting hetween the two ar
more optical functional devices.
The optical functional device mounted on the opto-
electronic hybrid platform may have two or more monitor
ports, the monitor optical waveguides of a number
corresponding to the number of the monitor ports are
10 provided on the opto-electronic hybrid platform; and at
least one of the monitor ports may loe set to a width wider
than the signal port width, or at least one of these signal
optical waveguides may be set to a width wider than the
signal optical waveguide width.
According to another aspect of the present invention,
one of the foregoing objects can be achieved by providing
an optical sub-module, havinge an optical functional device
having an optical device height reference surface at a
predetermined distance from an active layers an optical
20 device holding surface for holding fhe optical functional
device; and a carrier having a carrier height reference
surface at a predetermined distance from the optical device
holding surface and a carrier electrical wiring; the
optical device height reference surface of the optical
functional device and the optical device holding surface of
the carrier being contacted and fixed, arid an active layer
side electrode of the optical functional device and the
carrier electrical wiring being electrically connected.
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The carrier may be formed of a substrate having
protrusion and recess and a dielectric layer formed on the
substrate recess, the optical device holding surface and
the carrier height reference surface are formed of the
substrate protrusion, and the carrier electrical wiring may
be formed on the dielectric layer.
The dielectric layer forming tl-,ie carrier may be a film-
formed material having an electrical wiring layer formed on
the surface and inside.
10 The carrier electrical wiring may be formed on the
surface and inside of the carrier.
According to another aspect of the present invention,
one of the foregoing objects can be achieved by providing
an opto-electronic hybrid integrated circuit, having: an
opto-electronic hybrid platform, the platform including: an
optical waveguide including an under-clad, a core, and an
over-clad; a silicon terrace, a dielectric layer, and a
conductor pattern provided inside or on the surface of the
dielectric layers thickness of the dielectric layer being
20 set so that height of the conductor pattern may be
substantially equal to a height of the optical wavegubide
over-clad surface; a carrier having an optical device
holding surface for holding an optical device, a carrier
height reference surface located at a predetermined
distance from~the~optical device holding surface, and a
carrier electrical wiring; and an optical device held on
the optical device holding surface; wherein a height from
the optical functional device active layer to the carrier
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height reference surface may be set nearly equal to a step
between the optical waveguide core and the silicon terrace
upper surface; the carrier electrical wiring and an active
layer side electrode of the optical functional device are
electrically connected forming an optical. sub-module; a
silicon terrace of the opto-electronic hybrid packaged
substrate and the carrier height reference surface of the
optical device sub-module contact, and the conductor
pattern on the dielectric layer of the opto-electronic
10 hybrid packaged substrate and the carrier electrical wiring
of the optical sub-module are electrically connected.
The above and other objects, effects, features and
advantages of 'the present invention will become more
apparent from the following description of embodiments
thereof taken in conjunction with t:he accompanying
drawings.
Fig. 1 is a schematic perspective view showing
20 construction called "silicon optical bench'°;
Fig. 2 is a graph illustrating high-frequency
characteristics of a 0.6 mm long coplanax wiring formed
directly on the silicon substrate:
Fig. 3A is a cross-sectional view showing a platform
having a structure of ridge type optical waveguide;'
Fig. 3B is a cross sectional view showing an optical
device mounting part of the platform as shown in Fig. 3A;
Fig. 3C is a cross sectional view showing a platform
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having a structure of embedded type optical waveguide;
Fig. 3D is a cross sectional view showing an optical
device mounting part of the platform as shown in Fig. 3D;
Fig. 4 is a schematic perspective view showing a
platform having a ridge type optical waveguide;
Fig. 5 is a schematic perspective view showing a
platform having an embedded type optical waveguide;
Fig. 6 is a schematic perspective view showing
construction of a hybrid optical integrated circuit
10 disclosed in Japanese Patent Application Laying-open No.
62-242362;
Fig. 7 is a schematic perspective view showing
construction of a hybrid optical integrated circuit
disclosed in Japanese Patent Application Publication 5-
2748;
Fig. 8 is a schematic perspective view showing an
example of a conventional optical semi-conductor device;
Fig. 9 is a schematic perspective view showing a first
embodiment of an opto-electronic hybrid integrated circuit
20 according to the present inventions
Fig. 10 is a schematic perspective view showing a
second embodiment of an,opto-electronic hybrid integrated
circuit according to the present invention;
Fig. 11 is a cross-sectional view showing an optical
device mounting part afwthe circuit as showmin Fig. 10;
Fig. 12 is a cross-sectional view taken on line A-A' of
Fig. 10;
Fig. 13 is a cross-sectional view taken on line B~B' of
- 22 -
CA 02441159 2003-09-19
- ~;.:~~
s Fig. 10;
Figs. 14A to 14D are cross-sectional views showing an
embodiment of a process for fabricating a glatform
according to the present invention, respectively;
Fig. 14A is a cross-sectional view showing a process
for forming a silica-based optical waveguide on a
substrate;
Fig. 14B is a cross-sectional view showing a step for
forming silicon terraces for mounting an optical device and
an electrical circuit, respectively;
Fig. 14C ~-s a cross-sectional view showing a step for
removing a layer of polyimide which is formed on the
terraces as shown in Fig. 14B to expose the terraces;
Fig. 14D is a cross-sectional view showing a step for
forming an electrical wiring part o:n the polyimide layer;
Fig:. 15 is a schematic perspective view showing a third
embodiment of an opto-electronic hybrid integrated circuit
according to the present invention;
Figs. 16A to 16E are cross-sectional views showing
another embodiment of a process for fabricating a platform
d
according to the present invention, respectively;
Fig. 16A is a cross-sectional view showing a step for
forming a part corresponding to a sa.licor~ terrace on a
substrate;
Fig. 16B a-s a cross-sectional view showing a step for
forming an under-cladding layer of silica-based optical
waveguide in a recess of the substrate;
Fig. 16C is a cross-sectional view showing a step for
- 23 -
CA 02441159 2003-09-19
forming a core pattern and an over-cladding layer on the
under-cladding layers
Fig. 16D i.s a cross-sectional view showing a step for
removing the core pattern and the over-cladding layer to
expose the silicon terraces
Fig. 16E is a cross-sectional view slxowing a step for
forming an electrical wring part on the under-cladding
layer;
Fig. 17 is a schematic perspective view showing a
10 fourth embodiment of an opto-electronic hybrid integrated
circuit according to the present inventiGn;
Fig. 18 is a cross-sectional view taken on line A-A of
Fig. 17;
Fig. 19 is a graph illustrating the curvature radius of
the substrate and the axis deviation between LD array and
an optical waveguide core;
Fig. 20 is a schematic perspective view showing an
optical device as a single body corresponding to the array
optical device as shown in Fig. 18;
20 Fig. 21 is a cross-sectional view taken on line A--A of
Fig. 20;
Fig. 22 i~> a cross-sectional side view showing the
circuit as shown in Fig. 18;
Fig. 23 is a cross-sectional side view showing a
circuit whose coplanar wiring part :is lowered as compared
t~ Fig. 18;
Fig. 24 is a cross-sectional side view showing a
circuit whose coplanar wiring part is formed on an under
- 24 -
CA 02441159 2003-09-19
i
. --
1
cladding part, and whose the under-cladding part is thick
as compared to Fig. 18;
Fig. 25 is a schematic perspective view showing a fifth
embodiment of an opto-electronic hybrid integrated circuit
according to the present invention;
Fig. 26 is a cross-sectional view taken on line D-D of
Fig. 25; ,
Fig. 27 i:9 a schematic perspective view showing a sixth
embodiment of an opto-electronic hybrid integrated circuit
10 according to the present invention;
Fig. 28 is a cross-sectional view taken on line C-C of
Fig. 27;
Fig, 29 is a schematic perspective view showing a
seventh embodiment of an opto-electronic hybrid integrated
circuit according to the present invention;
Fig. 30 is a cross-sectional view taken on line E-E of
Fig. 29;
Fig. 31 is. a schematic perspective view showing an
eighth embodiment of an opto-electronic hybrid integrated
20 circuit according to the present invention;
Fig. 32 is a cross-sectional view taken on line X--X of
Fig. 31;
Fig. 33 is a schematic perspective view showing a ninth
embodiment of an opto-electronic hybrid integrated circuit
according to the present'inverrtion;
Fig. 34 is a schematic perspective view showing a
eleventh embodiment of an opto-electronic hybrid integrated
circuit according to the present invention;
- 25 -
CA 02441159 2003-09-19
~.: i
Fig. 35 is a schematic perspective view showing a
twelfth embodiment of an opto--electronic hybrid integrated
circuit according to the present invention;
Fig. 36 is a schematic perspective view showing a
thirteenth embodiment of an opto-electronic hybrid
integrated circuit according to the present invention;
Fig. 37 is a schematic perspective view showing a
fourteenth embodiment of an opto-electronic hybrid
integrated circuit according to the present invention;
10 Fig. 38 is a schematic perspective view showing a
platform used in a fifteenth embodiment- of an opto-
electronic hybrid integrated circuit acc~arding to the
present invention;
Fig. 39 is a cross-sectional view taken on line A-A' of
Fig. 38;
Fig. 40 is a schematic perspective view showing a
platform used in a sixteenth embodiment of an opto-
electronic hybrid integrated circuit according to the
present invention;
20 Fig. 41 i;s a cross-sectional v5.ew taken on line B-B' of
Fig. 40;
Fig. 42 is a schematic perspective view showing a
seventeenth embodiment of an opto-electronic hybrid
integrated circuit according to the present invention;
Fig. 43 i~ a cross-sectional view taken on line C--C' of ,
Fig. 42;
Fig. 44A is a schematic perspective view showing an
eighteenth embodiment of an opto-electronic hybrid
- 26 -
CA 02441159 2003-09-19
_ Lc<_....~
integrated circuit according to the present invention;
Fig. 44B is a cross-sectional view taken on line B-B°
of Fig. 44A;
Fig. 45A ~.s a schematic perspective view showing a
nineteenth embodiment of an opto-electronic hybrid
integrated circuit according to the present invention;
Fig. 45B is a cross-sectional view taken on line B-B°
of Fig. 45A;
Fig. 46 i:> a schematic perspective view showing a
10 process for mounting an optical functional device on a sub-
carrier of the circuit as shown in :Figs. 45A and 45B;
Fig. 47 is a schematic perspective view showing a
twentieth embodiment of an opto-electronic hybrid
integrated circuit according to the present inventions
Fig. 48 i5 a cross-sectional view taken on line D-D° of
Fig. 47;
Fig. 49 is a schematic perspective view showing a
platform used in a twenty-first embodiment of an opto
electronic hybrid integrated circuit according to the
20 present invention;
Fig. 50 Is a CrOSS-Sectional view showing the platform
with a warping of Fig. 49:
Fig. 51 is a schematic perspective view showing a
platform used in a twenty-second embodiment of an opto-
electronic hybrid integrated circuit aca~rdi:ng to the
present invention;
Fig. 52 is a schematic perspective view showing a
twenty-second embodiment of an opto-electronic hybrid
-- 27 -
CA 02441159 2003-09-19
r,..
< integrated circuit according to the present invention;
Fig. 53 is a cross-sectional view taken on line III-
III' of Fig. 52;
Fig. 54 is a cross-sectional view showing the circuit
of Fig. 53 after reflow of a solder bump;
Fig. 55 iv a schematic perspective view showing a
platform used in a twenty-third embodiment of an opto-
electronic hybrid integrated circuit: according to the
present invention;
Fig. 56 is a schematic perspective view showing a
structure of the platform of Fig. 55 when flat-surface
alumina substrate is used as a substrate for the platform
and silica-based optical waveguide is used as an optical
waveguide for ~:he platform;
Fig. 57 is a schematic top plan view showing a twenty-
fifth embodiment of an opto-electronic hybrid integrated
circuit according to the present invention;
Fig. 58 is an enlarged detailed perspective view
showing a part t~III of Fig. 57;
Fig. 59 is a schematic top plan view showing a twenty-
sixth embodiment of an opto-electronic hybrid integrated
circuit according to the present invention;
Fig. 60A is a cross-°sectional view taken on line xa-Xa'
of Fig. 59, the view showing a laser diode which is mounted
on the platform; w - -
Fig. 60B is a crass-sectional view taken on line Xb-Xb'
of Fig. 59., the view showing a modulation array which is
mounted on the platform;
_. 2 8 _
CA 02441159 2003-09-19
~J~
Fig. &1 is a schematic top plan view showing a twenty-
seventh embodiment of an opto-electronic hybrid integrated
circuit according to the present invention;
Fig. 62 is a schematic top playa view showing a twenty-
eighth embodiment of an opto-electronic hybrid integrated
circuit according to the present in~erention;
Figs. 63A and 63B are drawings of a process for
alignment of an optical functional device which is to be
mounted on the circuit of Fig. 62;
10 Fig. 63A is a schematic top plan view showing core
adjustment and mounting of an 1D array as-the optical
functional device;
Fig. 63B is a schematic top plan view showing care
adjustment and mounting of the modulator array as the
optical functional device;
Fig. 64 is a schematic top plan view showing a twenty-
ninth embodiment of an cipto-electronic hybrid integrated
circuit according to the present invention;
Fig. 65 is a schematic top plan view showing a
20 thirtieth embodiment of an opto-electronic hybrid
a
integrated circuit according to the present invention;
Fig. 66 is a schematic perspective view showing an
optical device and a carrier in a first embodiment of an
optical sub-module which is possible to mount on a platform
of an opto-electronic hybrid integrated circuit according
to the present invention;
Fig. 67 i~; a cross-sectional view taken on line A-A' of
Fig. 66;
29
CA 02441159 2003-09-19
F..: .,.
Fig. 68 is a schematic perspective view showing a
second embodiment an optical sub-module which is possible
to mount on a platform of an opta-electronic hybrid
integrated circuit according to the present invention;
Fig. 69 is a schematic perspective view showing a third
embodiment an optical sub-module which is possible to mount
on a platform of an opto~electronic hybrid integrated
circuit according to the present invention;
Fig. 70 is a schematic exploded perspective view
showing a thirty-fourth embodiment of an opto-electronic
hybrid integrated circuit according to the present
invention, the circuit using the optical sub-module of
Figs. 66 and 67;
Fig. 71 is a cross-sectional view taken on line B-B' of
Fig. 70;
Fig. 72 is a cross-sectional view taken on line C-C' of
Fig. 70;
Fig. 73 is a schematic perspective view showing a
fourth embodiment an optical sub-module which is possible
to mount on a platform of a thirty-fifth embodiment of an
opto-electronic hybrid integrated circuit according to the
present invention;
Fig. 74 is a schematic perspective view showing a
thirty-sixth embodiment of an opto-electronic hybrid
integrated circuit according to the present inventiono
Fig. 75 is a schematic exploded perspective view
showing a fifth embodiment an optical sub-module which is
possible to mount on a platform of a thirty-seventh
-
,;; , . . : " ., ~,: ,:u,",~... ... ". m........ _ .....
J
CA 02441159 2003-09-19
1
Y ..5
embodiment of an opto-electronic hybrid integrated circuit
according to the present invention;
Fig. 76 is a schematic expladed perspective view
showing a thirty-eighth embodiment of an opto-electronic
hybrid integrated circuit according to the present
invention;
Fig. 77 is a schematic perspective view showing a sixth
embodiment an optical sub-module which is possible to mount
on a platform of a thirty-ninth embodiment of an opto-
10 electronic hybrid integrated circuit according to the
present invention;
Fig. 78 is a schematic perspective view showing a
seventh embodiment an optical sub-module which is possible
to mount on a platform of a fortieth embodiment of an opto-
electronic hybrid integrated circuit according to the
present invention;
Fig. 79 is a schematic perspective view showing an
eighth embodiment an optical sub-module which is possible
to mount on a platform of a forty-first embodiment of an
20 opto-electronic hybrid integrated circuit according to the
present invention;
Fig. 80 is a cross-sectional view taken on line D-Dq of
Fig. 79; and
Fig. 81 is schematic perspective view showing a forty-
second embodiment of an opta-electronic hybrid circuit
according to the present invention.
Embodiment 1
- 31 -
CA 02441159 2003-09-19
.-v
~i
~:./ Fig. 9 is a schematic perspective view showing a first
embodiment of the hybrid optical integrated circuit of the
present invention. The reference numeral 1 indicates a
substrate, and the present embodiment uses a silicon
substrate provided with a protrusion and s recess on the
surface. The reference numeral 30 indicates a silicon
terrace which functions ~s an optical device mounting part,
utilizing the protruded upper surface of the silicon
substrate 1. The reference numeral 31 indicates an optical
10 fiber used as an optical waveguide of the present
embodiment, which is held in an optimum position in a V-
groove provided in the silicon terrace 30. The reference
numeral 52 indicates a thin film electrode for contacting
with the surface electrode of the an optical functional
device disposed an the silicon terrace 30, which is formed
by patterning a l~t.m thick Au-Sn sol.der on a 0.5~.~.m thermal
oxide film provided on the silicon terrace 30 surface.
This thin film electrode 52 is electrically connected to a
surface electrode pattern 51 of the optical functional
20 device disposed on the surface of a. dielectric layer 50
6
formed in a recess of the silicon substrate of the
electrical wiring portion. The reference numeral .35
indicates a silicon terrace for electronic circuit. The
terrace 35 is surrounded by a dielectric layer 33, and a
conductor pattern 51 for electronic circuit is faraned on
the surface. In the present embodiment, the silicon recess
has an SO~.m step, the dielectric layer 50 has a thickness
of 50~m, and the conductor pattern 51 on the dielectric
- 32 -
CA 02441159 2003-09-19
layer 50 is formed by a S~Zm thick Au plating. As a result, a
25~m step is provided between the upper surface of the terrace
35 and the upper surface of the conductor pattern 51.
The reference numeral 37 indicates an optical functional
device, and the present embodiment uses a. semiconductor laser
(LD). The device 37 is put on a device mounting part on the
silicon terrace 30 in an upside-down configuration with the
active layer facing down, thereby achieving positioning in the
10 height direction between the fiber and LD without core
adjustment. Positioning in the lateral direction may be made
by monitoring the optical coupling efficiency of the optical
fiber and the LD, or using a guide structure formed at the
substrate side without core adjustment. In this case, the
active layer side electrode of the LD 37 contacts the thin
film electrode 52 on the silicon terrace 30, and electrically
connected with a conductor pattern 51 on the dielectric layer
50. In the thin film electrode 52, the solder is heat melted
to fix the LD 37 on the substrate. Since, in the present
20 embodiment, the LD is fixed using the thin film electrode 52
on the silicon terrace 30 as shown above, the silicon terrace
30 can be utilized as a heat sink. At the same time, since
electrical wiring except the connection with the optical
functional device is provided on the dielectric layer 50
having a sufficient thickness,. superior PligY1-frequency
characteristics can be obtained.
The electronic circuit 38 is disposed on the silicon
- 33 -
CA 02441159 2003-09-19
terrace 35 with the device forming surface facing down. In
this case, since the upper surface of the conductor pattern
51 on the dielectric layer 50 is set 25~im lower than the
upper surface of the silicon terrace 35, when an about 25Nm
thick solder bump is used, the surface of the central
portion of the electronic circuit can be contacted to the
upper surface of the silicon terrace 35 and, at the same
time, the electronic circuit electrode can be contacted
with the conductor pattern 51 of the dielectric layer 50
10 without using an electrical wiring. Therefore, in the
present embodiment, heat dissipation of the electronic
circuit using the silicon terrace 35 is possible, and a
high-frequency electrical wiring is achieved not through
the silicon substrate 1.
As described above, with the optical/electronic hybrid
integrated substrate of the present invention, the optica l
bench function of the silicon terrace, that is, optical
axis positioning function between the optical functianal
device and the optical fiber, a heat dissipation function
20 of the optical functional device arAd the electronic circuit
can be achieved, and the high-frequency electrical wiring
function can be provided.
Embodiment 2
Fig. 10 is a schematic perspecti~re view showing the
entire construction of a second embodiment of the
optical/electronic hybrid optical integrated circuit of the
present invention. Fig. 7.1 is a schematic cross sectional
34 -
CA 02441159 2003-09-19
ew in the vicinity of the circuit shown in Fig. 10, Fig. 12
is a cross sectional view taken along surface AA' in Fig. 10,
and Fig. 13 is a cross sectional view taken along surface BB'
in Fig. 10.
As shown in Fig. 10, the packaged substrate of the
present embodiment uses the silicon substrate 1 provided with
a protrusion and a recess on the surface as in Embodiment 1.
In the optical waveguide unit, a silica-based optical
waveguide 40 is formed in the recess of the silicon substrate
10 1. As shown in Fig. 12, the silicon terrace 35 is provided on
the electrical wiring part. In the electrical wiring portion,
a dielectric layer 50 comprising a polyimide resin is formed
in the recess of the silicon substrate, t:he conductor patterns
51 and 510 are provided on the surface and inside. The
silicon terrace 35 for electronic circuit is disposed at the
center of the electrical wiring portion.
As shown in Fig. 11, there is a l7,um step in the silicon
recess in the optical waveguide part on the left side of the
silicon terrace 35, and a silica-based optical waveguide 40
20 comprising an under-clad 41 (20~m. thick), a core 42 (6~m X
6/~m), an over-clad 43 (15~.m. thick) is stacked on top. The
waveguide structure is referred to as an "embedded type
structure", which has superior optical waveguide
characteristics since the core pattern is embedded in a clad
layer with a sufficient thickness.
The silicon terrace 30 has an inclined side surface, and
the upper surface and the electrical wiring side
_ 35 _
CA 02441159 2003-09-19
. J
surface are provided with a thin film electrode 52 farmed
by patterning a l~tm thick Au-Sn solder. Distance from the
surface of the thin filcr~ electrode 52 to the optical
waveguide core center is 5~tm. This size is equal to the
distance from the surface of the mounted LD to the active
layer, and positioning in the height direction of the
optical waveguide pore 4~ and the optical functional device
can be achieved without adaustment by mounting the optical
functional device on the silicon terrace 30 in the upside-
10 down condition with the surface of the active layer facing
down.
The electrical wiring portion on the right of the
silicon terrace includes the dielectric layer 50 comprising
a l5um thick polyimide on the recess of 25Nzn depth in
silicon, the conductor pattern 51 comprising a 5~1m thick Au
pattern formed on the surface, and the conductor pattern
510 formed inside. The conductor pattern 51 on the
dielectric layer 50 electrically contacts the thin film
electrodes 52 formed on the upper surface and the side
20 surface of the silicon terrace. In this case, there is a
a
step of about 10E1.m between the surface of the silicon
terrace 35 and the surface of the dielectric layer 50, and
such electrical wiring can be achieved between two layers
with different heights because the side surface of the
silicon terrace is inclined. When the silicon terrace 35
side surface is formed nearly vertical, it is difficult to
electrically connect the twa layers without using a wire
because the electrical wiring is opened by the step between
- 36 --
CA 02441159 2003-09-19
the thin film electrode on the silicon terrace and the
conductor pattern on the dielectric layer.
In the electrical wiring portion, as shown in Fig. 10,
the silicon terrace for electronic circuit is provided at
the center, where the electronic circuit is d9_sposed. The
electrical wiring connecting the silicon terrace for
optical device arid the silicon terrace for electronic
circuit is formed of a coplanar wiring comprising a central
conductor 51a and a ground conductor 51b. Electrical
10 wiring around the electronic circuit is formed of a
microstrip wiring comprising the surface conductor pattern
51 and the ground conductor 510 provided in the dielectric
material. As shown in Fig. 13, the ground conductor 51b of
the coplanar wiring and the ground conductor 510 of the
microstrip wiring are connected with a through electrode
520 provided in the dielectric layer.
Comparing the coplanar wiring and the microstrip
wiring, the former can be easily formed since it is formed
of a single layer of electrical wiring, but the wiring
20 density is not high. On the other hand, the latter has a
multilayer of electrical wiring and requires a complex
fabrication work, but can achieve a high wiring density.
Since, in the present embodiment, polyimide is used, which
is easy to form a multilayer wiring as a dielectric layer
in the electrical wiring portion, formation of the
microstrip wiring is possible. By the use of such a
packaged substrate structure, integration of the optical
functional device and the electronic circuit with a number
- 37 -
CA 02441159 2003-09-19
',--. 'v
~e ;
of connection terminals.
The optical functional device 37 mounted on the
packaged substrate is a semiconductor laser (LD), which is
mounted on a sub-carrier 44, which is formed by processing
a heat conductive material such as the silicon substrate.
The sub-carrier 44 has a protrusion and a recess formed on
the surface, and is fixed so that, after a conductor
pattern electrically connected from the protrusion surface
to the recess surface, the LD backside contacts on the
recess, and the LD backside and the conductor pattern on
the sub-carrier are electrically connected. To mount the
LD mounted on the carrier on the silicon terrace 30, the
active layer side surface of the LD is faced down and
contacted with the silicon terrace 30. the LD active layer
side electrode and a first thin film electrode 53a directly
contact each other; and the LD backside electrode contacts
a second thin film electrode 53b on the packaged substrate
through the sub-carrier. ''n this case, since the distance
from the thin film electrode surface on the silicon terrace
to the waveguide care center and the distance from the LD
device to the active layer are in line with each other,
positioning in the height direction with the optical
waveguide is completed merely by mounting the LD.
Positioning within the surface is made by monitoring the
coupling effect of the optical waveguide with the LD. The
silicon terrace is a reference surface with high precision
when mounting the device and, at the same time, functions
as a heat sink.
- 38 -
.. r,~ri .. > vE~:,~ ,. , ..~ . .. ...
CA 02441159 2003-09-19
The electronic circuit is mounted on the silicon
terrace using solder bump with the device surface facing
down as in Embodiment 1. In this case, as described above,
the height of the dielectric layer of the electrical wiring
portion and the conductor pattern surface formed thereon is
lower than the upper surface of the silicon terrace. As a
result of the structure,. it is possible to contactOmount
the electronic circuit on the SILICON terrace, and directly
contact all electrodes of the electronic directly with the
10 conductor pattern on the dielectric layer not through the
electrical wiring on the silicon terrace. Thus, the
electronic circuit can be mounted with superior heat
dissipation characteristics and high-speed operation.
As described above, in the present embodiment, the
silicon terrace for electronic circuit is provided in the
electrical wiring portion, and the height of the conductor
pattern surface around the circuit is set lower than the
SILICON terrace. Therefore, in the optical/electronic
hybrid integrated circuit of the present embodiment, the
20 electronic circuit electrodes and the conductor pattern on
6
the dielectric layer can be electrically directly connected
using solder bump and, at the same time, the electronic
circuit can be packaged while maintaining contact with the
silicon terrace. Further, since the side surface of the
SILICON terrace is inclined, in spite of the step between
the upper surface of the SILICON terrace and the conductor
pattern on the dielectric layer, the thin film electrode
provided on the SILICON terrace for the optical device and
- 39 -
CA 02441159 2003-09-19
~:5
f
the conductor pattern on the dielectric layer can be
electrically connected. Therefore, the electrode leads of
the optical functional device can be provided on the
SILICON terrace to enhance the heat sink effect, and all
electrical wirings other than the electrode leads can be
formed on the dielectric layer, thereby achieving superior
high-frequency characteristics.
With the present embodiment, the optical bench
function, that is, the optical axis positioning function
10 between the optical functional device and the optical fiber
and the heat dissipation function of the optical functional
device and the electronic circuit are possible, and the
high-frequency electrical wiring function can be provided.
The packaged substrate of the present embodiment can be
fabricated, for example, in steps shown in Fig. 14A to 14b.
First, by a method described later, a recess is formed on
the silicon substrate 1, and the silica-based optical
waveguide 40 comprising the under-clad layer 41, the core
pattern 42, and the over-clad layer 93 is formed (Fig~~
20 14A). Then, the surface of the SILICON substrate I is
processed to form the silicon terrace 30 for optical device
and the silicon terrace 35 for electronic circuit are
formed. In this case, on the bottom surface of the silicon
recess in the vicinity of the silicon terrace 35 for
electronic circuit, the conductor film silicon s~uah as gold
or copper is provided as a ground conductor layer (Fig.
14~). On top of it, polyimide is coated and cured as a
dielectric material for the electrical wiring portion,
40 _
CA 02441159 2003-09-19
unnecessary polyimide is removed by dry etching or the like
to expose the silicon terraces 30 and 35. Further, the
polyimide layer 50 is etched so that the layer is lower by
a predetermined step from the silicon terrace (Fig. 14C).
Finally, the conductor pattern 51 is formed on the surface
of the dielectric material 50, and the thin film electrade
52 is formed to electrically connect with the conductor
pattern 51 on the dielectric layer 50 on the silicon
terrace 30 for the optical device.
10
Embodiment 3
Fig. 15 is a schematic perspective view showing
construction of a third embodiment of the hybrid optical
integrated circuit of the present invention. A major
difference of the present embodiment from Embodiment 2 is
that the dielectric layer of the electrical wiring portion
is formed using the same material as the optical waweguide.
That is, the silicon recess is formed by providing a
33~.m step from the silicon terrace surface with the optical
20 waveguide and the electrical wiring portion. In the
silicon recess corresponding to the optical waveguide, the
silica-based optical waveguide 40 having the under-clad 41.
(35~.tm thick) , the core 42 (6~Lm X 6~im) , and the over-clad 43
(30E1m thick) is formed. On the other hand, on the silicon
recess corresponding to the electrical wiring portion, the
under-clad layer 41 of the silica-based optical waveguide
if formed as the dielectric layer 50. It has a thickness
of 25~m, and is 10~m lower than the upper surface of the
- 41 -
CA 02441159 2003-09-19
~r7
ssilicon terrace ZO for the optical device and the silicon
terrace 35 for the electronic circuit. Since the height of
the conductor pattern upper surface of the electrical
wiring portion is set lower then the upper surface of the
silicon terrace, important electrical wiring can all be
formed on the dielectric layer and connected using solder
bump, and the electronic circuit and the silicon terrace
can be contacted. Therefore, the packaged substrate has
high-frequency electrical characteristics and good device
heat dissipation function.
The structure of the present embodiment, in which the
dielectric material of the electrical wiring portion and
the optical waveguide are formed of the same material, has
an effect to simplify the substrate formation step. For
the effect, the substrate formation process will be
described with reference to Figs. 1~A to 16E. A first step
of the substrate fabrication is to :Form a step
corresponding to the silicon terrace on the substrate (Fig.
26A). In the present embodiment using silicon as the
substrate, a desired step can be formed by anisotropic
etching using an alkali etching solution such as KOH. By
appropriately selecting the crystal orientation of the
silicon substrate, the silicon terrace side surface can be
formed with an inclination of about 7~ as shown. After
that, the under=clad layer 41 of the dielectric optical
waveguide such as silica-based optical waveguide is formed
on the substrate recess, and the surface is flattened by
polishing or the like (Fig. 16B). Then, the core pattern
42 -
".-
CA 02441159 2003-09-19
~t
'x.42 and the over-clad layer 43 of the optical waveguide are
formed (Fig. 16C). After that, the optical waveguide
formed in the region of the electrical wiring including the
silicon terrace is removed by etching to expose the silicon
terrace. At this time, in the etching step of the silica-
based optical waveguide and the polymer waveguide
(polyimide optical waveguide, etc.), that is, in reactive
ion etching using a mixture of CFq and H2 or U2 gas as an
etchant, the silicon substrate 1 can be used as an etching
10 stop layer. Therefore, when the silicon terraces 30 and 35
are exposed as the etching advances; etching of the surface
does not advance.
On_the other hand, etching of the optical waveguide
portion is continued. As a result, the step between the
dielectric surface of the electrical wiring portion and the
silicon terrace can be formed by a single etching step
(Fig. 16D) .
Finally, the conduct or pattern is formed on the
dielectric surface of the electrical wiring portion, and
20 the thin film electrodes are formed or, the surface and the
inclined surface of the silicon terrace to form the
packaged substrate of tYze present embodiment (Fig. 16E).
In this case, an anisotropic etching of the silicon
substrate is used in the step shown in Fig. 15A, an
inclination can be automatically formed on the silicon
terrace side surface. Since this method can easily form
the inclination of the silicon terrace side surface, even
with a step between the silicon terrace and the upper
- 43 -
CA 02441159 2003-09-19
surface of the dielectric layer, the electrical wiring can
be formed without open circuit between both.
Thus, by forming the dielectric optical waveguide and
the dielectric layer of the electrical wiring portion using
the same material, the fabrication process can be
simplified compared. to formation of both parts with
different.materials. ,
Further, that the silicon terrace side surface is
inclined as described above, rather than formed vertically,
10 has an effect to considerably relax difficulty of packaged
substrate fabrication. That is, when the silicon terrace
side surface is formed nearly vertical, for example, in the
packaged substrate in Fig. 9, if there is a step between
the silicon terrace for optical device and the upper
surface of the dielectric layer 50, it is difficult to
electrically connect the thin film electrode 52 on the
silicon terrace 30 and the conductor. pattern 51a on the
dielectric Layer 50. Therefore, formation of the upper
surface of the silicon terrace and 'the upper surface of the
20 dielectric layer without a step in 'the process of Fig. 16D
in order to achieve an electrical wiring as shown in Fig. 9
using a silicon terrace having a vertical side surface
requires very high control over the etching time and
etching rate of the optical waveguide, which.makes
fabrication of the packaged substrate of this structure
extremely difficult. This difficulty is eliminated. by
inclining.the side surface of the silicon terrace as
described above.
44 -
CA 02441159 2003-09-19
Embodiment 4
Fig. 17 is a schematic perspective view of a fourth
embodiment of the hybrid optical integrated circuit of the
present invention, and Fig. 18 is a schematic cross
sectional view taken along line A-A in Fig. 1'7. The
Figures show an embedded type optical waveguide 80 in which
an under-cladding layer 60c, a core 60b, and an over-
cladding layer 60a are integrated on the silicon substrate
10 1. Since the example shown in Fig. 17 is intended to mount
a 400[am pitch 4-array optical device, the cores 60b are
arranged at 400Etm intervals.
As shown in Fig. 18, a coplanar line 61 comprising a
central conductor 61a of 400~im interval and a ground
conductor 61b is formed. A width Y~ of the central
conductor 61a, a gap interval S between the central
conductor 61a and the ground conduct or 61b, and a thickness
H of the silica-based waveguide layer between the coplanar
line 61 and the silicon substrate 1 are important
20 parameters affecting the high-frequency characteristics of
c
the coplanar line 51. The parameters will be described
later with reference to a table.
A mounting part 63 of an optical device 62 is formed by
etching the over-cladding layer 60a to expose the upper
surface of the under-cladding layer 60c, where an-
electrical wiring layers 63a and 63b are formed. In this
case, a S~m thick Au plated wire is used as the electrical
wiring layers 61a, 611x, 63a, and 63b, and the length of the
- 45 -
CA 02441159 2003-09-19
wiring layers 63a and 63b is set to less than 1 mm to
reduce the loss.
The central conductor 61a of the four coplanar lines 61
is connected by gold ribbon wires 64 to copper, block, and
a guide post 65a called ground post, connected to the
electrical wiring layer (electrode) 63a on the under-clad
60c, and connected to four electrodes 62c under the optical
device 62 through a solder pattern 66 comprising a gold-tin
alloy.
10 The ground conductor 61b of the coplanar line 61 is
similarly connected to the guide post 65b.by a gold ribbon
wire 64, connected to the electrical wiring layer
(electrode) 63b on the under-clad 60c, and connected to the
electrical wiring layer 67a of a silicon sub-carrier 67
through the solder pattern 66. Here, the silicon sub-
carrier is formed on the surface with a conductive layer
67a, and held by connecting the electrode 62b on the
backside of the optical device 62 to the conductive layer
67a of the recess by gold-tin solder. Therefore, with the
20 optical device 62 mounted on the mounting part 63, it is
possible to high-frequency drive with the four arrays by
the coplanar lane 61.
With the optical device 62 mounted on the mounting part
63, four active layers 62a of the optical device 62 are
optically coupled with the core 60b of the silica-based
optical waveguide at the front side in Fig. 17. In the
present embodiment,.positions of the electrode 62 and
solder pattern 66 of the optical device 62 are shifted to
- 46 -
CA 02441159 2003-09-19
....
,.-~y
. w,-.''
the side from directly beneath the active layer 62a of the
optical device 62, thereby preventing stress due to
mounting of the optical device from directly acting on the
active layer.
Here, the S parameter S21 and az~is deviation as an
optical bench function will be considered on the~main
parameters W, S, and H which affect the high-°frequency
characteristics of the coplanar line.
_. q~
CA 02441159 2003-09-19
O
V C
O
~ ,
t\ d c' ~
-
G ~ o 0 0
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1 I I 1 9
ri
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U
N 1 1 t 1 1 r1 -rl
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W ri
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t5 ~. 1"~ _ _ _ _ o ~ U
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~ gU ~ N N N N N U
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a ~ v= ~ t7
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-ri t1-1 ~t
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v cr
.ty r.1 ~u v -.~
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o .~ -.~ ti
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m
x ''~
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sa ~s a~ ,
n ~ ~ ~S
I 0 0 0 0 ~ p
v
>U .+J . ' U r-i
~ cr V a b' c~
1 N N N N N
x 1-1
~ ~ ~ U
Cf~ --ri 'C5 .~"..G ri
~d S-1 ~ f-'. .6.~ft~.4-~
H ~ r-l~e
, t2aO
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r-1 1 B I I 1 1-iU
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r
0 0 0 0 0
L
- 48 _
CA 02441159 2003-09-19
r. . _,
Table 1 shows the relationship between w and s and
transmission loss S~1 of the coplanar line, and the silicon
substrate 1 has an average resistivity of less than 1 ohm-
cm. For parameters W and S, since patterning is made by
coating a resist on the substrate having a several tens 1
step such as silica--based optical waveguide, it is
difficult to form less than 20~1.m with good repeatability.
Therefore, w and s are more than 20p.~m. In Table 1, the
10 thickness h of the under-clad 2c is 24~1m, and the thickness
H of the entire silica-based waveguide is 601, and w is
varied from Embodiment I-1 to Embodiment I-5. As a result,
the S parameter S21 is smallest when w and s are smallest,
and the loss is the smallest. Since, in Table 1, the
thicknesses h and H are not varied, the axis deviation is a
constant value of 0.7um even with 4 arrays.
- 49 -
CA 02441159 2003-09-19
~
O 'C~
U
c: ro c ~o ~ ~ ao o
. y N
o ~' > . . ra
..~ ~ 0 0 0 0 0 ~ ~ ~ U
O a~~~~ 11
w
x
0o N o ~ ~ .r ~r O 0
o ,-a -a o a o 0 0
.
oc~ .-af ~ 1 t i
4
N
O ~ t~a5 ~o v'c~"aM N N
"~
x QJ
V c90 0 0 0 0 0 o O U
N i i i ~ ~ o i -.-I
-.-i
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r~ 'O
w
o U
-a ..., ~. .~ ... c~
0 0 0 0 0 0 o S-1
U
W N N N N N N N 4y r-1
n1
O +~
-rl !.1 C 3
N N N N N N CV
~ O
a~ rt
t~.
va f1.
U
N
+~ O as p 'C3
~ f-I
O ~ ~ ~ 0 0 0 0 0 0 0
5 U ~ N t t~ o ~co 0 0 o I
-~
U G U ~' cn N e~ ~ N v, a c!'
~
Ol r-i ~
,
z3 .-1 N U
-.-t
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,u .,.a
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?
.1-i ~ O ,C to ..
~ -.i
ttS
N p H .ams U
3
, en
tn N Pj.~,~ .
e~ zs x o
O O O O O O O
Qy ~ p V o ~ o a ~r c ~r U .-f
.-~ ri N N 1n 07 O
x ~ "t U
s ~ ' ' (U sCS
t
-ri ,~..'
T3 ~..
ri
4-t S.a .G G .i~
N .!,
O r~ H ~ ,-!
R.,
, ~O
'j N M ~ M to j ~ S-i
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N ~ U .ss t.fa-~.u +~ ~ ~
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- 50
CA 02441159 2003-09-19
~"''~
Table 2 utilizes the results of Table 1 so that (w, s)
- (20,20)uzn where S21 is smallest, and S parameter and. axis
deviation are picked up when the thickness h of the under-
clad 60c and H are varied. In Reference Examples II-1 and
II-7, the prior art structure is applied, and in Reference
Examples II-2 to II-5, h and H are varied. As a result,
good results are shown irk the vicinity of H = 50 to 90.
Axis deviation is caused by warping of the substrate due to
the thickness of the clad, which leads to an increase in
10 coupling loss.
Table 2 will be described in detail. As 'to the
thickness H dependence, in general, loss in the
high-frequency must be less than 1.0 dB/cm and, considering
wide applications of the hybrid substrate of the present
embodiment, it is required to be less than 1.5 dB/cm. From
Table 2, to reduce the loss to less than 1.5 dB/cm, the
total thickness H of the silica layer must be more than 50
Elm .
Further, for the hybrid substrate to maintain a good
20 optical bench function, warping of the substrate must be
b
small. In Fig. 38, since the silica-based optical
waveguide layer and the silicon substrate 1 differ in
thermal expansion coefficient, warping of substrate
increases as H increases. When warping of the substrate is
increased, the optical waveguide end face and optical
device, for example, the active layer of the LD array,
causes dislocation, resulting in optical coupling loss and
impairing the optical bench function. Since the opto-
- 51 -
CA 02441159 2003-09-19
electronic hybrid packaged substrate is required to be
developed to 4 X 4 switches and the like, it is required
that, for example, a 4-array LD module or the like is
mounted on the substrate to deal with array application of
the optical device. As a result, the value in the right
column of Table 2 (axis deviation) is required to be
decreased. Fig.. 1~ shows relationship of the thickness H
of the silica layer on the silicon substrate, warping of
the silicon substrate (curvature radius), and the axis
deviation in a 400N.m interval 4-array LD module. It can be
seen from the Figure that the thickness H must be less than
120ø1m to reduce the axis deviation to less than l~.m.
In summary, in the silica-based optical waveguide in
Fig. 18, to satisfy the high-frequency electrical wiring
function and the optical bench function for mounting the
optical device, H is required to be more than 50),t,m and less
than 120u.m.
As can be seen from Table 1 and Table 2, the example
shown in Fig. 17 is practically and optimally usab7_e as a
low-loss optical waveguide, which uses a hybrid optical
integrated substrate of under-clad h = 30j.dm, core diameter
- 6 x 6~.m, over-clad = 30~.m, and total silica layer = 66).lam.
Further, transmission loss of the optical waveguide shown
in Fig. 17 is less than 0.1 dB/cm, and when LD is used as
an optical device-,-good characteristics are obtained in
high-speed modulation of 10 GHz for the 4 arrays.
Thus, the present embodiment has a low-lass optical
waveguide function, an optical bench function with reduced
- 52 -
CA 02441159 2003-09-19
axis deviation, and a high-frequency electrical wiring
function with reduced S21~
Figs. 20 and 21 show the 4-array of Fig. 17 divided
into discrete devices. In this case, since it is not an
arrayed device but the arrayed device is divided into
discrete devices, even when warping of the substrate
occurs, no axis deviation. occurs, and it has the above
three functions even except the condition of the thickness
H of less than 120~m. On the contrary, when discrete
devices are combined into an array, the condition of
thickness H of less than 120~.cn is added.
In the present embodiment, the coplanar line 61 is
formed on the surface of the over-clad, but the coplanar
line can also be formed in other positions. Fig. 22 shows
a side view of Fig. 17, Fig. 23 shows a side view in which
the over-clad ~Oa under the coplanar line 61 is made thin,
and Fig. 24 shows a side view in wh:Cch the entire under-
cladding layer 60c is made thicker, and the coplanar like
61 is formed directly on the under-clad 60c. As in the
examples shown in Figs. 23 and 24, even when the height of
the coplanar wiring layer is set lover than the upper
surface of the over-clad of the optical waveguide, it can
also be used as a good opta-electronic packaged substrate
as well.
Embodiment 5
Embodiment 4 was an example using a general-purpose
silicon substrate (resistivity: up to 1 ohm-cm). On the
- 53 -
,.,. ", " ....z. ry. .~f.»:~ . .u~..~ .~-~.~.~:_~-~ty .r-.._~_,. _;._._ rw~___
.____._.__.
CA 02441159 2003-09-19
other hand, the high-frequency electrical wiring function
can be even further improved by increasing the resistivity
of the silicon substrate. This enables a thinner
silica-based optical waveguide between the coplanar line
and the silicon substrate, and construction is possible as
shown in Fig. 25 in which the high-frequency line can be
placed on a thinner under; clad 2c, thereby expanding the
application.
First, far the structural parameter of the substrate
10 used in Fig. 25, optimization is made in view of the high-
frequency electrical wiring function and the optical bench
function by Fig. 26 which has the same structure as the D-D
cross sectional view of the high-frequency electrical
wiring portion in Fig. 25. In Figs. 25 and 26, the
reference numeral 61a indicates a central conductor of the
coplanar line, 61b indicates a ground conductor, 61c
indicates an under-cladding layer, and 1 is a silicon
substrate having a higher resistance than Embodiment 1
shown in Fig. 17.
20 In Fig. 25, 67 is a sub-carrier of silicon, and the
a
optical device 62 is held in the recess. A conductive
layer &7a is formed on the surface of the sub-carrier 67,
which electrically connects with the backside of the
optical device 62. By connecting both legs of the sub-
carrier to solder pattern 67b, the coplanar line 61 and the
electrode 62b on the backside of the optical device 62 are
electrically connected. On the other hand, the electrode
62c on the side of the active layer of the optical device
- 54 -
CA 02441159 2003-09-19
is connected by a solder pattern 6i'b formed on the central
conductor 61a of the coplanar line 61, and the optical
device 62 can be operated by the coplanar line. Further,
the silicon sub-carrier 67 absorbs heat generated in the
optical device, and dissipates the heat to the air or the
coplanar line 61. In the present embodiment, the position
of the solder pattern 67b connecting to the electrode 62c
of the optical device 62 is shifted. to the side from
directly beneath the active layer 62a of the optical
10 device, thereby preventing a stress associated with
mounting of the optical device from. acting directly on the
active layer.
Main parameters affecting the high-frequency
characteristics of the coplanar line are thickness h of the
silica under-cladding layer between the coplanar line and
the silicon substrate, width w of the central conductor 61a
of the coplanar line, and gap spacing s between the central
conductor 61a and the ground conductor layer 61b of the
coplanar line.
20 RelationsYiip between the parameters S and w and S
parameter S21 representing loss of the coplanar line is
shown in Table 3, and the S parameter 521, and axis deviation
by the thickness of the under-clad 2c based on s and w of
Table 3 are shown in Table 4.
The silicon substrate uses one which has an average
resistivity of up to 50 ohm-cm. For w and s, since
patterning is .made by coating a resist an the substrate
which has a step of several tens Eun such as silica-based
- 55 -
CA 02441159 2003-09-19
r~ w
,"~l~
optical waveguide and the like, it is difficult to form in
less than 20~.tm with good reproducibility. Further, Figs.
25 and 26 are examples of discrete optical devices, and
Table 4 shows axis deviation due to warping of the
substrate when a 4-array optical device is mounted in 400~.~.m
pitch.
First, changes in conductor width w which is a
structural parameter of the coplanar line and S parameter
S21 by the gap s are shown in Table 3.
-~ 5 6 -
CA 02441159 2003-09-19
' W N
U
b ~ v' a' a'~r c~
0 0 0 0 0 .~ V
~
~ ~
U
. ,~ -rf
a G II
O w ~ ~~
x
N N C' l0.-tO 'L3 O
O
~
~ N .~ai i1 ~
C4 ~
,fir
O O n7O t~ tntt)t17
Cx3~-tO o o O U1 U
U
N 1 1 1 I 1 -r-I -ri
G
W T~ U
td 'CS
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O U
...~. .-.,.. ttf
O ~ y ~ ~ N N N N N
~ ~ U ~ 3 O m
.. N l a~ N R W r
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N
GU
b
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1J 13 1J1) ;J 3 Td
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H
CA 02441159 2003-09-19
...,z
As can be seen from Table 3, a.s results of Embodiments
III-1 to III-5, (w, s) - (20, 20)x. gives the smallest loss
as in Table 1.
- 58 -
CA 02441159 2003-09-19
W
U r o r
,q ~ ,Zs at n o o O ..,
~ O O ri e-i .-~M 61 M
O O O O C7e-fr1 ri r-i"
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~~~~ 9~1
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-ri
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i
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0
.l U
.
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w
4-1 ~
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rr V M ~' In in l0O1 N M t
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to
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m U
m w
a~ w,
x
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~ y n ~ o c~ 0 0 0 <? O "O
o sr~ o 0 o e~ ~ O U r-i
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.,O
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.C~, H H H H H H H H
S-1
c!'~ U U U ~ ~ '~ '1'3U U
1~
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m
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'4 '
- 59 -
CA 02441159 2003-09-19
Further, as shown in Table 4, with (w, s) _ (20, 20)Eun,
S21 and axis deviation with changes in the under-clad
thickness h are shown. As shown, in order to reduce S21 to
less than 1.5 dB/cm at 10 MHz, h is required to be more
than 20 Eim. By increasing the resistivity of the silicon
substrate, the thickness of the silica layer on the silicon
substrate can be reduced to less than Embodiment Z.
Further, to reduce the axis deviation between the active
layer of the optical device and the care of the optical
waveguide, the total thickness H of the silica layer must
be less than 120 um. v
As described above, in the silica-based optical
waveguide of Figs. 25 and 26, it has been found_that, to
satisfy the high-frequency electrical wiring function and
the high precision optical bench function for mounting the
optical device, the under-clad thickness h of the silica-
based optical kraveguide must be more than 20 ~tm. Further,
when an optical. device of 4-array or more is mounted in 400
dun pitch, a condition is added that the total thickness H
of the silica-based optical waveguide must be less than 120
a
~azn .
As can be seen from Table 3 and Table 4, an example
using a discrete LD module as an optical device using a
substrate in which under-clad h = 30ELm, core diameter = 6 X
6Nxn, over-clad thickness = 30pa,~m, amd the entire silica
layer of 66~tm is shown in Fig. 25, which is considered to
be optimum_as a low loss silica-based optical waveguide.
As described above, the hybrid optical integrated
- 60 -
_,..- .. _...d. __, , ..a.~ . -;. :.~-__ .. ~-.a-. .... -~., < -~ R~-3:'e.~
ca.:.. , a~ ~k .-_.sa,~..--~~. , .~ .._-~_-..>...-.-~_,.-.,~ . ....H-
__b...__.,.m.
CA 02441159 2003-09-19
' substrate of Embodiment 5 satisfies not only the proven low
loss optical waveguide function, but also the
high-frequency wiring function for driving the optical
device and the high precision optical bench function for
ensuring the flatness of the substrate. Further, as
compared with Embodiment l, the present embodiment uses an
under-clad of 30 ~m thick which has been proven as optical
waveguide, and does not use a guide post or the like,
thereby simplifying the electrode structure. Therefore,
the high-frequency characteristics are improved and the
packaging work has been simplified.
Transmission loss of the optical waveguide of the
hybrid optical integrated circuit w<~s less than 1 dB/cm.
Further, when bD is used as an optical device, good
characteristic) are shown in high-speed modulation at 10
GHz.
Embodiment 6
Fig. 27 is a schematic view showing a sixth embodiment
of the hybrid optical integrated circuit of the present
invention. The present embodiment uses the silicon
substrate 1 having protrusion and recess in place of the
flat silicon substrate 1 used in Embodiment 4. The under-
cladding layer 60c of the silica-based optical waveguide is
formed in the recess of the silicon substrate I~ and
protrusions 68a and 68b of the silicon substrate are
exposed to an optical device mounting part 68 as shown,
which can be used as a height reference surface when
- 61 -
CA 02441159 2003-09-19
mounting the optical device 62.
The B-B cross section in Fig. 27 is the same in
structure as i.n Fig. 26, wherein the under-cladding layer
60c of thickness h = 30p,~m which is optimized in Table 3 and
Table 4. A C-C cross sectional view in the optical device
mounting part 68 is shown in Fig. 28. On the protrusion
68a of the silicon substrate 1, a thin electrode 62c is
formed separately from the active layer 62a of the optical
device 62, which functions as the height reference surface
and an electrode of the optical device 62.. The coplanar
line uses a 5~zn thick gold plating layer on the under-olad;
but uses a gold spatter film of less than. lEtm in thickness
on silicon terraces 68a and 68b. The electrode 62b on the
backside of the optical device 62 is held. by the silicon
sub-carrier, aced electrically connected to the electrode
61b on the silicon terrace 68b through the conductive layer
67a on the surface of the silicon sub-carrier 67a and a
conductive bonding material 69.
Using the silicon substrate having the protrusion, the
silicon protrusion 68a can be used as the mounting height
reference surface, and positioning of the optical device 62
and the optical waveguide core 62a can be made with even
higher precision. Heat generated in the optical device 62
can be dissipated to heat conductive silicon substrate 1
through the sub-carrier 67 and 68b and, since the substrate
1 is closely contacted to a highly heat conductive package
70, heat dissipation of the optical device 62 is remarkably
improved.
- 62 -
,. , .... , , .. , . ., . ", w , ~ ." " .-,.", , exx-xa"n r._. . , ~ ~. _. ...
..,s" .. , " .r."- .-~~, ~ _. -~w
CA 02441159 2003-09-19
High-frequency characteristics in the coplanar line 14
are also good as in Embodiment 4. Although the high-
frequency line is located immediately above the electrode
on the silicon terraces 68a and 68b, the distance flowing
high-frequency is actually very short, and the loss is very
small.
The thickness H including the under-clad 60c, the core
60b, and the over-clad 60a uses 66 ~l.m opt.imized in Table 9,
which is a good optical bench with reduced warping.
10
Embodiment 7
Fig. 29 is a schematic perspective view showing a
seventh embodiment of the hybrid optical integrated circuit
of the present invention. The present embodiment uses an
LD 71 as the og7tical device 62 of Embodiment 6, and further
an LD driver 72 for driving the LD is mounted on the same
substrate 1. The optical device mounting part 68 is the
same in structure as in Fig. 27. The input side coplanar
like 61b to the LD driver is the same in structure as the
20 coplanar line 61 in Fig. 27. However, the coplanar line
61a connecting the LD driver 72 and the LD 71 is insexted
with a high-frequency chip resistor 73 for impedance
matching of the 50-ohm coplanar line with the LD. An E-E
cross sectional view of the LD driver 72 is shown in.Fig.
30. As shown, the LD driver 72 is placed on a protrusion
79 of the silicon substrate in order to efficiently
dissipate heat of the LD driver 72 which has high heat
evolution. As in Embodiment 5, heat of the LD is
- 63 -
CA 02441159 2003-09-19
efficiently absorbed by the silicon substrate. By
contacting the entire LD module closely with a package of
highly heat conductive material, heat can be efficiently
dissipated. Connection between the LD driver 72 and the
coplanar line 61a and between the hD driver 72 and a DC
bias line 61c, as shown in Fig. 30, is made using a guide
post &5c and a gold ribbon wire 64 to reduce loss of t:he
high-frequency components to a minimum. Since the silicon
protrusion 74 contacts only the bottom surface of the
driver, and separates from the coplanar line, the high-
frequency characteristics are not deteriorated.
Transmission loss of the optical waveguide of the
hybrid optical integrated circuit was less than 1 dB/em.
Further, by inputting a 1O GHz modulation signal from a
coplanar line input end 75 to the LD driver 72 and
adjusting the amplitude and modulation potential by the DC
bias line 61c, the hD device showed good modulation
characteristics up to 10 GHz.
As described above, by utilizing the low-loss optical
waveguide function, high-frequency electrical wiring
function, and high precision optical bench function of the
hybrid optical integrated substrate of the present
embodiment, such a high-speed LD module can be achieved on
the same substrate of several cm square.
Embodiment 8
Fig. 31 is a schematic perspective view showing an
eighth embodiment of the hybrid optical integrated
_. . r. p°MIk 'w r ow., u. . tV~ ,(riW -Y" , , i ,... r.n <." , , , ,
..,..,. " . . ,. ".....,. ..,.
CA 02441159 2003-09-19
,.
substrate of the present invention. The present embodiment
has the same construction for the silica-based optical
waveguide, the optical device mounting part 13, the
coplanar wiring parts 61a and 61b, and the LD driver
mounting part 61c. However, the silicon substrate 1 is
extended to form a guide groove 77 so that a fiber 76 can
be connected on an end face 62d of the silica-based optical
waveguide without core adjustment. An X-X cross sectional
view of the guide groove 77 is shown in Fig. 32. 'The guide
10 groove 77 can be easily formed by etching the optical
waveguide and the silicon substrate. By the guide groove
77, the optical fiber 76 can be easily connected to the
optical waveguide core 62b without core adjustment, thereby
even further expanding application of the hybrid optical
integrated substrate.
Embodiment 9
Fig. 33 is a schematic perspective view showing a ninth
embodiment of the hybrid optical integrated circuit of the
20 present invention. In the present embodiment, portions
other than the silica-based optical waveguide have the same
construction as Embodiment 4, and tl~e si7.ica-based optical
waveguide is changed from the embedded type to the ridge
type. In association with the change, only the thickness
of the over-clad 62a is the same as that of a ridge type
optical waveguide 78 and is thus small. As previously
described, the ridge type optical waveguide is slightly
inferior in characteristics to the embedded type but, for
- 65 -
CA 02441159 2003-09-19 '_
4 other points, functions as a good packaged substrate for
hybrid optical integration.
Embodiment 10
A tenth embodiment (not shown) is the same as
Embodiment 4 shown in Fig. 20, except for the optical
device mounting part 3, in which the optical device
mounting part 63 is changed to an optical device mounting
part 68 using the silicon terrace as shown in Fig. 27"
Compared with Embodiment 4, good characteristics are
maintained in terms of the optical waveguide function and
the electrical wiring function as in Embodiment 4 and, as
described in Embodiment 6, the silicon terrace can also be
used as a height reference surface of optical device
mounting, and heat dissipation is improved.
Embodiment 11
Fig. 34 is a schematic perspective view showing an
eleventh embodiment of the hybrid optical integrated
circuit of the present invention. The present embodiment
is the same in structure as Embodiment 5 shown in Fig°. 25
except for the silica-based optical waveguides 60a and 60b,
and the embedded type optical waveguides 60a and 60b are
changed to ridge type optical waveguides 78a, 78b, and 78c.
As previously described, the ridge type optical waveguide
is slightly inferior to the embedded type optical waveguide
in optical waveguide characteristics, but Embodiment 11
functions as a good packaged substrate for hybrid
- 66 -
a
CA 02441159 2003-09-19
r':.,
integration a~> in Embodiment 5 in terms of the high-
frequency electrical wiring function and the optical bench
function.
Embodiment 12
Fig. 35 is a schematic perspective view showing a
twelfth embodiment of the hybrid optical integrated Ci.rCUlt
of the present invention.
The present embodiment is the same in structure as
Embodiment 6 shown in Fig. 27 except for the silica-based
optical waveguides 60a and 60b, and the embedded type
optical waveguides 60a and 60b are changed to ridge type
optical waveguides 78a, 78b, and 78c. As previously
described, the ridge type optical waveguide is slightly
inferior to the embedded type optical waveguide in optical
waveguide characteristics, but Embodiment 12 functions as a
good packaged substrate for hybrid integration as in
Embodiment 6 in terms of the high-frequency electrical
wiring function and the optical bench function.
As descrik>ed above, ira, the hybrid optical integrated
packaged substrate of the above embodiment, the
disadvantage of high dielectric loss at nigh frequencies of
the silicon substrate proven as a law loss silica-based
optical wav:eguide substrate is solved by using a silica-
based buffer layer with an appropriate-thickness ands in-
view of the high precision optical k~ench function, the
thickness of the silica-based optical waveguide is
optimized so that warping of the suk>strate is reduced to
- 67 -
,.; ~.~:~ . . ..;.x , .Yr~~u ~ _.~ . _ ~~~.~. -,~~~ _ ~;,~».. ~...: ..__~_aw_
_~ :....__ ._F ,~ _.~ __..mm_~ w_:~ _._ _.
CA 02441159 2003-09-19
..,.~
the extent that coupling loss is not increased due to axis
deviation relative to the optical waveguide even when an
arrayed optical device is mounted. Therefore, an active
device can be mounted to the optical waveguide with good
precision, and it can used as an opto-electronic packaged
substrate or a platform which operates with improved high-
frequency chazvacteristics.
The high-frequency electrical characteristics are even
further improved by enhancing the resistivity of the
10 silicon substrate, and sufficiently good high-frequency
characteristics can be maintained even though the thickness
of silica layer between the coplanar line and the silicon
substrate. Therefore, it is also possib:Le to use the
under-cladding layer of about 30~tm in th:~ckness which is
proven as an optical waveguide, and use a. structure where
the coplanar line is lower than the core layer, thereby
expanding the application.
Further, by using the silicon substrate with protrusion
and recess, forming the under-cladding layer of the silica
20 based optical waveguide is formed i:n the recess, and the
protrusion is exposed in the optical dev5_ce mounting part
and used as a height reference surface, thereby providing
an even higher precision optical bench function. In this
structure, the highly heat conductive silicon substrate can
be utilized as a heat-dissipation paate-for~thewoptical
device and its driving IC through the silicon terrace.
By forming a fiber guide groove in the silicon
substrate, it is possible to connect the fiber to the
- 68 _
Y r
CA 02441159 2003-09-19
silica-based optical waveguide without core adjustment.
Embodiment 13
Fig. 36 is a schematic cross sectional view showing a
thirteenth embodiment of the opto-electronic hybrid optical
integrated circuit of the present invention. The reference
numeral 1 indicates a silicon substrate having a
resistivity of 100 ohm-cm. In the optical waveguide
section, a silica-based optical waveguide 2 is formed in
'the recess provided on the substrate surface. The under
clad has a thickness of 30~tm, the core is 6~.tm thick, and
the over-clad is 30~1m thick. A dielectric layer 50
comprising the same material as the silica-based under-
cladding layer is formed in the silicon recess of the
electrical wiring part. Thickness c~f the dielectric layer
50 between the optical device silicon terrace 30 and the
electronic circuit terrace 35 is 20Wn, and a 5~izn thick
conductor pattern 51 is formed on top. Thin film
electrodes 52 are formed on the upper surface of the
optical device silicon terrace 30 and the inclined side
c
surface, and electrically connected to the conductor
pattern 51. True optical active device 37 is mounted upside
down on the silicon terrace 30 while maintaining electrical
connection with the thin film electrode 52. The electronic
circuit 38 is mounted on the silicon terrace 30 with the
device surface facing down, and fixed with the conductor
pattern 5l.with a 5 ~,zn high solder bump 53. In the
electrical wiring part on the right of the electronic
69 -
. ",~.~ . . .m~.,,"~, . . " . .~. . .,. .. .. , . , .W .... . . ..,... .. ,..
CA 02441159 2003-09-19
circuit, a second dielectric layer 520 is st.ac3ced on the
dielectric layer 50 comprising the silica-based optical
waveguide under-cladding layer. A multiiayered conductor
pattern 510 is provided in the second dielecaric layer 520,
and a conductor pattern 51b is provided on the surface.
In the present embodiment, the dielectric layer of the
electric wiring part is the dielectric: layer 50 comprising the
same material as the silica-based optical waveguide, the
second dielectric layer 520 comprising polyi_mide is provided
10 in part of the dielectric layer, and the muJ.tilayered
electrical wiring 510 is provided inside. Ysith this
construction, the optical device of low wir~_ng density and the
electronic circuit are connected with the h~_gh-speed coplanar
line, and the electronic circuit of high wiring density can be
wired using a multilayered microstrip wiring. Further, in the
present embodiment, the coplanar wiring area and the
microstrip wiring area use the under-clad layer of the optical
waveguide for the first dielectric layer. ~ls a result,
compared with Embodiment 2 for achieving the same object as
20 the present embodiments fabrication process of the pacl~aged
substrate can be simplified.
Embodiment 24
Fig. 37 is a schematic cross sectional view showing a
fourteenth embodiment of the hybrid optical integrated circuit
of the present invention. The substrate 1 in the present
embodiment is a ceramic substrate, and the optical
_ 70 _
CA 02441159 2003-09-19
.f. :..
deV3Ce silicon terrace 30 and the e.lectrc>nic circuit
silicon terrace 35 are provided on top. The optical
waveguide 40 is a silica-based optical waveguide. The
dielectric layer 50 of the electrical wiring part is formed
of polyimide. The present embodiment is characterized in
that not only the conductor pattern 51 is provided on the
surface and inside the dielectric layer ~;0 of the
electrical wiring part, but also an electrical wiring 530
is provided in the ceramic substrate.
In the present embodiment, silicon terrace with high
thermal conductivity is used for the device mounting part,
a silica-based optical waveguide is used as the optical
waveguide, in the electrical wiring part, conductor
patterns are provided inside and on the surface of the
dielectric layer on the substrate, and a conductor pattern
is provided also in the ceramic substrate which is easy to
provide a multilayered electrical wiring. As a result" the
packaged substrate of the present embodiment has a high-
performance optical wavegui.de function, the silicon bench
function, and the high-free~uency electrical wiring
function, and a very high density electrical wiring can be
formed.
To provide a silicon terrace on a substrate of
different material such as ceramic, for eacample, an anodic
bonding technique-caw -be used:' In this technique, a thin
Si02 film is previously formed on the surface of the ceramic
substrate and backside of the silicon~terrace, and both are
heated to join ,
- 71 -
CA 02441159 2003-09-19
Embodiment 15
Fig. 38 is a schematic perspective view showing an
optical packaged substrate in a fifteenth embodiment of the
hybrid optical integrated circuit of the present invention..
In the Figure, the reference numeral 7. indicates a silicon
substrate, on the surface of which are' formed protrusion and
recess structures. An aptieal waveguide part I is formed on
the silicon substrate recess, and 60b indicates a silica-based
10 optical waveguide core (6 X 6~.~m), whic:h is embedded in the
30um thick over-cladding layer 60a. In an optical device
mounting part II, the silicon substrate protrusion is exposed,
which is the height reference surface 30 when mounting the
optical device. The height reference surface 30 is divided
into two parts about the position corresponding to the
waveguide core 60b, and around of which is filled with the
silica-based optical waveguide under-cladding layer 60c. The
under-cladding layer 60c in the optical waveguide mounting
part II is 35~cm in thickness, an electrical wiring layer 500
20 of coplanar structure comprising the central conductor pattern
49 and the ground conductor pattern 51 is farmed on the
surface thereof, and the solder pattez:n 52 is formed at ane
end of the central conductor pattern, that is, in the gap of
the divided height reference 30. The thickness 35E.cm of then
silica-based optical waveguide under-cladding layer 60c is a
sufficient thickness far the electrical wiring formed on the
surface to provide superior high-frequency
72 -
CA 02441159 2003-09-19
characteristics without being affected by the silicon
substrate. The electrical wiring layer 500 and the solder
pattern 52 are both S~Cm in thickness. In the present
embodiment, the electrical wiring layer 500 is formed of gold,
and the solder pattern 52 is formed of a gold-tin alloy.
Fig. 39 is a cross-sectional view taken on line A-A° of
Fig. 38 when t:he semiconductor device is mounted on the hybrid
optical integrated substrate of Fig. 38. In the present
embodiment, the height reference surface 30 comprising the
10 silicon protrusion is divided into twa parts, the gap is
filled with the under-cladding layer 50c of the silica-based
optical waveguide, and the central conductor pattern 49 as the
electrical wiring and a solder pattern 52 are formed on the
surface. Therefore, in mounting the semiconductor optical
device 37, all the electrical wiring ).avers, including the
connection with an electrode pad 37a of the semiconductor
optical device, can be formed on the surface of the under-
cladding layer 60c of the silica-based optical waveguide
having a sufficient thickness. As a resultF effects of the
20 low resistivity and the high dielectric constant of the
silicon substrate on the electrical wiring can be neglected.
Since the silica-based optical wavegui.de is better as an
electrical wiring substrate than silicon substrate in terms of
the resistivity and dielectric constant, the electrical wiring
of the present embodiment can provide improved high-frequency
characteristics.
- 73
CA 02441159 2003-09-19
l....,
Height from the protrusion surface 30 as the height
reference surface of the silicon substrate I to the center
of the optical waveguide core 60b is set equal to the
height from the active layer 37b of the semiconductor
optical device 37 to the device surface. Therefore, in
mounting the optical semiconductor device 37, it is
possible to set the height of the silica-based optical
waveguide core 60b in line with the height of the active
layer 37b of t:h.e semiconductor optical device, merely by
10 mounting the semiconductor optical device upside down on
the height reference surface 30 of the protrusion of the
silicon substrate 1. At the same time, the protrusion of
the silicon substrate also functions as a heat sink of~ the
semiconductor optical device. Further, the optical device
mounting part is formed by removing unnecessary
silica-based optical waveguide laye~c by etching and, in
this case, the silicon substrate fuIlCtions as an etching
stop layer. Therefore, the height of the positioning
height reference surface 30 is can be determined with very
20 high precision.
Transmission loss of the optical waveguide of the
hybrid optical integrated circuit w<is Less than 0.1 dB/cm.
Further, the positioning precision of the semiconductor
optical device with the silica-based optical waveguide is
about 2 ~.m, and the semiconductor optical. device showed
good characteristics even in high-speed modulation at 10
GHz.
As described above, the present embodiment has the low-
- 74 -
CA 02441159 2003-09-19
;,1
loss optical waveguide function, the optical bench
function, and the high-frequency electrical wiring
function.
Embodiment 1G
Fig. 40 is a schematic perspective view showing an
optical packaged substrate in a sixteenth embodiment of the
hybrid optical integrated circuit of the present invention.
A difference off: the present embodiment from Embodiment l5
10 is that in the optical device mounting part II, an in-plane
direction positioning guide 79 of the semiconductor device
is provided, and other construction is the same as
Embodiment 15. In the present embodiment, the guide 7'~ is
formed on the same material as the optical waveguide 50,
that is, silica-based glass.
Fig. 41 is a schematic BB' cross sectional view of Fig.
40 when the semiconductor optical device 37 is mounted on
the substrate ~.. of Fig. 40. The guide 79 provided on the
substrate 1 is 5~.tm in height and, corresponding to this, a
20 6[am deep positioning groove 80 is provided in the
r
semiconductor optical device 37. Therefore, the
positioning groove 80 and the guide 79 on the substrate
contact with th.e semiconductor optical device 37 mounted
upside down, and merely by mounting the optical device on
the device mounting part so~that the uppeywurface of-the'-
optical device contacts the silicon protrusion surface 30,
positioning of the optical waveguide with the optical
semiconductor device is completed without core adjustment.
- 75 -
CA 02441159 2003-09-19
Embodiment 17
Fig. 42 is a schematic perspective view showing an
optical packagmd substrate in a seventeenth embodiment of the
hybrid optical integrated circuit of the present invention.. A
difference of the present embodiment from Embodiments 15 and
I6 is that the optical device 37 held by the sub-carrier is
mounted on the optical device mounting part II, and other
construction is basically the same as Embod:_ment 1 or 2.
Referring to Fig. 42, the solder pattern 52 for the
optical device active layer is formed on the central conductor
pattern 49 of the electrical wiring layer 5U0 of the optical
device mounting part II, and a solder pattern 53 for the s~ab-
carrier is formed on the ground conducaor pattern 51. A
condition where the optical device held on the sub-carrier 67
is mounted on the substrate 1 is shown in Fig. 43. Fig. 43 is
a C-C' cross sectional view of Fig. 4:.>. In Fig. 43, the sub-
carrier 67 is formed of the same material as the substrate 1,
and the optical device 37 is held on t:he recess 67a. A
conductive layer is formed on the surface of the recess 67a to
be conductive to the backside of the optical device 37. The
protrusion surface 67b of the sub-carrier 6°J is in line with
the surface (lower surface in Fig. 43;i of the optical device
37 or set lower than the height of the surface of the optical
device 37. Therefore, when the sub-c<~rrier 67 is mounted on
the device mounting part of the hybrid optical integrated
substrate,
- 76 _
CA 02441159 2003-09-19
the optical device 37 surface is contacted with the silicon
protrusion 30 to complete the height adjustment. The
electrode 37a at the active layer 37b side of the optical
device 37 is electrically connected with the central conductor
pattern 49 on the substrate through the solder pattern 52. In
the present embodiment, the positions of the electrode 37a of
the optical de~fice 37 and the solder pattern. 52 are shifted to
the side from directly beneath the optical c.evice active layer
37b. This prevents a stress associated with mounting the
10 optical device from acting directly upon the active layer.
Further, the e:Lectrode (not shown) on the optical device
backside passes through the conductive layer formed on the
recess 67a surface of the sub-carrier 67, and is connected to
the ground conductor pattern 51 on the: substrate through the
solder pattern 53. Further, the surface of the sub-carrier. 67
and the silicon protrusion 30 are thermally connected through
a thermal conductive material 81 to complete mounting of the
optical device 37 on the substrate.
In the present embodiment with the above construction,
20 since the optical device backside elecarode can be taken out
from the same surface as the active layer side electrode
through the sub-carrier 67, wireless :,urface packaging of the
optical device is possible. Therefore, by combining with the
substrate structure of the present inventioxl, superior high-
frequency characteristics can be provj.ded. Further, as a heat
sink of the optical device, a path foz~ directly heat
dissipating from the optical device
_ 77 _
CA 02441159 2003-09-19 w"
-.. ,.
surface to the protrusion of the silicon substrate 1 and a
path for heat dissipating to the protrusion of the silicon
substrate 1 from the optical device backside through the
sub-carrier are formed, thereby providing improved heat
dissipation.
Embodiment 18
Figs. 44A and 44B are schematic views showing an
eighteenth embodiment of the opto-electronic hybrid
10 integrated circuit of the present invention. Fig. 44A being
a perspective view, and Fig. 44B being a cross-sectional
view taken on line B-B~ of Eig. 44A. A difference of the
present embodiment from Embodiment 1'7 is in the structure
of connection of the sub-carrier 67 for holding the optical
functional device with the silicon terrace 30. That is,
the active layer side surface electrode 37a of the optical
functional dev~.ce 37 is connected and mounted through the
conductor pattern 51a provided on the dielectric layer 50
and a solder bump 53a which is an el.ectroconductive bonding
20 material. On the other hand, the device backside electrode
is connected t:°lrough the conductor pattern on the sub'
carrier 67 surface, the thin film electrode 52 provided on
the silicon terrace 30, and a solder bumg 53b provided on
the electrode 52.
In previor.~s Embodiment 17, where mounting the sub-
carrier C7 to the solder bump 53b, the conductor pattern
connecting to the sub-carrier 67 is provided on the
dielectric layer 60c. Therefore, it is required to coat a
_ 78 _
CA 02441159 2003-09-19
thermal conductive material between the sub-carrier 67 and
the silicon terrace 30 in order to enhance heat dissipation
effect of the device, which results in complex packaging
process. On the other hand, in the present embodiment,
since the sub-carrier 67 is mounted on the silicon terrace
30 through the solder bump 53b, the solder bump S3b can
also be utilized as a thermal conductive material. As a
result, the packaging process can loe simplified.
10 Embodiment 19
Figs. 45A and 4S8 are schematic views showing..a .
nineteenth embodiment of the opto-electronic hybrid
integrated circuit of the present invention, Fig. 45A being
a perspective view, and Fig. 45B being a cross-sectional
view taken on line B-B' of Fig. 45A. Differences of the
present embodiment from Embodiment 18 are that the packaged
substrate 1 is provided with a guide for directional
positioning in plane of the optical functional device 37a
and, in the sub-carrier holding the optical functional
20 device, the distance from the outer side surface 67c of the
sub-carrier 67 to the active layer 37b is set equal to a
distance D from a guide inner wall 60d of the packaged
substrate 1 to the optical waveguide core center. With
this construction, alignment-free optical device hybrid
integration is possible while using the sub-carrier.
To set the distance from the outer side surface b7c of
the sub-carrier 67 to the active layer 37b of the optical
functional device 37 to the desired value D, for example,
- 79 -
CA 02441159 2003-09-19
f .....,
~.=.~'
the optical functional device can be mounted on the sub
carrier as shown in Fig. 4~. That :is, the reference
numeral 90a indicates a device holding tool, on which
surface are provided a guide 90b fox setting the sub-
carrier at the desired position, and a marker 91 for
setting the optical functional devicre at the desired
position. Therefore, first the optical device 37 is placed
on the tool 90a so that the marker ~1 formed on the surface
at the active layer side of the optical device 37, with the
10 active layer side surface facing doran, i:; in line with the
market 91 on the tool 90a, and the optical functional-
device 37 can be mounted on the sub-carrier 67 with the
outer side surface 67c of the sub-carrier. contacted against
the guide 90b on the tool 90a.
A device mounting method in which the positioning
reference surface provided on the optica3. device is
contacted directly against the guide surface on the
packaged substrate had a problem in view of reliability of
the optical device because a lattice defect may be
20 generated in the optical device. On the other hand, in the
present embodiment, the outer side surface 67c of the
sub-carrier 67 is contacted against the positioning guide
90b, thereby achieving alignment-free device mounting
without contacting the optical functiona7_ device side
surface against the guide. Therefore, packaging is
possible without deteriorating the :reliability of the
device even in device mounting usin~~ a guide structure.
- $0 -
CA 02441159 2003-09-19
Embodiment 20
Fig. 47 is a schematic perspective view showing an
optical packaged substrate in a twentieth embodiment of the
hybrid optical integrated circuit of the present invention.
The present embodiment features that in the optical device
mounting part II, the ground conductor layer 51a is embedded
between the recess of the silicon substrate 1 and the under-
cladding layer &0c, and other subject matters are almost the
same as Embodiments 15 to i7. With the construction, in the
10 optical device mounting part II, the under-clad 60c, the
electrical wiring 49 provided on the surface, and the embedded
ground conductor 51a form the microstrip like, therehy
providing improved high-frequency characteristics. Using the
microstrip line, the electrical wiring density can be easily
enhanced compared to the coplanar line as used in Embodiments
15 to 17.
Fig. 48 is a schematic cross secaional view along line D-
D° in Fig. 47 when the LD array 37 is mounted on the hybrid
optical integrated substrate shown in: Fig. 47. The electrical
20 wiring part 500 is formed on the recess of the silicon
substrate 2 including the electrode connection part with the
optical device. Further, the protrusion surface of the
silicon substrate 1 is the height referencE: surface of the LD
array, and al,~o functions as a heat ;ink.
Thus, tha present embodiment can Simultaneously provide
the low-loss function, the high-frec~;~ency electrical wiring
function, and the optical bench function.
- 81 -
CA 02441159 2003-09-19
Embodiment 21
Fig. 49 is a schematic perspective view showing an
optical packaged substrate in a twenty-first embodiment of
the hybrid optical integrated circuit of the present
invention, showing a construction wr~ere the length of 'the
optical device is increased. The optical device 37 is a 15
mm long LiNb03 (LN) waveguide. The present embodiment is
formed of the silica-based optical waveguide on the silicon
substrate as irq other Embodiments. when the optical device
10 length is increased as in the present embodiment,
longitudinal warping of the substrate and optical device
cannot be neglected. In the present embodiment, the
silicon protrusion is divided into four parts, and the
individual par~:s are provided close to the optical
waveguide so that the silicon protrusion surface 30
functions as a good height reference surface even with a
warping in the substrate and the LN chip as shown in Fig.
50. Further, t:he electrical wiring 500 is formed as
coplanar line c>n the surface of the silica-based optical
20 waveguide under-cladding layer 60c formed in an area
between the fo~:~r-divided silicon protrusion.
As a result, as shown in Fig. 50, the silicon
pratrusion functions as a height reference surface even
when unnegligilrle warping exists in the substrate and LN
waveguide. Further; the electrical wiring part shows
improved high-frequency characteristics as in other
Embodiments.
Construction of the hybrid optical integrated substrate
- $2 -
CA 02441159 2003-09-19
. !
of the present invention has been described above with
reference to a case of silica-based optical waveguide
formed on the silicon substrate, however, the present
invention can also be applied to other materials. The
substrate of the optical waveguide has a sufficient
difference in etching speed to an enchant used in etching
to form the de°uice mount~;ng part in the optical waveguide,
and a combination of the substrate and dielectric optical
waveguide can 'rae used so that the substrate functions as an
IO etching stop layer to achieve the present invention. When
such a combinat ion of the substrate and the dielectric
optical wavegu:ide is used, the substrate protrusion
functions a high precision height reference surface.
Further, in view of the high-frequency characteristics of
electrical wiring, it is preferable no use an optical
waveguide of a material having a lower dielectric constant
than the substrate material.
Examples of such combination of the substrate and the
dielectric optical waveguide, in addition to the
20 silica-based optical waveguide/sili<:on substrate, include
silica-based optical waveguide/alumina ceramic substrane,
silica-based optical waveguide/nitri.de alumina ceramic
substrate, and use of a polymer-based dielectric optical
waveguide such as polyimide optical waveguide or the like
in place of the silica--based optica.7. waveguide. However,
when a substrate of poor thermal conductivity such as
alumina ceramiz~ is used, it is necessary no provide a heat
sink of the optical device on a separate substrate as shown
-- g3
CA 02441159 2003-09-19
f. ....
'~.:_.~
in Embodiment 20 (Fig. 46).
Further, examples of mounting the optical device have
been shown in the above individual embodiments, it is of
course possible to integrate an optical device driving
electronic circuit, or a signal processing electronic
circuit in addition to the optical device.
As described above, in the hybx:id optical integrated
substrate of the above embodiment, the basic structure is
that the dielectric optical waveguide is formed on the
recess on the substrate having protrusion and recess, and
the protrusion is used as an optical dev_LCe mounting part
to form an optical waveguide substrate having a terrace,
and the electrical wiring layer is formed an the dielectric
optical waveguide formed an the recess of the substrate.
As a result, even when a substrate having a relatively low
resistivity (e. g. silicon substrate) is used, or even with
a substrate having a relatively high dielectric constant
(e. g. alumina ceramic substrate), the electrical
characteristics are not affected by the .substrate, and
improved high~frequenoy characteristics can be obtained.
a
Further, in the hybrid optical integrated substrate of
the present invention in which the substrate protrusion of
the optical device mounting'part is divided into two or
more parts, the dielectric optical waveguide layer is
formed in the area therebetween, and the electrode pad part
for connecting the optical device to the electrical wiring
on the substrate is provided on the dielectric optical
waveguide layer, since all of the electrical wiring part
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CA 02441159 2003-09-19
can be formed on the dielectric optical waveguide layer,
the high-frequency characteristics are remarkably improved
and, at the same time, the upper surface of the substrate
protrusion can be used as a height reference surface for
mounting the optical device, thereby achieving precision
optical device mounting.
Embodiment 22
Fig. 51 is a schematic perspective view showing
construction of an optical packaged substrate in a twenty-
second embodiment of the hybrid optical integrated circuit
of the present invention. In Fig. 21, tyke reference
numeral 1 indicates a substrate, la is a substrate recess,
and 30 is a substrate protrusion. 'The reference numeral 92
indicates a dielectric optical waveguide, 92a is a signal
optical waveguide, 92b is a monitor optical waveguide, and
93 and 93a are cladding layers. The reference numeral 95
indicates an electrical wiring surface of the optical
device mounting part, 95a and 95b are a central conductor
and a ground conductor as an electra.cal wiring layer, and
96 is a fixing material. 'rhe surface of the substrate
protrusion functions as a height reference surface of the
optical device mounting part. Further, the surface is
provided with a monitor thin electrode 9°~.
The optical packaged substrate shown in Fig. 51 uses a
silicon substrate as the substrate l, and a silica-based
optical waveguide as the optical wa~c~eguide circuit 92. The
silicon substrate is provided with ;protrusion and recess of
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CA 02441159 2003-09-19
' 40~t.m step. An under-cladding layer comprising a g2[.Cm thick
silica-based glass is provided on the recess, a core of 6 X
6gam, a signal optical waveguide 92a with a refractive index
difference D=~9.°75~, and a monitor optical waveguide 92b are
formed on top. The distance between the protrusion of the
silicon substrate 1 and the waveguide core center is set to
5wcn in line with the size, of the optical functional device
which will be described later. An end of the monitor
optical waveguide 92b is disposed at a position
corresponding to the height reference surface comprising
the protrusion of the silicon substrate 1, and an end of
the signal opt ical waveguide 92a i:> disposed at a position
corresponding to the electrical wiring surface 95. A 0.5~n
thick thin film gold electrode is formed. on the height
reference surface 30. There is a ~LO~.m step between the
protrusion surface of the silicon substrate 1 as the height
reference suri~ace and the electrical wiring surface 9S, and
the under-cladding layer 93a of 30~.m thick silica-based
optical waveguide is provided undez: the electrical wiring
surface 5. The electrical wirings 95a and 95b are 4~m
thick gold plating pattern, and a Cl~.m thick solder bump is
formed as the fixing material at the end..
By mounting a desired optical functional device on the
optical device. mounting part on the optical packaged
substrate of t:he~above construction, a hybrid optical
integrated circuit as shown in Fig. 52 can be formed. An
optical functional device 100 in tree present embodiment is
a semiconductor laser, which has a signal port 100a and a
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CA 02441159 2003-09-19
monitor port 100b. Arrangement order and pitch of the
individual ports correspond to input/output end pitch of
the optical waveguides 92a and 92b of the optical waveguide
circuit. When the optical functional device 100 is mounted
upside down on the optical devise mounting part, the
monitor port 100b of the optical functional device is
disposed on the height reference surface 30 of the
protrusion of the silicon substrate 1, arad the signal port
100a is disposed on the electrical 'wiring surface.
10 Fig. 53 is a schematic cross sectional view taken along
line III-IIIo in; Fig. 52. The active la'rers 100a and 100b
of the semiconductor laser 100 are located at positions of
4.5~tzn from the device surface. 0n the other hand, in the
hybrid optical integrated substrate, the distance from the
surface of the thin film electrode 97 on the height
reference surface (silicon protrusion) to the optical
waveguide core center is set to 4.5Etm. '.Cherefore, by
merely mounting-the semiconductor laser tin the height
reference surface as shown, positioning in the height
20 direction of the optical waveguide and the semiconductor
laser can be completed.
To achieve in-plane direction ~>ositioning, positioning
must be carried out by monitoring the optical coupling
efficiency of the semiconductor laser and the optical
waveguide. Since the-surface electrode 100c under the
optical signal port 100a of the semiconductor laser does
not contact the electrical wiring 95 on the substrate 1 and
the solder bump 96, core adjustment cannot be performed
_ 8~ _
CA 02441159 2003-09-19
utilizing the optical signal port 100a. However, in the
present embodiment, the monitor optical waveguide 100a and the
monitor port 100b are provided on the hybrid optical
integrated circuit and the optical functional device, and the'
surface electrode 100c under the monitor port 100b is
contacted with the thin film electrode ~7 on the height
reference surface 30, core adjustment utilizing the monitor
port is possible.
The core adjustment can be carried out by functioning the
10 semiconductor laser as a light-receiving device. That is,
monitor light is transmitted in the monitor optical waveguide,
the light-receiving currant of the monitor port relative to
the monitor light is monitored to find a position where the
current is a maximum.
Further, as active alignment, it is possible to use a
method in which the LD 100 is caused to emit light, and a
position where the optical output from the monitor optical
waveguide is a maximum.
Then, as shown in Fig. 54, after core adjustment, by
20 heating to reflow the solder bump 96, since the solder bump
contacts the signal port upper electrode 100c of the
semiconductor laser, electrical connection and device :Fixing
between the semiconductor laser and the hybrid optical
integrated substrate can be achieved. In this case, the
contact position between the solder and the optical functional
device is set slightly shifted from immediately beneath the
port (active layer), thereby preventing a stress associated
with solidification
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CA 02441159 2003-09-19
i
shrinkage of solder from directly acting upon the optical
signal port of the optical functional device.
Excessive coupling loss by position deviation in the
hybrid optical integrated circuit was less than 0.5 dB.
This indicates that in the hybrid optical integrated
circuit of the present embodiment, LD surface packaging can
be achieved with a precision within lp,cmm. This becomes
possible first by using the silicon protrusion surface as
the height reference surface, and secondly by active
alignment for in-plane direction positioning.
As described above, in the present embodiment, it is
possible to make active alignment for core adjustment in
in-plane direction while functioning the optical functional
device, and optical device mounting by solder bump.
Therefore, compared with prior art device mounting by
passive alignment, optical device hybrid integration can be
achieved with higher precision, and problems of reduction
in mounting strength and large stress to the optical
functional device due to the use of thin film solder, which
was a problem in prior art active alignment, can be solved.
Further, the present embodiment uses a highly heat
conductive silicon substrate, protrusion and recess are
provided thereon, and the protrusion is used as a height
reference surface for optical functional device mounting.
With this construction; ~i~eat ~~o~.u'tion -of the optical
functional device can be efficiently dissipated through the
silicon protrusion.
In the present embodiment, the electrical wiring
_ 8g _
. . n~ ,~, a ry"~. ~,~ .: ~,P.~~ ~~~.u,"..,. , ~ "., .. ,.,. .. .
CA 02441159 2003-09-19
..'
surface of the optical device mounting part is provided on
the silica-based optical waveguide cladding layer with a
sufficient thickness. With such a construction, a hybrid
- optical integrated circuit with superior high-frequency
characteristics can be achieved. That is, i11 the prior art
as shown in Fig. l, in general, electrical wiring is formed
directly on the silicon ~SUbstrate, or on a very thin oxide
film having a thickness of about 0.5j-1m. However, such a
prior art construction had a problem in that the high-
frequency characteristics of the electrical wiring part are
considerably deteriorated by an influence of the silicon
substrate as a semiconductor. In the present embodiment,
this problem is solved by providing a dielectric layer of a
sufficient thickness between the silicon substrate and the
electrical wiring surface. In practice, it was confirmed
that the electrical wiring part in the hybrid optical
integrated circuit of the present embodiment had a band of
about 10 GHz.
Embodiment 23
Fig. 55 is a schematic perspective view showing
construction of a twenty-third embodiment of the hybrid
optical integrated circuit of the present invention. The
present embodiment.features that, unlike Embodiment 22, in
addition to the -rrei:ght reference surface for optical
functional device, a protrusion is provided on the silicon
substrate_1 as the optical device mounting part, an
electronic circuit mounting surface 98 is provided on the
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CA 02441159 2003-09-19
silicon protrusion, and not only the electrical wiring for
optical functional device but also electrical wiring for the
t
electronic circuit are provided an the electrical wiring
surface 95. Other components are similar to Embodiment. 22.
Similar components as those used in Embodiment 22 are
indicated by similar reference symbols, and detailed
description thereof is omitted.
With this construction, similar effects to those obtained
in Embodiment 22 can be provided and, in addition, since the
silicon substrate protrusion is also used as the electronic
circuit mounting surface 98, heat evolution of the electronic
circuit mounted thereon can be efficiently dissipated. what
is, the optical packaged substrate used in the hybrid optical
integrated circuit of the present invention can provide
functions as an opto-electronic hybrid packaged substrate.
Embodiment 24
In previous Embodiment 22, the silicon substrate having
protrusion and recess is used as the substrate, and the
silica-based optical waveguide as the dielectric optical
waveguide. However, to achieve both optical functional device
positioning by active alignment, which is the object of the
present invention, and device mounting by a thick film solder
such as solder bump, other combinations than the material
system can naturally be used. Such combination examples are
shown below.
First, it is needless to say that the optical waveguide
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CA 02441159 2003-09-19
in Embodiment 22 is not limited to a silica-based optical
waveguide. For example, when a polymer-based optical
waveguide such as polyimide waveguide is used, all of the
effects as obtained in Embodiment 22 can be provided.
Secondly, the substrate in Embodiment 22 can also be
other than silicon substrate. for example, a ceramic
substrate such as alumina substrate, which is proven as a
pac~.aged substrate of electronic circuit, provided on the
surface with protrusion and recess can also be used.
10 Further, for the optical waveguide in this case, a silica-
based optical waveguide, a polymer-based waveguide, and
other materials can be used. When an alumina substrate is
used as the substrate, the heat dissipation effect is
inferior to Embodiment 22, but other functions are almost
similar to Embodiment 22. Especially, it is sometimes
superior to Embodiment 22 in terms of the high-frequency
characteristics of the electrical wiring and expandability
of wiring size.
Thirdly, Embodiment 22 uses a substrate having
20 protrusion and recess formed on the surface but, instead,
it is of course possible to use a substrate having a flat
surface. Fig. 5f is a perspective view showing a substrate
structure, as an example of this configuration, in which an
alumina substrate having a flat surface and a silica-based
optical waveguide are u~ed~>--fhe--height referencewsurface
30 of the optical device mounting part can be formed of an
optical waveguide cladding layer.
In this case, height precision between the height
_ 92 _
CA 02441159 2003-09-19 '''"~
reference surface 30 and the center of the optical
waveguide cores 92a and 92b may be inferior to Embodiment
22. Further, when a ceramic substrate is used as the
substrate, the heat dissipation effect may also be
deteriorated.
However, also in the present embodiment, both the
active alignment and thick film solder mounting, which are
the object of the present invention, ca;n be simultaneously
achieved. Further, it is of course possible to use a
silicon substrate as the flat surface substrate. A silica
substrate can also be used as the substrate.
Fourthly, Embodiment 22 shows an example of "embedded
structured optical waveguide" in which the optical
waveguide core is embedded in the cladding layer having a
sufficient thickness, but configuration of the optical
waveguide is not limited to this. For examples as in Fig.
4 showing the prior arty the present embodiment can also be
applied to a ''ridge type optical waveguide" in which the
core is exposed, or coated with a thin cladding layer.
Fifthly, other materials than the dielectric material
can be used as the optical waveguide to achieve the main
object of the present invention. Such materials include a
silicon waveguide.
Further, Embodiment 22 uses solder bump. as the fixing
material 96 to achieve electrical connection and fixing '
between the optical signal port of the optical functional
device and the electrical wiring on the optical waveguide
circuit. Instead, it is also possible to use such
_ 93 _
CA 02441159 2003-09-19
materials as electroconductive bonding materials or
conductive rubber. In this case, as in Embodiment 22,
application of a stress associated with device mounting to
the optical signal port can be prevented.
Embodiment 25
Fig. 57 is a schemata.c plan view showing a twenty-fifth
embodiment of the hybrid optical integrated circuit of the
present invention. Fig. 58 is a schematic enlarged
10 perspective view showing part of Fig. 57. The signal
optical waveguide 92a of the optical waveguide circuit
comprises an .input~'output waveguide part I/0, a round
waveguide part R, and a directional coupler C for optical
coupling between both waveguides, forming a °°ring resonance
circuit" as a whole. A semiconductor amplifier as the
optical functional device 100 is mounted in the course of
the round waveguide part R, the signal port 100a of this
device and the signal optical waveguide are optically
coupled. The hybrid optical integrated circuit functions
20 as a °°ring laser°° as a whole.
r
Since the ring resonance circuit of the present
embodiment has a sharp optical frequency selectivity, when
the semiconductor optical amplifier 100 is attempted to be
integrated in the optical.waveguide by active alignment
using the signal optical waveguide and the signal port,
usable optical frequency of monitor light is limited. To
greatly relax limitation of the monitor light frequency,
the present embodiment provides the monitor aptical
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CA 02441159 2003-09-19
waveguide 92b and the monitor port 100b individually in the
optical waveguide circuit and the semiconductor optical
amplifier, and core adjustment is made using these devices.
That is, the monitor optical waveguide 92b is disposed
outside the round waveguide R of the optical waveg~uide
circuit, and the monite~r port 100b is disposed in
juxtaposition with the signal port 100a of the
semiconductor amplifier. Therefore, in mounting the
semiconductor amplifier, since the monitor optical
10 waveguide with no wavelength selectivity can be used,
limitation to the monitor light frequency is remarkably
relaxed.
In particular, referring to the optical device mounting
part structure of the optical waveguide shown in f'ig. 5~,
when the height reference surface 10 and the lower
electrical wiring surface 95 are formed in two layers, as
described in detail in Embodiment 22, low stress device
mounting is possible using thick film solder or an
electroconductive bonding material.
20
Embodiment 26
Fig. 59 is a schematic plan view showing construction
of a twenty-sixth embodiment of the hybrid integrated
circuit of the present invention. The present embodiment
features that a plurality of optical functional devices
arranged in series are mounted in the optical waveguide
circuit. In Fig. 59, the reference numeral 100 is an LD
array as a first optical functional device, and 101 is a
_ 95 _
CA 02441159 2003-09-19
' I semiconductor modulator array as a second optical
functional device. This is a construction where a Mach-
Zehnder interference oircuit type strength modulation
circuit is arrayed. In this optical waveguide circuit, the
optical signal output from the LD array 100 is transmitted
in a first signal optical waveguide array 220a, modulated
by the modulator array 101, and transmitted through a
second signal optioal waveguide array 221a to the substrate
surface.
This hybrid optical integrated circuit functions as an
°'LD module with an external modulator°° in which the
optical
output from the LD is modulated by the modulator array.
In this construction, the signal optical waveguide is
divided into sections to mount the second optical
functional device 101, and active alignment is difficult
using the waveguide. Further, when the signal port of the
modulator array 101 does not pass Light when unenergized,
core adjustment is difficult using the signal optical
waveguide 221x.
Then, in the present embodimervt, a monitor optical
waveguide 220b connecting the first optical functional
device 100 and an end of the optical waveguide circuit
substrate, and a monitor optical waveguide 221b connecting
the second optical functional device 101 and the substrate
end are provided on the optical waveguide circuit.
On the other hand, a monitor port 100b is provided on ,
the LD 100, and the port 100b functions as a semiconductor
laser as the signal port 100x. A port that functions as a
- 96 -
CA 02441159 2003-09-19
l~
semiconductor laser can also function as a light receiving
device. A monitor port lOlb is provided in the modulator
array 101, and the port 101b functions as a light receiving
device.
In the present embodiment, the optical device mounting
part has the same structure as in Embodiment 22.
Figs. 60A and 60B ars cross sectional views of the
circuit shown .in Fig. 59, Fig. 60A is a cross sectional
view taken~along line ~a-Xa' showing LD mounting
configuration, and Fig. 60B is a cross sectional view taken
along line Xb-Xb' showing modulation array mounting
configuration.
With this construction, it is possible that monitor
light is input to the manitor optical waveguide 220b, and
the light receiving current is monitored to achieve active
alignment of the LD 100. Quite similarly, alignment of the
modulator array 101 is achieved using the monitor optical
waveguide 221bw
Further, since the arrangement of the monitor optical
waveguide in the present embodiment is on the assumption
8
that the monitor port of the optical functional device has
a light receiving function, the application is limited to
semiconductor devices.
Embodiment 2? --
Fig. 61 is a schematic plan view showing construction
of a twenty-seventh embodiment of the hybrid optical
integrated circuit of the present invention. The present
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CA 02441159 2003-09-19
....
embodiment features that, unlike Embodiment 26 shown in
Fig. 59, the second optical functional device, that is, the
monitor optical waveguide 221b to the modulator array 101
is connected with the first optical functional device, that
is, between the LD 100 and the modulator array 101. Since
other components are the same as in Embodiment 26, similar
components are indicated,by similar reference numerals, and
detailed description thereof is omitted. That is, the
monitor optical waveguide 221b to the modulator 101 is
10 combined with the monitor optical waveguide 220b
immediately before the LD 100~ and connected-to the monitor
port 100b of the LD 40.
With this construction, optical device mounting is
possible using the following procedure. First, active
alignment is made using the monitor optical waveguide 220b.
In this case, the LD may be caused to emit light, or the
light receiving function may be used. After the completion
of device mounting, alignment of the modulator array 101 is
made using the monitor optical wavegui.de 221b. In this
20 case, with the LD monitor port 100b caused to emit light,
the monitor port 101 is functioned. as a light receiving
device, and the light receiving current is monitored.
The features of this method are that, in alignment of
the first optical functional device the optical fiber is
connected to the mon=tor-optical waveguide, and the monitor
light must be input or output. However, since the monitor
optical waveguide for connecting the optical~functional
devices each other is provided, fiber connection is
_ 98 _
CA 02441159 2003-09-19
< . needless in alignment of the second optical functional
device, thereby simplifying the alignment work.
Embodiment 28
Fig. 62 is a schematic plan view of a twenty~eighth
embodiment of the hybrid optical integrated circuit of the
present invention. Figs. 63A and 63B are plan views for
explaining the alignment method of the optical functional
device to be mounted on the circuit shown in Fig. G2, in
which Fig. 63A shows core adjustment and mounting of the LD
array, and Fig. 63B shows.core adjustment a.nd mounting of
the modulator array.
The present embodiment features that, unlike Embodiment
27, as the monitor optical waveguide to modulator 101, in
addition to the waveguide connecting to the LD, a waveguide
connecting to the end of the optical waveguide circuit
substrate is also provided.
With this construction; means for monitoring alignment
to the modulator 101 is increased and, as a result,
alignment is also possible to the optical functional device
comprising a material other than semiconductor devices.
The alignment procedure with the construction is described
below.
Alignment of the optical integrated circuit of this
construction will be~descx~ib-ed with reference to Figs. ~3A
and G3B. First, monitor light is transmitted to the
monitor optical waveguide 220b, while monitoring optical
coupling with the monitor port 100b of the Li7 array 100,
_ 9g _
CA 02441159 2003-09-19
.~.~~~.k:~.
~} .
alignment of the signal optical wa.veguide 220a and the
optical signal port 100a is made, and t'he LD array 100 is
fixed. Then, core adjustment and fixing of the modulator
array may be made using the monitor optical waveguide 221b
and the monitor port 101b. As a mnonitoring method in this
case, the monitor port lOlb is used as a passive waveguide,
monitor light incident t~ the monitor optical wavegui_de
221b is transmitted to the monitor port 101b and, finally,
incident to the monitor port 100b of the LD 100. At this
10 time, the monitor port 100b of the LD 100 may be functioned
as a light receiving device to fine a position where the
light receiving current is a maximum. t~urther, the light
transmission direction is reversed., the monitor port 100b
of the LD 100 is caused to emit light, and the output light
from the monitor waveguide 221b at this time may be
monitored.
Since the monitor port of the modulator array is used
as a passive waveguide, this method can be applied of
course when the optical functional device 101 is formed of
20 a semiconductor material as in the present embodiment, and
even when an optical device other than semiconductor,tfor
example, electrooptical crystals such as LiNb03 or
magnetooptical crystals are used.
As described above; in the present embodiment, in
hybrid integration of.a plurality of optical functional
devices, since monitor optical waveguides are provided
corresponding to the individual dewicesb. and it is possible
to mount a plurality of devices in series in the optical
- 100 -
CA 02441159 2003-09-19
waveguide circuit.
Embodiment 29
Fig. 64 is a schematic plan view showing a twenty-ninth
embodiment o:E the hybrid optical integrated circuit of the
present invention. The present embodiment features that as
the monitor optical waver~uide of the optical waveguide
circuit or the monitor port of the optical functional
device, a plurality of monitor waveguides 92b and 92c or
10 monitor ports 200b and 100c are provided.
As shown in Fig. 64, the monitor pcsrts 100b and 100c of
the optical functional device are formed with the same
width, the width of the monitor optical waveguide 92b of
the optical waveguide circuit is set ec~~xal to the signal
optical waveguide 92a, and the monitor optical waveguide
92c is wider in waveguide width than 92b.
With this construction, after rough core adjustment
using the monitor optical waveguieie 92c. and the monitor
port 100c, fine adjustment is possible using the monitor
20 optical waveguide 92b and the monitor port 100b. By such
two-step pore adjustment,. it is possible to reduce t'he time
required for active alignment.
Embodiment 30
Fig. 65 is a schematic plan view showing a thirtieth --
embodiment o:~ the hybrid optical integrated circuit of the
present invention. The present embodiment features 'that,
contrary to previous Embodiment 29, the monitor port of the
- 101 -
CA 02441159 2003-09-19
optical functional device is set equal in width to the
signal port to set the monitor port 100c wider than the
signal port.
With this construction, it is also~possible to reduce
the time required for active alignment by two-step core
adjustment of rough adjustment - fine adjustment.
As descr:~bed above, ,in the hybrid optical integrated
circuit of the present embodiment, the monitor optical
waveguide is provided in the optical waveguide circuit
10 along with the signal optical waveguide, the optical
functional device is~provided with the ;signal part and the
monitor port corresponding to the waveguide arrangement o~
the optical waveguide circuit, the monitor optical
waveguide of the optical waveguide circuit and the monitor
port of the optical functional device are optically coupled
and, at the same time, the signal optical waveguide and the
signal port are optically coupled, and 'the optical
functional device can be disposed on the optical device
mounting part on the optical waveguide circuit. Therefore,
20 the signal optical waveguide part has wavelength
selectivity/optical frequency selectivity and the like, or
the signal port of the optical functional device has
various functions, even when active alignment using the
signal optical waveguide and the signal port is difficult,
active alignment is possible usingwthe monitor optical
waveguide anc3 the monitor port.
Further, since the optical device mounting part is
provided with the height reference surface formed with a
- 102 -
CA 02441159 2003-09-19
thin film electrode on the surface and the electrical
wiring surface which has a lower height. The height
reference surface is disposed at a position corresponding
to the monitor optical waveguide, and the electrical wiring
surface is disposed at a position corresponding to the
signal optical waveguide, in mounting the optical
functional device on the,substrate, it is possible to make
active alignment of the optical functional device with the
optical waveguide, and device mounting using thick film
10 solder such as solder bump. Therefore, since high
positioning precision of the optical waveguide with the
optical functional device is achieved, arid the upper
surface of the signal port of the optical functional device
does not contact directly with the substrate, application
of a stress associated with device mounting to the signal
port is prevented.
Further, when a substrate with protrusion and recess is
used as the substrate, and a dielr~ctric optical waveguide
is used as the optical waveguide oircu.it, height setting
~0 precision of the height reference surface of the optical
a
device mounting part is remarkably improved, and the high-
frequency characteristics are remarkably improved.
When a silicon substrate having are excellent thermal
conductivity is used as the substrate above, heat
dissipation for the optical functionaW-device is remarkably
improved, in addition to the advantage above.
Further, when the monitor optical waveguide on the
optical wave~guide circuit is arranged at a position between
- 103 -
CA 02441159 2003-09-19
t the optical functional devices, if desired, in addition to
a position between the optical functional device and the
optical wavegrlide circuit, it is possible to mount a
plurality of optical functional de~rioes in the optical
waveguide, the devices being in line. It is also possible
to form a hybrid integrated circuit including optical
functional devices which,are many kinds of materials
lnCllldlng semi°COnductlve materials, Of cOUrSe.
Embodiment 31
Figs. 66 and 67 show construction .of a first embadiment
of optical sub-module which can be mounted an the hybrid
optical integl:ated circuit of the present invention, in
which Fig. 66 is a schematic perspective view showing
construction of an optical device 301 and a carrier 302
which are camponents of the optical sub-module of the
present embodiment, and Fig. 67 is a cross sectional view
taken along line AA' in Fig. 66.
The optical device 3dl is an arrayed semiconductor
optical ampli~:ier, 311 is its active layer, the active
layer 311 has four arrays formed at: 4001 intervals, and the
active layers 311 are separated from an optical device
surface 312 by 6Nzn. An active layer side electrode on the
active layer 313a is formed on each active layer 311, and a
ground side electrodew313b is formed on the backside
reverse to the optical device surface 312. 314 is an
optical device: height reference surface, which is provided
at a position 3~im towards the backside from the active
-- 104 -
CA 02441159 2003-09-19
>.;
layer 311, that is~ 9~tm lower than the optical device
surface 312. 315 is a lateral direction reference surface
of the optical device, which is formed perpendicular to the
optical device surface 312 and the optical device height
reference sui:face 314. The position of the reference
surface 315 ~_s 400~im away from both ends of the outside
active layer 311 of the four active layers 311. In the
present embodiment~ the optical device lateral direction
reference su~:faces 315 are provided on the right and left
10 sides, but its function can be sufficiently achieved by
only one side..
The carrier is formed by providing three steps on the
surface of ti-~e silicon substrate a.s shown in Fig. ~6. A
carrier protrusion 321 is an '°opti.cal device holding
surface 321a"' for holding the optical device height
reference suxvface 314 of the optical desrice 301, which also
functions as a ''carrier height reference surface 321b°°
which is a reference surface when mounting on the packaged
substrate. '1"hat is~ in general cases, ''the optical device
20 holding surface°° and ''the carrier height reference surface"
are separately formed as surface of different heights,
however, they are the same surface in the present
embodiment. A region 325 surrounded by the carrier
protrusion 321 is formed by providing a lSg,.~m step from the
carrier protrusion 321" A carrier electric wiring 324
comprising a 2~n thick gold is formed on the surface of the
region 325. A solder pattern 326 is prrwided at the tip.
The region 325 serves the function of aj.~ electrode lead of
~ 105 -
CA 02441159 2003-09-19
the active layer side electrode 313a of the optical device
301. A peripheral region 323 is formed by providing a 40~Cm
step from the carrier protrusion 321, and the carrier
electrical wiring 324 is continuously formed also on its
surface. This region 323 serves electrical connection with
the optical packaged substrate side electrical wiring.
The carrier 302 having multiple steps of the present
embodiment was formed by repeating anisotropic etching of the
silicon substrate. That is, the protrusion 321 of the silicon
10 substrate was first formed, and then the step of the region
325 was formed. When the steps are formed by anisotropic
etching, the side surfaces between the steps are not vertical,
but an angle of about 550 can be formed between steps of the
region 325 and the region 323 without cutting the electrical
wiring 324.
Fig. 67 is a schematic cross sectional view taken along
line AA' in Fig. 66 showing an optical sub-module when the
semiconductor amplifier 301 is mounted on the carrier 302.
The optical device height reference surface 314 of the
20 semiconductor amplifier 301 is contacted with the carrier
holding surface 321 of the carrier 302. In this condition,
the optical device active layer side electrode 313a and the
carrier electrical wiring 324 provided on the carrier region
325 are connected by heating the carrier 302 to reflow solder
326. Since the steps between the individual carrier regions
and the step Y>etween the optical device height reference
surface and the active layer are set as above, the active
layer is positioned 3~m above the carrier
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CA 02441159 2003-09-19
height reference surface (carrier holding surface) 321b.
With the optical device formed as an optical
sub-module, it is easy to previously check the
characteristics of the optical device. That is, since the
optical device active layer side electrode 312a is already
connected to the carrier electrical wiring 324, checking
can be carrier out without contacting directly with the
optical device surface.
I0 Embodiment 32
Fig. 68 is a schematic cross sectional-view showing a
second embodiment of an optical sub-module which can be
mounted on the hybrid optical integrated circuit of the
present invention.
In the optical sub-module of the present invention, the
distance between the active layer of the optical device and
the carrier reference surface can always be unified to a
value even whew using optical devices of different sizes.
In previous Embodiment 31, the step was 3Eim between the
20 optical device height reference surface 314 and the active
layer 311, but suppose a case when. mounting an optical
device where the step is SEtm. In this case, as shown in
Fig. 68, a 2~.4m step can be provided between the optical
device holding surface 321a of the carrier 302 and the
carrier height reference surface 321b.
Embodiment 33
Fig. 69 is a schematic cross sectional view showing a
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CA 02441159 2003-09-19
third embodima_nt of an optical sub--module which can be
mounted on the hybrid optical integrated circuit of the
present invention. Even when the optical device surface
312 at a 6~un height from the active layer 311 is used as
the optical device heighf, reference surface 314, as shown
in Fig. 69, the optical device height reference surface 314
of the carrier 302 can be set 9~Lm higher than the carrier
height reference surface 321a.
By setting the size as in Embodiment 31 or 32, the step
10 between the carrier height reference suz~face and the active
layer can be aet to 3~m as in Embodiment 33, shown in Fig.
67.
Embodiment 34
Fig. 70 is a schematic exploded perspective view
showing construction of a thirty-fourth embodiment of the
hybrid optical integrated circuit using the optical
sub-module of Embodiment 31 shown in Figs. 88 and 67. The
reference numeral 304 indicates an optical packaged
20 substrate, in which an optical wave~guide part 342, an
electrical wixing 348 as a substrate electrical wiring, and
an optical de~Jice mounting part 34~3 are formed an a silicon
substrate 341 with a step..
The optical waveguide part 342 is formed bn the silicon
substrate recess, which is a three--layered embedded type
silica-based optical waveguide having an under-clad 342a
(30~.m thick , a core 342b (6~tm thick X 6~.m wide) , and an
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CA 02441159 2003-09-19
< . over-clad 342c (30)1m thick) .
The substrate electrical wiring 34~ is formed on the
surface of th.e over-clad 342c, which uses a coplanar
structure coariprising a central conductor 346a and a ground
conductor 346b so that high-frequency operation is
possible. These wirings by depositing and patterning gold
(&N.m thick) after the over-clad is formed. This wiring
layer has a sufficient thickness (66~,m) and is formed on
silica glass having a small dielectric constant, and thus
has good electrical characteristics. Further, at the tip
of the central conductor 346a iv the substrate electrical
wiring 346, a solder pattern 327 is deposited and patterned
for electrical connection with the optical sub-module.
The opti<:al device mounting part 342 is formed in a
region including the silicon protrusion 343. Height of the
silicon protrusion 343 surface is in line with the height
of the upper surface of the optical waveguide undermclad
342a, which functions as a height reference surface
(hereinafter referred to as substrate height reference
surface 343) when mounting the optical sub-module. That
l
is, height from the substrate height rep°erence surface 343
to the center of the optical waveguide core 342b is 3Elm,
which is ecdual to the height from the carrier height
reference surface 321b to the active layer 311 of the
optical sub-module in Ernbodirnent 31.' s:i.licon recess region
other than the substrate height reference surface 343 is an
optical devic-a inserting groove 349, which has a depth of
about 110~a.m from the substrate height re=.ference surface
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CA 02441159 2003-09-19
343. On the bottom surface of the groove 349, the ground
electrical wiring layer 347 comprising 2~m thick gold is
formed simultaneously with the substrate electrical wiring
346 on the over-clad 342c. Since the ground electrical
wiring layer 347 does not require fine patterning, it can
be easily formed on such a deep groove bottom. A wiring
take-out part 349a is prcavided at an end of the groove 349
bottom, and the ground electrical wiring layer 347 and the
ground conductor 346b of the optical packaged substrate 304
10 are connected with a lead 345.
Since in the optical packaged substrate 304 of the
present embodiment, the substrate electrical wiring for
taking out the electrode 313a of the optical device active
layer 311 side can be formed on the optical waveguide
surface, even when the arrayed optical device 301 is
inserted in the course of the optical wavegui_de as above, a
relatively fine electrical wiring pattern can be easily
formed. In mounting in the prior art optical device upside
down configuration, the substrate electrical wiring must be
20 formed on the bottom surface of the stepped substrate,
which was difficult.
Then, the process for fabricating a hybrid optical
integrated circuit by mounting the optical sub-module
including the optical device 301 and the carrier 302 on the
optical packaged substrate 304-will be described with
reference to Figs. 70, 71, and 72. Fig. 71 is a cross
sectional.view taken along line BB' of Fig. 70, and Fig. 72
is a cross sectional view taken along line CC' of Fig. 70.
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CA 02441159 2003-09-19
Referring to Figs. 70 and 71, by contacting the carrier
height reference surface 321 of the optical sub-module with
the substrate height reference surface 343 of the optical
packaged substrate, positioning in the height direction of
the optical device active layer 311 with the optical
waveguide core 342b can be completed. In the present
embodiment, as to the lateral direction (plane direction of
the silicon substrate and the direction perpendicular to
the optical waveguideD. an optimum position was set while
10 monitoring optical coupling rate of the optical waveguide
with the optical device. After the completion of
positioning, an electroconductive bonding material was
dropped on the bottom surface of the optical device
inserting groove 349 of the optica:L packaged substrate to
fix the optical sub-module and the optical packaged
substrate.
Finally, as shown in Fig. 72, solder 327 provided at
the end of the substrate electrical wiring on the optical
packaged substrate is reflowed to achieve electrical
20 connection of the electrical wiring of the optical sub-
module and the electrical wiring of the substrate 304, thus
completing fabrication of the hybr~_d optical integrated
circuit.
In the present embodiment, reflow of solder is made by
heating the entire substrate but, alternatively, this is
also possible by locally heating the connection.
In the prior art optical device upside down packaging
configuration, optical device mounting and electrical
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CA 02441159 2003-09-19
wiring must be in the process at a time. However, in the
packaging process of the present embodiment, the core
adjustment process of the optical sub-module with the
optical packaged substrate, and the electrical wiring
process of both can be separated i:rom each other as
described above.
Further, for an optical device having a number of
electrical wiring terminals, in the prior art method,
electrically unconnected terminals tend to occur, leading
10 to a reduced yield. On the other hand, with the present
invention, electrical wi~:ing can be made- after fixing the
optical device, and the hybrid optical integrated circuit
can be fabricated with an optical device having a number of
electrical wiring terminals.
Further, with the optical sub--module and the hybrid
optical integrated circuit of the present invention, the
size in the height direction is not required to be changed
even with an optical deice having a different size in the
height direction. $y appropriately setting the height
20 between the indiva.dual reference surfaces of the optical
sub-module as shown in F~_gs. 67 arid 68, and setting t~e
height between the carrier reference surfaces 321, 321a,
and 321b and the optical device active layer 311, the
optical packaged substrate of the present embodiment can be
applied to any type of optical device.
As described above, with the present invention,
difficulties in 1) mounting multiple devices of multiple
types, 2) electrical wiring formation on the substrate, and
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.~
CA 02441159 2003-09-19
1
3) previous inspection of the optical device, which have
been problems with the prior art hybrid optical integrated
circuit of upside down configuration, can be simultaneously
eliminated.
Embodiment 35
Fig. ?3 is a schematic perspective view showing
construction of a fourth embodiment of optical sub-module
which can be mounted on a thirty-fifth embodiment of the
10 hybrid optical integrated circuit of the present invention.
Differences of the present embodiment from the optical sub-
module of Embodiment 31 are that the positioning reference
surface in the lateral direction is provided, and that a
step between the region 325 and the region 323 is removed.
As shown in Fig. ?3, the optical device 301 an arrayed
semiconductor optical amplifier which is the same as in
Embodiment 31, and various dimensions axe the same. In the
carrier 302, as in Embodiment 31, the optical device
holding surface 321a and the carrier height reference
20 surface 321b are formed on the same surface with no step,
and an optical device mounting lateral direction reference
surface 322a for positioning in the lateral direction of
the optical device is formed on the inside surface of the
optical device holding surface 321,x. In mounting the
optical device 301 on the carrier-v02; the--optical device
height reference surface 314 is contacted with the optical
device holding surface 322a, and th.e optical device lateral
direction reference surface 315 is contacted with the
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CA 02441159 2003-09-19
' ~ optical device mounting lateral direction reference surface
322a, thereby determining a relative position between the
carrier 302 and the optical device 301. A carrier lateral
direction reference surface 322b is formed on the outer
side surface of the carrier height reference surface 321b
of the carrier 302, and the carrier lateral direction
reference surface 322b an~3 the optical device mounting
direction reference surface 322a are separated by 300~Im.
The structure and sizes of the carrier 302 other than the
above are the same as in Embodiment 31. Therefore~ when
the optical device 301 is mounted an the carrier 302,
distances between the optical device active layer 311 and
the carrier height reference surface 321b and the carrier
lateral direction reference surface 322b are 3EIm and 700Eten,
respectively.
Embodiment 36
Fig. 74 is a schematic cross sectional view showing
construction of a thirty-sixth embodiment of the hybrid
optical integrated circuit of the present inwention~ The
present embodiment is characterized in that the optical
sub-module of Embodiment 35 is inc).uded.
The optical packaged substrate mounting the optical
sub-module of Embodiment 35 is the same in structure as
shown in Fig. 70. However, in the present embodiment,
distance from the optical waveguide core center to a device
mounting groove side wall 348b is v:et to 700[am. Other
sizes are the same as in Embodiment 34.
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CA 02441159 2003-09-19
>:, i.:. .. . ...:
s
In the present embodiment, in mounting the optical
sub-module, as shown in Fig. 74, positioning' of the optical
device active layer 311 with the optical waveguide core
342b is completed by contacting tk;~e carrier height
reference surface 321b of the optical sub-module with the
substrate height reference surface 343 of the optical
packaged substrate, and contacting the carrier mounting
lateral direction reference surface 322b with the device
mounting groove side wall 348b. After that, the hybrid
optical integrated circuit can be fabricated through the
same process as Embodiment-34 shown- 3n Figs. 7U to 72:
Even with different size of the optical device, when
the individual height reference surface and the lateral
direction reference surface provided on the carrier are
appropriately selected, distances between the optical
device active layer 313. arid the carrier height reference
surface 321b and the carrier mounting lateraa direction
reference surface 322a can always he set to 3~ttn and 700N.m,
respectively. Therefore, with the present embodiment, even
when the size of the optical device is changed, true hybrid
optical integrated circuit can be formed without changing
the size of the optical device mounting part of the optical
packaged substrate. In addition, various effects obtained
in the above individual embodiments can be achieved by the
present embodiment as well.
Embodiment 37
Fig. 75 is a schematic exploded perspective view
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CA 02441159 2003-09-19
showing construction of a fifth embodiment of an optical
sub-module which can be mounted on a thirty-seventh
embodiment of the hybrid optical integrated circuit of the
present invention. In the present embodiment, a.
transparent silica glass is used as a material of the
carrier 302. Compared with the carrier of Embodiment 31,
structural differences arm that an optical device
positioning marker 210 and a carrier positioning marker 230
are provided respectively on the optical device holding
10 part 321a and the peripheral region 323. Further, the
optical device electrode take-out region 325 and the
peripheral region 323 are set at the same height. Other
construction is the same as the carrier structure of the
optical sub-module of Embodiment 33 shown in Fig. 69. The
active layer side surface 312 of the optical device 301 is
set to the optical device height reference surface 314, and
on which a marker (not shown) corresponding to the optical
device positioning marker 210 is formed.
Since, in the present embodiment, transparent silica
20 glass is used as the carrier, on mounting the optical
device 301 on the carrier 302, the markers formed on the
optical device and the carrier can be,observed through the
transparent carrier. then, the optical device height
reference surface 314 and the carrier holding surface 321a
are contacted and the optical device is mounted so that
the marker formed on the optical device is in line with the
optical device positioning marker pxovided on the carrier,
thereby achieving exact positioning in both the height
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CA 02441159 2003-09-19
direction and the lateral direction.
Further, in the present embodiment, since the
electrical wiring 324 is a coplanar wiring, and formed on
the surface of silica glass with a smahl dielectric
constant, much superior high-frequency characteristics can
be obtained compared to Embodiment 36 using the silicon
substrate as the carrier 302.
Embodiment 33
10 Fig. 76 is a schematic exploded perspective view
showing construction of a thirty-eighth embodiment of the
hybrid optical integrated circuit of the present invention.
The present embodiment features that the optical sub-module
of Embodiment 37 shown in Fig. 75 is mounted on the optical
packaged substrate 304. Except for a substrate marker 410
provided on the over-clad of the optical waveguide 302,
other construction is almost the same as Embodiment 34
shown in Fig. 70. Hxhen the optical sub-module is mounted
on the substrate, the substrate marker 410 can be set in
20 line with the carrier positioning marker 230, and the
carrier height reference surface and the substrate height
reference are contacted and fixed.
In the silica glass carrier of the present embodiment,
the thermal conductivity is much inferior compared with the
silicon carrier of Embodiments 31 and 32:w However, when
mounting on the optical packaged substrate of Fig. 76,
there is no problem because the optical packaged substrate
itself functions as a heat sink.
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CA 02441159 2003-09-19 '
Embodiment 39
Fig. 77 is a schematic perspective view showing
construction of a sixth embodiment of an aptical sub-module
which can be mounted on a thirty-ninth embodiment of the
hybrid optical integrated circuit of the present invention.
In the present embodiment,, the carrier 302 is constructed
using a ceramic substrate having the multilayered
electrical wiring 324 on the surface and inside. The
carrier (ceramic substrate) 302 is formed therein with an
electrical wiring 324h in the perpendicular direction for
connecting electrical wirings on the upper and lower
surfaces, an electrode of the optical device 301 is
connected on the lower surface of the ceramic substrate
302, and again taken from the lower. surface through a
wiring 324s on the upper surface of the substrate.
The optical device holding surface 321a and the carrier
height reference surface 321b are formed of polyimide.
Such a construction can be achieved, after forming a thick
polyimide film on the ceramic substrate, by removing
unnecessary portion of polyirnide by etching.
Using the optical sub-°module, .it can be mounted on the
optical packaged substrate to obtain the hybrid optical
integrated circuit of the present invention by the same
method of other embodiments described above.
In the present embodiment, since the ceramic substrate
is used as, the carrier for the optical sub°module, good
electrical characteristics can be obtained, and
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CA 02441159 2003-09-19
multilayered electrical wiring can be easily achieved.
Further, since the electrical wiring can be provided on the
carrier, previous inspection of the optical device is very
easy.
Embodiment 40
Fig. 73 is a schematic perspective view showing
construction of a seventh embodiment of an optical
sub-module which can be mounted on a fortieth embodiment of
the hybrid optical integrated circuit of the present
invention. The carrier 302 of the present embodiment
includes a silicon substrate 302a of protrusion and recess
configuration, a silica glass layer 302b as a sufficiently
thick dielectric layer formed in the recess, the electrical
wiring 324 formed on the dielectric layer 302b, the optical
device holding surface 321a formed on the silicon
protrusion, and the carrier height reference surface 321b
as basic components.
Use of the highly heat conductive silicon substrate and
the carrier of silica glass laminate structure with a
sufficient thickness provides effects that 1) since the
electrical wiring is formed on the surface of the silica
glass layer having a small dielectl:ic constant, good
high-frequency characteristics are obtained as in
Embodiment 33y and 2) since silicon is exposed on the
optical device holding surface and the carrier he~.ght
reference surface, and both surfaces individually contact
with the optical device height reference surface and the
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CA 02441159 2003-09-19
-..
substrate height reference surface, an improved heat
dissipation can be obtained.
As the dielectric layer, othez: than Silica glass, a
polymeric dielectric material such as polyimide can be
applied. When polyimide is used, it is easy to form
multilayered high-density electrical wiring, which is
suitable for packaging of large-scale optical integrated
chip having multiple electrical wirings such as a matrix
optical switch.
10
Embodiment 41
Fig. 79 is a schematic exploded perspective view
showing construction of an eighth embodiment of an optical
sub-module which can be mounted on a forty-first embodiment
of the hybrid optical integrated circuit of i~he present
invention, and Fig. 80 is a cross sectional view taken
along line ~-D' of Fig. 79.
Tn the present embodiment, as shown in Fig. 79, the
carrier 302 comprises the silicon substrate 302a of
20 protrusion and recess configuration, and a wiring film 302b
having electrical wiring. In the protrusion region of the
silicon substrate 302a, a signal wiring 324a is provided on
the polyimide film surface, and a microstrip wiring with
the ground wiring 324b is formed on the backside. The film
302bW s provided wsth a window 352. An inner lead 324c for
connecting the signal wiring 324b and the opi:ical device
active layer side electrode extend inside the window 352.
Further, in the outer periphery of the film 302b, an outer
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CA 02441159 2003-09-19
lead 24d connecting to the signal wiring 324<a and an outer
lead 324c connecting to the ground wiring 324b are
provided.
The optical sub-module is fabricated using the
following procedure. That is, First, the optical device
active layer side electrode 313a and the inner lead 324c of
the wiring film are connected with solder, the protrusion
of the silicon substrate 302a is inserted from the window
352 of the wiring film, and the optical device height
10 reference surface 314 and the optical device lateral
direction reference surface 315 of the optical device 301
are individually contacted with the optical device holding
surface 321a and the optical device mounting direction
reference surface 322a and fixed.
Embodiment 42
Fig. 81 is a schematic perspective view showing
construction of a forty-second embodiment of the hybrid
optical integrated circuit of the present invention. The
20 present embodiment features that the optical sub-module of
s
Embodiment 41 is included.
The optical packaged substrate of the present
embodiment is the same in structure as in Embodiment 34
shown in Figs. '70 to 72. The carrier height reference
surface and the carrier lateral-directionwreference~surface
of the optical sub-module are individually contacted and
fixed with.the substrate height reference surface ahd the
substrate lateral direction reference surface of the
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CA 02441159 2003-09-19
..'~.
optical packaged substrate, the outer lead 324b of the
optical sub--module and the substrate electrical wiring 346
on the over-clad of the optical packaged substrate 304 are
electrically connected.
As described above, in the optical sub-module of the
present embodiment, the carrier is constructed by combining
the silicon substrate in protrusio~m and recess
configuration having positioning function with the and the
wiring film having electrical wiring function. In
10 particular, electrical connection of the wiring film and
the optical device electrode is achieved usirag-the inner
lead. As a result, compared with. the structure of
Embodiment 34 and Embodiments 36 to 38 in which the optical
device electrode is connected directly to the electrical
wiring provided on the carrier surface, a stress acting
upon the optical device can be remarkably reduced. This
substantially improves reliability of the optical device.
At the same time, using the inner lead, the yield of the
electrical wiring process of the optical device electrode
20 and the optical sub-module electrical wiring can be greatly
improved. Further, since microstrip wiring can be easily
formed on the wiring film, the wiring density can be
enhanced. The electrical wiring can also be formed not
only on the film surface but also inside, multilayered
electrical wiring can beweasilyachieved. Iw addition,
since the outer lead extends from the optical sub-module,
previous inspection of the optical device before mounting
on the optical packaged substrate c:an be carried out very
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CA 02441159 2003-09-19
,. v. ,
~:a
easily.
Since, in the hybrid optical integrated circuit of the
present embodiment, the process fo.r positioning and fixing
the optical sub-module on the optical packaged substrate
and the process for electrically connecting the optical
device electrode and the substrate electrical wiring can be
separated from each other, the yield of fabrication can be
remarkably improved.
As described. above, in the optical sub-module of the
10 present embodiment, the-optical device is mounted on the
carrier having the electrical wiring function for taking
out the electrode of the optical device active layer side
and the positioning function of the optical device and the
optical packaged substrate so that the active layer side
contacts. As a result, electrical wiring of superior high-
frequency characteristics can be formed within the optical
sub-module, and the high-speed characteristics of the
optical device can be greatly improved. Further, previous
inspection prior to mounting the optical device on the
20 optical packaged substrate can be rnade very easily.
Further, the distance from the carrier positioning
reference surface to the optical device active layer can be
set to a standardized value regardless of the optical
device size.
Further, in the hybrid~opticalw iwtegrated-circuitwof-
the present embodiment, since formation of fine electrical
wiring pattern is needless on the bottam surface of the
device mounting part where a large step is formed, it is
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CA 02441159 2003-09-19
< ' possible to mount not only an optical device of a single
end coupling type but also that of both end coupling type
despite the embedded type optical waveguide is used.
Further, since the electrical wiring is provided on the
carrier and previously connected to the optical device
before mounting on the substrate, difficulty in
simultaneously making code adjustment and electrical
connection is removed, and the fabrication work is greatly
facilitated.
The present invention has been described in detail with
respect to preferred embodiments,-and it will nowwbe-that
changes and modifications may be made without departing
from the invention in its broader aspects, and it is the
intention, therefore~ in the appended claims to cover all
such changes and modifications as fall within the true
spirit of invention.
c
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