Note: Descriptions are shown in the official language in which they were submitted.
CA 02528641 2010-01-20
A Method And System For Calibrating A Light Emitting Device Display
FIELD OF INVENTION
[0001] The present invention relates to a light emitting device display, and
more
specifically to a method and system for calibrating the light emitting device
display.
BACKGROUND OF THE INVENTION
[001)2] Recently active-matrix organic light-emitting diode (AMOLID) displays
with
amorphous silicon (a-Si), poly-silicon, organic, or other driving backplane
have
become more attractive due to advantages over active matrix liquid crystal
displays
(AM LCDs). For example, the advantages include: lower power, wider viewing
angle,
and faster refresh rate displays.
[00031 Currently most of the AMOLED displays use poly-silicon backplanes.
However, due to its relative infancy, ongoing processing concerns, and limited
available capacity, the usage of the poly-silicon backplanes does not lend
itself to
low-cost manufacturing.
[0004] By contrast, amorphous silicon (a-Si) leverages the vast installed
infrastructure
of proven AMLCD production, promising much lower manufacturing costs as
opposed
to that of polysilicon. As well, an a-Si solution exposes the large global
base of current
liquid crystal display manufacturers to the AIMOLEDs, thereby accelerating its
introduction commercially.
[0005] However the usage of a-Si in AMOLED backplanes encounters two issues,
namely low mobility and device instability due to the shift of the threshold
voltage of a
transistor The threshold voltage shift poses a design constraint for the
AMOLED
backplanes.
[O(X)6] To overcome these issues, many pixel circuits have been proposed
([Rcf. I ] A.
Nathan, A. Kumar, K. Sakariya, P. Scrvati, S. Sambandan, K.S. Karim, D.
Strialchilev,
"Amorphous silicon thin film transistor circuit integration for organic LED
displays on
glass and plastic," IEEE Journal of Solid State Circuits, vol. 39, pp. 1477-
1486, 2004,
[Ref. 2] J.-C. Goh, J. Jang, K.-S. Cho, and C.-K. Kim, "A new a-S]:H thin-film
transistor pixel circuit for active-matrix organic light-emitting diodes,"
IEEE Electron
1
CA 02528641 2005-12-01
Device Lett., vol. 24, no. 9, pp. 583-585, 2003, [Ref. 3] James L. Sanford and
Frank R.,
Libsch, "TFT AMOLED Pixel Circuits and Driving Methods," SID 2003, pp. 10-13).
These circuits can be broadly classified as being either current programmed or
voltage
programmed.
[0007] Despite the accuracy, the current programmed circuits by A. Nathan et
al. [Ref.
1] may face a "settling time" problem due to the low transconductance of the a-
Si TFT
coupled with a high line capacitance.
[0008] The voltage programmed circuits by J.-C. Goh, et al. [Ref. 2] and James
L.
Sanford et al. [Ref. 3] generally do not suffer from this "settling time"
problem.
However, they require techniques to decrease the dependence of OLED current on
the
threshold shift of a thin film transistor (TFT).
[0009] Numerous other compensation techniques have been introduced. However
they
either use complex pixel circuits, each having more than 2 TFTs and/or have
programming methods which suffer from the same programming time issues as with
current programmed circuits.
SUMMARY OF INVENTION
[0010] It is an object of the invention to provide a method and system that
obviates or
mitigates at least one of the disadvantages of existing systems.
[0011] In accordance with an aspect of the present invention, there is
provided a system
for calibration of a display array having a plurality of pixel circuits, which
includes: an
error extraction system for extracting error including: a first module for
monitoring a
row current in a row of the display array; a second module for generating a
reference
current; and a third module for obtaining an error between the row current and
the
reference current, and an error estimation system for estimating a correction
parameter
based on the error to adjust a data voltage applied to the display array.
[0012] In accordance with a further aspect of the present invention, there is
provided a
of calibration of a display array having a plurality of pixel circuits,
includes the steps of:
extracting error, including: providing a reference current; monitoring a row
current in
a row of the display array; and for the row, obtaining an error between the
row current
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and the reference current, estimating a correction parameter for the row based
on the
error and a total data voltages applied to the pixel circuits in the row of
the display array.
[0013] This summary of the invention does not necessarily describe all
features of the
invention.
[0014] Other aspects and features of the present invention will be readily
apparent to
those skilled in the art from a review of the following detailed description
of preferred
embodiments in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] These and other features of the invention will become more apparent
from the
following description in which reference is made to the appended drawings
wherein:
[0016] Figure 1 is a diagram showing system architecture for implementing a
calibration technique in accordance with an embodiment of the present
invention to a
display array;
[0017] Figure 2 is a diagram showing an example of a conventional voltage
programmed pixel circuit which is applicable to the display array of Figure 1;
[0018] Figure 3 is a flow chart showing an example of the operation applied to
the
system architecture of Figure 1; and
[0019] Figure 4 is a graph showing a simulation result for the calibration
technique.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE
INVENTION
[0020] Embodiments of the present invention is described using a pixel circuit
having
an organic light emitting diode (OLED) and a drive thin film transistor (TFT).
However,
the pixel circuit described herein may include a light emitting device other
than the
OLED, and may include a transistor(s) other than the TFT. It is noted that in
the
description, "pixel circuit" and "pixel" may be used interchangeably.
[0021] Figure 1 is a diagram showing system architecture for implementing a
calibration technique in accordance with an embodiment of the present
invention to a
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display array 20. Referring to Figure 1, an external calibration system 100 is
provided
outside the display array 20. The calibration system 100 includes a switch
network
system for selectively implementing one of a normal display operation and a
calibration
operation to the display array 20, an error extraction system 50 for
extracting error
information related to the shift of the characteristic(s) of a pixel using a
dummy row 70,
a correction parameter estimation system 60 for providing a correction
parameter w for
compensation, and a controller and scheduler 80 for managing the normal
display
operation (mode) and the calibration (mode).
[0022] The display array 20 includes a plurality of voltage-programmed pixel
circuits
to arranged in row and column. The pixel circuit may be a top or bottom pixel
circuit.
Each row of the display array 20 is connected to a voltage supply line 26
(e.g. VDD of
Figure 2), hereinafter referred to as VDD line 26. Each row of the display
array 20 is
selected by a select line 28 (i.e. SEL of Figure 2) connected to a row select
demultiplex
(DEMUX) 22. Each column of the display array 20 is driven by a signal line 30
(e.g.
VDATA of Figure 2) connected to a data driver 24.
[0023] The pixel circuit in the display array 20 with the calibration system
100 may be
fabricated using conventional logic circuitry technology, such as CMOS, NMOS,
HVCMOS and BiMOS integrated circuit technology.
[0024] The dummy row 70 is described in detail. The dummy row 70 is a row of
pixel
circuits. Each pixel circuit in the dummy row 70 has a structure same as that
of the pixel
circuit in the display array 20. The dummy row 70 has the same number of
columns as
that of the display array 20. In Figure 1, 5 column lines are shown as
example. The
pixel circuit in the dummy row 70 is referred to as a dummy row pixel.
[0025] During the calibration, each dummy row pixel receives a data voltage
from the
data driver 24. During the normal display operation, the dummy row 70 is
disconnected
from the data driver 24, thus, does not have to display images.
[0026] The drive transistors of the dummy row pixels (e.g. transistor 8 of
Figure 2) are
stressed occasionally, only for the calibration, and thus are not expected to
have a
threshold voltage shift. These drive transistors of the dummy row pixels
provide a
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reference current iREF to the initial threshold voltage. During the
calibration, the
monitored row current is compared to this reference current iREF.
[0027] The switch network system of the calibration system 100 is described in
detail.
The switch network system includes switch networks 40, 42 and 44. The switch
network 40 is provided for the rows of the display array 20 for the normal
display
operation. The switch network 42 is provided for the rows of the display array
20 for
the calibration. The switch network 44 is provided for the columns of the
dummy row
70 for the calibration. The controller and scheduler 80 controls the switch
networks 40,
42 and 44 to implement the normal display operation and the calibration.
[0028] The switch network 40 includes a switch TkX for the kth row of the
display array
(k=1, ... , m: m is the number of the rows). The VDD line 26 for the kth row
of the
display array 20 is selectively connected to a main voltage supply line VDDX
through the
switch Tk,.
[0029] The switch network 42 includes a switch Tky for the kth row of the
display array
15 20 (k=l, .., m: m is the number of the rows). The VDD line 26 for the kth
row of the
display array 20 is selectively connected to the error extraction system 50
through the
switch Tky.
[0030] The switch network 44 includes a plurality of switches TCTRL. The data
driver
24 is selectively connected to the dummy row 70 through the switch network 44.
Each
20 dummy row pixel receives a data voltage from the data driver 24 through the
corresponding switch TCTRL.
[0031] The switches Tkx, Tky and TCTRL may be low leakage CMOS switches, based
on
CMOS, NMOS, HVCMOS and BiMOS integrated circuit technology.
[0032] During the normal display operation, the controller and scheduler 80
allows the
rows of the display array 20 to be connected to the main voltage supply line
VDDX.
During the calibration, the VDD lines 26 are separately routed under the
control of the
controller and scheduler 80 so that the error extraction system 50 has access
to the rows
of the display array 20 sequentially.
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[0033] The error extraction system 50 is described in detail. The error
extraction
system 50 monitors a total pixel current in a row of the display array 20, and
compares
the monitored total pixel current with an expected row current. The total
pixel current
is the summation of pixel currents read from the kth row of the display array
20. The
error extraction system 50 generates a reference current iREF using the dummy
row 70
as the expected row current. The error extraction system 50 compares the
reference
current 'REF with the total pixel current in the row of the display array 20,
and obtains
error information for the row. In Figure 1, ROW represents a current
associated with the
total pixel current in a row of the display array 20.
[0034] The error extraction system 50 includes sensors 52 and 54, and a
comparator 56.
The sensor 52 is selectively connected to the VDD line 26 for a row of the
display array
through the switch network 42. The sensor 52 senses a current on the selected
VDD
line 26, and generates the current iROW. The sensor 54 senses a current drawn
from the
dummy row 70, and generates the reference current iREF.
15 [0035] The sensors 52 and 54 are accurate CMOS current mirrors. One branch
of the
current mirror senses the current drawn by the dummy row 70 as is done by the
sensor
54 (or row in the display array 20 as done by the sensor 52), while the other
branch
replicates or mirrors this current. Using these current mirrors (52 and 54),
the TFT
sections in the display array 20 and the dummy row 70 are isolated from the
comparator
20 56
[0036] The comparator 56 compares the reference current iREF with the current
iROW,
and outputs an error voltage VERROR. VERROR is proportional to the error
current TERROR,
and is:
VERROR =A-'ERROR
where A represents the transfer function (e.g. gain) of the comparator 56. The
transfer
function A of the comparator 56 is the gain of the comparator 56 when it deals
with do
currents.
[0037] The correction parameter estimation system 60 is now described in
detail. The
correction parameter estimation system 60 provides the correction parameter w.
The
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correction parameter w may be obtained through a look up table 62 and a sum
block 64
as shown in Figure 1.
[0038] The sum block 64 sums the data voltages applied to the dummy row 70,
and
outputs it as a total data voltage VTOTAL. The sum block 64 may include one or
more
Operational Amplifiers (Opamps) to perform the summation of the data voltages
provided by the data driver 24.
[0039] The correction parameter w is retrieved from the look up table 62 using
(a) the
error current TERROR provided by the comparator 56 and (b) the total data
voltage VTOTAL
provided by the sum block 64. The correction parameter w read from the look up
table
62 may be stored in a capacitor (not shown) to be used during the normal
display
operation. The average of the correction parameters w for all of the rows may
be used
for the compensation.
[0040] The correction parameter w is described in detail with reference to
Figures 1 and
2. Figure 2 illustrates a voltage programmed pixel circuit 2 which is
applicable to the
display array 20 of Figure 1. It is noted that the voltage programmed pixel
circuit in the
display array 20 of Figure 1 is not limited to the pixel circuit 2.
[0041 ] The pixel circuit 2 of Figure 2 includes an OLED 4, a storage
capacitor 6, a drive
transistor 8 which operates in saturation, and a switch transistor 10. The
transistors 8
and 10 are n-type TFTs. However, the transistors may be p-type transistors.
[0042] The source terminal of the drive transistor 8 is connected to the anode
electrode
of the OLED 4. The drain terminal of the drive transistor 8 is connected to a
voltage
supply line VDD (26 of Figure 1). The gate terminal of the drive transistor 8
is connected
to the storage capacitor 6.
[0043] The gate terminal of the switch transistor 10 is connected to a select
line SEL
(28 of Figure 1). In the description, "select line SEL" and "pixel select
signal SEL" may
be used interchangeably. The drain terminal of the switch transistor 10 is
connected to
a signal line VDATA (30 of Figure 1). The source terminal of the switch
transistor 10 is
connected to the gate terminal of the drive transistor 8 and the storage
capacitor 6. The
storage capacitor 6 and the cathode electrode of the OLED 4 are connected to a
common
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ground GND. The brightness of the OLED 4 is determined by the magnitude of
current
flowing through the OLED 4.
[0044] The normal display operation of the pixel circuit 2 includes a
programming
cycle and a driving cycle. During the programming cycle, the pixel select
signal SEL
goes high, and thus the switch transistor 10 turns on. This enables a data
voltage
(programming voltage) on VDATA to be written onto the storage capacitor 6.
During the
driving cycle, the switch transistor 10 turns off, and the drive transistor 8
sources
programmed current into the OLED 4. The pixel circuit 2 does not internally
compensate for the threshold voltage shift in the drive transistor 8.
[0045] In the calibration mode, the calibration system 100 of Figure 1
monitors a
current in a row of the display array 20, and compensates for the data
voltages applied
to the display array 20 so as to reduce the effects of the threshold voltage
shifts. The
calibration system 100 uses fuzzy technique described below. The threshold
shift in the
TFT is a slow process. Thus, the use of the fuzzy technique for approximate
threshold
shift compensation is justified.
[0046] The transfer function of the drive transistor 8 is an unknown factor.
In other
words, since the threshold in the drive transistor 8 may shift, the transfer
function of the
drive transistor 8 is time dependent.
[0047] A pixel current flowing through the OLED 4 is given by:
1P/XEL = f (VDATA - skJ _ v)Z ... (1)
R = ( Cox W)/(2L)
where iP,YEL represents the pixel current of the pixel circuit 2 in the kth
row and jth
column of the display array 20, VD TA represents a data voltage applied to the
pixel
circuit 2 in the kth row and jth column of the display array 20 through VDATA,
U
represents the initial threshold voltage in the drive transistor 8, and s k'
represents the
threshold voltage shift in the drive transistor 8 of the pixel circuit 2 in
the kth row and
jth column of the display array 20, is the mobility, Cox is the gate
capacitance per unit
area, W is the channel width, and L the channel length of the drive transistor
8.
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[0048] In order to compensate for the change in current flowing through the
OLED 4
and thus correct brightness level, a correction parameter w is estimated and
is applied to
the data voltage provided to VDATA.
[0049] Since the change in the transfer function of the drive transistor 8 is
slow
phenomena, the display array 20 can be calibrated occasionally and row-wise.
During
the calibration of the kth row, the total current in the kth row is compared
to a reference
current to evaluate an error:
k k k (
T ERROR _ - T REF - T PIXEL 2)
n /~/
'REF /.'(VDATA -v)2 ... (3)
j=1
where TERROR represents the evaluated error for the kth row, iREF represents
the
reference current for the kth row, and iP,XEL represents the summation of the
pixel
currents in the kth row (i.e. total pixel current in the kth row).
[0050] It is noted that ROW of Figure 1 corresponds to iPIXEL of (2), iREF of
Figure 1
corresponds to iREF of (2) and (3), and TERROR of Figure 1 corresponds to
TERROR of (2).
[0051] The error current TERROR is indicative of the amount of threshold
voltage shift,
and therefore is related to the correction parameter w. The correction voltage
w depends
on the error l ERROR*
[0052] In this embodiment, the correction parameter w is a voltage, and is
added to a
data voltage so as to compensate for the difference in current, resulting in
that the pixel
current becomes:
PIXEL = N (VDATA - kl - v + W) 2 ... (4)
[0053] If the threshold voltage shifts in all pixels are almost the same, the
threshold
voltage shift can be expressed as s =skj for all k and j. When s =skj, the
error
current in the kth row can be:
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n
k k*
ZERROR = 2/3~ (VDATA -U) ... (5)
l=1
[0054] A mapping parameter Kp, which is specific to the total data voltage and
the
transfer function A of the comparator 56, is defined as:
n
Kp = 2,8A I (VDATA - U) ... (6)
l=1
where /j A and v are constants.
[0055] Thus, from (6), the mapping parameter Kp is expressed as:
Kp = 2 fA E V ATA - 2/3An v ... (7)
%=1
[0056] In other words, the mapping parameter Kp can be generated by summing
the
data voltages applied to the pixel circuits. This summing function is
performed by the
sum block 64 using the data voltages applied to the dummy row 70.
[0057] The correction parameter w is used to cancel the effect of the
threshold voltage
shift t Thus, w=c. The value of can be computed from (5) and (6). It is
noted that
from (5) and (6), the error current in the kth row can be expressed as:
k
ZERROR =Kp= ... (8)
[0058] Thus once the mapping parameter Kp is obtained, w is obtained from (8)
as
follows:
k
TERROR _ = W (9)
Kp
=k
[0059] The look up table 62 stores the ratio 1EOR , along with the values of
TERROR and
Kp
.k
Kp. The correction parameter w, which is the ratio 1ER OR , is then looked up,
using the
Kp
nearest values of TERROR and Kp obtained while actually performing the
calibration.
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[0060] In Figure 1, the look up table 62 is used to obtain the correction
parameter 56.
However, an arithmetic processing unit may be used to directly compute the
correction
k
parameter w by actually computing IERROR
Kp
[0061] As described below, the average of the correction parameters for all
rows may
be appended to the data voltages for all of the pixel circuits in the display
array 20.
[0062] The operation of the display architecture of Figure 1 is described in
detail with
reference to Figures 1 and 3. Figure 3 illustrates an example of the operation
applied to
the system architecture of Figure 1.
[0063] During the normal display operation mode, the switches T1, ..., T,,X
are closed,
all of the switches Tly ..., Tmy are open, and all of the switches TCTRL are
open (step S2).
The display array 20 is connected to the supply voltage line VDDx. A current
is drawn
from the display array 20 through the regular VDD line 26. The normal display
operation is implemented until the calibration mode is activated by the
controller 70
(step S4).
[0064] When the calibration mode is activated, a counter k is initialized. The
counter
k is set to 1 (step S6). As described below, the counter k is incremented
(step S 12) until
k reaches m+1 where m is the number of rows in the display array 20. The
controller
and scheduler 80 determines whether the value of the counter k reaches m+1
(k=m+l)
(step S8). If yes (k=m+1), the operation of the display array 20 returns to
the normal
display operation mode (step S2). If no (k<m+1), the row associated with the
value of
the counter k (i.e. kth row of the display array 20) is calibrated.
[0065] During the calibration for the kth row of the display array 20 (step S
10), the
switch Tk, is open, the switch Tky is closed, and all of the switches TCTRL
are closed.
The pixel circuits in the kth row of the display array 20 are selected by the
select lines
28, and receive data voltages from the data driver 24. Since the switch Tky is
closed, a
current on the VDD line 26 of the kth row is sensed by the sensor 52. The
sensor 52
generates the current iROW, which is associated with a total pixel current for
the kth row
of the display array 20.
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[0066] Since the switches TCTRL are closed, the dummy row 70 is connected to
the data
driver 24. The drive transistors in the dummy row pixels receive data voltages
identical
to those of the pixel circuits in the kth row of the display array 20. The
sensor 54 senses
a current drawn from the dummy row 70, and generates the reference current
iREF.
[0067] The reference current iREF is compared with the current iRow at the
comparator
56. The correction parameter w for the kth row is estimated. The correction
voltage w
is stored for the next normal display operation.
[0068] Then the counter k is incremented (step S12). The operation goes to
step S8 to
determine whether the counter k reaches (m+l).
[0069] If the counter k reaches (m+1), the operation returns to step S2. The
correction
parameter w obtained for each row is used for that row for the compensation
purpose.
[0070] The average of the correction parameters obtained for all of the rows
may be
used for the pixel circuits in all of the rows of the display array 20 for the
compensation.
The average of the correction parameters may be appended to the data voltages
for all
pixel circuits in the display array 20 when implementing the next normal
display
operation. The look up table 62 or the data driver 24 may include a module for
calculating this average.
[0071] In Figure 3, VDD lines (26 of Figure 1) for all rows are monitored.
However,
the controller and scheduler 80 of Figure 1 may randomly select one or more
rows (less
than all rows), implement the step S 10 of Figure 3, and obtain one correction
parameter
w for all of the pixel circuits in the display array 20.
[0072] A simulation for the calibration technique described above was
implemented
using a behavioral model of the devices. The behavioral model simulated a
system
using a mathematical equation that describes the system described above. The
result of
the simulation is illustrated in Figure 4. The threshold voltage shift was
based on a data
input having a normal distribution. By implementing the calibration and
compensation
operation, the current mismatch decreases with time. This is due to the fact
that with
time, the calibration system (i.e. 100 of Figure 1) has more information, thus
can
estimate the error more precisely.
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10073] When all of the pixels receive data voltages which belong to the same
distribution, all pixels will have an almost identical threshold voltage
shift, Thus, this
can be compensated for by the use of one correction parameter w.
[0074] The calibration technique described above works more efficiently when
all
pixels receive data voltage chosen from the same probability distribution (
[Ref. 4] W.
Marco, "Low-power arithmetic for the processing of video signals," IEEE Trans,
VLSI
Systems, vol. 6, no, 3, pp. 493-497, Sep 1998.).
[00751 The calibration technique described above does not estimate the
threshold
voltage shift in each pixel circuit and provide individual correction.
Instead, by
providing all pixels with the same correction parameter w (e.g. the average of
the
correction parameters), the spatial and temporal resolution of the display is
improved,
and an efficient low cost solution is provided. Such an approach is efficient
since the
threshold voltage shift is rather small, and ball park values for the
correction parameter
are sufficient to remove observable gray level errors during the display
operation.
[0076] The display array 20 of Figure I may be an A,MOLEI7 display having a-Si
based
TFTs. The combination of the 2-lET pixel circuit 2 of Figure 2 and the
calibration
system 100 promises high spatial and temporal resolution, i.e. high speed, and
higher
yield.
[0077] However, the calibration technique in accordance with the embodiment of
the
invention is applicable to any display array other than the AMOLED display
having
a-Si based TFTs. The display array 20 may have a voltage-programmed pixel
circuit
other than a 2-TFT voltage programmed, AMOLED pixel circuit. The transistors
may
be fabricated using amorphous silicon, nano/micro crystalline silicon, poly
silicon,
organic semiconductors technologies (e.g., organic TFT), NMOSfPMOS technology
or
CMOS technology (e.g. MOSFET).
[0079] The present invention has been. described with regard to one or more
embodiments. However, it will be apparent to persons skilled in the art that a
number
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of variations and modifications can be made without departing from the scope
of the
invention as defined in the claims.
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