Note: Descriptions are shown in the official language in which they were submitted.
CA 02531719 2006-O1-26
A Voltage Programmed Pixel Circuit, Display System And Driving Method Thereof
FIELD OF INVENTION
[0001 ] The present invention relates to a light emitting device display, and
more
specifically to a driving technique for the light emitting device display.
BACKGROUND OF THE INVENTION
[0002] Recently active-matrix organic light-emitting diode (AMOLED) displays
with
amorphous silicon (a-Si), poly-silicon, organic, or other driving backplane
have
become more attractive due to advantages over active matrix liquid crystal
displays. An
AMOLED display using a-Si backplanes, for example, has the advantages that
include
low temperature fabrication that broadens the use of different substrates and
makes
flexible displays feasible, and its low cost fabrication that yields high
resolution
displays with a wide viewing angle.
[0003] The AMOLED display includes an array of rows and columns of pixels,
each
having an organic light-emitting diode (OLED) and backplane electronics
arranged in
the array of rows and columns. Since the OLED is a current driven device, the
pixel
circuit of the AMOLED should be capable of providing an accurate and constant
drive
current.
[0004] Figure 1 shows a pixel circuit as disclosed in U.S. Patent. No.
5,748,160. The
pixel circuit of Figure 1 includes an OLED 10, a driving thin film transistor
(TFT) 11,
a switch TFT 13, and a storage capacitor 14. The drain terminal of the driving
TFT 11
is connected to the OLED 10. The gate terminal of the driving TFT 11 is
connected to
a column line 12 through the switch TFT 13. The storage capacitor 14, which is
connected between the gate terminal of the driving TFT 11 and the ground, is
used to
maintain the voltage at the gate terminal of the driving TFT 11 when the pixel
circuit is
disconnected from the column line 12. The current through the OLED 10 strongly
depends on the characteristic parameters of the driving TFT 11. Since the
characteristic
parameters of the driving TFT 11, in particular the threshold voltage under
bias stress,
vary by time, and such changes may differ from pixel to pixel, the induced
image
distortion may be unacceptably high.
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[0005] U.S. Patent No. 6,229,508 discloses a voltage-programmed pixel circuit
which
provides, to an OLED, a current independent of the threshold voltage of a
driving TFT.
In this pixel, the gate-source voltage of the driving TFT is composed of a
programming
voltage and the threshold voltage of the driving TFT. A drawback of U.S.
Patent No.
6,229,508 is that the pixel circuit requires extra transistors, and is
complex, which
results in a reduced yield, reduced pixel aperture, and reduced lifetime for
the display.
[0006] Another method to make a pixel circuit less sensitive to a shift in the
threshold
voltage of the driving transistor is to use current programmed pixel circuits,
such as
pixel circuits disclosed in U.S. Patent No. 6,734,636. In the conventional
current
programmed pixel circuits, the gate-source voltage of the driving TFT is self
adjusted
based on the current that flows through it in the next frame, so that the OLED
current is
less dependent on the current-voltage characteristics of the driving TFT. A
drawback
of the current-programmed pixel circuit is that an overhead associated with
low
programming current levels arises from the column line charging time due to
the large
line capacitance.
SUMMARY OF THE INVENTION
[0007] It is an object of the invention to provide a method and system that
obviates or
mitigates at least one of the disadvantages of existing systems.
[0008] In accordance with an aspect of the present invention, there is
provided a pixel
circuit including: a light emitting device having a first electrode and a
second electrode;
a driving transistor having a gate terminal, a first terminal and a second
terminal, the
first terminal of the driving transistor being connected to the first
electrode of the light
emitting device; a first capacitor having first and second terminals, the
first terminal of
the first capacitor being connected to the gate terminal of the driving
transistor, the
second terminal of the first capacitor being connected to the first terminal
of the driving
transistor and the first electrode of the light emitting device; a first
switch transistor
having a gate terminal, a first terminal and a second terminal, the first
terminal of the
first switch transistor being connected the gate terminal of the driving
transistor and the
first terminal of the first capacitor; and a programming circuit for locally
adjusting a
pixel current during the programming cycle of the pixel circuit, the
programming circuit
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having a programming transistor, the programming transistor being connected to
the
first electrode of the light emitting device and being biased during the
programming
cycle of the pixel circuit.
[0009] In accordance with a further aspect of the present invention, there is
provided a
display system, including: a display array including a plurality of pixel
circuits, a driver
system for driving the display array to establish a programming cycle and a
driving
cycle; and a controller for controlling the driver system, each pixel circuit
including a
light emitting device having a first electrode and a second electrode; a
driving transistor
having a gate terminal, a first terminal and a second terminal, the first
terminal of the
driving transistor being connected to the first electrode of the light
emitting device; a
first capacitor having first and second terminals, the first terminal of the
first capacitor
being connected to the gate terminal of the driving transistor, the second
terminal of the
first capacitor being connected to the first terminal of the driving
transistor and the first
electrode of the light emitting device; a first switch transistor having a
gate terminal, a
first terminal and a second terminal, the first terminal of the first switch
transistor being
connected the gate terminal of the driving transistor and the first terminal
of the first
capacitor; and a programming circuit for locally adjusting a pixel current
during the
programming cycle, the programming circuit having a programming transistor,
the
programming transistor being connected to the first electrode of the light
emitting
device and being biased during the programming cycle.
[0010] In accordance with a further aspect of the present invention, there is
provided a
method of driving a pixel circuit, the pixel circuit comprising a light
emitting device
having a first electrode and a second electrode; a driving transistor having a
gate
terminal, a first terminal and a second terminal, the first terminal of the
driving
transistor being connected to the first electrode of the light emitting
device; a first
capacitor having first and second terminals, the first terminal of the first
capacitor being
connected to the gate terminal of the driving transistor, the second terminal
of the first
capacitor being connected to the first terminal of the driving transistor and
the first
electrode of the light emitting device; a first switch transistor having a
gate terminal, a
first terminal and a second terminal, the first terminal of the first switch
transistor being
connected the gate terminal of the driving transistor and the first terminal
of the first
capacitor; and a programming circuit having a programming transistor, the
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programming transistor being connected to the first electrode of the light
emitting
device; the method including the steps: at a programming cycle of the pixel
circuit,
biasing the programming transistor to locally adjust a pixel current; at a
driving cycle
of the pixel circuit, enabling the programming transistor to be off.
[0011 ] In accordance with a further aspect of the present invention, there is
provided a
pixel circuit incorporating a short term biasing condition in which a
programming TFT
is stable.
[0012] In accordance with a further aspect of the present invention, there is
provided a
pixel circuit structure including two distinct parts having one programming
part and one
driving part, in which the programming part is under stress for a small
fraction of frame
time and adjusting the pixel current, while the driving part drives an OLED.
[0013] This summary of the invention does not necessarily describe all
features of the
invention. Other aspects and features of the present invention will be readily
apparent to
those skilled in the art from a review of the following detailed description
of preferred
embodiments in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] These and other features of the invention will become more apparent
from the
following description in which reference is made to the appended drawings
wherein:
[0015] Figure 1 is a diagram showing a conventional 2-TFT voltage programmed
pixel
circuit;
[0016] Figure 2 is a diagram showing a pixel circuit in accordance with an
embodiment
of the present invention;
[0017] Figure 3 is a timing diagram showing an example of waveforms for
driving the
pixel circuit of Figure 2;
[0018] Figure 4 is a diagram showing a display system having the pixel circuit
of Figure
2;
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[0019] Figure 5 is a diagram showing a pixel circuit in accordance with a
further
embodiment of the present invention;
[0020] Figure 6 is a timing diagram showing an example of waveforms for
driving the
pixel circuit of Figure 5;
[0021 ] Figure 7 is a diagram showing a display system having the pixel
circuit of Figure
5;
[0022] Figure 8 is a diagram showing a pixel circuit in accordance with a
further
embodiment of the present invention;
[0023] Figure 9 is a timing diagram showing an example of waveforms for
driving the
pixel circuit of Figure 8;
[0024] Figure 10 is a diagram showing a pixel circuit in accordance with a
further
embodiment of the present invention;
[0025] Figure 11 is a timing diagram showing an example of waveforms for
driving the
pixel circuit of Figure 10;
[0026] Figure 12 is a timing diagram showing an example of programming and
driving
cycles applied to the array of Figures 4 and 7; and
[0027] Figure 13 is a diagram showing simulation result for the driving
technique
applied to Figures 2 and 3.
DETAILED DESCRIPTION
[0028] Embodiments of the present invention are described using a pixel having
an
organic light emitting diode (OLED) and a driving thin film transistor (TFT).
OLED
may be a NIP inverted or PIN non-inverted OLED. However, the pixel may include
any
light emitting device other than OLED, and the pixel may include any driving
transistor
other than TFT. It is noted that in the description, "pixel circuit" and
"pixel" may be
used interchangeably.
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[0029] The embodiments of the present invention provide locally referenced
voltage
programmed pixel circuits in which a stable biasing condition is used for a
part of the
pixel circuit (programming part), and a programming circuit is used to adjust
the pixel
current during the programming cycle of the pixel circuit locally.
[0030] The embodiments of the present invention provide a technique for
driving a
voltage programmed pixel to provide a stable current source to the OLED. The
embodiments of the present invention provide a technique for driving a
column/row of
voltage programmed pixels to provide stable light emitting device display
operation.
[0031 ] Figure 2 illustrates a locally referenced voltage programmed pixel
circuit 20 in
accordance with an embodiment of the present invention. The pixel circuit 20
includes
an OLED 22, a storage capacitor 24, a driving transistor 26, a switch
transistor 28, and
a programming circuit having a programming transistor 30. A select line SEL[n]
is
connected to the switch transistor 28. A signal line VDATA1 is connected to
the
programming transistor 30. A signal line VDATA2 is connected to the switch
transistor
28. A negative voltage line SEL[n+1] is connected to the programming
transistor 30.
A positive voltage line VDD is connected to the driving transistor 26.
[0032] The transistors 26, 28 and 30 are n-type TFTs. However, the transistors
26, 28
and 30 may be p-type transistors. The driving technique applied to the pixel
circuit 20
is also applicable to a complementary pixel circuit having p-type transistors.
The
transistors 26, 28 and 30 may be fabricated using amorphous silicon,
nano/micro
crystalline silicon, poly silicon, organic semiconductors technologies (e.g.
organic
TFT), NMOS/PMOS technology or CMOS technology (e.g. MOSFET). A plurality of
pixel circuits 20 may form an AMOLED display.
[0033] The gate terminal of the driving transistor 26 is connected to VDATA2
through
the switch transistor 28. The drain terminal of the driving transistor 26 is
connected to
VDD. The source terminal of the driving transistor 26 is connected to the
anode
electrode of the OLED 22 (at node B 1 ). The cathode electrode of the OLED 22
is
connected to a common ground.
[0034] The gate terminal of the switch transistor 28 is connected to SEL[n].
The drain
terminal of the switch transistor 28 is connected to VDATA2. The source
terminal of
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the switch transistor 28 is connected to the gate terminal of the driving
transistor 26 (at
node A1).
[0035] The gate terminal of the programming transistor 30 is connected to
VDATA1.
The drain terminal of the programming transistor 30 is connected to the anode
terminal
of the OLED 22 (at node B1). The source terminal of the programming transistor
30 is
connected to SEL[n+1].
[0036] One terminal of the storage capacitor 24 is connected to the gate
terminal of the
driving transistor 26 and the source terminal of the switch transistor 28 at
node A1. The
other terminal of the storage capacitor 24 is connected to the source terminal
of the
driving transistor 26, the drain terminal of the programming transistor 30 and
the anode
electrode of the OLED 22 at node B1.
[0037] The programming transistor 30 is a stable local reference transistor
due to its
biasing condition, and is used to adjust the pixel current during the
programming cycle
of the pixel circuit as a local current source. Thus, the pixel current
becomes stable
despite the aging effects of the driving transistor 26 and the OLED 22. It is
noted that
in the description, the terms "programming transistor" and "local reference
transistor"
may be used interchangeably.
[0038] Figure 3 illustrates a timing diagram showing an example of waveforms
applied
to the pixel circuit 20 of Figure 2. Referring to Figures 2 and 3, the
operation of the
pixel circuit 20 includes a programming cycle X11 and a driving cycle X12.
[0039] SEL[n+1] is shared between nth and (n+1)th rows, and plays two
different roles
during the programming cycle of nth and (n+1)th row. During the programming
cycle
of nth row, SEL[n+1 ] is used to provide a signal VSS. During the programming
cycle
of the (n+1)th row, SEL[n+1] is used to provide the address signal of (n+1)th
row.
Therefore, at the second programming cycle X12 of nth row which is the first
programming cycle X11 of (n+1)th row as well, SEL[n+1] goes to a high voltage
to
address (n+1)th row.
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[0040] The first operating cycle X11: SEL[n] is high and SEL[n+1] has a
negative
voltage VSS. VDATA2 goes to a bias voltage VB, and VDATA1 has the programming
voltage VP+VSS.
[0041] In X11, voltage at node A1 is VB. Thus, voltage at node B1 can be
written as
1/2
vBl-vB_ (WlL)T3 yP_ovT ...(1)
(W l L)T,
OVT = ((W/L)T3/(W/L)T1)1/2VT3-uT1 ... (2)
VP=VDATA1-VSEL[n+1]. ... (3)
where VB1 represents the voltage of node B1, VT1 represent the threshold
voltage ofthe
driving transistor 26, VT3 represent the threshold voltage of the programming
transistor
30, (W/L)T1 is the aspect ratio of the driving transistor 26, and (W/L)T3 is
the aspect
ration of the programming transistor 30.
[0042] The second operating cycle X12: SEL[n] is low, and SEL[n+1] is high
because
of the next row programming cycle. During the driving cycle X12, the voltage
of
SEL[n+1 ] is changed. That is due to the programming cycle of a next row as
described
below, and it does not affect the programming of current row.
[0043] In X12, voltage at node B1 goes to VpLED~ and voltage at node A1 goes
to
1/z
VA1 = ~ (W ~ ~~T3 ~ vp + O 1T + V~LED . . . (4)
1T1
wherein VoLED represents voltage at the OLED 22.
[0044] The gate-source voltage VGS of the driving transistor 26 is given by:
VGS=((W/L)T3/(W/L)T~)liz VP+ OVT ... (5)
[0045] In this embodiment, the programming transistor 30 is positively biased
only
during the first operating cycle X11, and is not positively biased during the
rest of the
frame time. Since the programming transistor 30 is on for just small fraction
of time,
the shift of the threshold voltage VT3 is negligible. Therefore, the current
of the driving
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CA 02531719 2006-O1-26
transistor 26 during the operating cycle X21 is independent of the shifts in
its threshold
voltage and OLED characteristics.
[0046] Figure 4 illustrates a display system having the pixel circuit 20 of
Figure 2.
VDD[j/2] and VDD[j/2+1] of Figure 4 correspond to VDD of Figure 2. VDATA1 [j]
and VDATA1 [j+1] of Figure 4 correspond to VDATA1 of Figure 2. VDATA2[j] and
VDATA2[j+1] of Figure 4 correspond to VDATA2 of Figure 2. SEL[j], SEL[j+1],
SEL[j+2], SEL[j+3] of Figure 4 corresponds to SEL[n] or SEL[n+1] of Figure 2.
[0047] In Figure 4, six pixel circuits are shown as examples. The display
system of
Figure 4 may include more than six pixel circuits In Figure 4, two VDATA1
lines, two
VDATA2 lines, two VDD lines and four SEL lines are shown as examples. The
display
system of Figure 4 may include more than two VDATA1 lines, more than two
VDATA2 lines, more than two VDD lines and more than four SEL lines.
[0048] The display array 40 of Figure 4 is an AMOLED display having a
plurality of the
pixel circuits 20 of Figure 2. In the array 40, the pixel circuits 20 are
arranged in rows
and columns. VDATA1 [i] and VDATA1 [i+1 ] are shared between the common column
pixels in the display array 40. VDATA2[iJ and VDATA2[i+1] are shared between
the
common column pixels in the display array 40. SEL[j], SEL[j+1 ], SEL(j+2] and
SEL(j+3] are shared between common row pixels in the display array 40.
VDD[j/2] and
VDD[j/2+1 ] are shared between common row pixels in the display array 40. In
order to
save the area and increase the aperture ratio, VDD [j/2] (VDD[j/2+1 ]) is
shared between
two consecutive rows.
[0049] A driver 42 is provided for driving VDATA1 [j], VDATA1 [j+1 ] while a
driver
44 is provided for driving VDATA2[j], VDATA2[j+1]. One of the drivers 42 and
44
contains the display data and the other does not. Depending on the line
interface
requirement, the drivers 42 and 44 may be located on the two sides of the
display.
[0050] A driver 46 is provided for driving VDD[j/1], VDD[j/2+1] and SEL[j],
SEL[~+1], SEL[j+2], SEL[j+3]. However, a driver for VDD[j/1], VDD[j/2+1] may
be
provided separately from a driver for SEL[j], SEL[j+1], SEL[j+2], SEL[j+3]. A
controller 48 controls the drivers 42, 44 and 46 to drive the pixel circuits
as described
above.
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[0051] Figure 5 illustrates a locally referenced voltage programmed pixel
circuit 60 in
accordance with a further embodiment of the present invention. The pixel
circuit 60
includes an OLED 62, a storage capacitor 64, a driving transistor 66, a switch
transistor
68 and a programming circuit having a programming transistor 70. A select line
SEL[n]
is connected to the switch transistor 68. A signal line VDATA is connected to
the
programming transistor 70. A negative voltage line SEL[n+1 ] is connected to
the
programming transistor 70. A positive voltage line VDD is connected to the
driving
transistor 66 and the switch transistor 68. The voltage in VDD is
controllable.
[0052] The transistors 66, 68 and 70 are n-type TFTs. However, the transistors
66, 68
and 70 may be p-type transistors. The driving technique applied to the pixel
circuit 60
is also applicable to a complementary pixel circuit having p-type transistors.
The
transistors 66, 68 and 70 may be fabricated using amorphous silicon,
nano/micro
crystalline silicon, poly silicon, organic semiconductors technologies (e.g.
organic
TFT), NMOS/PMOS technology or CMOS technology (e.g. MOSFET). A plurality of
pixel circuits 60 may form an AMOLED display.
[0053] The gate terminal of the driving transistor 66 is connected to VDD
through the
switch transistor 68. The drain terminal of the driving transistor 66 is
connected to
VDD. The source terminal of the driving transistor 66 is connected to the
anode
electrode of the OLED 62 (at node B2). The cathode electrode of the OLED 62 is
connected to a common ground.
[0054] The gate terminal of the switch transistor 68 is connected to SEL[n].
The drain
terminal of the switch transistor 68 is connected to VDD. The source terminal
of the
switch transistor 68 is connected to the gate terminal of the driving
transistor 66 (at
node A2).
[0055] The gate terminal of the programming transistor 70 is connected to
VDATA.
The drain terminal of the programming transistor 70 is connected to the anode
terminal
of the OLED 62 (at node B2). The source terminal of the programming transistor
70 is
connected to SEL[n+1].
[0056] One terminal of the storage capacitor 64 is connected to the gate
terminal of the
driving transistor 66 and the source terminal of the switch transistor 68 at
node A2. The
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other terminal of the storage capacitor 64 is connected to the source terminal
of the
driving transistor 66, the drain terminal of the programming transistor 70 and
the anode
electrode of the OLED 62 at node B2.
[0057] The programming transistor 70 is a stable local reference transistor
due to its
biasing condition and is used to adjust the pixel current during the
programming cycle.
Thus, the pixel current becomes stable despite the aging effects of the
driving transistor
66 and the OLED 62.
[0058] Figure 6 illustrates a timing diagram showing an example of waveforms
applied
to the pixel circuit 60 of Figure 5. Referring to Figures 5 and 6, the
operation of the
pixel circuit 60 includes a programming cycle X21 and a driving cycle X22.
[0059] As descried above, SEL[n+1 ] is shared between nth and (n+1)th rows,
and plays
two different roles during the programming cycle of nth and (n+1 )th row.
During the
programming cycle of nth row, SEL[n+1 ] is used to provide the VSS signal.
During the
programming cycle of the (n+1 )th row, SEL[n+1 ] is used to provide the
address signal
of (n+1)th row. Therefore, at the second programming cycle X22 of nth row
which is
the first programming cycle X21 of (n+1)th row as well, SEL[n+1] goes to a
high
voltage to address (n+1)th row.
[0060] The first operating cycle X21: SEL[n] is high and SEL[n+1 ] has a
negative
voltage VSS. VDATA goes to a programming voltage VP+VSS, and VDD has a bias
voltage VB.
[0061 ] In X21, voltage at node A2 is VB. Thus, voltage at node B2 can be
written as
1/2
VB2 = va - ( ~W l L~T3 ~ yP _ 0 yT . . . (6)
T1
4VT = ((W~L)T3~(w~L)T1)'/2VT3-VTi ... (7)
VP=VDATA1-VSEL[n+1] ... (8)
where VB2 represents the voltage of node B2, VTl represent the threshold
voltage of the
driving transistor 66, VT3 represent the threshold voltage of the programming
transistor
CA 02531719 2006-O1-26
70, (W/L)T~ is the aspect ratio of the driving transistor 66, and (W/L)T3 is
the aspect
ration of the programming transistor 70.
[0062] The second operating cycle X21: SEL[n] is low, and SEL[n+1] is high
because
of the next row programming cycle. During the driving cycle X22, the voltage
of
SEL[n+1 ] is changed. That is due to the programming cycle of a next row as
described
below, and it does not affect the programming of current row.
[0063] In X22, voltage at node B2 goes to VoLED, and the voltage at node A2
goes to:
1/2
VA2 - ~ (W l L)T 3 ~ VP + 4VT + hpLED ...
[0064] The gate-source voltage VGS of the driving transistor 66 is given by:
VGS=((W/L)T3/(W/L,)TI)'/2 VP+VT1-VT3 ... (10)
[0065] In this embodiment, the programming transistor 70 is positively biased
only
during the first operating cycle X21, and is not positively biased during the
rest of the
frame time. Since the programming transistor 70 is on for just small fraction
of time,
the shift of the threshold voltage VT3 is negligible. Therefore, the current
of the driving
transistor 66 during the operating cycle is independent of the shifts in its
threshold
voltage and OLED characteristics.
[0066] Figure 7 illustrates a display system having the pixel circuit 60 of
Figure 5.
VDD[j/2] and VDD[j/2+1 ] of Figure 7 correspond to VDD of Figure 5. VDATA1 [i]
and VDATA1 [i+1 ] of Figure 7 correspond to VDATA of Figure 5. SEL[j], SEL[j+1
],
SEL[j+2], SEL[j+3] of Figure 7 corresponds to SEL[n] or SEL[n+1] of Figure 5.
[0067] In Figure 7, six pixel circuits are shown as examples. The display
system of
Figure 4 may include more than six pixel circuits In Figure 7, two VDATA
lines, two
VDD lines and four SEL lines are shown as examples. The display system of
Figure 7
may include more than two VDATA lines, more than two VDD lines and more than
four SEL lines.
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[0068] The display array 80 of Figure 7 is an AMOLED display having a
plurality of the
pixel circuits 60 of Figure 5. The pixel circuits are arranged in rows and
columns.
VDATA [i] and VDATA [i+1] are shared between the common column pixels in the
display array 80. SEL[j], SEL[j+1], SEL[j+2] and SEL[j+3] are shared between
common row pixels in the display array 80. VDD[j/2] and VDD [j/2+1 ] are
shared
between common row pixels in the display array 80. In order to save the area
and
increase the aperture ratio, VDD [j/2] (VDD[j/2+1 ]) is shared between two
consecutive
rows.
[0069] A driver 82 is provided for driving VDATA [j], VDATA [j+1]. A driver 84
is
provided for driving VDD[j/1], VDD[j/2+1] and SEL[j], SEL[j+1], SEL[j+2],
SEL[j+3]. However, a driver for VDD[j/1], VDD[j/2+1] may be provided
separately
from a driver for SEL[j], SEL[j+1], SEL[j+2], SEL[j+3]. A controller 86
controls the
drivers 82 and 84 to drive the pixel circuits as described above.
[0070] Figure 8 illustrates a locally referenced voltage programmed pixel
circuit 90 in
accordance with a further embodiment of the present invention. The pixel
circuit 90
includes an OLED 92, a storage capacitor 94, a driving transistor 96, a switch
transistor
98, and a programming circuit 106. The programming circuit 106 includes a
programming transistor 100, a switch transistor 102 and a storage capacitor
104.
[0071] A select line SEL[n] is connected to the switch transistor 98. A signal
line
VDATA1 is connected to the switch transistor 102. A signal line VDATA2 is
connected to the switch transistor 98. A negative voltage line SEL[n+1 ] is
connected to
the programming transistor 100. A positive voltage line VDD is connected to
the
driving transistor 96. The array structure of Figure 4 can be used for the
pixel circuit 90
of Figure 8.
[0072] The transistors 96, 98, 100 and 102 are n-type TFTs. However, the
transistors
96, 98, 100 and 102 may be p-type transistors. The driving technique applied
to the
pixel circuit 90 is also applicable to a complementary pixel circuit having p-
type
transistors. The transistors 96, 98, 100 and 102 may be fabricated using
amorphous
silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors
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CA 02531719 2006-O1-26
technologies (e.g. organic TFT), NMOS/PMOS technology or CMOS technology (e.g.
MOSFET). A plurality of pixel circuits 90 may form an AMOLED display.
[0073] The gate terminal of the driving transistor 96 is connected to VDATA2
through
the switch transistor 98. The drain terminal of the driving transistor 96 is
connected to
VDD. The source terminal of the driving transistor 96 is connected to the
anode
electrode of the OLED 92 (at node B3). The cathode electrode of the OLED 92 is
connected to a common ground.
[0074] The gate terminal of the switch transistor 98 is connected to SEL[n].
The drain
terminal of the switch transistor 98 is connected to VDATA2. The source
terminal of
the switch transistor 98 is connected to the gate terminal of the driving
transistor 96 (at
node A1).
[0075] The gate terminal of the programming transistor 100 is connected to
VDATA1
through the switch transistor 102. The drain terminal of the programming
transistor 100
is connected to the anode terminal of the OLED 92 (at node B3). The source
terminal
of the programming transistor 100 is connected to SEL[n+1 ].
[0076] The gate terminal of the switch transistor 102 is connected to SEL[n].
The
source terminal of the switch transistor 102 is connected to VDATA1. The drain
terminal of the switch transistor 102 is connected to the gate terminal of the
programming transistor 100 (at node C3).
[0077] One terminal of the storage capacitor 94 is connected to the gate
terminal of the
driving transistor 96 and the source terminal of the switch transistor 98 at
node A3. The
other terminal of the storage capacitor 94 is connected to the source terminal
of the
driving transistor 96, the drain terminal of the switch transistor 90 and the
anode
electrode of the OLED 92 at node B3.
[0078] One terminal of the storage capacitor 104 is connected to the gate
terminal of the
programming transistor 100 and the drain terminal of the switch transistor 102
at node
C3. The other terminal of the storage capacitor 104 is connected to SEL[n+1 ].
[0079] The programming circuit 106 is now described in detail. The operation
of the
pixel circuit 90 includes a programming cycle and a driving cycle. The
programming
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CA 02531719 2006-O1-26
transistor 100 is a stable local reference transistor due to its biasing
condition, and is
used to adjust the pixel current during the programming cycle. During the
programming cycle, a programming voltage is written into the capacitor 104
through
the switch transistor 102, and the programming transistor 100 adjusts the
pixel current.
During the driving cycle, a reset voltage is written into the capacitor 104
and so turns
off the programming transistor 100. Therefore, the pixel current flows through
the
OLED 92. Since the programming transistor 100 is on only during the
programming
cycle, it does not experience any threshold shift. Thus, the pixel current
which is
defined by the programming transistor 100 becomes stable.
[0080] Figure 9 illustrates a timing diagram showing an example of waveforms
applied
to the pixel circuit 90 of Figure 8. Referring to Figures 8 and 9, the
operation of the
pixel circuit 90 includes a programming cycle having operation cycles X31 and
X32
and a driving cycle having an operation cycle X33.
[0081 ] As described above, SEL[n+1 ] is shared between nth and (n+1)th rows,
and
plays two different roles during the programming cycle of nth and (n+1)th row.
During
the programming cycle of nth row, SEL[n+1 ] is used to provide a signal VSS.
During
the programming cycle of the (n+1 )th row, SEL[n+1 ] is used to provide the
address
signal of (n+1)th row. Therefore, at the second programming cycle X32 of nth
row
which is the first programming cycle X31 of (n+1 )th row as well, SEL[n+1 ]
goes to a
high voltage to address (n+1)th row.
[0082] The first operating cycle X31: SEL[n] is high and SEL[n+1] has a
negative
voltage VSS. VDATA1 goes to a programming voltage VP+VSS, and VDATA2 has a
bias voltage VB.
[0083] Node C3 is charged to VP+VSS. Node A3 is charged to the bias voltage VB
As a result, voltage at node B3 goes to:
mz
VB3-ye- (W~L)T3~ vP-~yT ...(11)
(~ ~ L)Tl
OVT = ((W~L)T3~(wIL)T1)1/2VT3-VTl~ ... (12)
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CA 02531719 2006-O1-26
where VB3 represents the voltage of node B3, VT1 represent the threshold
voltage of the
driving transistor 96, and VT3 represent the threshold voltage of the
programming
transistor 100, (W/L)T1 is the aspect ratio of driving transistor 96, and
(W/L)T3 is the
aspect ration of the programming transistor 100.
[0084] The gate-source voltage of the driving transistor 96 is given by:
VGS= ((W/L)T3/(W/L)T1)I/2 VP+VT1-VT3 ... (13)
VGS remains at the same value during X32 and X33.
[0085] The second operating cycle X32: SEL[n] goes to an intermediate voltage
in
which the switch transistor 98 is off and the switch transistor 102 is on.
VDATA1 goes
to zero. Thus the programming transistor 100 turns off.
[0086] The third operating cycle X33: SEL[n] is low, and SEL[n+1 ] is high
because of
the next row programming cycle as described above.
[0087] In X33, node C3 is charged to a reset voltage. Voltage at node B3 goes
to VoLED
which is the corresponding OLED voltage for the give pixel current. Thus,
voltage at
node A3 goes to
mz
YA3 - ~ y / ~)T3 Yp + 4VT + YpGED .. . (14)
[0088] In this embodiment, the programming transistor 100 is positively biased
only
during the first operating cycle X31, and is not positively biased during the
rest of the
frame time. Since the programming transistor 100 is on for just a small
fraction of time,
its threshold shift is negligible. Therefore, the current of the driving
transistor 96 during
the operating cycle is independent of the shifts in its threshold voltage and
OLED
characteristics.
[0089] Figure 10 illustrates a locally referenced voltage programmed pixel
circuit 110
in accordance with a further embodiment of the present invention. The pixel
circuit 110
includes an OLED 112, a storage capacitor 114, a driving transistor 116, a
switch
transistor 118, and a programming circuit 126. The programming circuit 126
includes
a switch transistor 120, a programming transistor 122 and a storage capacitor
124.
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CA 02531719 2006-O1-26
[0090] A select line SEL[n] is connected to the switch transistors 118 and
122. A
signal line VDATA is connected to the switch transistor 122. A negative
voltage line
SEL[n+1] is connected to the programming transistor 120. A positive voltage
line
VDD is connected to the transistors 116 and 118. The voltage of VDD is
changeable.
The array structure of Figure 7 can be used for the pixel circuit 110 of
Figure 10.
[0091 ] The transistors 116, 118, 120 and 122 are n-type TFTs. However, the
transistors
116, 118, 120 and 122 may be p-type transistors. The programming and driving
technique applied to the pixel circuit 110 is also applicable to a
complementary pixel
circuit having p-type transistors. The transistors 116, 118, 120 and 122 may
be
fabricated using amorphous silicon, nano/micro crystalline silicon, poly
silicon, organic
semiconductors technologies (e.g. organic TFT), NMOS/PMOS technology or CMOS
technology (e.g. MOSFET). A plurality of pixel circuits 110 may form an AMOLED
display.
[0092] The gate terminal of the driving transistor 116 is connected to VDD
through the
switch transistor 118. The drain terminal of the driving transistor 116 is
connected to
VDD. The source terminal of the driving transistor 116 is connected to the
anode
electrode of the OLED 112 (at node B4). The cathode electrode of the OLED 112
is
connected to a common ground.
[0093] The gate terminal of the switch transistor 118 is connected to SEL[n].
The drain
terminal of the switch transistor 118 is connected to VDD. The source terminal
of the
switch transistor 118 is connected to the gate terminal of the driving
transistor 116 (at
node A4).
[0094] The gate terminal of the programming transistor 120 is connected to
VDATA
through the switch transistor 122. The drain terminal of the programming
transistor 120
is connected to the anode terminal of the OLED 112 (at node B4). The source
terminal
of the programming transistor 120 is connected to SEL[n+1 ].
[0095] The gate terminal of the switch transistor 122 is connected to SEL[n].
The
source terminal of the switch transistor 122 is connected to VDATA. The drain
terminal of the switch transistor 122 is connected to the gate terminal of the
programming transistor 120 (at node C4).
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CA 02531719 2006-O1-26
[0096] One terminal of the storage capacitor 114 is connected to the gate
terminal of the
driving transistor 116 and the source terminal of the switch transistor 118 at
node A4.
The other terminal of the storage capacitor 114 is connected to the source
terminal of
the driving transistor 116, the drain terminal of the programming transistor
120 and the
anode electrode of the OLED 112 at node B4.
[0097] One terminal of the storage capacitor 124 is connected to the gate
terminal of the
programming transistor 120 and the drain terminal of the switch transistor 122
at node
C4. The other terminal of the storage capacitor 124 is connected to SEL[n+1 ].
[0098] The programming circuit 126 is described in detail. The operation of
the pixel
circuit 110 includes a programming cycle and a driving cycle. The programming
transistor 120 is a stable local reference transistor due to its biasing
condition, and is
used to adjust the pixel current during the programming cycle. During the
programming cycle, a programming voltage is written into the capacitor 124
through
the switch transistor 122, and the programming transistor 120 adjusts the
pixel current.
During the driving cycle, a reset voltage is written into the capacitor 124
and so turns
off the programming transistor 120. Therefore, the pixel current flows through
the
OLED 112. Since the programming transistor 120 is on only during the
programming
cycle, it does not experience any threshold shift. Thus, the pixel current
which is
defined by the programming transistor 120 becomes stable.
[0099] Figure 11 illustrates a timing diagram showing an example of waveforms
applied to the pixel circuit 110 of Figure 10. Refernng to Figures 10 and 11,
the
operation of the pixel circuit 110 includes a programming cycle having
operation cycles
X41 and X42 and a driving cycle having an operation cycle X43.
[00100] As described above, SEL[n+1] is shared between nth and (n+1)th rows,
and plays two different roles during the programming cycle of nth and (n+1 )th
row.
During the programming cycle of nth row, SEL[n+1 ] is used to provide a signal
VSS.
During the programming cycle of the (n+1 )th row, SEL[n+1 ] is used to provide
the
address signal of (n+1)th row. Therefore, at the second programming cycle X42
of nth
row which is the first programming cycle X41 of (n+1 )th row as well, SEL[n+1
] goes to
a high voltage to address (n+1)th row.
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CA 02531719 2006-O1-26
[001 O 1 ] The first operating cycle X41: SEL[n] is high and SEL[n+1 ] has a
negative voltage VSS. VDATA goes to a programming voltage VP+VSS, and VDD has
a bias voltage VB.
[00102] Node C4 is charged to VP+VSS. Node A4 is charged to the bias voltage
VB. As a result, voltage at node B4 goes to:
nz
VB4 - y8 _ (W l L)T3 Vp _ OVT ... (15)
(W l L)T,
OVT = ((W/L)T3/(W/L)T1)~/2VT3-uTl ... (16)
where VB4 represents the voltage of node B4, VTR represent the threshold
voltage ofthe
driving transistor 116, and VT3 represent the threshold voltage of the
programming
transistor 120, (W/L)T1 is the aspect ratio of the driving transistor 116, and
(W/L)T3 is
the aspect ration of the programming transistor 120.
[00103] The gate-source voltage VGS of the driving transistor 116 is given by:
VGS= ((W/L)T3/(W/L)T1)~~z VP+VT1-VT3 ... (17)
VGS remains at the same value during X42 and X43.
[00104] The second operating cycle X42: SEL[n] goes to an intermediate voltage
in which the switch transistor 118 is off, and the switch transistor 122 is
on. VDATA
goes to zero. Thus, the programming transistor 120 turns off.
[00105] The third operating cycle X43: SEL[n] is low, and SEL[n+1 ] is high
because of the next row programming cycle as described above.
[00106] In X43, node C4 is charged to a reset voltage. Voltage at node B4 goes
to VpLED whlCh is the corresponding OLED voltage for voltage for the give
pixel
current. As a result, voltage at node A4 goes to:
mz
VA4 = (W l L)T 3 Vp + OVT + VoLEO ... (18)
T1
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CA 02531719 2006-O1-26
[00107] In this embodiment, the programming transistor 120 is positively
biased
only during the first operating cycle X41. During the rest of the frame time,
the
programming transistor 120 is not positively biased. Since the programming
transistor
120 is on for just a small fraction of time, its threshold shift is
negligible. Therefore, the
current of the driving transistor 116 during the operating cycle is
independent of the
shifts in its threshold voltage and OLED characteristics.
[00108] Figure 12 is a diagram showing programming and driving cycles for
driving the display arrays of Figures 4 and 7. In Figure 13, each of ROW(j),
ROW(j+1 ),
and ROW(j+2) represents a row of the display array. The programming and
driving
cycles for the frame at a ROW overlap with the programming and driving cycles
for the
same frame at a next ROW. Each programming and driving cycles are those of
Figures
3,6,8or10.
[00109] Figure 13 illustrates he simulation result for the circuit and
waveform
shown in the Figures 2 and 3. The result shows that the change in the OLED
current due
2-volt threshold-shift in the driving transistor 26 is less than 4%
[00110] According to the embodiments of the present invention, the shifts) of
the characteristics) of a pixel elements) (e.g. the threshold voltage shift of
a driving
transistor and the degradation of a light emitting device under prolonged
display
operation) is compensated for by voltage stored in a storage capacitor and
applying it to
the gate of the driving transistor. Thus, the pixel circuit provides a stable
current
independent of the threshold voltage shift of the driving transistor and OLED
degradation under prolonged display operation, which efficiently improves the
display
operating lifetime. According to the embodiments of the present invention, the
brightness stability of the OLED is enhanced by using circuit compensation.
[00111] Because of the circuit simplicity, it ensures higher product yield,
lower
fabrication cost and higher resolution than conventional pixel circuits.
Further the
driving technique can be employed in large area display due to its fast
settling time.
[00112] Further, the programming circuit (transitory) is isolated from the
line
parasitic capacitance unlike the conventional current programming circuit, it
ensures
fast programming.
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CA 02531719 2006-O1-26
[00113] All citations are hereby incorporated by reference.
[00114] The present invention has been described with regard to one or more
embodiments. However, it will be apparent to persons skilled in the art that a
number
of variations and modifications can be made without departing from the scope
of the
invention as defined in the claims. Therefore, the invention as defined in the
claims,
must be accorded the broadest possible interpretation so as to encompass all
such
modifications and equivalent structures and functions.
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