LOW-POWER LOW-COST DRIVING SCHEME FOR MOBILE APPLICATIONS

SYSTEME DE PILOTAGE A FAIBLE PUISSANCE ET A PRIX MODIQUE POUR APPLICATIONS MOBILES

English Abstract

Disclosed is a technique for driving technique to increase the accuracy in the
AMOLED
voltage programmed pixel circuits while reducing the cost.

Description

CA 02537173 2006-02-20
Provisional Application
Applicant:
G. Reza Chaji
507-197 Westmount Road North
Waterloo, ON, N2L3G5
CANADA
Canadian resident
Inventor:
G. Reza Chaji
507-197 Westmount Road North
Waterloo, ON, N2L3G5
CANADA
Canadian resident
Filing: Canada or USA

CA 02537173 2006-02-20
BRIEF DESCRIPTION OF THE DRAWINGS
FIG.1 is timing diagrams for AMOLED displays: shared signaling
FIG. 2 shows a pixel circuit suitable for the shared signaling addressing
scheme.
FIG. 3 shows the pixel current stability.
FIG. 4 shows a pixel circuit suitable for the shared signaling addressing
scheme.
FIG. 5 shows array structure for the pixel circuit in FIG.4.

CA 02537173 2006-02-20
FIG.1 shows the new addressing schedule proposed to reduce the interface and
driver complexity. Here, the display is divided into few segments. The
threshold voltage
of the drive TFT is generated for each segment at the same time. Therefore,
all the extra
signals required to generate the VT is shared between the rows in each
segment. After that
these segment is put back on the normal operation. Considering that the
leakage current
of the TFT is very small, using a reasonable storage capacitor to store the
generated VT
results in less frequent VT generation cycle. As a result, the power
consumption reduces
dramatically.
In this figure, the number of row in each segment is h. and the number of
frames that
use the same generated VT is 'f. As it is seen, the timing of the driving
cycle at the last
frame is reduced for each rows by i*iP where 'i' is the number of rows before
that row in
the segment and ip the timing budget assigned to the programming cycle. To
minimize
this effect, the sequence of programming the rows can be change after each VT
generation
cycle.
The pixel in FIG. 2 employs a bootstrapping effect to add the programming
voltage
to the generated VT. Here, the VT generation cycles include the first three
cycles. During
the first operating cycle, node A is charged to a compensation voltage, VDD-
VOLED. The
timing of the first operating cycle should be very small to control the effect
of unwanted
emission. During the second operating cycle, VSS goes to a high positive
voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes
to V 1(=20
V) turning off the OLED. During the third operating cycle, the voltage at node
A is
discharged through T2 and T1 and settles to V2+VT where VT is the threshold
voltage of
TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and
so node A
goes to VT. The current regulation occurs in the fourth operating cycle during
which node
B is charged to a programming voltage (VpG= 6 V); thus the voltage at node A
changes to
VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used
to store
the VT during the VT_generation interval.
As demonstrated in FIG.3, the pixel circuit provides a highly stable current
even
after a 2-V shift in the VT of T1.

CA 02537173 2006-02-20
The pixel in FIG. 4 employs a bootstrapping effect to add the programming
voltage
to the generated VT. Here, the VT generation cycles include the first three
cycles. During
the first operating cycle, node A is charged to a compensation voltage, VDD-
VOLED. The
timing of the first operating cycle should be very small to control the effect
of unwanted
emission. During the second operating cycle, VSS goes to a high positive
voltage (V 1=
20 V), and so node A is bootstrapped to a high voltage, and also node C goes
to V 1(=20
V) turning off the OLED. During the third operating cycle, the voltage at node
A is
discharged through T2 and TI and settles to V2+VT where VT is the threshold
voltage of
TI and V2 is 16 V. VSS goes to zero before the current-regulation cycle, and
so node A
goes to VT. The current regulation occurs in the fourth operating cycle during
which node
B is charged to a programming voltage (VPG= 6 V); thus the voltage at node A
changes to
VPG+VT resulting in an overdrive voltage independent of VT. Here, Csl is used
to store
the VT during the VT_generation interval.
FIG.5 shows an array structure based on the pixel circuit depicted in FIG.4.
As it is
seen, SEL2 and VSS signals of the rows in one segment are connected together
and form
the GSEL and GVSS signals.