Note: Descriptions are shown in the official language in which they were submitted.
CA 02558769 1998-07-17
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METHOD AND APPARATUS FOR TRANSMITTING DATA IN A HIGH-SPEED,
MULTIPLEXED DATA COMMUNICATION SYSTEM
This application is divided from Canadian Patent Application Serial Number
2,296,396,
filed July 17, 1998.
FIELD OF THE INVENTION
This application relates to a high speed data transmission system and, more
particularly, to a method and apparatus for improved data encoding in a
multiplexed,
high speed data transmission.
BACKGROUND OF THE INVENTION
Many conventional data transmission systems monitor the synchronization of
received
data frames to verify that the received data is in synchronization with
a"superframe"
that contains a plurality of multibit "frames". The synchronization monitor
may use a
method which is too ready to declare loss of synchronization, and is also less
ready
than is absolutely necessary to declare reestablishment of synchronization
(the loss of
synchronization forces a total loss of data traffic). A data transmission
system that
refuses to detect loss of synchronization until the worst possible operating
conditions
will work best with error correction.
Many conventional data transmission systems use some type of error correction
(EC)
encoding to send data from transmitter to a receiver. For example, ITU
Recommendation G. 742, which governs El and E2 data transmissions, specifies
that
each multibit "frame" of E2 data contains one "justification control flag
"formed of three
redundant justification control bits (also called "stuff bits") per each of
the four
multiplexed E1"tributaries."These justification bits are used by the data
transmission
system to control the justification of received data.
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As is well-known in the art, three justification control bits per
justification control
flag allows one error in one justification control bit to be correct. In this
conventional
method (majority decision), errors in two or more of the justification control
bits cause
the justification control flag value to be incorrect.
One type of error in the multibit E2 frame, an error in the justification
control flag for an
El tributary, causes that El tributary to experience a synchronization loss or
"pattern
slip."
When the frame is modified (by adding two-bit EC to the frame) so that the
error
threshold begins at three errors per frame, the uncorrected E2 frame bit error
rate ("E2
BER") level at which pattern slips occur changes very little, although the El
tributary bit
error rate ("El BER") is actually greatly improved a that E2 BER level by the
two-bit
EC. The rate of pattern slips is therefore greatly increased with respect to
the El BER.
A way of improving the EC of the justification control flag alone, rather than
pay the
cost of improving the EC of the frame as a whole, and an improved algorithm
for
superframe synchronization, which together greatly improve the synchronization
loss
level of the system with only a very slight decrease in data information
efficiency, are
needed.
SUMMARY OF THE INVENTION
The present invention may provide a method and apparatus for detecting loss of
synchronization in superframe data and a method and apparatus for detecting
resynchronization of a superframe. In addition, the number of justification
bits is
increased to increase the reliability of the justification flag value without
having to add
extra error correction circuitry. In one embodiment of the present invention,
a
justification flag includes seven justification bits instead of three. In
another
embodiment of the present invention a justification flag includes five
justification bits.
Another embodiment of the present invention allows backward compatibility
between
systems having different numbers of justification bits. In order to maintain
field
CA 02558769 1998-07-17
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compatibility with earlier three bit justification systems, a dedicated bit in
the
frame, which has a fixed value of'1"in the old system is altered to a value of
"0," as a
backwards compatibility flag. Newer systems will detect the "0" or "1" at this
flag
location and activate the proper circuitry to affect the old or new
justification method. In
this way, a new system can be interconnected with an older system and still
function.
In order to insure correct recovery of this crucial flag bit in the newer
system even
under high error rate conditions, the value is sampled for many consecutive
frames
and only updated if all bits are identical and different from the stored
value. One
embodiment samples eight consecutive frames.
Thus, the present invention may provide for more efficient detection of
synchronization
loss and detection of resynchronization. The present invention may incorporate
an
improved justification method, which, in one embodiment of the present
invention, can
be backwards compatible with older systems.
In accordance with one aspect of the invention there is provided a method of
determining whether a stuff opportunity in a frame contains valid data. The
method
involves steps, performed by a high speed data receiver, including receiving a
high
speed data stream from a sending system, including seven justification control
bits and
a backwards compatibility flag, based on a value of the backwards
compatibility flag,
determining a majority value of the seven justification control bits or a
majority value of
a subset of the severe justification control bits, and determining, depending
on the
value of backwards compatibility flag and if the majority value of the seven
justification
control bits or the subset of the seven justification control bits may be
active, that a
stuff opportunity contains valid data.
The method may involve delivering the stuff opportunity bit to one of a
plurality of
tributaries as valid data.
In accordance with another aspect of the invention there is provided a method
of
determining whether a stuff opportunity in a frame contains valid data. The
method
involves steps, performed by a high speed data receiver, including receiving a
high speed
data stream, including five justification control bits, determining a majority
value of the five
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justification control bits, and determining, if the majority value of the five
justification control bits may be active that a stuff opportunity contains
valid data.
The method may involve delivering the stuff opportunity bit to one of a
plurality of
tributaries as valid data.
In accordance with another aspect of the invention there is provided a method
of
determining whether a stuff opportunity in a frame contains valid data. The
method
involves steps, performed by a high speed data receiver, including receiving a
backwards
compatibility flag, receiving a high speed data stream, including a plurality
of justification
control bits, determining a first majority value of the justification control
bits, if the
backwards compatibility flag indicates that there are 3 justification control
bits, determining
a second majority value of the justification control bits, if the backwards
compatibility flag
indicates that there are 7 justification control bits, and determining, if the
majority value of
the justification control bits may be an active value, that a stuff
opportunity contains valid
data.
The first majority value may be 2 out of 3.
The second majority value may be 4 out of 7.
In accordance with another aspect of the invention there is provided a method
of
determining whether a stuff opportunity in a frame contains valid data. The
method
involves steps, performed by a high speed data receiver, including receiving a
backwards
compatibility flag; receiving a high speed data stream, including a plurality
of justification
control bits, determining a first majority value of the justification control
bits, if the
backwards compatibility flag indicates that there are a first number of
justification control
bits, determining a second majority value of the justification control bits,
if the backwards
compatibility flag indicates that there are a second number of justification
control bits, the
second number being different than the first number, and determining, if the
majority value
of the justification control bits may be an active value, that a stuff
opportunity contains
valid data.
= CA 02558769 2008-04-16
The method may involve receiving superframe synchronization bits, comparing
received
superframe synchronization bits to a predefined superframe synchronization
pattem,
determining, if there are at least six errors in the received superframe
synchronization bits,
5 that the superframe has lost synchronization, and determining, if there are
not at least six
errors in the received superframe synchronization bits that the superframe has
not lost
synchronization.
The method may further involve, when synchronization has been lost, receiving
four
frames, each frame having a respective bit of four superframe synchronization
bits,
comparing the four received superframe synchronization bits to a plurality of
predefined superframe synchronization patterns and, determining if the four
received
superframe synchronization bits match one of the plurality of pre-defined
superframe
synchronization patterns, that synchronization has been regained at a position
in the
frame at which the four received superframe synchronization bits match the
superframe synchronization pattern.
A fuller understanding of the invention will become apparent and appreciated
by
referring to the following description and claims taken in conjunction with
the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. I is a block diagram of a local transceiver and a remote transceiver in
an
exemplary data transmission system.
Fig. 2 is a system interface unit (SIU) of Fig. 1.
Fig. 3 is a block diagram of a superframe data structure in the system of Fig.
2.
Fig. 4 is a state diagram representing a detection of superframe
synchronization loss
and a detection of superframe resynchronization.
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Fig. 5 is a table showing an example of a one-bit pattern slip and an
associated
number of bit errors caused by the pattern slip.
Fig. 6 is a table showing a number of bit errors associated with various
pattern slips.
Fig. 7 is a block diagram of a circuit detecting superframe synchronization
loss.
Fig. 8 is a block diagram of a circuit detecting superframe resynchronization.
Figs. 9 (a) through 9(j) are circuit diagrams showing details of Fig. 7 and 8.
Fig. 10 (a) is a timing diagram of the circuitry of Figs. 9 (a) through 9
Figs. 10 (b) through 1 0(f) provide details of the timing diagram of Fig.
10 (a).
Fig. 11 (a) shows an example format of a data frame.
Figs. 11 (b) through 11 (d) show examples of frame formats having seven
justification
bits and a backwards compatible bit.
Figs. 11 (e) and 11 (f) provide a key to Figs. 11 and 12.
Figs. 12 (a) through 12 (d) show examples of frame formats having five
justification
bits.
Figs. 13 (a) through 13 (c) are circuit diagrams showing use of the
justification bits and
backward compatibility flag.
Fig. 14 shows a state diagram of an alternate circuit for establishing
superframe
synchronization.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
1. Background
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The present invention operates in a high-speed multiplexed data transmission
system, such as a multiple-T1 line. A preferred embodiment of the present
invention
operates in a digital radio for microwave communications, although the present
invention could also be implemented in any appropriate system.
FIG. 1 is a block diagram of a local transceiver 100 and a remote transceiver
150 in an
exemplary data transmission system. In a presently preferred, but not required
arrangement, each transceiver is of the type described in U.S. Patent No.
5,987,060
granted Nov.16, 1999, entitled "Digital Cable System and Method for Microwave
Communications". In the system of FIG. 1, a digitally modulated microwave
signal 160
travels between local system 100 and remote system 150. Each of local system
100
and remote system 150 operates as both a transmitter and a receiver. Remote
system
150 receives multiplexed data from local system 100 and stores it in the form
of
"superframes" in a memory of remote system 150. The data is then passed to a
plurality of "tributaries." A preferred embodiment of the system has a frame
rate of 36
KHz through 4.5 KHz and a superframe rate of 36/16 KHz through 4.5/16 KHz.
Remote
system 150 includes a Remote Indoor Unit (IDU) that includes a MUX/DEMUX 675.
Fig. 2 is a block diagram of MUX/DEMUX 675 of Fig. 1. In a described
embodiment,
the functionality described herein is part of an FPGA 202 that implements
DEMUX 202.
DEMUX 202 receives data, which was originally sent, for example, from system
100,
over a cable interface 670. DEMUX 202 outputs multiplexed data streams to a
plurality
of tributaries 210. It will be understood that MUX/DEMUX 610 of system 100
also
includes the functionality described herein, so that system 100 can receive
data sent
by system 150.
II. Synchronization of a Superframe
Fig. 3 is a block diagram of a superframe data structure 300 in a memory of
MUX/DEMUX 200 of Fig. 2. As will be understood by persons of ordinary skill in
the
art, the present invention operates in a high speed data stream environment in
which
high speed data is received at different input rates. The contents of each
frame in the
superframe is built from a plurality of received data bits. Each item of
received data is
stored in a corresponding location in a 520 bit frame. Sixteen frames are
preferably
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used to form a superframe. Each frame contains a predefined synchronization
bit (also called a"superframe bit"). Thus, the 16 frames in a superframe
establish a 16
bit synchronization pattern. In Fig.3, the bit synchronization pattern
is"1001100110000111", although any appropriate pattern can be used. An
appropriate
pattern has a very low cross-correlation (See Fig. 6). Fig. 14 shows another
appropriate pattern. A superframe is said to be synchronized ("locked") when
the 16
synchronization bits contain the predefined synchronization pattern. Fig. 11
(a) shows
an example of a frame containing a synchronization bit indicated by reference
numeral
1100.
Fig. 4 is a state diagram representing detection of superframe synchronization
loss and
detection of superframe resynchronization. If a superframe is synchronized
(state 402)
and the receiver detects six or more errors in the synchronization bits, the
current state
changes to state 404 (not synched). The receiver then enters a"Iook for
synchronization"state 406. The receiver determines that synchronization has
been
reestablished when it detects twenty consecutive bits of the synchronization
pattern.
Fig. 5 is a table showing an example of a one-bit pattern misalignment of the
example
synchronization pattern"1001100110000111 "and an associated number of bit
errors
caused by the pattern misaiignment. In the table, column 502 represents an
expected
synchronization pattern. Column 504 represents the pattern of column 502
shifted by
one bit. Column 506 represents a number of bit errors caused by shifting the
synchronization pattern by one bit. As shown in Fig. 5, shifting the
synchronization
pattern by one bit causes six bit-errors in the synchronization bits.
Fig. 6 is a table showing a number of bit errors associated with various
pattern
misalignments of the example synchronization pattern "1001100110000111". This
table shows that false synchronization of superframes will not remain
undetected. As
discussed above, for example, a misalignment by one bit causes six bit-errors
in the
synchronization bits. Similarly, a misalignment by two bits causes twelve bit
errors in
the synchronization bits, and so on.
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It will be understood that the synchronization pattern can be any pattern of
sixteen bits that causes at least six bit errors for all possible bit
misalignments.
Alternate embodiments might use a different minimum error number than six. See
Fig.
14 for an embodiment using a minimum error number of eight.
Fig. 7 is a block diagram of a circuit detecting superframe synchronization
loss. As the
synchronization bits of the superframe are received, they are compared to
respective
bits of a predefined synchronization pattern. If respective bits of the
synchronization
bits and the synchronization pattern do not match, an error is found for the
synchronization bits. A counter 706 counts the number of errors for the frame.
If six or
more errors are found, then a'9oss of synchronization"signal 710 is set
active.
Fig. 8 is a block diagram of a circuit detecting superframe resynchronization.
In a
preferred embodiment, the receiver compares respective bits of the
synchronization
bits and the predefined synchronization pattern. If twenty consecutive bits
are found to
match, the system determines that the superframe has resynched and sends a
synchronization restored signal 810.
Figs. 9 (a) through 9(j) are circuit diagrams showing details of the circuitry
of Figs. 7
and 8. Some of this circuitry is shared between the synchronization loss
detection
function of Fig. 7 and the synchronization regain function of Fig. 8. The
input
superframe synchronization bits of respective received frames are input to the
circuitry
of Fig. 9 as a signal MUXDDLY 998 of Fig. 9 (g) in accordance with a clock
signal
RXSYSCK 904 of Fig. 9 (a).
In Figs. 9 (a) and 9 (b), elements 910,912,914,916,920 form a superframe
counter. An
input signal SCRFRMI 902 is active (high) during the superframe
synchronization bit of
each frame. The input signal RXSYSCK 904 is the system clock of the receiver,
synchronized to the bits of the superframe.
In Fig. 9 (c), signal 922 tests for the expected sequence of superframe
synchronization
bits. In Fig. 9 (d), signals 924,926,928 detect errors in the synchronization
bits and
drive the error counter of Fig. 9 (f) accordingly. The circuitry of Fig. 9 (e)
generates a
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SF16 signal 932 when it detects the end of the superframe (i. e., when it
detects
the 15t"subframe). Fig. 9 (e) also outputs a SFSYNCO signal 930 that detects
the end
of a superframe after synchronization is achieved. The circuitry of Fig. 9 (f)
outputs an
SFE6 signal 960 when six errors are detected for the superframe.
5
Figs. 9 (g) and 9 (h) show circuitry that detects the start of the
synchronization pattern
("0111"). When the beginning of the pattern is detected, the receiver sends a
Superframe Start (SFS) signal 970. In Fig. 90), the receiver outputs a
Superframe
present (SF_PRES) signal 980 when twenty bits of the synchronization pattern
have
10 been found. The SF_ER signal 982 of Fig. 90) ils active high during the
initial search
for twenty correct synchronization bits only. It should be noted that the
synchronization
detector circuitry also uses the counter of Fig. 9 (.
Fig. 10 (a) is a timing diagram of the signals in the circuitry of Figs. 9 (a)
through 9 Q).
Figs. 10 (b) through 10 (f) provide details of Fig. 10 (a). Specifically, Fig.
10 (b) shows
an example of a superframe synchronization after a global reset (GR). Fig. 10
(d)
shows an example of a superframe synchronization loss, with no
reestablishment. Fig.
10 (e) shows an example of a superframe resynchronization after a "false
synchronization. "Loss of superframe synchronization is indicated by SFER_OUT
active low.
III. Justification and Backwards Compatibility
As is known to persons of ordinary skill in the art, the presence of valid
data in one or
more "stuff opportunity" bits of the frame is indicated by setting a
justification control
flag (also called a "stuff flag") of the frame. Each frame contains redundant
copies of
the justification control bit. In the described embodiment, each justification
control flag
controls one stuff opportunity for a tributary. The position of the
justification control flag
in the superframe determines which tributary is indicated. When a majority of
the
justification control flags for a tributary are active, the justification
control flag is set for
the tributary. If the justification control flag is set, valid data is present
in the "stuff
opportunities" of the frame for the tributary. Other embodiments may include
multiple
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justification control flags per frame, where each justification control flag
has
redundant bits, and controls a single stuff opportunity.
Because it is desirable for systems having varying sizes of justification
control flags to
work together, frames of certain embodiments of the present invention include
a
backwards compatibility flag. The bits currently being used for the backwards
compatibility flag in the current invention were defined as to be set ("1 ")
in earlier
systems, but were not defined as a backwards compatibility flag. These bits
were used
as part of an IDU "FIRMWARE VERSION" flag, which was defined to have a certain
bit
set to"1 ". Thus, all bits of the backwards compatibility flag are set ("1 ")
in old systems
having three-bit justification control flags. In contrast, all bits of the
backwards
compatibility flag are clear ("0") in a system having a seven-bit
justification control flag.
Thus, a receiver can determine whether a sending system uses a conventional
three-
bit justification control flag or a seven-bit justification control flag by
checking the
backwards compatibility flag. Other embodiments of the present invention may
use a
different bit or bits that had a predefined value in older systems as a
backwards
compatibility flag.
Fig. 11 generally shows a plurality of frame formats having additional
redundant
justification bits and a backwards compatible flag. Fig. 11 (a) shows a basic
format for
a frame. Figs. 11 (b)-11 (d), respectively, show the following frame formats:
2XE1;
4XE1; and 4XT1. As shown in Figs. 11 (b)-11 (d), each frame has seven
justification
control bits (1106,1116,1126), as represented by circles and square boxes.
Each
frame also contains a backwards compatibility flag (1102,1112,1122),
represented by
an asterisk. Each bit of the justification control bits should have the same
value. Figs.
11 (e) and 11 (provide keys to Figs. 11 (b)-11 (d) and to Fig. 12.
Figs. 12 (a)-12 (d), respectively, show formats of the following frames: 4XE1
C; 8XE1 C;
4XT1 Cand 8XT1 C. (The number preceding the "X" represents number of output
tributaries 210). As shown in Figs. 12 (a)-12 (d), each frame has five
justification
control bits (1206,1216,1226), as represented by circles and square boxes.
Unless a
transmission error has occurred, all of the justification control bits in a
justification
control flag should have the same value. The frames of Fig. 12 do not have a
CA 02558769 1998-07-17
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backwards compatibility flag, but other five bit justification control flag
embodiments may include such a flag.
Figs. 13 (a) through 13 (c) are circuit diagrams showing how to determine the
setting of
the majority of the justification control bits.
Fig. 13 (a) sets the stuff size control based on whether eight"1 "flag bits in
a row or 8 "0"
flag bits in a row are detected. The system preferably assumes 7 bit
justification
control. The probability of a false switching is BER5, or for BER of 1 x10-3,
the
probability is about 1 x10-24 per frame. A signal stuff-size 1306 indicates
whether the
justification control flag is 3 bits or seven bits. Active low indicates seven
bits.
Fig. 13 (b) recovers the value of the justification control flag for the
frame. Four new
bits in the aggregate data stream (common among 4XE1,2XE1, and 4XT1) are used
to
increase the number of stuff control bits to use. The circuit of Fig. 13 (b)
sets the
justification control flag result to"1"if four or more of the received stuff
bits are set to"1"
(or if two or more bits are set to"1"for a 3 bit method). This is accomplished
by
incrementing a counter every time a value of'1" is received, then outputting a
one if the
count exceeds three (or one for 3-bit systems). This changes the probability
of a
justification control flag error from (3xBER2-2xBER3) to (35xBER'-84xBER'+
70xBER'-
20xBER') per frame.
Fig. 13 (c) shows a circuit that blanks the four new justification control
positions for
three bit stuffing and blanks all justification control positions after the
seven justification
control positions. This prevents the new justification control positions from
altering the
majority value when operating in three bit mode, and prevents the stuff
opportunity
from modifying the final value of the majority result.
A system having five justification control bits, such as a system using the
frame shown
in Fig. 12, includes circuitry similar to that of Fig. 13, except that no
backwards
compatibility bit is included or checked.
CA 02558769 1998-07-17
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Fig. 14 shows a state diagram of an alternate circuit for establishing
superframe
synchronization. The circuit corresponding to the state diagram of Fig. 14
uses a
superframe pattern of "0000010100110111," which will stay synched with up to 8
errors and will establish resynchronization in a minimum of five frames. The
circuit of
Fig. 14 reads in the next four frames in the high-speed data input stream and
checks
the four superframe synchronization bits of these four frames against each of
a
plurality of four-bit superframe synchronization patterns (each of these four-
bit patterns
is shown in the Figure). If, for example, the four-bit pattern is "1001", it
will match bit
pattern 1401 of the Figure, which indicates that the frame has just received
frame
number 11 (see element 1402) and that the next frame will be frame 12. Thus,
the
receiving system has reestablished synchronization at frame 12. In a preferred
embodiment of the present invention, the receiving system may also check the
synchronization bits in some additional number of input frames, such as 16, to
confirm
that synchronization has been reestablished.
In summary, the present invention uses a new method of superframe
synchronization
detection. Specifically, the receiving system determines that synchronization
has been
lost when it detects six superframe synchronization bit errors in a
superframe.
Synchronization is considered regained when the receiver detects twenty
consecutive
correct synchronization bits. Error correction is further enhanced and
simplifie by
increasing the number of bits in a justification control flag. Alternate
embodiments have
either five or seven justification control bits. Even though the number of
justification
control bits has been enhanced, systems in accordance with the present
invention can
inter-operate with older systems, since the present invention includes a
backward
compatibility flag that indicates which justification control flag format is
being used.
While the invention has been described in conjunction with a specific
embodiment, it is
evident that many alternatives, modifications and variations will be apparent
to those
skilled in the art in light of the foregoing description. Accordingly, it is
intended to
embrace all such alternatives, modifications and variations as fall within the
spirit and
scope of the appended claims and equivalents.
