Note: Descriptions are shown in the official language in which they were submitted.
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LINEAR SAMPLING SWITCH
This is a divisional of Application Serial
No. 2,355,871, filed January 11, 2000.
BACKGROUND OF THE INVENTION
I. Field of the Invention
The invention relates to analog/radio frequency
circuit design. More particularly, the invention relates to
an analog/RF switch.
Ii. Description of the Related Art
A simple switched capacitor sample and hold
circuit can be used to convert between an analog continuous
time domain and a sampled data domain. Figure 1 is a
conceptual schematic diagram showing a simple switched
capacitor sample and hold circuit. Typically the input
signal (v1n) is a radio frequency (RF) or intermediate
frequency (IF) signal which carries a band-limited,
modulated signal. The input signal is applied to a switch
which opens and closes at a periodic clock frequency. A
capacitor 22 is connected between the output of switch 20
20 and a common ground. The output voltage is generated across
the capacitor 22. The capacitor 22 is typically a linear
poly-poly or metal-metal capacitor. The output signal (vo)
is a sampled data signal. The sampling frequency at which
the switch 20 is opened and closed must be higher than twice
the modulated bandwidth of the input signal in order to
satisfy the Nyquist Theorem. Thus, for a narrow-band
signal, the sampling rate can be lower than the carrier
frequency as long as it is twice the modulated bandwidth.
Using a sampling frequency lower than the carrier frequency
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of the input signal is referred to as subsampling and is
used to downconvert the input signal to a lower frequency.
The spectrum of the output signal contains copies
of the input signal centered around multiples of the
sampling frequency. For example, the spectral content of
the output signal (foõt) can be expressed as shown in
Equation 1.
fovt = nfc1k fin (1)
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where:
is equal to the sampling frequency;
is equal to the frequency of the input signal; and
n is equal to 0, 1, 2, 3.... 5
The output signal can be filtered to reduce the power level at the
undesired frequencies. For instance, if the input signal is centered on a
carrier at 240 megahertz (MHz) and the sampling circuit is clocked at 60
MHz, a replica of the modulated input signal appears at baseband, 60
MHz, 120 MHz, 180 MHz, as well as at several higher frequencies. The
replicas above the baseband frequency can be filtered such that only the
baseband replica is preserved.
The on resistance of the switch 20 is not ideal and, therefore, the
switch 24 exhibits ohmic resistance even when the switch 20 is closed.
Figure 2 is a schematic diagram showing an equivalent circuit when the
switch 20 is closed. A resistor 26 represents the on resistance of the switch
20. Due to the resistive nature of the closed switch, the output signal is
related to the input signal in accordance with Equation 2, below.
v. v;,, (2)
where:
v;n is the voltage level of the input signal;
vout is the voltage level of the output signal;
C is the capacitance value of capacitor; and
R is the on-resistance of the closed switch.
It is evident from examining Equation 2 that the switched capacitor
sampling circuit acts as a low pass filter.
In reality, the resistive value of the switch 20 is not constant and
instead is a function of the voltage level of the input signal. Figure 3 is
an x/y graph showing the resistive value of an exemplary single
nMOSFET switch as a function of the voltage level of the input signal. In
Figure 3, the horizontal axis represents the input signal voltage level in
volts. The vertical axis represents the ohmic resistance of the switch on a
logarithmic scale in Ohms (S). As shown in Figure 3, the on resistance of
a FET is a strong function of the voltage level of the input signal which is
applied to it.
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Taking into consideration the curve shown in Figure 3, Equation 3
more accurately reflects the effect of the on resistance of the switch 20.
v
V ~ m (3)
1 + s vin
where:
R(v;,,) is equal to the voltage level dependent on resistance of the
closed switch.
By examining Equation 3, one can see that not only does the switch act as
a low pass filter but, in addition, the response of the low pass filter is a
function of the voltage level of the input signal. For this reason, the
switch is nonlinear and tends to create extremely high levels of distortion
to the output signal.
Figure 4 is a schematic diagram showing a parallel nMOSFET and
pMOSFET (metal oxide semi-conductor field effect transistor) switch 24.
The parallel switch 24 conducts signals so long as the voltage range of the
input signal remains within the power supply voltages used to bias it.
The parallel switch 24 exhibits substantially less variance in on resistance
as a function of input signal level and, therefore, provides a more linear
response.
Figure 5 is an x/y graph showing the resistive value of a prior art
parallel switch as a function of the voltage level of the input signal. In
Figure 5, the horizontal axis represents the input signal voltage level in
volts. The vertical axis represents the ohmic resistance of the parallel
switch in Ohms (S). Notice that between 1.0 to 1.4 Volts (V) the resistance
of the switch varies by about 2.5 (i.e. R(v;,, = 1)*2.5 = R(v;,, = 1.4). Such
high levels of variance of on resistance as a function input voltage can
cause significant distortion in the sampling process.
The frequency response of the on-resistance of prior art parallel
switches is also dependent on the input voltage level. Figure 6 is an x/y
graph showing the frequency response of a prior art parallel switch. The
solid curve 28 represents the frequency response of the parallel switch at
an input voltage level of 1.4V. The dotted curve 30 represents the
frequency response of the parallel switch at an input voltage level of
1.OV. Figure 7 is an x/y graph showing the phase response of a prior art
parallel switch. The solid curve 32 represents the phase response of the
parallel switch at an input voltage level of 1.4V. The dotted curve 34
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represents the phase response of the parallel switch at an input voltage
level of 2.OV. The divergence of the high frequency characteristics as a
function of the input signal contributes additional nonlinearities to the
performance of the switch and tends to more greatly distort the output
signal.
When a switch with such non-linear properties is used to
subsample a high frequency RF signal, the resultant samples are
distorted. Therefore, the resultant samples do not accurately reflect the
actual characteristics of the RF signal. As the distorted samples are
subject to further processing within the receiver, the distortion produces
errors. The errors can be so significant that using the switches at high
frequencies is not practical and more expensive, larger and power-hungry
down-conversion methods must be employed.
For these reasons, there is a need in the industry to develop a
switch which exhibits a more linear response.
SUMMARY OF THE INVENTION
A linear switch is constructed with a p-channel and an n-channel
field effect transistor (FET). A source node of the p-channel FET is
coupled to a drain node of the n-channel FET to form a terminal of the
switch. A drain node of the p-channel FET is coupled to a source node of
the n-channel FET to form another terminal of the switch. The n-
channel FET has a n-channel width. The p-channel FET has a p-channel
width. The p-channel width is larger than the n-channel width in order
to increase the linearity of the on-resistance of the resulting switch as a
function of input voltage applied to one terminal and output voltage
produced at the other terminal.
In one embodiment, a sampling capacitor is coupled to an output
terminal of the switch. An input terminal of the switch is connected to a
band-limited, modulated signal. Complementary clock signals are
coupled to the gate node of the p-channel FET and the gate node of the n-
channel FET. The complementary clock signals operate at a lower
frequency than a center frequency of the band-limited, modulated signal.
The output terminal produces a subsampled version of the band-limited,
modulated signal.
In another embodiment, a linear switch is incorporated into an
active sample and hold switch. The active sample and hold circuit is
symmetric and configured to accept a balanced input. Two linear
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switches couple a positive input signal of the balanced
input to two different sampling capacitors. After the
sampling capacitors are charged, another set of switches
configures the sampling capacitors such that one of the
5 sampling capacitor is in the feed back of an op amp and the
other is connected from the input of the op amp to ground.
In this configuration, the op amp has a gain of two and the
output of the op amp is twice the voltage sampled by the
sampling capacitors.
In yet another embodiment, a linear switch is
incorporated into a double sampled switch. The double
sampled switch is symmetric and configured to accept a
balanced input. Two linear switches alternately in time
couple a first and second sampling capacitor to the positive
input signal of the balanced input. While the first
sampling capacitor is coupled to the input, the second
sampling capacitor is configured to be connected in the
feedback of an op amp. Likewise, while the second sampling
capacitor is coupled to the input, the first sampling
capacitor is configured to be connected in the feedback of
the op amp, thus producing samples at double frequency.
The invention may be summarized according to one
aspect as a symmetric, doubled sampled circuit having a
positive input portion comprising: first and second linear
switches each having a first side coupled to a positive
input of a balanced input and configured to be clocked by a
delayed phase of a phase 1 clock and a delayed phase of a
phase 2 clock, respectively; a first holding capacitor
coupled to a far side of said first linear switch; a second
holding capacitor coupled to a far side of said second
linear switch; a third switch coupled between the junction
of said first linear switch and said first holding capacitor
and a positive output of an op amp and configured to be
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clocked by said phase 2 clock; a fourth switch coupled
between the junction of said second linear switch and said
second holding capacitor and said positive output of an op
amp and configured to be clocked by said phase 1 clock;
fifth and sixth switches in series to ground coupled to said
far side of said first sampling capacitor, said fifth switch
configured to be clocked by a main clock operating at twice
the frequency of said phase 1 and phase 2 clocks and said
sixth switch configured to be clocked by said phase 1 clock;
seventh and eighth switches in series to ground coupled to
said far side of said second sampling capacitor, said
seventh switch configured to be clocked by said main clock
and said eighth switch configured to be clocked by said
phase 2 clock; a ninth switch coupled between said far side
of said first sampling capacitor and a negative input to
said op amp and configured to be clocked with said delayed
phase of said phase 2 clock; and a tenth switch coupled
between said far side of said second sampling capacitor and
said negative input to said op amp and configured to be
clocked with said delayed phase of said phase 1 clock;
wherein said phase 1 and phase 2 clocks are non-overlapping
and derived from said main clock.
BRIEF DESCRIPTION OF THE DRAWINGS
The features, objectives, and advantages of the
invention will become more apparent from the detailed
description set forth below when taken in conjunction with
the drawings:
Figure 1 is a conceptual schematic diagram showing
a simple switched capacitor sample and hold circuit.
Figure 2 is a schematic diagram showing an
equivalent circuit to that of the switch in Figure 1 when
the switch of that circuit is closed.
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Figure 3 is an x/y graph showing the resistive
value of a prior art single nMOSFET switch as a function of
the voltage level of the input signal.
Figure 4 is a schematic diagram showing a parallel
nMOSFET and pMOSFET switch.
Figure 5 is an x/y graph showing the resistive
value of a prior art parallel switch as a function of the
voltage level of the input signal.
Figure 6 is an x/y graph showing the frequency
response of a prior art parallel switch.
Figure 7 is an x/y graph showing the phase
response of a prior art parallel switch.
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Figure 8 is a schematic diagram showing a switched capacitor
sample and hold circuit comprising the linear resistance parallel switch
configured according to the invention.
Figure 9 is an x/y graph showing the resistive value of an
exemplary parallel switch, configured according to the invention, as a
function of the voltage level of the input signal.
Figure 10 is an x/y graph showing the frequency response of an
exemplary parallel switch configured according to the invention.
Figure 11 is an x/y graph showing the phase response of an
exemplary parallel switch configured according to the invention.
Figure 12 is a schematic diagram showing an exemplary
embodiment of a sample and hold circuit comprising a parallel switch
configured according to the invention.
Figure 13 is a timing diagram showing the time relationship of the
clocks used to operate the circuit of Figure 12.
Figure 14 is a schematic diagram showing an exemplary
embodiment of a double sampled, unity gain, switched capacitor arcuit
comprisinga parallel switch configured according to the invention.
Figure 15 is a timing diagram showing the time relationship of the
clocks used to operate the circuit of Figure 14.
DETAILED DESCRIPTION OF THE INVENTION
Referring initially to Figure 8, a schematic diagram is illustrated
showing a switched capacitor sample and hold circuit comprising the
linear resistance, parallel switch according to the invention. An n-
channel FET 40 and a p-channel FET 42 are connected in parallel to create
the switch. A source node of the p-channel FET 42 is coupled to a drain
node of the n-channel FET 40 to form a terminal of the switch. A drain
node of the p-channel FET 42 is coupled to a source node of the n-
channel FET 40 to form another terminal of the switch. In general, the
switch is bi-directional and either terminal can be used as either input or
output. A capacitor 44 is used to sample the input voltage level when the
switch is closed and to hold the output signal when the switch is open.
The n-channel FET 40 and the p-channel FET 42 are coupled to
complementary clock signals which open and close the switch. The
conductance of the switch can be expressed in terms of the on
conductance of the n-channel FET 40 and the p-channel FET 42 according
to Equation 4.
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gan = gn +gp (4)
where:
g,õ is equal to the on conductance of the switch;
gõ is equal to the on conductance of the n-channel FET 40; and
g,, is equal to the on conductance of the p-channel FET 42.
Substituting the well known equation for on conductance of a MOSFET,
Equation 5 can be derived from Equation 4.
Son - gnCox ~ (VDD -vrn -Vm )+t'~pCoz T \vin -V1p / (5)
n L' p
where:
W
L is the width to length ratio of the n-channel MOSFET;
W
T- is the width to length ratio of the n-channel MOSFET;
P
VDD is the drain voltage applied to the n-channel FET 40;
v;n is voltage level of the input signal;
Vtn is the threshold voltage of the n-channel FET 40;
Vtp is the threshold voltage of the p-channel FET 42;
coY is a technology dependent oxide capacitance;
,t,l.is the mobility of the n-channel FET; and
,un is the mobility of the p-channel FET.
As can be seen by Equation 5, the on-conductance of the parallel switch is a
function of the input voltage. The on-aonductance of the parallel switch is
both a linear function of the input voltage level and a non-linear function
of the input voltage level.
The on-aonductance of the parallel switch varies nonlinearly due to
the dependence of the threshold voltages on the input voltage level as
given by Equation 6.
v, = vo + 7 vSB - ~- ~ (6)
where:
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V,o is the zero back bias threshold;
yis the body factor;
-0f.- is absolute value of the surface inversion potential; and
vsB is the source to bulk potential (i.e. (VSS -v;n) for n-channel FET
or (VDD -ZJin) for p-channel FET) sometimes called the back
gate voltage.
If we assume for a moment that the on-(Dnductance is only a linear
function of the input voltage level, we can take a derivative with respect to
input voltage level of Equation 5. By setting the derivative equal to 0, we
get the result shown in Equation 7.
W _ W
L õ- n L p (7)
Substituting the result shown in Equation 7 into Equation 5 yields the
results shown below in Equation 8 for the region in which both FETs are
on as shown by the limitation in Equation 9.
- 2f1n w ) IVDD (Vin + Vtp I 1 (8)
g~~I constant L ~
for:
V,P < v,.n G Voo - V,n (9)
Notice that the linear dependence on the input voltage level is removed
when the product of the p-channel mobility and the width to length ratio
of thep-channel FET is equal to the product of the n-channel mobility and
the width to length ratio of the n-channel FET. Thus, this condition is a
good base point from which to design a parallel switch.
Typically, the n-channel electron mobility is equal to 1300
centimeters squared per volt second (cm2/vs) for silicon. Typically, the p-
channel hole mobility is equal to 500 cm2/vs for silicon. However, the
mobility of a function of the doping of a substrate and, thus, varies
depending on the substrate technology on which the FET is formed. In
prior art parallel switches, the width to length ratio for the n-channel and
p-channel FETs are set equal to one another resulting in an on-resistance
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curve such as the one shown in Figure 5. However, as seen by
examination of Equation 7 and based upon the marked difference between
electron and hole mobility, setting the width to length ratio equal is notthe
optimal starting point. In fact, for silicon, assuming that the length of the
MOSFETs is maintained at the minimum available on the technology for
best performance, it is advantageous to design the width of the p-channel
FET to be 2, 2.3 2.5, 2.8, 3 times or more wider than the width of the n-
channel FET. For germanium, it is also advantageous to design the width
of the p-channel FET to be 2, 2.3 2.5, 2.8, 3 times or more wider than the
width of the n-channel FET.
As noted above, the conductance of the parallel switch is also
dependent on the input voltage level in a non-linear fashion. Therefore,
in order to optimize the estimate, a design can be optimized in a
commercial available DC simulator such as SPICE which was developed of
the University of California, Berkeley.
In one exemplary embodiment, the switch is constructed from two
FETs formed on a common substrate using 0.25 micron silicon technology.
The width of the n-channel FET is set at 12 microns and the width of the p-
channel FET was optimized to be 44 microns.
Figure 9 is an x/y graph showing the resistive value of the
exemplary parallel switch described above according to the invention as a
function of the voltage level of the input signal using a 1 picofarad (pF)
sampling capacitor. In Figure 9, the horizontal axis represents the input
signal voltage level in volts. The vertical axis represents the ohmic
resistance of the parallel switch in Ohms (S). Notice that between 1.0 to
1.4 V the resistance of the switch varies by about 5%. The linearity of the
switch can be reduced below 5% such as 4%, 2%, 1% or even less than 1%
over the usable input voltage range depending on the tolerance with
which the substance used to construct the device may be controlled but
may be slightly more in other implementations such as 6, 7, 8, 9% or
more. Figure 10 is an x/y graph showing the frequency response of an
exemplary parallel switch according to the invention. The solid curve
represents the frequency response of the parallel switch at an input
voltage level of 1.4V. The dotted curve represents the frequency response
of the parallel switch at an input voltage level of l.OV. Notice that they
are nearly identical. Figure 11 is an x/y graph showing the phase
response of an exemplary parallel switch according to the invention. The
solid curve represents the phase response of the parallel switch according
to the invention at an input voltage level of 1.4V. The dotted curve 34
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represents the phase response of the parallel switch according to the
invention at an input voltage level of 1.OV. Notice that they are nearly
identical. In both Figures 10 and 11, the 3 decibel (dB) point of the circuit
was found to be 590 MHz at each voltage level plotted.
5 One advantage of sample and hold circuits is that they can used in
the place of traditional front end assemblies. Traditional front end
assemblies typically comprise a series of amplifiers, mixers and samplers.
High frequency signals are received by the front end, amplified, down
converted to a lower frequency and sampled. Through the use of
10 subsamplin& a sample andholdcircuit mayreceive a high frequency signal
and produce a sampled low frequency signal. If the sample and hold circuit
is capable of high frequency operation, it may replace a substantial amount
of the functions of a traditional front end assembly. A sample and hold
circuit may provide improved performance, higher levels of integration,
lower power consumption and reduced costs compared to conventional
front end assemblies. However, if the sample and hold circuit produces a
non-linear effect, the performance of the system may be degraded in
comparison to traditional front end assemblies. Therrefore, a subsampling,
sample and hold circuit whidl is designed to operate at relatively high
input frequenciesis an ideal circuit in which to incorporate theinvention.
Figure 12 is a schem atic diagram showing an exemplary
embodiment of a sample and hold circuit comprising a parallel switch
according to the invention. Vlp and V;n represent a balanced input to the
sample andholdcircuit. In the preferred embodiment, the switches 50, 52,
54 and 56 are linear switches constructed as detailed above although other
switch structures can be used The inverted and non-inverted output of
the circuit produce a subsampled version of a band-limited, modulated
signal applied to the input. The linearity of switches 62, 64, 70, 74 and 76
and the swibch pair 72 is less critical than the linearity of the switches
whidl
pass the high frequency signals and these switches can be either linear
switches as detailed above or other switches. The capacitors 58, 60, 66 and
68 can be metal-metal or poly-poly type capacitors or any other type of
capacitor exhibiting a linear relationship between charge (Q) and voltage
(v). An operational amplifier 78 buffers the signal and also provides gain
to the circuit. The illustrated circuit has a gain of two.
Each of the switches is switched on and off according to a clock
signal. If the circuit shown in Figure 12 is used to subsample a high
frequency signal, the clock frequency should be more than twice as high as
theband-limited, modulation carried on the input signal. The frequency
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of the clock can be lower than the carrier frequency which carries the
band-limited, modulated signal at the input to the circuit. Figure 13 is a
timing diagram showing the time relationship of the clocks used to operate
the circuit in Figure 12. The clock 01 is the phase 1 clock. The clock Ole is
an
early phase of the phase 1 clock. The clock Old is a delayed phase of the
phase 1 clock. Theclock 0Z is a non-ov erlapping phase 2 clock. The phase 1
and phase 2 clocks are non-overlapping in that the phase 1 clock's rising
and falling edges each occur without an interveningtransition in the phase
2 dock and vice versa. The dock 02.d is a delayed phase of the non-
overlapping phase 2 clock whidz is also non-overlapping with any of the
phase 1 clocks. The docks Cd ,f2d and fie are the inverse of the docks O,a,
02d and 0Z, respectively.
Referring again to Figure 12, it can be seen thatthe switch 50 and the
switch 52 are both coupled to the positive input V;p and the capacitor 58 and
the capaci-tor 60 are connected to the far side of the switches 50 and 52,
respectively, in order to hold the sampled values. Likewise, the switch 54
and the switch 56 are both coupled to the negative input V;r, and the
capacitor 66 and the capacitor 68, respectively, are connected to the far side
of the swibches 54 and 56 in order to hold the sampled value. The switch 62
is coupled between the junction of the switch 52 and the capacitor 60, and
ground. The switch 64 is coupled between the j unction of the switch 54 and
the capacitor 66, and ground.
The far side of the capacitors 58 and 60 are coupled to the negative
input of the op amp 78. The far side of the capacitors 66 and 68 are coupled
to the positive input of the op amp 78. In addition, the switch 70 and
switch pair 72 are connected in parallel between the negative and positive
inputs of the op amp 78. In one embodiment, the switch 70 is an
nMOSFET switch which exhibits good mobility and conductance. In one
embodiment, the switch pair 72 is a set of nMOSFET switches which exhibit
good mobility and conductance. The switch pair 72 also has a ground
connection. The switch 74 is coupled between the j unction of the switch 50
and the capacitor 58, and the non-inverted output Vap of the op amp 78.
The switch 76 is coupled between the junction of the switch 56 and the
capacitor 68, to the inverted output Von of the op amp 78.
The phase 1 clock is used to sample the input. The phase 2 clock is
used to transfer the charge from the capacitors 60 and 66 to the capacitors 58
and 68, respectively, to produce the sampled output with a gain of two.
When the switches 70, 50, 52, 54 and 56 and the switch pair 72 are closed
and the remainder of the switches are open, the capacitors 58, 60, 66 and
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68 sample the input voltage level. Subsequently, when the switches 70,
50, 52, 54 and 56 and the switch pair 72 open and the switches 62, 64, 74
and 76 close, the capacitors 58 and 68 form the feed back loop to op amp
78. The capacitors 60 and 66 are grounded to set the gain of the circuit to
two.
The switch 70 is clocked with the phase 1 clock 0, and the switch pair
72 is docked with the early phase of the phase 1 clodc o1e. This clock
sequencingensures thatthepotential on far side of the capacitors 60 and 66
is set to ground shortly before the switch 70 opens to determine the
sampling instance. The switches 50, 52, 54 and 56 are clocked with the
delayed phase of the phase 1 clock O,d and clock Cid , and are opened shortly
after the sampling instance to dismnnect the sampling capacitors 58, 60, 64
and 68 from the input such that the sampled charges are stored thereon.
This clock sequencing reduces any signal dependent charge injections into
the sampling capacitors 58, 60, 66 and 68.
The switches 74 and 76 are dosed with the phase 2 clock 0z and clock
T'2 in order to dose the feed back loop around the op amp 78. Shortly
thereafter, the switches 64 and 62 are docked with the delayed phase of the
phase 2 dodc 02d and clodc f2d in order to connect the input of the sampling
capacitors 58, 60, 66 and 68 to ground. By grounding the input of the
sampling capacitors 60 and 66, the charges on the sampling capacitors 60
and 66 are transferred to the sampling capacitors 58 and 68 which are now
in the op amp 78 feedback path. Because the input to the op amp 78 is at a
ground potential, the output of the op amp 78 is now twice the sampled
voltage level, thus, completingone sample cycle.
If the switches 50, 52, 54 and 56 are con stru cted according to the
invention to provide linear switching characteristics, the sample and hold
circuit exhibits a high degree of linearity due to the relative independenoe
of the freqZency and resistive response of the circuitry to the voltage level
of the input signal. In addition, the cirazit offers an advantage over the
simple parallel switch shown in Figure 8 in that it provides a gain of two,
and isolation between the input and the output as well as substantial
current driving capabilities.
Figure 14 is a schematic diagram showing an exemplary
embodiment of a double sampled, unity gain, switched capacitor circuit
comprising a parallel switch configured according to the invention. In
Figure 14, the parallel switches according to the invention are shown as
single switches in order to avoid over clutteringthe drawing. In additional
to the information given below, information concerning double sampled
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circuits can be found in "A 160 MHz Fourth-Order pouble-Sampled SC
Bandpass Sigma-Delta Modular" IEEE Transactions on Circuits and
Systems -11: Analog and Digital Signal Processing, May 1998, Vol. 45, No. 5,
pp. 547-555 by Seyfi Bazarjani and W. Martin Snelgrove whidl is
incorporated herein by this reference.
The double sampled, unity gain, switched capacitor circuit accepts a
balanced input. The design is differentially symmetric and the positive and
negative input portions of the circuit operate in the same manner. Each of
the switches is switched on and off according to a clock signal. If the
circuit
shown in Figure 14 is used to subsample a high frequency signal, the clock
frequency should be more than twim as high as the band-limited,
modulation carried on the input signal. The frequency of the clock can be
lower than the carrier frequency which carries the band-limited,
modulated signal at the input to the circuit. Figure 15 is a timing diagram
showing the time relationship of the clocks used to operate the circuit in
Figure 14. The main system dock CK is used to derive the two other clocks
shown in Figure 15. The period of the dock CK, T, is fixed according to the
desired sampling frequency, fs. The dock 01 is the phase 1 dock. The clock
Old, not shown, is a delayed phase of the phase 1 cloclc. The dock 0Z is a
non-overlapping phase 2 clock. The dock C, not shown, is a delayed phase
of the non-overlapping phase 2 clock.
The balanced input is applied at the positive input V;p and the
negative input V;,,,. A switch 100 and a switch 112 are both coupled to the
positive input V;p and a capacitor 102 and a capacitor 114 are connected to
the far side of the switches 100 and 112, respectively, in order to
alternately
hold the sampled values. Likewise, a switch 124 and switch 136 are both
coupled to the negative input Vu, and a capacitor 126 and a capacitor 138,
respectively, are connected to the far side of the swibches 124 and 136 in
order to alternatelyhold the sampled value.
A switch 110 is coupled between the junction of the switch 100 and
the capacitor 102, and the positive output Vop of an op amp 150. A switch
122 is coupled between the junction of the switch 112 and the capacitor 114,
and the positive output Vop of the op amp 150. A switch 134 is coupled
between the junction of the switch 124 and the capacitor 126, and the
negative output Voõ of theop amp 150. A switch 146 is coupled between the
junction of the switch 136 and the capacitor 138, and the negative output
V on of the op amp 150.
The far side of the capacitors 102 and 114 are coupled to the negative
input of the op amp 150 through a switch 104 and a switch 116, respectively.
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14
The far sides of the capacitors 126 and 138 are coupled to the positive input
of the op amp 150 through a switch 128 and a switch 140, respectively. A
switch 106 and a switch 108 are connected in series to ground from the
j unction of the capacitor 102 and the switch 104. A switch 116 and a switch
120 are connected in series to ground from the junction of the capacitor 114
and the switch 116. A switch 130 and a switch 132 are connected in series to
ground from the j unction of the capacitor 124 and the switch 128. A switch
142 an d a switch 144 are connected in series to ground from the junction of
the capacitor 138 and the switch 140.
In the preferred embodiment, the switches 100, 112, 124 and 136 are
linear switches constructed as detailed above although other switch
structures can be used. It is advantageous for the switches 100, 112, 124 and
136 to have linear properties in order to avoid distortion of the incoming
high frequency signal during the sampling process as detailed above. The
other switches can be linear switches as detailed above or they may have
other circuit structures such as standard pMOSFET or nMOSFET switches
which exhibit good mobility and conductance. The sampling capacitors 102,
114, 126 and 138 can be metal-metal or poly-poly type capacitors or any other
type of capacitor exhibiting a linear relationship between charge (Q) and
voltage (v).
The main clock CK is used to trigger collection of samples by
means of the switches 106,118,130 and 142. The switch 108 in series with
switch 106 prevents the grounding of the junction of the capacitor 102
and the switch 104 at the falling-edges of the clock CK which occur while
the phase 1 clock is high and the phase 2 clock is low. Likewise, the switch
120 prevents the grounding of the junction of the capacitor 114 and the
switch 116 at the falling-edges of the clock CK which occur while the
phase 2 clock is high and the phase 1 clock is low. The switch 132
performs the same function as the switch 108 and the switch 144
performs the same function as the switch 120.
Using the clock CK ensures that the sampling instances are
uniformly spaced in time with relation to one another independent of
which capacitor is being used to sample the input. The time between
falling-edges of the clock CK is uniform if the frequency of the clock CK is
fixed. For example, the clock CK operates at a frequency fs and, therefore,
has a period of Ts as labeled on Figure 15. The paper referred to above
does not disclose the use of a uniform clock CK or the corresponding
switches 106, 116, 142 or 130 and, therefore, must rely on the falling-edge
of the phase 1 and phase 2 clocks which are not guaranteed to be
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uniformly spaced in time with relation to one another adding further
distortion to the sampling process.
The switches 100 and 112 are clocked by the delayed phase of the
phase 2 clock 02d and the delayed phase of the phase 1 clock Old,
respectively,
5 alternately connecting the positive input to one of the two sampling
capacitors 102 and 114. While the switch 112 connects the capacitor 114 to
the input, the switches 104 and 110 close to connect the capacitor 102 into
the feed back of the op amp 150 while the switches 106 and 108 are open.
While the switch 100 connects the capacitor 102 to the input, the switches
10 116 and 122 close to connect the capacitor 114 into the feed back of the op
amp 150. A corresponding operation is carried out within the negative
input portion of the circuit. Thus, samples are produced at the output of
the op amp at the frequency fs of the clock CK rather than the lower
frequency of the phase 1 andphase 2 clocks. At thesametime, the clock CK
15 is not used in the dosed loop configuration of the op amp. Therefore, the
op amp 150 is only required to settle within the relatively long period of
time overwhich the phase 1 andphase 2 docks are high, Th, rather than the
shorter period of time over which the dock CC is high reducing the op
amp performance characteristics demanded by the circuit.
The cirauit shown in Figure 14 consumes about one half of the
power of the circuit shown in Figure 12 when running at the same
frequency. Alternatively, the circuit shown in Figure 14 can operate at
twiae the frequency of the circuit shown in Figure. 12 while consuming
approximately the same curient. These efficiencies are gained because the
op amp is nearly constantly producing an output in comparison with
Figure 12 where the op amp lies idle about one half of the time. This
circuit can be used in a variety of applications such as sample and hold
circuits or analog to digital converters.
A myriad of alternate embodiments within the scope of the
invention will be readily disoernible to one skilled in the art upon
examination of the above disdosure. The techniques can be applied to
complimentary metal oxide semiconductors (CMC6) and junction field
effect technology (jFET) semiconductr)rs. These same principles may be
applied to gallium arsenide (GAs) as well. Also, the capacitors 60 and 66 of
Figure 12 maybe removed if unity gain is desired.
The invention may be embodied in other spedfic forms without
departing from its spirit or essential characteristics. The described
embodiment is to be considered in all respects only as illustrative and not
restrictive and the scope of the invention is, therefore, indicated by the
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16
appended claims rather than by the foregoing description. All changes
whidl come within the meaning and range of equivalency of the claims
are to be embraced within their scope.
WHAT IS CLAIMED IS:
