Note: Descriptions are shown in the official language in which they were submitted.
CA 02690442 2010-01-19
DISTORTION CANCELLATION METHOD AND CIRCUIT
Field of the Invention
This invention relates generally to distortion cancellation in electronic
circuits. In
particular, this invention relates to distortion cancellation applied to a
circuit output, to reduce or
cancel intermodulation distortion products in the circuit.
Background
The intermodulation distortion (IMD) of an electronic circuit such as an
amplifier, mixer,
or other circuit is an important consideration in many applications. The third-
order
intermodulation product intercept point (IP3) is commonly used to characterize
IMD. This is
based on the typical situation where the desired signal and an interference
signal are nearby in
the frequency domain. Non-linearities in the circuit generate new signals that
can cause
interference with the desired signal. Third-order nonlinearities, in
particular, are often the most
important because they generate intermodulation distortion products that are
close to the desired
signal and cause interference, and often cannot be removed by filtering.
Several methods have been suggested that can potentially improve the linearity
of a
circuit such as an amplifier. These include predistortion, feedback,
feedforward, optimal biasing,
and derivative superposition.
Predistortion techniques rely on the ability to distort the input signal to a
circuit such that
it is the inverse of the circuit's nonlinearity, and are often used in power
amplifiers (e.g., [1]) and
mixers. Active feedback has been used to linearize a low-noise amplifier (LNA)
[2], but in some
cases the noise figure may be seriously degraded using this technique.
Feedforward distortion
cancellation was used in both [3] and [4]. While a high IP3 was obtained in
[3], only simulation
results awere shown. In [4], a duplication of the original amplifier is
required, which doubles the
power consumption, and also requires different input signal power levels for
the main and
auxiliary amplifier circuits. The optimal biasing technique relies on accurate
biasing of the
transistors such that the third-order nonlinearity coefficient is zero. While
this technique has
CA 02690442 2010-01-19
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been demonstrated with good results (e.g., a 10.5 dB IP3 improvement in [5]),
it is very sensitive
to bias variations. The derivative superposition technique uses parallel
transistors with different
biases such that when the signals are summed, the distortion terms are
cancelled. Two or more
FETs are used in parallel with different bias points and widths in order to
control distortion at the
output. This technique has been used in [6]-[8] with measured IP3 improvements
of 10 dB or
more.
A typical derivative superposition circuit with two FETs is shown in Figure 1.
This
circuit is most commonly used to control third-order intermodulation (1M3)
distortion by
separately biasing the two FETs such that one has a positive third-order
coefficient and the other
a negative third-order coefficient with equal magnitudes. This can result in a
significant
improvement in the IP3 of an amplifier, for instance. In [6], derivative
superposition was used in
a cascode amplifier design by adding an additional common source transistor in
parallel with the
original common-source transistor (each with appropriate gate bias and device
width).
A drawback common to all of the distortion cancellation techniques described
above is
that they usually must be integrated within the amplification circuitry. This
means that they must
be designed together with the amplifier, which limits design flexibility.
Summary
Described herein is a method for reducing or cancelling intermodulation
distortion in a
circuit, the circuit having an output including a fundamental signal and
intermodulation
distortion, comprising: generating, from the circuit output: (i) a primary
output including the
intermodulation distortion and the fundamental signal; (ii) an auxiliary
output, including a
portion of the intermodulation distortion that is substantially equivalent in
magnitude and
inverted relative to the intermodulation distortion in the primary output, and
the fundamental
signal; and summing the primary and auxiliary outputs such that the portion of
the
intermodulation distortion is reduced or cancelled; such that intermodulation
distortion of the
circuit is reduced or cancelled.
CA 02690442 2010-01-19
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The portion of the intermodulation distortion may be at least one odd-order
intermodulation product. The portion of the intermodulation distortion may be
a third-order
intermodulation product.
In one embodiment, the fundamental signals of the primary and auxiliary
outputs are
summed, such that output power of the fundamental signal is increased. The
contribution of the
auxiliary output to the fundamental signal output power may be smaller than
the contribution
from the primary output.
In another embodiment, generating the primary output may comprise using a
buffer, and
generating the auxiliary output may comprise using a buffer. The buffers may
be of substantially
the same type.
The method may include a derivative superposition technique.
In another embodiment the method may comprise generating, from the circuit
output: two
or more auxiliary outputs, each auxiliary output including a portion of the
intermodulation
distortion that is substantially equivalent in magnitude and inverted relative
to the
intermodulation distortion in the primary output, and the fundamental signal;
and summing the
primary and auxiliary outputs such that the portions of the intermodulation
distortion are reduced
or cancelled. The portions of the intermodulation distortion may be odd-order
intermodulation
products.
Also described herein is an intermodulation distortion reducing or cancelling
circuit,
comprising: a primary path circuit that receives a preceding circuit output
including a
fundamental signal and intermodulation distortion, and generates a primary
output including the
fundamental signal and the intermodulation distortion; an auxiliary path
circuit that receives the
preceding circuit output and generates an auxiliary output including the
fundamental signal and a
portion of the intermodulation distortion that is substantially equivalent in
magnitude and
inverted relative to the intermodulation distortion in the primary output; and
means that sums the
primary and auxiliary outputs such that the portion of the intermodulation
distortion is reduced or
cancelled; wherein intermodulation distortion of the preceding circuit is
reduced or cancelled.
CA 02690442 2010-01-19
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The portion of the intermodulation distortion may beat least one odd-order
intermodulation product. The portion of the intermodulation distortion may be
a third-order
intermodulation product.
In one embodiment, the primary path circuit may comprise a buffer and the
auxiliary path
circuit may comprise a buffer. The buffers may be of substantially the same
type. The buffers
may be source-follower buffers.
In another embodiment, the intermodulation distortion reducing or cancelling
circuit may
comprise two or more auxiliary path circuits that receive the preceding
circuit output and
generate auxiliary outputs including the fundamental signal and portions of
the intermodulation
distortion that are substantially equivalent in magnitude and inverted
relative to the
intermodulation distortion present in the primary output; and means that sums
the primary and
auxiliary outputs such that the portions of the intermodulation distortion are
reduced or
cancelled. The portions of the intermodulation distortion may be odd-order
intermodulation
products.
In the intermodulation distortion reducing or cancelling methods and circuits
described
herein, the preceding circuit may be an amplifier, a mixer, an active filter,
an active attenuator, or
a buffer.
Brief Description of the Drawings
For a better understanding of the invention, and to show more clearly how it
may be
carried into effect, the invention will be described, by way of example, with
reference to the
accompanying drawings, wherein:
Figure 1 is schematic diagram of a derivative superposition circuit using two
field effect
transistors (FETs) according to the prior art.
Figure 2(a) is a schematic diagram of a conventional cascode amplifier; Figure
2(b) is a
schematic diagram of a cascode amplifier with third-order IMD cancellation
according to an
embodiment; Figure 2(c) is a schematic diagram of a cascode amplifier with
third-order IMD
cancellation according to another embodiment.
CA 02690442 2010-01-19
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Figure 3 is a block diagram showing an embodiment of a distortion cancellation
circuit
with multiple auxiliary paths.
Figure 4 is a plot showing typical third-order nonlinearity coefficient as a
function of
gate-source voltage VGS.
Figure 5 is a plot showing measured S-parameters for a conventional cascode
amplifier
and for the embodiment of Figure 2(b).
Figure 6 is a plot showing output power spectra for a conventional cascode
amplifier and
for the embodiment of Figure 2(b).
Figure 7 is a plot showing IP3 measurements for a conventional cascode
amplifier and for
the embodiment of Figure 2(b).
Figure 8 is a photomicrograph of a chip including a conventional cascode
amplifier (top)
and the embodiment of Figure 2(b) (bottom).
Detailed Description of Embodiments
Described herein is a distortion cancellation technique which is applied to
the output of a
circuit that generates nonlinear distortion (i.e., intermodulation
distortion), particularly odd-order
intermodulation distortion. For example, distortion cancellation as described
herein may be
employed to improve third-order linearity and attenuate third-order
intermodulation distortion
products, without significantly increasing the noise figure of the circuit. As
will be appreciated
by those of ordinary skill in the art, the embodiments described herein may be
applied to circuits
such as, but not limited to, amplifiers, buffers, active attenuators, active
filters, and mixers.
Techniques conventionally employed to reduce distortion of a circuit, such as
predistortion, feedback, feedforward, optimal biasing, and derivative
superposition, are generally
integrated into the circuit design and do not use the circuit output. In
contrast, the technique
described herein implements distortion cancellation after a preceding circuit
to reduce or cancel
intermodulation distortion products generated by the preceding circuit. In
particular, a distortion
cancellation circuit as described herein receives the output of a preceding
circuit and uses the
CA 02690442 2010-01-19
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output to generate signals to reduce or cancel distortion. This opens the
possibility of enhancing
the linearity of a pre-existing circuit by following it with a distortion
cancellation circuit.
Furthermore, since the distortion cancellation circuit is connected to the
output of the preceding
circuit, it has no effect or only a minor effect on the gain and noise figure
of the preceding
circuit.
In some embodiments of the distortion cancellation circuit described herein,
the design is
based on a unity gain buffer or source follower. Such design is well-suited to
distortion
cancellation because of its inherently high linearity. In addition, unity
gain, or very low gain
(e.g., 0.1 to 0.3 dB), of this design render the distortion cancellation
circuit substantially
transparent when connected to a preceding circuit and/or a following circuit.
As such, a
distortion cancellation circuit as described herein can be inserted between
virtually any circuit
blocks of a system. Measurement results of an embodiment of the technique
described herein,
connected to the output of a cascode amplifier, show a very minor effect on
the gain and noise
figure characteristics of the original amplifier, but a significant
improvement in the IP3.
As described herein, distortion cancellation employs a derivative
superposition technique.
This technique includes feeding the output of a preceding circuit into a
distortion cancellation
circuit including a primary path and an auxiliary path. As used herein, the
term "preceding
circuit" refers to the circuit for which distortion is to be reduced or
cancelled. The output of the
preceding circuit includes a fundamental signal (i.e., the signal of interest)
and intermodulation
distortion. For example, the output of the preceding circuit may include odd-
order
intermodulation distortion products, even-order intermodulation distortion
products, or both. In
applications not involving extremely wide bandwidths, odd-order
intermodulation distortion may
be reduced or cancelled. Of the odd-order intermodulation distortion products,
the third-order
products typically have the greatest magnitude and can be reduced or cancelled
as described
herein.
In the following paragraph, operation of the distortion cancellation circuit
is described by
way of an example in which the third-order intermodulation product in the
output of a preceding
circuit is reduced or cancelled. The primary path of the distortion
cancellation circuit produces
an output that is substantially the same as the output of the preceding
circuit; that is, it includes
the fundamental signal and the third-order intermodulation product. The
auxiliary path is tuned
CA 02690442 2010-01-19
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so as to invert the third-order intermodulation product, relative to the
primary path, and to leave
the fundamental signal in phase with the primary path. In one embodiment, this
is accomplished
by biasing transistor(s) in the auxiliary path to have a negative gri3
coefficient whose absolute
value is the same as the 9,,,3 of the primary path, as shown in Figure 4. As
an example, the
auxiliary path may produce a third-order intermodulation product current that
is equal in
magnitude to that of the primary path, but substantially 180 out of phase.
The resulting third-
order intermodulation products of the primary path and the auxiliary path are
summed at the
output of the distortion cancellation circuit, substantially cancelling the
third-order
intermodulation products. The fundamental signals in the primary path and the
auxiliary path are
substantially in phase, and are added, thus potentially increasing the
fundamental output power.
However, the contribution of the auxiliary path to the fundamental output
power may be smaller
than from the primary path.
The primary path and the auxiliary path may be tuned as to their gain on the
magnitude of
the fundamental signal and on third-order intermodulation products, so as to
optimize
performance of the distortion cancellation circuit. For example, such tuning
may maximize the
difference in magnitude between the fundamental signal and the third-order
intermodulation
products, thereby substantially reducing or cancelling intermodulation
distortion (IMD).
However, it will be appreciated that such tuning of the primary path and the
auxiliary path has
substantially no effect on the phase of the fundamental signal.
Reduction or cancellation of further odd-order intermodulation products (e.g.,
fifth or
seventh order) may be accomplished by adding one or more further auxiliary
path circuits, each
auxiliary path circuit tuned to invert a specific odd-order product. For
example, Figure 3 shows
an embodiment of a distortion cancellation circuit 10 connected to the output
of a preceding
circuit 20. The distortion cancellation circuit includes a unity gain buffer
30 as the primary path
circuit and multiple auxiliary path circuits 40 - 70 each corresponding to an
odd-order
intermodulation distortion product. The outputs of the primary path circuit
and the auxiliary path
circuits are summed in a summer 80. Tuning of the primary path circuit and
auxiliary path
circuits is required to maximize the difference in magnitude between the
fundamental signal and
the odd-order intermodulation products, thereby substantially reducing or
cancelling IMD.
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As noted above, distortion cancellation as described herein may be applied to
a variety of
circuits, such as amplifiers, buffers, active attenuators, active filters, and
mixers. In the case of
an amplifier, it may be of a design such as, but not limited to, cascode,
common-source,
common-gate, class A, class AB, and travelling wave. It will be appreciated
that, because
distortion cancellation is applied to the output of, e.g., an amplifier, it
may easily be adapted to
an existing amplifier design or other circuit designs, avoiding the need for a
complete reworking
of the design. In addition, because distortion cancellation as described
herein is applied to the
output of an amplifier, it may be implemented as a retrofit to existing
hardware.
Distortion cancellation as described herein may be implemented in any suitable
technology, such as, CMOS, Bipolar, BiCMOS, SiGe, MESFET, HEMT, PHEMT, etc.
using,
for example, an integrated circuit based on substrates such as GaAs, Si, SiGe,
GaN, GaN, SiC,
InP, etc. Distortion cancellation as described herein is suitable for
broadband applications
because the technique used to invert the nonlinearity is not frequency-
dependent. Thus,
substantially the same bias settings work from approximately DC to the maximum
frequency of
the circuit(s) to which it may be applied. Accordingly, the technique may be
applied to the
signal path of circuits operating at frequencies in the audible range (e.g.,
audio systems) and
higher, for example, at radio frequencies (RF) and millimeter wave and
microwave frequencies,
as in, for example, radio and telecommunications systems. In contrast, a
conventional approach
such as a phase shift technique (e.g., using a delay line) is narrowband and
operates only within a
narrow frequency range. Furthermore, a phase shift technique inevitably
affects the fundamental
signal, whereas the methods and circuits described herein may be configured so
as to have
substantially no effect on the fundamental signal.
In one embodiment, a distortion cancellation circuit as described herein is
implemented
without or substantially without input and output matching networks. Such an
embodiment is
suitable for combining with an existing preceding circuit and/or an existing
following circuit. In
another embodiment, a distortion cancellation circuit as described herein is
implemented in
combination with a following circuit, and includes an input matching network.
In another
embodiment, a distortion cancellation circuit as described herein is
implemented in combination
with a preceding circuit, and includes an output matching network. In a
further embodiment, a
distortion cancellation circuit as described herein is implemented in
combination with preceding
CA 02690442 2010-01-19
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and following circuits, and includes an input matching network and an output
matching network.
This last embodiment is a stand-alone distortion cancellation (i.e.,
linearization) block. A
distortion cancellation circuit as described herein may be provided as a
module, with or without
input and/or output matching networks, to be inserted between circuit blocks
of existing systems.
Matching networks may induce some signal loss, and this may be compensated by
tuning of the
distortion cancellation circuit.
The primary path and the auxiliary path may each be an amplifier, mixer, or
buffer
circuit, such as, for example, a source-follower buffer. In one embodiment,
the primary path and
auxiliary path circuits may be connected in parallel. In some embodiments, the
primary and
auxiliary path circuits may be the same. Differences in performance of the
circuits in the
primary and auxiliary paths may be achieved by appropriately adjusting
independently the
biasing of those circuits.
Exemplary embodiments will be described below as applied to amplifiers.
However, as
noted above, distortion cancellation as described herein may be applied to
other circuits as well.
A conventional, general-purpose cascode amplifier is shown in Figure 2(a).
This amplifier uses
inductors Lg and LS for matching and the parallel tank circuit, C1 and L1, in
addition to any
parasitic capacitance, is designed to resonate at a desired frequency.
Figure 2(b) shows an embodiment of a distortion cancellation circuit, which
provides
third-order intermodulation distortion cancellation, applied to the cascode
amplifier of Figure
2(a). Operation of this circuit will be described below.
In general, the output drain current of a FET amplifier can be described by
the power
series:
2 3
id = 9rn1 'gs + 9m2V9S + gm v , +- ...
where
CHID
gnaw
&117 n
G, S
are the coefficients of the fundamental (n = 1) and higher order (n > 1) terms
that lead to
nonlinearities. The IP3 performance is predominantly determined by the third-
order nonlinearity
CA 02690442 2010-01-19
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coefficient, gm3. The input IP3 (IIP3), which is the point at which the power
in the third-order
intermodulation products is extrapolated to intersect the input power, for an
amplifier with a 50
ohm input impedance is given by [3]:
IIP3 = 10 lob 40
dBm (3)
3 g:
It is well known in the art that the gm3 coefficient can be either positive or
negative, depending
on the biasing conditions (e.g., see [5]). In fact, gm3 changes from positive
to negative as the
FET transitions from the weak to strong inversion regions, as shown in Figure
4. The ability to
control the sign of the third order coefficient is the property used in this
work to design an
amplifier with third-order IMD cancellation.
In the embodiment of Figure 2(b) the distortion cancellation circuit includes
two parallel
source-follower buffers. The load resistor, RL, may be designed to be somewhat
greater than 50
ohms so that the resulting increased voltage amplitude is equal to the loss
through the buffer
consisting of transistors M3 and M4. The result is a fundamental output that
is substantially the
same as the output of the amplifier in Figure 2(a). The auxiliary path through
the buffer M5 and
M6 is designed with appropriate biasing and device sizes such that the third-
order nonlinearity
current that is generated is equal in magnitude to the primary path, but 180
out of phase. The
phase inversion is achieved by biasing M3 and M5 independently in the negative
and positive
gm3 regions, respectively. For the primary path, through M3 and M4, the
required VGS will
typically be in the strong inversion region, and thus will have a negative
gm3. The auxiliary path
through M5 and M6 is therefore biased through Vg2 and Vg3 to be in the weak
inversion region
where there is a positive gm3. The resulting third-order nonlinearity currents
are summed at the
output, resulting in distortion cancellation. Since the fundamental signal
maintains the same sign
for both buffer circuits, it is added in-phase, thus increasing the
fundamental output power.
However, since a positive gm3 occurs in the weak or moderate inversion
regions, the
contribution of the auxiliary path to the fundamental output power is much
smaller than from the
primary path (since gm, is small in the weak and moderate inversion regions).
CA 02690442 2010-01-19
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Consider two input signals to the amplifier shown in Figure 2(b) with
different
frequencies, fl and f2. At the output of the conventional amplifier block are
the fundamental
signals, fl and f2, as well as the IM3 signals generated in the cascode
amplifier (2fl + f2 and 212
fl). The IM3 products at the output of M3-M4 are the sum of the IM3 signals
generated by the
conventional amplifier and those generated in M3-M4 from the amplified fl and
12 signals. The
M3-M4 buffer is biased such that the gm3 coefficient is negative. The
auxiliary path M5-M6
buffer is designed to be in the positive gm3 region, and it therefore produces
IM3 products that
are opposite in phase relative to those generated by the M3-M4 buffer. By
designing each
source-follower buffer in the distortion cancellation circuit to generate IM3
currents that are
equal in magnitude, but 180 out of phase, the IP3 performance of the
amplifier may be
significantly improved by summing these currents at the output.
In simulations, existing BSIM3 FET models were used in order to choose bias
points that
resulted in optimal distortion cancellation, and the simulations produced
accurate predictions. If
accurate device models are not available, this technique can still be used,
but IM3 measurements
for the chosen technology may be necessary to achieve optimal performance.
In the embodiment of Figure 2(b) there are two transistors shown in parallel
which
generate intermodulation components that cancel distortion from the preceding
circuit. It is also
possible to have more than two transistors in parallel. Having more than two
transistors in
parallel provides more flexibility and accuracy in the distortion cancellation
signals that are
generated, and reduces sensitivity to bias voltages. In particular, by using
more than two
transistors in parallel, the overall response with respect to bias voltage
(see Figure 4) can be
"flattened", making the circuit performance less susceptible to degradation
from voltage
fluctuations.
Figure 2(c) shows an embodiment similar to that of Figure 2(b), implemented
with
current sources.
Embodiments are further described by way of the following non-limiting
example.
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Example
A chip was fabricated using a standard CMOS process with a silicon substrate,
based on
the circuits of Figures 2(a) and 2(b). A photomicrograph of the fabricated
chip is shown in
Figure 8. The dimensions of the chip were 1 mm x 1 mm with each amplifier
using half of this
space (0.5 mm2). The additional chip area required by the distortion
cancellation circuitry was
approximately 300 pm x 200 pm (0.06 mm2).
The supply voltage for both amplifiers was set to 1.8 V and the bias voltages
on the third-
order IMD cancellation amplifier were Vgl = 1.0 V, Vg2 = 0.52 V, and Vg3 = 1.5
V. To
characterize the performance of both of the amplifiers, a full two-port
calibration was performed
and the S-parameters were measured using a vector network analyzer. The
results are shown in
Figure 5. It is clear that both amplifiers had very similar S 11 and S21
characteristics. Note that
the amplifier with third-order IMD cancellation achieved a slightly higher
gain and a slightly
larger bandwidth. For both amplifiers the gain and return loss at 2.4 GHz were
approximately 16
dB and -10 dB, respectively.
To determine the linearity of each amplifier, a two-tone input signal (2.400
GHz and
2.401 GHz) was used and the output power of the third-order distortion was
measured. Shown in
Figure 6 is the output spectrum for both amplifiers superimposed so that the
difference in third-
order intermodulation distortion is clear.
The input power used for each tone was -30 dBm. It was not possible to
distinguish
between the two amplifiers with regard to the fundamental outputs. For both
amplifiers, the two
fundamental outputs showed a power of approximately -14 dBm as expected since
the measured
S21 was approximately 16 dB. The third-order intermodulation distortion
products occurred at
2.399 GHz and 2.402 GHz (2fl - f2 and 2f2 - fl) for this two-tone test. In the
case of the
conventional amplifier, the output power of the third-order intermodulation
products was
approximately -67 dBm (dashed line). In the case of the amplifier with
distortion cancellation,
the third-order intermodulation products were attenuated by approximately 21
dB (solid line).
The plots of Figures 4 and 5 clearly illustrate that the distortion
cancellation method provides
much improved third-order linearity performance. The IP2 performance of the
amplifier was
degraded somewhat with this technique; however, since the second-order
distortion signals were
CA 02690442 2010-01-19
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far out of band (1 MHz and 4.801 GHz in this example), this would not be a
major concern in
most cases.
The input power of the two input tones was swept for each amplifier while the
fundamental and third-order distortion output powers were measured. The
results are shown in
Figure 7. The IIP3 of the conventional amplifier was approximately -2 dBm,
whereas the IIP3 of
the amplifier with distortion cancellation was approximately 10 dBm.
Therefore, a +12 dB
improvement in IIP3 was measured using the embodiment of Figure 2(b). With the
distortion
cancellation amplifier, the 1-dB compression point was reduced by
approximately 3 dB;
however, this may not be a significant concern, for example in cases where
there is a low input
power level (e.g., in a low-noise amplifier).
The noise figure of each amplifier was measured to determine the effect of the
distortion
cancellation circuit on the noise performance. At 2.4 GHz, the noise figure of
the conventional
amplifier was 4.02 dB, while the noise figure of the third-order IMD
cancellation amplifier was
4.18 dB, an increase of just 0.16 dB. Therefore, there was not a significant
degradation in the
noise figure with the circuit of Figure 2(b). The DC current used by the
conventional amplifier
was 21 mA, and for the distortion cancellation amplifier it was 31 mA. The
added current in the
proposed amplifier was due almost entirely to the M3-M4 source-follower
circuit shown in
Figure 2(b).
A commonly used figure of merit (FOM) [10] for low-noise amplifiers is defined
as:
OI F3
(F - 1) PDc
where OIP3 is the output-referred IP3 point, F is the noise factor, and PDC is
the DC power
consumption. The embodiment of Figure 2(b) achieved a FOM of 308, which
compares
favourably to most LNAs in the literature.
CA 02690442 2010-01-19
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Equivalents
Those skilled in the art will recognize, or will be able to ascertain,
equivalents to the
embodiments described herein. Such equivalents are within the scope of the
invention and are
covered by the appended claims.
CA 02690442 2010-01-19
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