Canadian Patents Database / Patent 2924874 Summary
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(12) Patent Application:  (11) CA 2924874 

(54) English Title:  DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 
(54) French Title:  DISPOSITIF ET PROCEDE DE TRAITEMENT DE DONNEES 
 Bibliographic Data
 Abstracts
 Claims
 Description
 Representative Drawing
 Admin Status
 Owners on Record
 Documents
(51) International Patent Classification (IPC): 


(72) Inventors : 

(73) Owners : 

(71) Applicants : 

(74) Agent:  GOWLING WLG (CANADA) LLP 
(74) Associate agent:  
(45) Issued:  
(86) PCT Filing Date:  20140912 
(87) Open to Public Inspection:  20150402 
(30) Availability of licence:  N/A 
(30) Language of filing:  English 
Patent Cooperation Treaty (PCT):  Yes 

(86) PCT Filing Number:  PCT/JP2014/074193 
(87) International Publication Number:  WO2015/045894 
(85) National Entry:  20160318 
(30) Application Priority Data:  


English Abstract
This technology pertains to a data processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In groupwise interleaving, an LDPC code having a code length of 64,800 bits and a code rate of 10/15, 11/15, 12/15, or 13/15 is interleaved on a perbitgroup basis, each bit group being 360 bits long. In groupwise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.
French Abstract
La présente invention se rapporte à une technologie d'un dispositif de traitement de données et d'un procédé de traitement de données qui permettent d'assurer une bonne qualité de communication lors de l'utilisation d'un code LDPC pour transmettre des données. Dans une imbrication par groupe, un code LDPC ayant une longueur de code de 64 800 bits et un taux de code de 10/15, 11/15, 12/15 ou 13/15 est imbriqué sur une base de groupe par bit, chaque groupe de bit ayant une longueur de 360 bits. Dans une désimbrication par groupe, le code LDPC imbriqué est restauré dans son ordonnancement d'origine. Ladite technologie peut s'appliquer, par exemple, à la transmission de données ou similaire à l'aide d'un code LDPC.
147
Claims
[1] A data processing device, comprising:
a groupwise interleave unit of performing group
wise interleave of interleaving in a 360bit group unit
an LDPC code whose code length is 64800 bits and code
rate is 10/15, 11/15, 12/15 or 13/15,
the (i + 1)th bit group from the beginning of the
LDPC code of the 64800 bits being as a bit group i, and
in the groupwise interleave, a sequence of bit
group 0 to 179 of the 64800 bits of the LDPC code being
interleaved into the following sequence of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[2] The data processing device according to claim 1,
further comprising:
a mapping unit of mapping the LDPC code onto any of
148
16 signal points defined by a modulation scheme in a 4
bits unit.
[3] The data processing device, according to claim 1,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 10/15,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
979 1423 4166 4609 6341 8258 10334 10548 14098 14514
17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721
18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727
17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580
16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395
17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438
149
16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304
14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913
16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384
18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618
15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240
17320 18126 19544 20208
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512
15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815
11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492
16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336
18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244
10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143
12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849
12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054
12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347
150
17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149
15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695
17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972
15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678
13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548
11914 13987 15442 15541 19707
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042
12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
151
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
152
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
153
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721.
[4] The data processing device, according to claim 1,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 11/15,
154
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157
10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195
15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027
12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917
13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009
15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109
16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633
14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082
14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974
16619 16961 17033 17237
155
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806
15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297
16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432
17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061
16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983
16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808
16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805
16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127
14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859
16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837
15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099
16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686
16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960
17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262
15795 16476 17084 17193 17220
156
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
157
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
158
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
159
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255.
[5] The data processing device, according to claim 1,
further comprising:
an encoder, which performs LDPC encoding based on a
160
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 12/15,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737
8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042
11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811
11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139
11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201
11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310
10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184
10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353
10583 11118 12762
161
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406
10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061
9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417
11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945
10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738
9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326
11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161
10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226
11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920
11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175
11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564
9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410
10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237
10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107
12411 12695 12812 12890
162
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074
11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663
8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038
9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473
9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
163
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
164
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
165
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
166
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904.
[6] The data processing device, according to claim 1,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 13/15,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
167
information matrix part for each 360 columns as
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681
6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534
8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529
8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365
8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456
8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548
8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504
8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612
8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495
8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509
8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580
8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394
8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544
8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922
168
8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515
8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320
8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521
8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302
8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513
8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484
8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512
8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578
8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270
8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518
8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383
8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527
8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
169
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
170
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
171
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
172
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
173
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979.
[7] A data processing method, comprising:
a step of groupwise interleaving, which groupwise
interleaves an LDPC code whose code length is 64800 bits
and code rate is 10/15, 11/15, 12/15 or 13/15 in a 360
bit group unit,
the (i + 1)th bit group from the beginning of the
LDPC code of the 64800 bits being as a bit group i, and
in the groupwise interleave, a sequence of bit
group 0 to 179 of the 64800 bits of the LDPC code being
interleaved into the following sequence of the bit group:
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681
6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534
174
8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529
8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365
8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456
8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548
8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504
8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612
8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495
8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509
8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580
8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394
8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544
8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922
8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515
8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320
175
8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521
8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302
8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513
8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484
8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512
8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578
8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270
8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518
8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383
8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527
8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
176
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
177
6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
178
22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
179
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
180
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979.
[8] A data processing device, comprising:
a groupwise interleave unit of performing group
wise interleave of interleaving in a 360bit group unit
an LDPC code whose code length is 64800 bits and code
rate is 10/15, 11/15, 12/15 or 13/15, and
of returning a sequence of the LDPC code after the
groupwise interleave obtained from data transmitted from
a transmitting device to the original sequence,
the (i + 1)th bit group from the beginning of the
LDPC code of the 64800 bits being as a bit group i, and
in the groupwise interleave, a sequence of bit
group 0 to 179 of the 64800 bits of the LDPC code being
interleaved into the following sequence of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
181
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[9] The data processing device according to claim 8,
further comprising:
a demapping unit of demapping the mapped data
obtained from the data transmitted from the transmitting
device further comprising a mapping unit of mapping the
LDPC code onto any of 16 signal points defined by a
modulation scheme in a 4 bits unit.
[10] The data processing device, according to claim 8,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 10/15, and
a decoder, which decodes the LDPC code provided from
the data transmitted from the transmitting device,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
182
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
979 1423 4166 4609 6341 8258 10334 10548 14098 14514
17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721
18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727
17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580
16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395
17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438
16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304
14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913
16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384
18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618
15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240
17320 18126 19544 20208
183
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512
15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815
11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492
16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336
18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244
10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143
12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849
12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054
12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347
17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149
15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695
17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972
15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678
13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548
11914 13987 15442 15541 19707
184
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042
12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
185
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
186
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
187
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721.
[11] The data processing device, according to claim 8,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 11/15, and
a decoder, which decodes the LDPC code provided from
the data transmitted from the transmitting device,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
188
information matrix part for each 360 columns as
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157
10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195
15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027
12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917
13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009
15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109
16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633
14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082
14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974
16619 16961 17033 17237
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806
15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297
16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432
17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061
16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983
189
16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808
16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805
16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127
14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859
16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837
15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099
16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686
16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960
17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262
15795 16476 17084 17193 17220
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
190
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
191
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
192
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
193
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255.
[12] The data processing device, according to claim 8,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 12/15, and
a decoder, which decodes the LDPC code provided from
the data transmitted from the transmitting device,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
194
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737
8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042
11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811
11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139
11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201
11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310
10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184
10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353
10583 11118 12762
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406
10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061
9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417
11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945
195
10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738
9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326
11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161
10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226
11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920
11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175
11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564
9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410
10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237
10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107
12411 12695 12812 12890
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074
11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663
8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038
9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473
196
9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
197
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
198
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
199
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
200
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904.
[13] The data processing device, according to claim 8,
further comprising:
an encoder, which performs LDPC encoding based on a
parity check matrix of an LDPC code whose code length is
64800 bits and code rate is 13/15, and
a decoder, which decodes the LDPC code provided from
the data transmitted from the transmitting device,
the LDPC code including information bits and parity
bits,
the parity check matrix including an information
matrix part corresponding to the information bits and a
parity matrix part corresponding to the parity bits,
the information matrix part being represented by a
parity check matrix initial value table, and
the parity check matrix initial value table being a
table indicating a position of an element 1 of the
information matrix part for each 360 columns as
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681
6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534
8539 8583
201
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529
8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365
8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456
8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548
8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504
8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612
8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495
8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509
8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580
8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394
8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544
8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922
8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515
8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320
8391 8526
202
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521
8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302
8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513
8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484
8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512
8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578
8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270
8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518
8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383
8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527
8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
203
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
204
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
22 830
205
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
206
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
207
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979.
[14] A data processing method, comprising:
a step of groupwise deinterleaving of returning a
sequence of the LDPC code after groupwise interleave
obtained from data transmitted from a transmitting device
to the original sequence, the transmitting device
comprising:
a groupwise interleave unit of performing group
wise interleave of interleaving in a 360bit group unit
an LDPC code whose code length is 64800 bits and code
rate is 10/15, 11/15, 12/15 or 13/15,
the (i + 1)th bit group from the beginning of the
LDPC code of the 64800 bits being as a bit group i, and
in the groupwise interleave, a sequence of bit group 0
to 179 of the 64800 bits of the LDPC code being
interleaved into the following sequence of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
208
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
CA 02924874 20160318
1
DESCRIPTION
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
Technical Field
[0001] The present technology relates to a data
processing device and a data processing method. In
particular, the present technology relates to a data
processing device and a data processing method that make
it possible to ensure good communication quality in a
data transmission using LDPC codes.
Background Art
[0002] Some of the information to be published in this
specification and drawings, Samsung Electronics Co. to
conduct joint development with Sony Corporation, Ltd.
(hereinafter, referred to as Samsung) is one that has
received the offer from the (explicitly in the drawings).
[0003] LDPC (Low Density Parity Check) code has high
error correction capabilities, and is widely used in
recent years in a transmission system including a digital
broadcasting such as DVB (Digital Video Broadcasting)
S.2, DVBT.2, DVBC.2 in Europe, and ATSC (Advanced
Television Systems Committee)3.0 in the United States
(for example, refer to NonPatent Document 1).
[0004] Recent studies has revealed that as the code
length of the LDPC code is prolonged, the LDPC code
achieves the performance as close as the Shannon limit
similar to the turbo code or the like. Also, the LDPC
CA 02924874 20160318
2
code has a property that the minimum distance is
proportional to the code length. As the advantageous
features of the LDPC code, the block error probability
characteristic is good, and a socalled error floor
phenomenon that is observed in the decoding
characteristic of the turbo code or the like is less
likely to occur.
[0005] NonPatent Document 1: DVBS.2 : ETSI EN 302
307 V1.2.1 (200908)
Summary of Invention
Problem to be solved by the Invention
[0006] Data transmission using an LDPC code, for
example, LDPC codes, is a symbol of QPSK (Quadrature
Phase Shift Keying) orthogonal modulation such as
(digital modulation) (is symbolized), the symbol, the
signal points of orthogonal modulation it is mapped to be
transmitted.
[0007] The data transmission using the LDPC code as
described above, it is becoming spread worldwide and is
requested to ensure a satisfactory communication quality.
[0008] The present technology has been made in view of
such circumstances, and, in the data transmission using
the LDPC code, is to ensure good communication quality.
Means for solving the Problem
[0009] The first data processing device/data
processing method of the present technology includes a
CA 02924874 20160318
3
groupwise interleave unit/step of performing groupwise
interleave of interleaving in a 360bit group unit an
LDPC code whose code length is 64800 bits and code rate
is 10/15, 11/15, 12/15 or 13/15, the (i + 1)th bit group
from the beginning of the LDPC code of the 64800 bits
being as a bit group i, and in the groupwise interleave,
a sequence of bit group 0 to 179 of the 64800 bits of the
LDPC code being interleaved into the following sequence
of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[0010] The first data processing device/data
processing method of the present technology performs
groupwise interleave of interleaving in a 360bit group
unit the LDPC code whose code length is 64800 bits and
code rate is 10/15, 11/15, 12/15 or 13/15. In the group
CA 02924874 20160318
4
wise interleave, the sequence of the 64800 bits of the
LDPC code bit group 0 to 179 is interleaved into the
following sequence of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[0011] The second data processing device/data
processing method of the present technology includes a
groupwise interleave unit of performing groupwise
interleave of interleaving in a 360bit group unit an
LDPC code whose code length is 64800 bits and code rate
is 10/15, 11/15, 12/15 or 13/15, and a groupwise
deinterleave unit/step of returning a sequence of the
LDPC code after the groupwise interleave obtained from
data transmitted from a transmitting device to the
original sequence, the (i + 1)th bit group from the
beginning of the LDPC code of the 64800 bits being as a
CA 02924874 20160318
bit group i, and in the groupwise interleave, a sequence
of bit group 0 to 179 of the 64800 bits of the LDPC code
being interleaved into the following sequence of the bit
group:
5 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[0012] The second data processing device/data
processing method of the present technology includes a
groupwise interleave unit of performing groupwise
interleave of interleaving in a 360bit group unit an
LDPC code whose code length is 64800 bits and code rate
is 10/15, 11/15, 12/15 or 13/15, and of returning the
sequence of the LDPC code after the groupwise interleave
obtained from data transmitted from a transmitting device
to the original sequence, the (i + 1)th bit group from
the beginning of the LDPC code of the 64800 bits being as
CA 02924874 20160318
6
a bit group i, and in the groupwise interleave, a
sequence of bit group 0 to 179 of the 64800 bits of the
LDPC code being interleaved into the following sequence
of the bit group:
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[0013] The data processing apparatus may be an
independent apparatus or may be an internal block making
up one device.
Effects of the Invention
[0014] According to the present technology, in the
data transmission using the LDPC code, it is possible to
ensure good communication quality.
[0015] Here, the effects described in are not
necessarily limited, it may be any of the effects
CA 02924874 20160318
7
described in the present disclosure.
Brief Description of Drawings
[0016]
[Fig. 1] A diagram illustrating a parity check matrix H
of an LDPC code.
[Fig. 2] A flowchart illustrating a decoding procedure
of an LDPC code.
[Fig. 3] A diagram illustrating an example of an LDPC
code of the parity check matrix.
[Fig. 4] A diagram illustrating a Tanner graph of the
parity check matrix.
[Fig. 5] A diagram showing a variable node.
[Fig. 6] A diagram showing a check node.
[Fig. 7] A diagram illustrating an example configuration
of an embodiment of a transmission system to which the
present technology is applied.
[Fig. 8] A block diagram showing a configuration example
of the transmitting apparatus 11.
[Fig. 9] A block diagram showing a configuration example
of the bit interleaver 116.
[Fig. 10] A diagram illustrating a parity check matrix
[Fig. 11] A diagram illustrating a parity matrix.
[Fig. 12] A diagram illustrating a parity check matrix of
an LDPC code prescribed in the standard of the DVBT.2.
[Fig. 13] A diagram illustrating a parity check matrix of
an LDPC code prescribed in the standard of the DVBT.2.
[Fig. 14] A diagram illustrating a Tanner graph for
CA 02924874 20160318
8
decoding of LDPC codes.
[Fig. 15] A diagram showing a parity matrix HT having a
staircase structure and a diagram illustrating a Tanner
graph corresponding to the parity matrix HT.
[Fig. 16] A diagram illustrating a parity matrix HT of the
parity check matrix H corresponding to the LDPC code
after the parity interleave.
[Fig. 17] A flowchart for explaining the processing
performed by a bit interleaver 116 and a mapper 117.
[Fig. 18] A block diagram showing a configuration example
of an LDPC encoder 115.
[Fig. 19] A flowchart illustrating a process of the LDPC
encoder 115.
[Fig. 20] A diagram illustrating an example of a parity
check matrix initial value table of a code rate of 1/4
and a code length of 16200.
[Fig. 21] A diagram for explaining a method of
determining a parity check matrix H from the parity check
matrix initial value table.
[Fig. 22] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 7/15.
[Fig. 23] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 7/15.
[Fig. 24] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 7/15.
CA 02924874 20160318
9
[Fig. 25] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 9/15.
[Fig. 26] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 9/15.
[Fig. 27] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 9/15.
[Fig. 28] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 11/15.
[Fig. 29] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 11/15.
[Fig. 30] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 11/15.
[Fig. 31] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 13/15.
[Fig. 32] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 13/15.
[Fig. 33] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 64k bits and code rate r is 13/15.
[Fig. 34] A diagram showing a parity check matrix initial
CA 02924874 20160318
value table of a first new LDPC code whose code length N
is 16k bits and code rate r is 6/15.
[Fig. 35] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
5 is 16k bits and code rate r is 8/15.
[Fig. 36] A diagram showing a parity check matrix initial
value table of a first new LDPC code whose code length N
is 16k bits and code rate r is 10/15.
[Fig. 37] A diagram showing a parity check matrix initial
10 value table of a first new LDPC code whose code length N
is 16k bits and code rate r is 12/15.
[Fig. 38] A diagram showing a parity check matrix initial
value table of a first other new LDPC code whose code
length N is 16k bits and code rate r is 10/15.
[Fig. 39] A diagram showing a parity check matrix initial
value table of a first other new LDPC code whose code
length N is 16k bits and code rate r is 12/15.
[Fig. 40] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 6/15.
[Fig. 41] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 6/15.
[Fig. 42] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 8/15.
[Fig. 43] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
CA 02924874 20160318
11
is 64k bits and code rate r is 8/15.
[Fig. 44] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 8/15.
[Fig. 45] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 10/15.
[Fig. 46] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 10/15.
[Fig. 47] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 10/15.
[Fig. 48] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 12/15.
[Fig. 49] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 12/15.
[Fig. 50] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 64k bits and code rate r is 12/15.
[Fig. 51] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 16k bits and code rate r is 7/15.
[Fig. 52] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 16k bits and code rate r is 9/15.
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12
[Fig. 53] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 16k bits and code rate r is 11/15.
[Fig. 54] A diagram showing a parity check matrix initial
value table of a second new LDPC code whose code length N
is 16k bits and code rate r is 13/15.
[Fig. 55] A diagram illustrating an example of a Tanner
graph of an ensemble of a degree sequence in which a
column weight is 3 and a row weight is 6.
[Fig. 56] A diagram showing an example of the Tanner
graph of a multiedge type ensemble.
[Fig. 57] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first new LDPC code whose code length N is 64k bits and
code rate r is 7/15, 9/15, 11/15 or 13/15.
[Fig. 58] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first new LDPC code whose code length N is 64k bits and
code rate r is 7/15, 9/15, 11/15 or 13/15.
[Fig. 59] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first new LDPC code whose code length N is 64k and code
rate r is 7/15, 9/15, 11/15 or 13/15.
[Fig. 60] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 7/15.
[Fig. 61] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
CA 02924874 20160318
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whose code length N is 64k bits and code rate r is 9/15.
[Fig. 62] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 11/15.
[Fig. 63] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 13/15.
[Fig. 64] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first new LDPC code whose code length N is 16k bits and
code rate r is 6/15, 8/15, 10/15 or 12/15.
[Fig. 65] A diagram illustrating the parity check matrix
of the first new LDPC code whose code length N is 16k
bits and code rate r is 6/15, 8/15, 10/15 or 12/15.
[Fig. 66] A diagram illustrating the parity check matrix
of the first new LDPC code whose code length N is 16k
bits and code rate r is 6/15, 8/15, 10/15 or 12/15.
[Fig. 67] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 6/15.
[Fig. 68] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 8/15.
[Fig. 69] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
whose code length N is 64k bits and code rate r is 10/15.
[Fig. 70] A diagram showing a simulation result of
measurement of BER/FER about the first new LDPC code
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14
whose code length N is 64k bits and code rate r is 12/15.
[Fig. 71] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first other new LDPC code whose code length N is 16k bits
and code rate r is 10/15.
[Fig. 72] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first other new LDPC code whose code length.N is 16k bits
and code rate r is 10/15.
[Fig. 73] A diagram showing a minimum cycle length and a
performance threshold of the parity check matrix of the
first other new LDPC code whose code length N is 16k bits
and code rate r is 10/15.
[Fig. 74] A diagram showing a simulation result of
measurement of BER/FER about the first other new LDPC
code whose code length N is 16k bits and code rate r is
10/15.
[Fig. 75] A diagram showing a simulation result of
measurement of BER/FER about the first other new LDPC
code whose code length N is 16k bits and code rate r is
12/15.
[Fig. 76] A diagram illustrating the parity check matrix
of the first other new LDPC code whose code length N is
16k bits and code rate r is 12/15.
[Fig. 77] A diagram illustrating the parity check matrix
of the first other new LDPC code whose code length N is
16k bits and code rate r is 12/15.
[Fig. 78] A diagram showing a simulation result of
CA 02924874 20160318
measurement of BER/FER about the first other new LDPC
code whose code length N is 16k bits and code rate r is
12/15.
[Fig. 79] A diagram illustrating the parity check matrix
5 of the second new LDPC code whose code length N is 64k
bits and code rate r is 6/15, 8/15, 10/15, 12/15.
[Fig. 80] A diagram illustrating the parity check matrix
of the second new LDPC code whose code length N is 64k
bits and code rate r is 6/15, 8/15, 10/15, 12/15.
10 [Fig. 81] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 64k bits and code rate r is 6/15.
[Fig. 82] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
15 whose code length N is 64k bits and code rate r is 8/15.
[Fig. 83] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 64k bits and code rate r is 10/15.
[Fig. 84] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 64k bits and code rate r is 12/15.
[Fig. 85] A diagram illustrating the parity check matrix
of the second new LDPC code whose code length N is 16k
bits and code rate r is 7/15, 9/15, 11/15, 13/15.
[Fig. 86] A diagram illustrating the parity check matrix
of the second new LDPC code whose code length N is 16k
bits and code rate r is 7/15, 9/15, 11/15, 13/15.
[Fig. 87] A diagram showing a simulation result of
CA 02924874 20160318
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measurement of BER/FER about the second new LDPC code
whose code length N is 16k bits and code rate r is 7/15.
[Fig. 88] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 16k bits and code rate r is 9/15.
[Fig. 89] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 16k bits and code rate r is 11/15.
[Fig. 90] A diagram showing a simulation result of
measurement of BER/FER about the second new LDPC code
whose code length N is 16k bits and code rate r is 13/15.
[Fig. 91] A diagram showing illustrative types of the
constellation.
[Fig. 92] A diagram showing an example of a constellation
for eight code rates r of the LDPC code when the
modulation scheme is 16QAM.
[Fig. 93] A diagram showing an example of a constellation
for eight code rates r of the LDPC code when the
modulation scheme is 64QAM.
[Fig. 94] A diagram showing an example of a constellation
for eight code rates r of the LDPC code when the
modulation scheme is 256QAM.
[Fig. 95] A diagram showing an example of a constellation
for eight code rates r of the LDPC code when the
modulation scheme is 1024QAM.
[Fig. 96] A diagram showing a simulation result of
measurement of BER where UC, 1D NUC or 2D NUC is used as
constellation when the modulation scheme is 16QAM.
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[Fig. 97] A diagram showing a simulation result of
measurement of BER where UC, 1D NUC or 2D NUC is used as
constellation when the modulation scheme is 64QAM.
[Fig. 98] A diagram showing a simulation result of
measurement of BER where UC, 1D NUC or 2D NUC is used as
constellation when the modulation scheme is 256QAM.
[Fig. 99] A diagram showing a simulation result of
measurement of BER where UC, 1D NUC or 2D NUC is used as
constellation when the modulation scheme is 1024QAM.
[Fig. 100] A diagram showing coordinates of the
signal points of UC commonly used for eight code rates r
of the LDPC code when the modulation scheme is QPSK.
[Fig. 101] A diagram showing coordinates of the
signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
16QAM.
[Fig. 102] A diagram showing coordinates of the
signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
64QAM.
[Fig. 103] A diagram showing coordinates of the
signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
256QAM.
[Fig. 104] A diagram showing coordinates of the
signal points of 1D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
1024QAM.
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[Fig. 105] A diagram showing a relationship between a
real part Re(zq) and an imaginary part Im(zq) of a
complex number as a coordinate of a symbol y and a signal
point zq of 1D NUC corresponding to the symbol y.
[Fig. 106] A block diagram showing a configuration
example of a block interleaver 25.
[Fig. 107] A diagram showing a column number C of
parts 1 and 2 for a combination of a code length N and a
modulation scheme and part column lengths R1 and R2.
[Fig. 108] A diagram for illustrating a block
interleave performed in the block interleaver 25.
[Fig. 109] A diagram for illustrating groupwise
interleave performed in a groupwise interleaver 24.
[Fig. 110] A diagram showing a first example of a GW
pattern for the LDPC code whose code length N is 64k bits.
[Fig. 111] A diagram showing a second example of the
GW pattern for the LDPC code whose code length N is 64k
bits.
[Fig. 112] A diagram showing a third example of the
GW pattern for the LDPC code whose code length N is 64k
bits.
[Fig. 113] A diagram showing a fourth example of the
GW pattern for the LDPC code whose code length N is 64k
bits.
[Fig. 114] A diagram showing a first example of a GW
pattern for the LDPC code whose code length N is 16k bits.
[Fig. 115] A diagram showing a second example of the
GW pattern for the LDPC code whose code length N is 16k
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bits.
[Fig. 116] A diagram showing a third example of the GW
pattern for the LDPC code whose code length N is 16k bits.
[Fig. 117] A diagram showing a fourth example of the
GW pattern for the LDPC code whose code length N is 16k bits.
[Fig. 118] A block diagram showing a configuration
example of the receiving device 12.
[Fig. 119] A block diagram showing a configuration
example of a bit deinterleaver 165.
[Fig. 120] A flowchart illustrating processes
performed by a demapper 164, the bit deinterleaver 165,
and an LDPC decoder 166.
[Fig. 121] A diagram showing an example of the parity
check matrix of the LDPC code.
[Fig. 122] A diagram illustrating a matrix
(conversion parity check matrix) obtained by applying row
permutation and column permutation to the parity check
matrix.
[Fig. 123] A diagram illustrating the conversion
parity check matrix divided into 5 x 5 units.
[Fig. 124] A block diagram showing a configuration
example of a decoding device, which collectively performs
P node operations.
[Fig. 125] A block diagram showing a configuration
example of the LDPC decoder 166.
[Fig. 126] A block diagram showing a configuration
example of a block deinterleaver 54.
[Fig. 127] A block diagram showing other
CA 02924874 20160318
configuration example of the bit deinterleaver 165.
[Fig. 128] A block diagram showing a first
configuration example of a receiving system to which the
receiving device 12 may be applied.
5 [Fig. 129] A block diagram showing a second
configuration example of the receiving system to which
the receiving device 12 may be applied.
[Fig. 130] A block diagram showing a third
configuration example of the receiving system to which
10 the receiving device 12 may be applied.
[Fig. 131] A block diagram showing a configuration
example of one embodiment of a computer to which the
present technology is applied.
Modes for Carrying Out the Invention
15 [0017] Hereinafter, embodiments of the present
technology will be described. Before that, an LDPC code
will be described.
[0018]
<LDPC code>
20 [0019] The LDPC code is a linear code and is not
necessarily required to be a binary code; however, it is
herein described supposing that this is the binary code.
[0020] The greatest characteristic of the LDPC code is
that a parity check matrix defining the LDPC code is
sparse. Herein, the sparse matrix is the matrix in which
the number of elements "1" of the matrix is very small
(most of elements are 0).
[0021] Fig. 1 is a view showing an example of a parity
CA 02924874 20160318
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check matrix H of the LDPC code.
[0022] In the parity check matrix H in Fig. 1, a
weight of each column (column weight) (the number of "1")
is "3" and the weight of each row (row weight) is "6".
[0023] In encoding by the LDPC code (LDPC encoding), a
code word (LDPC code) is generated by generation of a
generator matrix G based on the parity check matrix H and
multiplication of the generator matrix G by a binary
information bit, for example.
[0024] Specifically, an encoding device, which
performs the LDPC encoding, first calculates the
generator matrix G satisfying an equation GHT = 0 between
the same and a transposed matrix HT ofthe parity check
matrix H. Herein, when the generator matrixGisaKxN
matrix, the encoding device multiplies a bit column
(vector u) of K bits by the generator matrix G to
generate a code word c (= uG) configured of N bits. The
code word (LDPC code) generated by the encoding device is
received on a receiving side through a predetermined
communication channel.
[0025] Decoding of the LDPC code may be performed by
an algorithm suggested by Gallager as probabilistic
decoding being a message passing algorithm by belief
propagation on a socalled Tanner graph configured of a
variable node (also referred to as a message node) and a
check node. Hereinafter, the variable node and the check
node are appropriately and simply referred to as a node.
[0026] Fig. 2 is a flowchart showing a procedure of
CA 02924874 20160318
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the decoding of the LDPC code.
[0027] A real value (received LLR) representing
likelihood of a value to be "0" of an ith code bit of
the LDPC code (one cord word) received on the receiving
side by a log likelihood ratio is hereinafter
appropriately referred to as a received value un. A
message output from the check node is set to ujand the
message output from the variable node is set to vi.
[0028] First, in the decoding of the LDPC code, as
shown in Fig. 2, the LDPC code is received, the message
(check node message) ujis initialized to "0", and a
variable k being an integer as a counter of a repetitive
process is initialized to "0" at step Sll and the
procedure shifts to step S12. At step S12, the message
(variable node message) vi is obtained by an operation
(variable node operation) represented in equation (1)
based on the received value un obtained by receiving the
LDPC code and the message uj is obtained by an operation
(check node operation) represented in equation (2) based
on the message vi.
[0029]
[Equation 1]
Vi=Uoi Uj
j=1 (1)
[0030]
[Equation 2]
dc1
i Vi
tanh(U 2¨)= tanh( __ 2 )
i=1 (2)
CA 02924874 20160318
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[0031] Herein, d, and dc in equations (1) and (2) are
parameters indicating the numbers of "1" in a vertical
direction (column) and a horizontal direction (row) of
the parity check matrix H, which may be optionally
selected. For example, it is set that dv = 3 and dc = 6
in the case of the LDPC code ((3, 6) LDPC code) for the
parity check matrix H in which the column weight is 3 and
the row weight is 6 as shown in Fig. 1.
[0032] In the variable node operation in equation (1)
and the check node operation in equation (2), the message
input from an edge (line connecting the variable node and
the check node to each other) from which the message is
to be output is not a target of the operation, so that a
range of the operation is 1 to dv1 or 1 to dc1. Also, a
table of a function R(vi, v2) represented in equation (3)
defined by one output with respect to two inputs viand v2
is created in advance and this is continuously
(recursively) used as represented in equation (4) for
actually performing the check node operation in equation
(2).
[0033]
[Equation 3]
x=2tanh1 (tanh (v1/2) tanh (v2/2) } =R (vi , v2) (3)
[0034]
Ui =R (vi, R (v2, R (v3, " .13 (Vdc2, Vdci) )) )
(4)
[0035] At step S12, the variable k is incremented by 1
CA 02924874 20160318
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and the procedure shifts to step S13. At step S13, it is
judged whether the variable k is larger than a
predetermined number of times of repetitive decoding C.
When it is judged that the variable k is not larger than
C at step S13, the procedure returns to step S12 and a
similar process is hereinafter repeatedly performed.
[0036] Also, when it is judged that the variable k is
larger than C at step S13, the procedure shifts to step
S14 to perform an operation represented in equation (5),
so that the message vi as a decoding result to be finally
output is obtained to be output and a decoding process of
the LDPC code is finished.
[0037]
[Equation 5]
Uj
j=1 (5)
[0038] Herein, different from the variable node
operation in equation (1), the operation in equation (5)
is performed using the messages uj from all the edges
connected to the variable node.
[0039] Fig. 3 is a view showing an example of the
parity check matrix H of the (3, 6) LDPC code (code rate
1/2 and code length 12).
[0040] In the parity check matrix H in Fig. 3, the
weight of the column is 3 and the weight of the row is 6
as in Fig. 1.
[0041] Fig. 4 is a view showing the Tanner graph of
the parity check matrix H in Fig. 3.
CA 02924874 20160318
[0042] Herein, in Fig. 4, the check node is
represented by plus "+" and the variable node is
represented by equal "=". The check node and the variable
node correspond to the row and the column of the parity
5 check matrix H, respectively. A connection between the
check node and the variable node is the edge, which
corresponds to the element "1" of the parity check matrix.
[0043] That is to say, when a jth row ith column
element of the parity check matrix is 1, in Fig. 4, an i
10 th variable node (node of "=") from the top and a jth
check node (node of "+") from the top are connected to
each other by the edge. The edge indicates that the code
bit corresponding to the variable node has a constraint
condition corresponding to the check node.
15 [0044] In a sum product algorithm being the decoding
method of the LDPC code, the variable node operation and
the check node operation are repeatedly performed.
[0045] Fig. 5 is a view showing the variable node
operation performed in the variable node.
20 [0046] In the variable node, the message vi
corresponding to the edge to be calculated is obtained by
the variable node operation in equation (1) using the
messages uland U2 from other edges connected to the
variable node and the received value un. The message
25 corresponding to another edge is similarly obtained.
[0047] Fig. 6 illustrates the check node operation
performed in the check node.
[0048] Herein, the check node operation in equation
CA 02924874 20160318
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(2) may be rewritten as equation (6) using relationship
of an equation a x b = expfln(la1)+1n(lb1)1 x sign(a) x
sign(b). Sign(x) is 1 when x => 0 is satisfied and 1
when x < 0 is satisfied.
[0049]
[Equation 6]
(dc1
uj =2tanh1 fl tanh
2 I
dc1 d
=2tanh1 exp I n ( tanhE1v ) xc1 s gn (tanh
=1 2 i =1
dc1
=2tanh1 exp {¨ ( ¨ I n (tanh Ivi 2 )\ \I c101
X TT sign(vi)
i =1 jj i=1
(6)
[0050] When a function (p) (x) is defined by an
equation (1)(x) = ln(tan h(x/2)) when x => 0 is satisfied,
an equation (1)1(x) = 2 tan h(e) is satisfied, so that
equation (6) may be deformed to equation (7).
[0051]
[Equation 7]
(dc1 dc1
L11=01 (IVi I) X 7 sign(vi)
i=1 i=1
(7)
[0052] In the check node, the check node operation in
equation (2) is performed according to equation (7).
[0053] That is to say, in the check node, the message
u3 corresponding to the edge to be calculated is obtained
by the check node operation in equation (7) using
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messages vu v2, v3, v4, and V5 from other edges connected
to the check node as illustrated in Fig. 6. The message
corresponding to another edge is similarly obtained.
[0054] The function p(x) in equation (7) may be
represented by an equation p(x) = ln((ex+1)/(ex1)) and
p(x) = p1(x) when x > 0 is satisfied. When the functions
p(x) and p1(x) are implemented in hardware, there is a
case in which they are implemented using LUT (look up
table), and the same LUT is used for both of them.
[0055]
<Configuration example of transmission system to which
the present technology is applied>
[0056] Fig. 7 illustrates a configuration example of
one embodiment of a transmission system (the term
"system" is intended to mean a logical assembly of a
plurality of devices and it does not matter whether the
devices of each configuration are in the same housing) to
which the present technology is applied.
[0057] In Fig. 7, the transmission system is
configured of a transmitting device 11 and a receiving
device 12.
[0058] The transmitting device 11 transmits
(broadcasts) (transmits) a program of television
broadcasting. That is to say, the transmitting device 11
encodes target data to be transmitted such as image data
and audio data as the program, for example, into an LDPC
code and transmits the same through a communication
channel 13 such as a satellite circuit, a terrestrial
CA 02924874 20160318
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wave, and a cable (wire circuit).
[0059] The receiving device 12 receives the LDPC code
transmitted from the transmitting device 11 through the
communication channel 13 and decodes the same to the
target data to output.
[0060] Herein, it is known that the LDPC code used in
the transmission system in Fig. 7 exhibits an extremely
high ability in an AWGN (additive white Gaussian noise)
communication channel.
[0061] However, a burst error and erasure might occur
in the communication channel 13 such as the terrestrial
wave. For example, especially when the communication
channel 13 is a terrestrial wave, in an OFDM (orthogonal
frequency division multiplexing) system, there is a case
in which power of a specific symbol reaches 0 (erasure)
according to delay of an echo (a path other than a main
path) in a multipath environment in which a D/U (desired
to undesired ratio) is 0 dB (power of undesired (= echo)
is equal to power of desired (= main path)).
[0062] There is a case in which the power of all the
symbols of the OFDM at a specific time reaches 0
(erasure) by a Doppler frequency when the D/U is 0 dB
also in a flutter (communication channel in which a
Doppler frequencyshifted echo whose delay is 0 is added).
[0063] Further, the burst error might occur due to a
wiring status from a receiver (not shown) such as an
antenna, which receives a signal from the transmitting
device 11, to the receiving device 12 and instability of
CA 02924874 20160318
29
a power supply of the receiving device 12 on a side of
the receiving device 12.
[0064] On the other hand, in decoding of the LDPC code,
a variable node operation in equation (1) including
addition of (a received value uoi of) a code bit of the
LDPC code is performed as illustrated above in Fig. 5 in
a variable node corresponding to a column of a parity
check matrix H and eventually the code bit of the LDPC
code, so that, when the error occurs in the code bit used
in the variable node operation, accuracy of an obtained
message is deteriorated.
[0065] In the decoding of the LDPC code, a check node
operation in equation (7) is performed in the check node
using the message obtained in the variable node connected
to the check node, so that decoding performance is
deteriorated when the number of check nodes, in which
(the code bits of the LDPC code corresponding to) a
plurality of variable nodes connected thereto have the
error (including the erasure) at the same time, increases.
[0066] That is to say, when the erasure occurs in two
or more of the variable nodes connected to the check node
at the same time, the check node returns the message
indicating that probability that the value is 0 and the
probability that the value is 1 are equal to all the
variable nodes, for example. In this case, the check node,
which returns the message of the equal probability, does
not contribute to a single decoding process (one set of
the variable node operation and the check node operation),
CA 02924874 20160318
and as a result, this requires a large number of
repetitions of the decoding process, so that the decoding
performance is deteriorated and further, power
consumption of the receiving device 12, which decodes the
5 LDPC code, increases.
[0067] Therefore, the transmission system in Fig. 7 is
configured to improve resistance to burst error and
erasure while maintaining performance in the AWGN
communication channel (AWGN channel).
10 [0068]
[Configuration example of transmitting device 11]
[0069] Fig. 8 is a block diagram showing a
configuration example of the transmitting device 11 in
Fig. 7.
15 [0070] In the transmitting device 11, one or more
input streams as the target data are supplied to a mode
adaptation/multiplexer 111.
[0071] The mode adaptation/multiplexer 111 selects a
mode, multiplexes the one or more input streams supplied
20 thereto, and supplies the data obtained as a result to a
padder 112.
[0072] The padder 112 performs necessary zero padding
(null insertion) to the data from the mode
adaptation/multiplexer 111 and supplies the data obtained
25 as a result to a BB scrambler 113.
[0073] The BB scrambler 113 applies BB scramble (Base
Band Scrambling) to the data from the padder 112 and
supplies the data obtained as a result to a BCH encoder
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114.
[0074] The BCH encoder 114 performs BCH encoding of
the data from the BB scrambler 113 and supplies the data
obtained as a result to an LDPC encoder 115 as LDPC
target data being a target of LDPC encoding.
[0075] The LDPC encoder 115 performs the LDPC encoding
of the LDPC target data from the BCH encoder 114
according to a parity check matrix in which a parity
matrix being a part corresponding to a parity bit of the
LDPC code has a stepwise structure and outputs the LDPC
code in which an information bit is the LDPC target data.
[0076] That is to say, the LDPC encoder 115 performs
the LDPC encoding to encode the LDPC target data into the
LDPC code (corresponding to the parity check matrix) such
as the LDPC code specified in a predetermined standard
such as a DVBS.2 standard, a DVBT.2 standard and a DVB
C.2 standard or the LDPC code expected to be specified by
ATSC3.0 (corresponding to the parity check matrix), for
example, and outputs the LDPC code obtained as a result.
[0077] In the LDPC code specified in the DVBT.2
standard or the LDPC code expected to be specified by
ATSC3.0 is an IRA (irregular repeataccumulate) code and
the parity matrix in the parity check matrix of the LDPC
code has the stepwise structure. The parity matrix and
the stepwise structure are described later. The IRA code
is described in "Irregular RepeatAccumulate Codes, " H.
Jin, A. Khandekar, and R. J. McEliece, in Proceedings of
2nd International Symposium on Turbo Codes and Related
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32
Topics, pp. 18, Sept. 2000, for example.
[0078] The LDPC code output by the LDPC encoder 115 is
supplied to a bit interleaver 116.
[0079] The bit interleaver 116 performs bit interleave
to be described later of the LDPC code from the LDPC
encoder 115 and supplies the LDPC code after the bit
interleave to a mapper 117.
[0080] The mapper 117 maps the LDPC code from the bit
interleaver 116 onto a signal point indicating one symbol
of orthogonal modulation in units of one or more code
bits of the LDPC code (symbol unit) to perform the
orthogonal modulation (multilevel modulation).
[0081] That is to say, the mapper 117 maps the LDPC
code from the bit interleaver 116 onto the signal point
defined by a modulation scheme for performing the
orthogonal modulation of the LDPC code on an IQ plane (IQ
constellation) defined by an I axis representing an I
component in phase with a carrier wave and a Q axis
representing a Q component orthogonal to the carrier wave
and performs the orthogonal modulation.
[0082] If the number of signal points prescribed by
orthogonal modulation of a modulation scheme which is
performed by the mapper 117 is 2m, the mapper 117 maps the
LDPC code from the bit interleaver 116 in a symbol unit
onto the signal point indicating the symbol of the 2m
signal points as the m code bit of the LDPC code for a
symbol (1 symbol).
[0083] Herein, the modulation scheme of the orthogonal
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modulation performed by the mapper 117 includes the
modulation scheme including the modulation scheme
specified in the DVBT.2 standard, for example, the
modulation scheme expected to be specified by ATSC3.0,
and other modulation schemes, that is to say, BPSK
(Binary Phase Shift Keying), QPSK (quadrature phase shift
keying), 8PSK (PhaseShift Keying), 16APSK (Amplitude
PhaseShift Keying), 32APSK, 16QAM (quadrature amplitude
modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM
(Pulse Amplitude Modulation) and the like, for example.
The modulation scheme with which the orthogonal
modulation is performed by the mapper 117 is set in
advance according to operation of an operator of the
transmitting device 11, for example.
[0084] The data (symbol mapped onto the signal point)
obtained by the process by the mapper 117 is supplied to
a time interleaver 118.
[0085] The time interleaver 118 performs time
interleave (interleave in a time direction) in a symbol
unit of the data from the mapper 117 and supplies the
data obtained as a result to a SISO/MISO (Single Input
Single Output/Multiple Input Single Output) encoder 119.
[0086] The SISO/MISO encoder 119 applies timespace
encoding to the data from the time interleaver 118 to
supply to a frequency interleaver 120.
[0087] The frequency interleaver 120 performs
frequency interleave (interleave in a frequency
direction) for the unit of the data from the SISO/MISO
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34
encoder 119 in a symbol unit, and supplies it to a frame
builder & resource allocation 131.
[0088] On the other hand, control data for
transmission control (signaling) such as Base Band
Signaling, BB Header and the like is supplied to the BCH
encoder 121, for example.
[0089] The BCH encoder 121 performs the BCH encoding
of the control data supplied thereto in the same manner
as the BCH encoder 114 and supplies the data obtained as
a result to an LDPC encoder 122.
[0090] The LDPC encoder 122 performs the LDPC encoding
of the data from the BCH encoder 121 as the LDPC target
data in the same manner as the LDPC encoder 115 and
supplies the LDPC code obtained as a result to a mapper
123.
[0091] The mapper 123 maps the LDPC code from the LDPC
encoder 122 onto the signal point indicating one symbol
of the orthogonal modulation in units of one or more code
bits of the LDPC code (symbol unit) to perform the
orthogonal modulation and supplies the data obtained as a
result to a frequency interleaver 124 in the same manner
as the mapper 117.
[0092] The frequency interleaver 124 performs the
frequency interleave of the data from the mapper 123 in a
symbol unit to supply to the frame builder & resource
allocation 131 in the same manner as the frequency
interleaver 120.
[0093] The frame builder & resource allocation 131
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inserts a pilot symbol into a required position of the
data (symbol) from the frequency interleavers 120 and 124
and constitutes a frame configured of a predetermined
number of symbols (for example, a PL (Physical Layer)
5 frame, a T2 frame, a C2 frame and the like) from the data
(symbol) obtained as a result to supply to an OFDM
generation 132.
[0094] The OFDM generation 132 generates an OFDM
signal corresponding to the frame from the frame from the
10 frame builder & resource allocation 131 and transmits the
same through the communication channel 13 (Fig. 7).
[0095] The transmitting device 11 may be configured
without including some of the blocks shown in Fig. 8,
e.g., the time interleaver 118, the SISO/MISO encoder 119,
15 the frequency interleaver 120, and frequency interleaver
124.
[0096]
<Configuration example of bit interleaver 116>
[0097] Fig. 9 is block diagram showing a configuration
20 example of the bit interleaver 116 in Fig. 8.
[0098] The bit interleaver 116 has a function to
interleave the data, and is configured of a parity
interleaver 23, a groupwise interleaver 24, and a block
interleaver 25.
25 [0099] The parity interleaver 23 performs parity
interleave to interleave the parity bit of the LDPC code
from the LDPC encoder 115 to a position of another parity
bit and supplies the LDPC code after the parity
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interleave to the groupwise interleaver 24.
[0100] The groupwise interleaver 24 performs group
wise interleave of the LDPC code from the parity
interleaver 23 and supplies the LDPC code after the
groupwise interleave to the block interleaver 25.
[0101] Here, in the groupwise interleave, the LDPC
code for one code is divided into a 360bit unit equal to
the number of columns P being the unit of the cyclic
structure as described later from the beginning. One
division, i.e., 360bit, is considered as a bit group.
The LDPC code from the parity interleaver 23 is
interleaved in a bit group unit.
[0102] When the groupwise interleave is performed,
the bit error rate can be improved as compared with the
case that no groupwise interleave is performed. As a
result, in the data transmission, it is possible to
ensure good communication quality.
[0103] The block interleaver 25 performs the block
interleave for demultiplexing the LDPC code from the
groupwise interleaver 24, symbolizes the LDPC code for
one code into the m bit symbol in a mapping unit, and
supplies it to the mapper 117 (Fig. 8).
[0104] Here, there is a storage region where columns
for storing a predetermined number of bits in a column
(vertical) direction are arranged in equal numbers to the
bit numbers m of the symbol in a row (horizontal)
direction. In the block interleave, the LDPC code from
the groupwise interlever 24 is written in the column
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direction and read in the row direction, thereby
symbolizing the LDPC code for one code into the m bit
symbol.
[0105]
<Parity check matrix of LDPC code>
[0106] Fig. 10 shows the parity check matrix H used by
the LDPC encoder 115 in Fig. 8.
[0107] The parity check matrix H has an LDGM (low
density generation matrix) structure and this may be
represented by an equation H = [HAIHT] (a matrix in which
a left element is an element of an information matrix HA
and a right element is an element of a parity matrix HT)
by the information matrix HA of a part corresponding to
the information bit and the parity matrix HT corresponding
to the parity bit out of the code bits of the LDPC code.
[0108] Herein, the number of information bits and the
number of parity bits out of the code bits of one LDPC
code (one code word) are referred to as an information
length K and a parity length M, respectively, and the
number of code bits of one LDPC code is referred to as a
code length N (= K + M).
[0109] The information length K and the parity length
M of the LDPC code of a certain code length N are
determined according to the code rate. The parity check
matrix H is an M x N (row x column) matrix. The
information matrix HA is an M x K matrix and the parity
matrix HT is an M x M matrix.
[0110] Fig. 11 is a drawing showing an example of the
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parity matrix HT of the parity check matrix H used for the
LDPC encoding by the LDPC encoder 115 in Fig. 8.
[0111] The parity matrix HT of the parity check matrix
H used for the LDPC encoding by the LDPC encoder 115 is
similar to the parity matrix HT of the parity check matrix
H of the LDPC code specified in the DVBT.2 standard.
[0112] The parity matrix HT of the parity check matrix
H of the LDPC code specified in the DVBT.2 standard has
a lower bidiagonal matrix in which elements of 1 are
arranged in a socalled stepwise manner as shown in Fig.
11. A row weight of the parity matrix HT is 1 for a first
row and 2 for all other rows. A column weight is 1 for a
last column and 2 for all other columns.
[0113] As described above, the LDPC code of the parity
check matrix H in which the parity matrix HT has the
stepwise structure may be easily generated using the
parity check matrix H.
[0114] That is to say, the LDPC code (one code word)
is represented by a row vector c and a column vector
obtained by transposing the row vector is represented as
cT. A part of the information bit of the row vector c,
which is the LDPC code, is represented by a row vector A
and a part of the parity bit is represented by a row
vector T.
[0115] In this case, the row vector c may be
represented by an equation c = [AIT] (row vector in which
a left element is an element of the row vector A and a
right element is an element of the row vector T) by the
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row vector A as the information bit and the row vector T
as the parity bit.
[0116] The parity check matrix H and the row vector c
= [AIT] as the LDPC code are required to satisfy an
equation HcT = 0 and it is possible to sequentially obtain
(in order) the row vector T as the parity bit configuring
the row vector c = [AIT] satisfying such equation HcT = 0
by setting the element of each row to 0 in order from the
element of a first row of the column vector HcT in the
equation HcT = 0 when the parity matrix HT of the parity
check matrix H = [HAIHT] has the stepwise structure
illustrated in Fig. 11.
[0117] Fig. 12 is a view illustrating the parity check
matrix H of the LDPC code specified in the DVBT.2
standard.
[0118] The column weight is X for first to KXth
columns, the column weight is 3 for next K3 columns, the
column weight is 2 for next M1 columns, and the column
weight is 1 for a last column in the parity check matrix
H of the LDPC code specified in the DVBT.2 standard.
[0119] Herein, KX + K3 + M  1 + 1 equals to the code
length N.
[0120] Fig. 13 is a view showing the numbers of
columns KX, K3, and M and the column weight X for each
code rate r of the LDPC code specified in the DVBT.2
standard.
[0121] The LDPC codes whose code lengths N are 64800
bits and 16200 bits are specified in the DVBT.2 standard.
CA 02924874 20160318
[0122] For the LDPC code whose code length N is 64800
bits, 11 code rates (nominal rates) 1/4, 1/3, 2/5, 1/2,
3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are specified, and
for the LDPC code whose code length N is 16200 bits, 10
5 code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6,
and 8/9 are specified.
[0123] The code length N of 64800 bits is hereinafter
also referred to as 64k bits and the code length of 16200
bits is also referred to as 16k bits.
10 [0124] As for the LDPC code, it is known that a bit
error rate of the code bit corresponding to the column
whose column weight is larger of the parity check matrix
H is lower.
[0125] In the parity check matrix H specified in the
15 DVBT.2 standard illustrated in Figs. 12 and 13, the
column weight of the column closer to a top (leftmost)
column tends to be larger, therefore, as for the LDPC
code corresponding to the parity check matrix H, the code
bit closer to a top code bit closer to a top code bit
20 tends to be more tolerant to error (resistant to error)
and the code bit closer to a last code bit tends to be
less tolerant to error.
[0126]
<Parity interleave>
25 [0127] Referring to Fig. 14 to Fig. 16, the parity
interleave by the parity interleaver 23 in Fig. 9 is
described.
[0128] Fig. 14 shows (a part of) a Tanner graph of the
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41
parity check matrix of the LDPC code.
[0129] The check node returns the message indicating
that the probability that the value is 0 and the
probability that the value is 1 are equal to all the
variable nodes connected to the check node when the error
such as the erasure occurs in a plurality (for example,
two) of (code bits corresponding to the) variable nodes
connected to the check node at the same time as
illustrated in Fig. 14. Therefore, when the erasure and
the like occur at the same time in a plurality of
variable nodes connected to the same check node, the
decoding performance is deteriorated.
[0130] The LDPC code specified in the DVBS.2 standard
output by the LDPC encoder 115 in Fig. 8 is the IRA code
and the parity matrix HT of the parity check matrix H has
the stepwise structure as illustrated in Fig. 11.
[0131] Fig. 15 shows the parity matrix HT having the
stepwise structure and the Tanner graph corresponding to
the parity matrix HT, as shown in Fig. 11.
[0132] Fig. 15A shows the parity matrix HT having the
stepwise structure and Fig. 15B shows the Tanner graph
corresponding to the parity matrix HT in Fig. 15A.
[0133] In the parity matrix HT having the stepwise
structure, the elements of 1 are adjacent to each other
in each row (except the first row). Therefore, in the
Tanner graph of the parity matrix HT, two adjacent
variable nodes corresponding to the columns of the two
adjacent elements whose value is 1 of the parity matrix HT
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are connected to the same check node.
[0134] Therefore, when the error occurs in the parity
bits corresponding to the abovedescribed adjacent two
variable nodes at the same time due to the burst error,
the erasure and the like, the check node connected to the
two variable nodes (the variable nodes, which obtain the
message using the parity bits) corresponding to the two
parity bits in which the error occurs returns the message
indicating that the probability that the value is 0 and
the probability that the value is 1 are equal to the
variable nodes connected to the check node, whereby the
decoding performance is deteriorated. When a burst length
(the number of parity bits in which the error is
successively occurs) increases, the number of check nodes,
which return the message of the equal probability,
increases and the decoding performance is further
deteriorated.
[0135] Then, the parity interleaver 23 (Fig. 9)
performs the parity interleave to interleave the parity
bit of the LDPC code from the LDPC encoder 115 to the
position of another parity bit in order to prevent the
abovedescribed deterioration in decoding performance.
[0136] Fig. 16 shows the parity matrix HT of the parity
check matrix H corresponding to the LDPC code after the
parity interleave performed by the parity interleaver 23
in Fig. 9.
[0137] Herein, the information matrix HA of the parity
check matrix H corresponding to the LDPC code output by
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the LDPC encoder 115 has a cyclic structure, similar to
the information matrix of the parity check matrix H
corresponding to the LDPC code specified in the DVBT.2
standard.
[0138] The term "cyclic structure" is intended to mean
a structure in which a certain column is identical to a
column obtained by a cyclic shift of another column and
includes a structure in which a position of 1 in each row
of P columns is set to a position obtained by the cyclic
shift of a first column of the P columns in the column
direction by a value proportional to a value q obtained
by dividing the parity length M for each P columns, for
example. Hereinafter, P in the cyclic structure is
appropriately referred to as the number of columns being
a unit of the cyclic structure.
[0139] There are two types of LDPC codes whose code
lengths N are 64800 bits and 16200 bits as the LDPC code
specified in the DVBT.2 standard as illustrated in Figs.
12 and 13, and the number of columns P being the unit of
the cyclic structure is set to 360, which is one of
submultiples other than 1 and M out of the submultiples
of the parity length M for both of the two LDPC codes.
[0140] The parity length M is set to a value other
thanaprime number represented by an equationM=qxP
= q x 360 using the value q different according to the
code rate. Therefore, as the number of columns P being
the unit of the cyclic structure, the value q also is
another submultiple other than 1 and M out of the
CA 02924874 20160318
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submultiples of the parity length M and this may be
obtained by dividing the parity length M by the number of
columns P being the unit of the cyclic structure (a
product of P and q being the submultiples of the parity
length M is the parity length M).
[0141] When the information length is K, an integer
not smaller than 0 and smaller than P is x, and an
integer not smaller than 0 and smaller than q is y, the
parity interleaver 23 interleaves a K + qx + y + 1th
code bit out of the code bits of the Nbit LDPC code to a
position of a K + Py + x + 1th code bit as the parity
interleave as described above.
[0142] Both the K + qx + y + 1th code bit and the K +
Py + x + 1th code bit are the code bits after a K + 1th
code bit, so that they are the parity bits, therefore,
the position of the parity bit of the LDPC code is moved
by the parity interleave.
[0143] According to such parity interleave, (the
parity bits corresponding to) the variable nodes
connected to the same check node are apart from each
other by the number of columns P being the unit of the
cyclic structure, that is to say, herein 360 bits, so
that a situation in which the error occurs in a plurality
of variable nodes connected to the same check node at the
same time may be avoided in a case in which the burst
length is shorter than 360 bits, and as a result, the
resistance to burst error may be improved.
[0144] The LDPC code after the parity interleave to
CA 02924874 20160318
interleave the K + qx + y + 1th code bit to the position
of the K + Py + x + 1th code bit is identical to the
LDPC code of the parity check matrix obtained by
performing column permutation to change the K + qx + y +
5 1th column of the original parity check matrix H to the
K + qx + x + 1th column (hereinafter, also referred to
as a conversion parity check matrix).
[0145] Also, a quasicyclic structure in units of P
columns (360 columns in Fig. 16) appears in the parity
10 matrix of the conversion parity check matrix as
illustrated in Fig. 16.
[0146] Herein, the term "quasicyclic structure" is
intended to mean a structure in which a portion except a
part has the cyclic structure.
15 [0147] In the conversion parity check matrix obtained
by applying the column permutation corresponding to the
parity interleave to the parity check matrix of the LDPC
code specified in the DVBT.2 standard, one element 1 is
lacking (there is an element 0) in a portion of 360 rows
20 x 360 columns in a right corner of the conversion parity
check matrix (a shift matrix to be described later), so
that this does not have the (complete) cyclic structure
and has the socalled quasicyclic structure in this
point.
25 [0148] The conversion parity check matrix of the
parity check matrix of the LDPC code output by the LDPC
encoder 115 has a quasicyclic structure, similar to the
conversion parity check matrix of the parity check matrix
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H of the LDPC code specified in the DVBT.2 standard.
[0149] The conversion parity check matrix in Fig. 16
is the matrix obtained by applying permutation of the row
(row permutation) for allowing the conversion parity
check matrix to be configured of a constitutive matrix to
be described later to the original parity check matrix H
in addition to the column permutation corresponding to
the parity interleave.
[0150] Fig. 17 is a flowchart for explaining the
processing performed by the LDPC encoder 115, the bit
interleaver 116 and the mapper 117 in Fig. 8.
[0151] The LDPC encoder 115 encodes the LDPC target
data into the LDPC code at step S101 after waiting for
supply of the LDPC target data from the BCH encoder 114
and supplies the LDPC code to the bit interleaver 116,
then the process shifts to step S102.
[0152] The bit interleaver 116 performs the bit
interleave of the LDPC code from the LDPC encoder 115 and
supplies the symbol obtained by the bit interleave to the
mapper 117 at step S102, then the process shifts to step
S103.
[0153] That is to say, at step S102, in the bit
interleaver 116 (Fig. 9), the parity interleaver 23
performs the parity interleave of the LDPC code from the
LDPC encoder 115 and supplies the LDPC code after the
parity interleave to the groupwise interleaver 24.
[0154] The groupwise interleaver 24 performs the
groupwise interleave of the LDPC code from the parity
CA 02924874 20160318
47
interleaver 23 to supply to the block interleaver 25.
[0155] The block interleaver 25 performs the block
interleave of the LDPC code after the groupwise
interleave by the groupwise interleaver 24 and supplies
the m bit symbol obtained as a result to the mapper 117.
[0156] The mapper 117 maps the symbol from the block
interleaver 25 onto any of the 2m signal points defined
by the modulation scheme of the orthogonal modulation
performed by the mapper 117 to perform the orthogonal
modulation and supplies the data obtained as a result to
the time interleaver 118 at step S103.
[0157] As described above, it is possible to improve
the error rate in a case in which a plurality of code
bits of the LDPC code is transmitted as one symbol by
performing the parity interleave and the groupwise
interleave.
[0158] Herein, the parity interleaver 23, which is a
block to perform the parity interleave, and the group
wise interleaver 24, which is a block to perform the
groupwise interleave, are separately formed in Fig. 9
for convenience of description; however, the parity
interleaver 23 and the groupwise interleaver 24 may be
integrally formed.
[0159] That is to say, the parity interleave and the
groupwise interleave may be performed by the writing and
the reading of the code bit to and from the memory and
may be represented by a matrix to convert the address at
which the code bit is written (write address) to the
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48
address at which the code bit is read (read address).
[0160] Therefore, by obtaining the matrix obtained by
multiplying the matrix representing the parity interleave
by the matrix representing the groupwise interleave, it
is possible to obtain a result of performing the parity
interleave and performing the groupwise interleave of
the LDPC code after the parity interleave by converting
the code bit by the matrix.
[0161] It is also possible to integrally form the
block interleaver 25 in addition to the parity
interleaver 23 and the groupwise interleaver 24.
[0162] That is to say, the block interleave performed
by the block interleaver 25 may also be represented by
the matrix to convert the write address of the memory,
which stores the LDPC code, to the read address.
[0163] Therefore, by obtaining the matrix obtained by
multiplying the matrix representing the parity interleave,
the matrix representing the groupwise interleave, and
the matrix representing the block interleave together, it
is possible to collectively perform the parity interleave,
the groupwise interleave, and the block interleave by
the matrix.
[0164]
<Configuration example of LDPC encoder 115>
[0165] Fig. 18 is a block diagram illustrating a
configuration example of the LDPC encoder 115 in Fig. 8.
[0166] The LDPC encoder 122 in Fig. 8 also is
configured in the same manner.
CA 02924874 20160318
49
[0167] As illustrated in Figs. 12 and 13, the LDPC
codes of the two code lengths N of 64800 bits and 16200
bits are specified in the DVBS.2 standard.
[0168] As for the LDPC code whose code length N is
64800 bits, 11 code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3,
3/4, 4/5, 5/6, 8/9, and 9/10 are specified, and as for
the LDPC code whose code length N is 16200 bits, 10 code
rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9
are specified (refer to Figs. 12 and 13).
[0169] The LDPC encoder 115 may perform the encoding
(error correction encoding) by such LDPC code of each
code rate whose code lengths N are 64800 bits or 16200
bits according to the parity check matrix H prepared for
each code length N and each code rate, for example.
[0170] The LDPC encoder 115 is configured of an
encoding processor 601 and a storage unit 602.
[0171] The encoding processor 601 is configured of a
code rate set unit 611, an initial value table read unit
612, a parity check matrix generation unit 613, an
information bit read unit 614, an encoding parity
operation unit 615, and a controller 616, and this
performs the LDPC encoding of the LDPC target data
supplied to the LDPC encoder 115 and supplies the LDPC
code obtained as a result to the bit interleaver 116 (Fig.
8).
[0172] That is to say, the code rate set unit 611 sets
the code length N and the code rate of the LDPC code
according to the operation of the operator and the like,
CA 02924874 20160318
for example.
[0173] The initial value table read unit 612 reads a
parity check matrix initial value table to be described
later corresponding to the code length N and the code
5 rate set by the code rate set unit 611 from the storage
unit 602.
[0174] The parity check matrix generation unit 613
generates the parity check matrix H by arranging the
element 1 of the information matrix HA corresponding to
10 the information length K (= code length N  parity length
M) according to the code length N and the code rate set
by the code rate set unit 611 with a period of 360
columns (the number of columns P being the unit of the
cyclic structure) in the column direction based on the
15 parity check matrix initial value table read by the
initial value table read unit 612 and stores the same in
the storage unit 602.
[0175] The information bit read unit 614 reads
(extracts) the information bits as many as the
20 information length K from the LDPC target data supplied
to the LDPC encoder 115.
[0176] The encoding parity operation unit 615 reads
the parity check matrix H generated by the parity check
matrix generation unit 613 from the storage unit 602 and
25 calculates the parity bit for the information bit read by
the information bit read unit 614 based on a
predetermined equation using the parity check matrix H,
thereby generating the code word (LDPC code).
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51
[0177] The controller 616 controls each block
configuring the encoding processor 601.
[0178] A plurality of parity check matrix initial
value tables and the like corresponding to a plurality of
code rates and the like illustrated in Figs. 12 and 13
for each of the code lengths N such as 64800 bits and
16200 bits is stored in the storage unit 602, for example.
The storage unit 602 temporarily stores the data required
in the process of the encoding processor 601.
[0179] Fig. 19 is a flowchart illustrating the process
of the LDPC encoder 115 in Fig. 18.
[0180] At step S201, the code rate set unit 611
determines (sets) the code length N and the code rate r
with which the LDPC encoding is performed.
[0181] At step S202, the initial value table read unit
612 reads the parity check matrix initial value table
determined in advance corresponding to the code length N
and the code rate r determined by the code rate set unit
611 from the storage unit 602.
[0182] At step S203, the parity check matrix
generation unit 613 obtains (generates) the parity check
matrix H of the LDPC code whose code length N and the
code rate r determined by the code rate set unit 611
using the parity check matrix initial value table read by
the initial value table read unit 612 from the storage
unit 602 and supplies the same to the storage unit 602 to
store.
[0183] At step S204, the information bit read unit 614
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52
reads the information bits of the information length K (=
N x r) corresponding to the code length N and the code
rate r determined by the code rate set unit 611 from the
LDPC target data supplied to the LDPC encoder 115 and
reads the parity check matrix H obtained by the parity
check matrix generation unit 613 from the storage unit
602 to supply to the encoding parity operation unit 615.
[0184] At step S205, the encoding parity operation
unit 615 sequentially calculates the parity bit of the
code word c satisfying equation (8) using the information
bit from the information bit read unit 614 and the parity
check matrix H.
[0185]
HoT = 0 ... (8)
[0186] In equation (8), c represents the row vector as
the code word (LDPC code) and CT represents transposition
of the row vector c.
[0187] Herein, as described above, when the part of
the information bit and the part of the parity bit of the
row vector c as the LDPC code (one code word) are
represented by the row vector A and the row vector T,
respectively, the row vector c may be represented by the
equation c = [AIT] by the row vector A as the information
bit and the row vector T as the parity bit.
[0188] The parity check matrix H and the row vector c
[AIT] as the LDPC code are required to satisfy the
equation HcT = 0 and it is possible to sequentially obtain
the row vector T as the parity bit configuring the row
CA 02924874 20160318
53
vector c = [AIT] satisfying such equation HcT = 0 by
setting the element of each row to 0 in order from the
element of the first row of the column vector HcT in the
equation HcT = 0 when the parity matrix HT of the parity
check matrix H = [HAIHT] has the stepwise structure
illustrated in Fig. 11.
[0189] When the encoding parity operation unit 615
obtains the parity bit T for the information bit A from
the information bit read unit, this outputs the code word
c ¨ [AIT] represented by the information bit A and the
parity bit T as a result of the LDPC encoding of the
information bit A.
[0190] Thereafter, at step S206, the controller 616
judges whether to finish the LDPC encoding. At step S206,
when it is judged that the LDPC encoding is not finished,
that is to say, when there still is the LDPC target data
to be LDPC encoded, for example, the process returns to
step S201 (or step S204) and the processes at steps S201
(or step S204) to S206 are hereinafter repeated.
[0191] When it is judged that the LDPC encoding is
finished at step S206, that is to say, there is no LDPC
target data to be LDPC encoded, for example, the LDPC
encoder 115 finishes the process.
[0192] In this manner, the parity check matrix initial
value table corresponding to each code length N and each
code rate r is prepared, and the LDPC encoder 115
performs the LDPC encoding with a predetermined code
length N and a predetermined code rate r using the parity
CA 02924874 20160318
54
check matrix H generated from the parity check matrix
initial value table corresponding to the predetermined
code length N and the predetermined code rate r.
[0193]
<Example of parity check matrix initial value table>
[0194] The parity check matrix initial value table is
the table indicating the position of the element 1 of the
information matrix HA (Fig. 10) corresponding to the
information length K according to the code length N and
code rate r is the LDPC code (LDPC code defined by the
parity check matrix H) of the parity check matrix for
each 360 columns (the number of columns P being the unit
of the cyclic structure) and is created in advance for
each parity check matrix H of each code length N and each
code rate r.
[0195] Fig. 20 is a view illustrating an example of
the parity check matrix initial value table.
[0196] That is to say, Fig. 20 illustrates the parity
check matrix initial value table for the parity check
matrix H whose code length N is 16200 bits and code rate
(code rate in notation of DVBT.2) r is 1/4 specified in
the DVB.T2 standard.
[0197] The parity check matrix generation unit 613
(Fig. 18) obtains the parity check matrix H in a
following manner using the parity check matrix initial
value table.
[0198] Fig. 21 illustrates a method of obtaining the
parity check matrix H from the parity check matrix
CA 02924874 20160318
initial value table.
[0199] In other words, the parity check matrix initial
value table in Fig. 21 illustrates the parity check
matrix initial value table for the parity check matrix H
5 whose code length N is 16200 bits and code rate r is 2/3
specified in the DVB.T2 standard.
[0200] The parity check matrix initial value table is
the table indicating the position of the element 1 of the
information matrix HA (Fig. 10) corresponding to the
10 information length K according to the code length N and
code rate r is the LDPC code for each 360 columns (the
number of columns P being the unit of the cyclic
structure) as described above in which row numbers (the
row number of the first row of the parity check matrix H
15 is 0) of the elements of 1 of a 1 + 360 x (i  1)th
column of the parity check matrix H as many as the number
of column weights of the 1 + 360 x (i  1)th column are
arranged in an ith row.
[0201] Herein, the parity matrix HT (Fig. 10)
20 corresponding to the parity length M of the parity check
matrix H is determined as illustrated in Fig. 15, so that
the information matrix HA (Fig. 10) corresponding to the
information length K of the parity check matrix H is
obtained according to the parity check matrix initial
25 value table.
[0202] The number of rows k + 1 of the parity check
matrix initial value table differs according to the
information length K.
CA 02924874 20160318
56
[0203] The information length K and the number of rows
k + 1 of the parity check matrix initial value table
satisfy relationship in equation (9).
[0204]
K = (k+1) x 360 .... (9)
[0205] Herein, 360 in equation (9) is the number of
columns P being the unit of the cyclic structure
illustrated in Fig. 16.
[0206] In the parity check matrix initial value table
in Fig. 21, 13 values are arranged in each of first to
third rows and 3 values are arranged in each of fourth to
k + 1th rows (30th row in Fig. 21).
[0207] Therefore, the column weights of the parity
check matrix H obtained from the parity check matrix
initial value table in Fig. 21 are 13 from the first
column to 1 + 360 x (3  1) 1th column and 3 from the 1
+ 360 x (3  1)th column to a Kth column.
[0208] The first row of the parity check matrix
initial value table in Fig. 21 is 0, 2084, 1613, 1548,
1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622
and this indicates that the element of the rows whose row
numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297,
2481, 3369, 3451, 4620, and 2622 is 1 (and other elements
are 0) in the first column of the parity check matrix H.
[0209] Also, the second row of the parity check matrix
initial value table in Fig. 21 is 1, 122, 1516, 3448,
2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108
and this indicates that the element of the rows whose row
CA 02924874 20160318
57
numbers are 1, 122, 1516, 3448, 2880, 1407, 1847, 3799,
3529, 373, 971, 4358, and 3108 are 1 in a 361 (= 1 + 360
x (2  1))th column of the parity check matrix H.
[0210] As described above, the parity check matrix
initial value table indicates the position of the element
1 of the information matrix HA of the parity check matrix
H for each 360 columns.
[0211] The column other than the 1 + 360 x (i  1)th
column of the parity check matrix H, that is to say, each
column from a 2 + 360 x (i  1)th column to a 360 x ith
column is obtained by periodically performing the cyclic
shift to the element 1 of the 1 + 360 x (i  1)th column
determined by the parity check matrix initial value table
downward (in a direction toward a lower part of the
column) according to the parity length M to arrange.
[0212] That is to say, the 2 + 360 x (i  1)th column
is obtained by the cyclic shift of the 1 + 360 x (i  1)
th column downward by M/360 (= q) and a next 3 + 360 x (i
 1)th column is obtained by the cyclic shift of the 1 +
360 x (i  1)th column downward by 2 x M/360 (= 2 x q)
(the cyclic shift of the 2 + 360 x (i  1)th column
downward by M/360(= q)), for example.
[0213] Herein, if an ith row (ith row from the top)
jth column (jth column from left) value of the parity
check matrix initial value table is represented as hi, j
and the row number of a jth element 1 of a wth column
of the parity check matrix H is represented as Hwj, a row
number Hw_j of the element 1 of the wth column being the
CA 02924874 20160318
58
column other than the 1 + 360 x (i  1)th column of the
parity check matrix H may be obtained by equation (10).
[0214]
Hwi = mod{hi, jFmod((wl), P) x q, M) (10)
[0215] Herein, mod (x, y) represents a remainder
obtained when x is divided by y.
[0216] Also, P represents the abovedescribed number
of columns being the unit of the cyclic structure, which
is set to 360 as described above in the DVBS.2 standard,
the DVBT.2 standard and the DVBC.2 standard, for
example. Further, q represents a value M/360 obtained by
dividing the parity length M by the number of columns P
(= 360) being the unit of the cyclic structure.
[0217] The parity check matrix generation unit 613
(Fig. 18) specifies the row number of the element 1 of
the 1 + 360 x (i  1)th column of the parity check
matrix by the parity check matrix initial value table.
[0218] Further, the parity check matrix generation
unit 613 (Fig. 18) obtains the row number of the
element 1 of the wth column being the column other than
the 1 + 360 x (i  1)th column of the parity check
matrix H according to equation (10) and generates the
parity check matrix H in which an element of the row
number obtained from above is 1.
[0219]
<New LDPC code>
[0220]
At present, the standard for terrestrial digital
CA 02924874 20160318
59
television broadcasting which is called as ATSC3.0 is
planned.
[0221] A planned LDPC code (hereinafter also referred
to as a "new LDPC code") such as ATSC3.0 and other data
broadcasting will be described.
[0222] As for the new LDPC code, the parity matrix HT
of the parity check matrix H has the stepwise structure
(Fig. 11) as is the case with the LDPC code specified in
DVBT.2 from a viewpoint of maintaining compatibility
with DVBT.2 as far as possible.
[0223] Further, as for the new LDPC code, as is the
case with the LDPC code specified in DVBT.2, the
information matrix HA of the parity check matrix H has the
cyclic structure and the number of columns P being the
unit of the cyclic structure is set to 360.
[0224] The LDPC encoder 115 (Fig. 8, Fig. 18) performs
the LDPC encoding to the new LDPC encoding using the
parity check matrix H obtained from the parity check
matrix initial value table of the new LDPC encoding whose
code length N is 16k bits or 64k bits and any of the code
rates r of 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15 or
13/15 as described below.
[0225] In this case, the parity check matrix initial
value table is stored in the storage unit 602 of the LDPC
encoder 115 (Fig. 8).
[0226] Fig. 22, Fig. 23 and Fig. 24 each is a diagram
showing the parity check matrix initial value table of
the parity check matrix H of a first new LDPC code whose
CA 02924874 20160318
code length N is 64k bits and code rate r is 7/15
(hereinafter also referred to as a "first new LDPC code
of (64k, 7/15)).
[0227] Fig. 23 follows Fig. 22. Fig. 24 follows Fig.
5 23.
[0228] Fig. 25, Fig. 26 and Fig. 27 each is a diagram
showing the parity check matrix initial value table of
the parity check matrix H of a first new LDPC code whose
code length N is 64k bits and code rate r is 9/15
10 (hereinafter also referred to as a "first new LDPC code
of (64k, 9/15)).
[0229] Fig. 26 follows Fig. 25. Fig. 27 follows Fig.
26.
[0230] Fig. 28, Fig. 29 and Fig. 30 each is a diagram
15 showing the parity check matrix initial value table of
the parity check matrix H of a first new LDPC code whose
code length N is 64k bits and code rate r is 11/15
(hereinafter also referred to as a "first new LDPC code
of (64k, 11/15)).
20 [0231] Fig. 29 follows Fig. 28. Fig. 30 follows Fig.
29.
[0232] Fig. 31, Fig. 32 and Fig. 33 each is a diagram
showing the parity check matrix initial value table of
the parity check matrix H of a first new LDPC code whose
25 code length N is 64k bits and code rate r is 13/15
(hereinafter also referred to as a "first new LDPC code
of (64k, 13/15)).
[0233] Fig. 32 follows Fig. 31. Fig. 33 follows Fig.
CA 02924874 20160318
61
32.
[0234] Fig. 34 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a first new LDPC code whose code length N is 16k bits
and code rate r is 6/15 (hereinafter also referred to as
a "first new LDPC code of (16k, 6/15)).
[0235] Fig. 35 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a first new LDPC code whose code length N is 16k bits
and code rate r is 8/15 (hereinafter also referred to as
a "first new LDPC code of (16k, 8/15)).
[0236] Fig. 36 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a first new LDPC code whose code length N is 16k bits
and code rate r is 10/15 (hereinafter also referred to as
a "first new LDPC code of (16k, 10/15)).
[0237] Fig. 37 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a first new LDPC code whose code length N is 16k bits
and code rate r is 12/15 (hereinafter also referred to as
a "first new LDPC code of (16k, 12/15)).
[0238] Fig. 38 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a first other new LDPC code whose code length N is 16k
bits and code rate r is 10/15 (hereinafter also referred
to as a "first other new LDPC code of (16k, 10/15)).
[0239] Fig. 39 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
CA 02924874 20160318
62
of a first other new LDPC code whose code length N is 16k
bits and code rate r is 12/15 (hereinafter also referred
to as a "first other new LDPC code of (16k, 12/15)).
[0240] Fig. 40 and Fig. 41 each is a diagram showing
the parity check matrix initial value table of the parity
check matrix H of a second new LDPC code whose code
length N is 64k bits and code rate r is 6/15 (hereinafter
also referred to as a "second new LDPC code of (64k,
6/15)).
[0241] Fig. 41 follows Fig. 40.
[0242] Fig. 42, Fig. 43 and Fig. 44 each is a diagram
showing the parity check matrix initial value table of
the parity check matrix H of a second new LDPC code whose
code length N is 64k bits and code rate r is 8/15
(hereinafter also referred to as a "second new LDPC code
of (64k, 8/15)).
[0243] Fig. 43 follows Fig. 42. Fig. 44 follows Fig.
43.
[0244] Fig. 45, Fig. 46 and Fig. 47 each is a diagram
showing the parity check matrix initial value table of
the parity check matrix H of a second new LDPC code whose
code length N is 64k bits and code rate r is 10/15
(hereinafter also referred to as a "second new LDPC code
of (64k, 10/15))=
[0245] Fig. 46 follows Fig. 45. Fig. 47 follows Fig.
46.
[0246] Fig. 48, Fig. 49 and Fig. 50 each is a diagram
showing the parity check matrix initial value table of
CA 02924874 20160318
63
the parity check matrix H of a second new LDPC code whose
code length N is 64k bits and code rate r is 12/15
(hereinafter also referred to as a "second new LDPC code
of (64k, 12/15)).
[0247] Fig. 49 follows Fig. 48. Fig. 50 follows Fig.
49.
[0248] Fig. 51 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a second new LDPC code whose code length N is 16k bits
and code rate r is 7/15 (hereinafter also referred to as
a "second new LDPC code of (16k, 7/15)).
[0249] Fig. 52 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a second new LDPC code whose code length N is 16k bits
and code rate r is 9/15 (hereinafter also referred to as
a "second new LDPC code of (16k, 9/15)).
[0250] Fig. 53 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a second new LDPC code whose code length N is 16k bits
and code rate r is 11/15 (hereinafter also referred to as
a "second new LDPC code of (16k, 11/15)).
[0251] Fig. 54 is a diagram showing the parity check
matrix initial value table of the parity check matrix H
of a second new LDPC code whose code length N is 16k bits
and code rate r is 13/15 (hereinafter also referred to as
a "second new LDPC code of (16k, 13/15)).
[0252] (The parity check matrix initial value tables of
the parity check matrices H of) the second new LDPC codes
CA 02924874 20160318
64
shown in Fig. 40 to Fig. 54 are provided from Samsung.
[0253] The first new LDPC codes and the first other new
LDPC codes are highperformance LDPC codes.
[0254] Herein, the highperformance LDPC code is obtained
from an appropriate parity check matrix H.
[0255] The term the "appropriate parity check matrix
H" is intended to mean the parity check matrix, which
satisfies a predetermined condition to make the BER (and
FER) lower when the LDPC code obtained from the parity
check matrix H is transmitted with low Es/No or Eb/No
(signal power to noise power ratio per bit).
[0256] The appropriate parity check matrix H may be
obtained by the simulation of the measurement of the BER
at the time when the LDPC code obtained from the various
parity check matrices satisfying the predetermined
condition is transmitted with the low Es/No, for example.
[0257] The predetermined condition, which the
appropriate parity check matrix H should satisfy,
includes an excellent analysis result obtained by an
analyzing method of performance of the code referred to
as density evolution, absence of a loop of the elements
of 1 referred to as cycle4 and the like, for example.
[0258] Herein, it is known that the decoding
performance of the LDPC code is deteriorated when the
elements of 1 close up as the cycle4 in the information
matrix HA, so that the absence of the cycle4 is required
as the predetermined condition, which the appropriate
parity check matrix H should satisfy.
CA 02924874 20160318
[0259] The predetermined condition, which the
appropriate parity check matrix H should satisfy, may be
appropriately determined from a viewpoint of improvement
in the decoding performance of the LDPC code,
5 facilitation (simplification) of the decoding process of
the LDPC code and the like.
[0260] Fig. 55 and Fig. 56 are views illustrating the
density evolution with which the analysis result as the
predetermined condition, which the appropriate parity
10 check matrix H should satisfy, is obtained.
[0261] The density evolution is the analyzing method
of the code, which calculates an expected value of the
error probability for an entire LDPC code (ensemble)
whose code length N is co characterized by a degree
15 sequence to be described later.
[0262] For example, when a variance value of noise is
set to be larger from 0 on the AWGN channel, the expected
value of the error probability of a certain ensemble,
which is initially 0, is no longer 0 when the variance
20 value of the noise becomes a certain threshold or larger.
[0263] According to the density evolution, it is
possible to determine whether performance of the ensemble
(appropriateness of the parity check matrix) is excellent
by comparing the threshold of the variance value of the
25 noise (hereinafter, also referred to as a performance
threshold) at which the expected value of the error
probability is no longer 0.
[0264] It is possible to predict rough performance of
CA 02924874 20160318
66
a specific LDPC code by determining the ensemble to which
the LDPC code belongs and performing the density
evolution to the ensemble.
[0265] Therefore, when a highperformance ensemble is
found, the highperformance LDPC code may be found from
the LDPC codes belonging to the ensemble.
[0266] Herein, the abovedescribed degree sequence
indicates a ratio of the variable node and the check node
having the weight of each value to the code length N of
the LDPC code.
[0267] For example, a regular (3, 6) LDPC code whose
code rate is 1/2 belongs to the ensemble characterized by
the degree sequence in which the weight (column weight)
of all the variable nodes is 3 and the weight (row
weight) of all the check nodes is 6.
[0268] Fig. 55 shows the Tanner graph of such ensemble.
[0269] In the Tanner graph in Fig. 55, there are N
(equal to the code length N) variable nodes represented
by a circle (0) in the drawing and N/2 (equal to a
product obtained by multiplying the code rate 1/2 by the
code length N) check nodes represented by a square (0) in
the drawing.
[0270] Three edges, the number of which is equal to
the column weight, are connected to each variable node,
so that there are a total of 3N edges connected to the N
variable nodes.
[0271] Also, six edges the number of which is equal to
the row weight, are connected to each check node, so that
CA 02924874 20160318
67
there are a total of 3N edges connected to the N/2 check
nodes.
[0272] Further, there is one interleaver in the Tanner
graph in Fig. 55.
[0273] The interleaver randomly rearranges the 3N
edges connected to the N variable nodes and connects the
rearranged edges to any of the 3N edges connected to the
N/2 check nodes.
[0274] There are (3N)!(= (3N) x (3N  1) x === x 1)
rearranging patterns of rearranging the 3N edges
connected to the N variable nodes by the interleaver.
Therefore, the ensemble characterized by the degree
sequence in which the weight of all the variable nodes is
3 and the weight of all the check nodes is 6 is a set of
(3N)! LDPC codes.
[0275] In the simulation for obtaining the high
performance LDPC code (appropriate parity check matrix),
a multiedge type ensemble is used in the density
evolution.
[0276] In the multiedge type, the interleaver through
which the edge connected to the variable node and the
edge connected to the check node pass is divided into a
multiedge one, so that the ensemble is more strictly
characterized.
[0277] Fig. 56 shows an example of the Tanner graph of
the multiedge type ensemble.
[0278] In the Tanner graph in Fig. 56, there are two
interleavers, which are a first interleaver and a second
CA 02924874 20160318
68
interleaver.
[0279] In the Tanner graph in Fig. 56, there are vi
variable nodes with one edge connected to the first
interleaver and no edge connected to the second
interleaver, v2 variable nodes with one edge connected to
the first interleaver and two edges connected to the
second interleaver, and v3 variable nodes with no edge
connected to the first interleaver and two edges
connected to the second interleaver.
[0280] Further, in the Tanner graph in Fig. 56, there
are cl check nodes with two edges connected to the first
interleaver and no edge connected to the second
interleaver, c2 check nodes with two edges connected to
the first interleaver and two edges connected to the
second interleaver, and c3 check nodes with no edge
connected to the first interleaver and three edges
connected to the second interleaver.
[0281] Herein, the density evolution and
implementation thereof are described in "On the Design of
LowDensity ParityCheck Codes within 0.0045 dB of the
Shannon Limit", S. Y. Chung, G. D. Forney, T. J.
Richardson, and R. Urbanke, IEEE Communications Leggers,
VOL. 5, NO. 2, Feb 2001, for example.
[0282] In the simulation for obtaining (the parity
check matrix initial value table of) the first new LDPC
codes and the first other new LDPC code, the ensemble in
which the performance threshold being Eb/No (signal power
to noise power ratio per bit) at which the BER starts to
CA 02924874 20160318
69
decrease (to be lower) is a predetermined value or
smaller is found by multiedge type density evolution and
the LDPC code to decrease the BER is selected as the
highperformance LDPC code out of the LDPC codes
belonging to the ensemble.
[0283] The parity check matrix initial value tables of
the abovedescribed first new LDPC codes and first other
new LDPC codes are determined by the above simulation.
[0284] Accordingly, by the first new LDPC codes and
the first other new LDPC codes obtained from the parity
check matrix initial value tables, it is possible to
ensure a good communication quality in the data
transmission.
[0285] Fig. 57 is a view showing a minimum cycle
length and a performance threshold of the parity check
matrices H obtained from the parity check matrix initial
value tables of the first new LDPC codes of (64k, 7/15),
(64k, 9/15), (64k, 11/15) and (64k, 13/15) (hereinafter
also referred to as "the parity check matrices H of the
first new LDPC codes of (64k, 7/15), (64k, 9/15), (64k,
11/15) and (64k, 13/15)) shown in Fig. 22 to Fig. 33.
[0286] Here, the minimum cycle length (girth) means a
minimum value of a length of a loop (loop length)
configured of the elements of 1 in the parity check
matrix H.
[0287] The parity check matrices H of the first new
LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15) and
(64k, 13/15) have no cycle4 (the loop length of four, a
CA 02924874 20160318
loop of the elements of 1).
[0288] The performance threshold of the first new LDPC
code of (64k, 7/15) is 0.093751, the performance
threshold of the first new LDPC code of (64k, 9/15) is
5 1.658523, the performance threshold of the first new LDPC
code of (64k, 11/15) is 3.351930 and the performance
threshold of the first new LDPC code of (64k, 13/15) is
5.301749.
[0289] Fig. 58 is a view illustrating the parity check
10 matrices H of the first new LDPC codes of (64k, 7/15),
(64k, 9/15), (64k, 11/15) and (64k, 13/15) in Fig. 32 to
Fig. 33.
[0290] The column weight is X1 for first to KX1th
columns of the parity check matrices H of the first new
15 LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15) and
(64k, 13/15), the column weight is X2 for next KY2
columns, the column weight is Y1 for next KY1 columns,
the column weight is Y2 for next KY2 columns, the column
weight is 2 for next M1 columns, and the column weight
20 is 1 for a last column, respectively.
[0291] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
equal to the code length N = 64800 bits of the first new
LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15) and
(64k, 13/15).
25 [0292] Fig. 59 is a view showing the numbers of
columns KX1, KY2, KY1, KY2 and M, and the column weights
Xl, X2, Yl, and Y2 in Fig. 58 for the parity check
matrices H of the first new LDPC codes of (64k, 7/15),
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71
(64k, 9/15), (64k, 11/15) and (64k, 13/15).
[0293] As for the parity check matrices H of the first
new LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15)
and (64k, 13/15), as is the case with the parity check
matrix illustrated in Figs. 12 and 13, the column weight
of the column closer to the top (left) column tends to be
larger, so that the code bit closer to the top code bit
of the new LDPC code tends to be more tolerant to error
(have resistance to error).
[0294] Fig. 60 is a view showing a simulation result
of the BER/FER (bit error rate/frame error rate) of the
first new LDPC code of (64k, 7/15) measured using the
QPSK as the modulation scheme.
[0295] Fig. 61 is a diagram showing a simulation
result of measurement of BER/FER about the first new LDPC
code of (64k, 9/15) measured using the QPSK as the
modulation scheme.
[0296] Fig. 62 is a view showing a simulation result
of the BER/FER of the first new LDPC code of (64k, 11/15)
measured using the QPSK as the modulation scheme.
[0297] Fig. 63 is a view showing a simulation result
of the BER/FER of the first new LDPC code of (64k, 13/15)
measured using the QPSK as the modulation scheme.
[0298] In the simulation, the AWGN channel is supposed,
and 50 times is adopted as the number of times of
repetitive decoding C for decoding the LDPC code.
[0299] In Fig. 60 to Fig. 63, Es/No is plotted along
the abscissa and the BER/FER is plotted along the
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72
ordinate. A solid line represents the BER, and a dotted
line represents the FER.
[0300] According to Fig. 60 to Fig. 63, as for the
first new LDPC codes of (64k, 7/15), (64k, 9/15), (64k,
11/15) and (64k, 13/15), excellent BER/FER are obtained.
Accordingly, it can confirm that a good communication
quality is ensured in the data transmission using the
first new LDPC codes of (64k, 7/15), (64k, 9/15), (64k,
11/15) and (64k, 13/15).
[0301] Fig. 64 is a view showing a minimum cycle
length and a performance threshold of the parity check
matrices H of the first new LDPC codes of (64k, 6/15),
(64k, 8/15), (64k, 10/15) and (64k, 12/15) shown in Fig.
34 to Fig. 37.
[0302] The parity check matrices H of the first new
LDPC codes of (16k, 6/15), (16k, 8/15), (16k, 10/15) and
(16k, 12/15) have no cycle4.
[0303] The performance threshold of the first new LDPC
code of (16k, 6/15) is 0.01, the performance threshold of
the first new LDPC code of (16k, 8/15) is 0.805765, the
performance threshold of the first new LDPC code of (16k,
10/15) is 2.471011 and the performance threshold of the
first new LDPC code of (16k, 12/15) is 4.269922.
[0304] Fig. 65 is a view illustrating the parity check
matrices H of the first new LDPC codes of (16k, 6/15),
(16k, 8/15), (16k, 10/15) and (16k, 12/15) in Fig. 34 to
Fig. 37.
[0305] The column weight is X1 for first to KX1th
CA 02924874 20160318
73
columns of the parity check matrices H of the first new
LDPC codes of (16k, 6/15), (16k, 8/15), (16k, 10/15) and
(16k, 12/15), the column weight is X2 for next KY2
columns, the column weight is Y1 for next KY1 columns,
the column weight is Y2 for next KY2 columns, the column
weight is 2 for next M1 columns, and the column weight
is 1 for a last column, respectively.
[0306] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
equal to the code length N = 16200 bits of the first new
LDPC codes of (16k, 6/15), (16k, 8/15), (16k, 10/15) and
(16k, 12/15).
[0307] Fig. 66 is a view showing the numbers of
columns KX1, KY2, KY1, KY2, and M, and the column weights
X1, X2, Y1, and Y2 in Fig. 65 for the parity check
matrices H of the first new LDPC codes of (16k, 6/15),
(16k, 8/15), (16k, 10/15) and (16k, 12/15).
[0308] As for the parity check matrices H of the first
new LDPC codes of (16k, 6/15), (16k, 8/15), (16k, 10/15)
and (16k, 12/15), as is the case with the parity check
matrix illustrated in Figs. 12 and 13, the column weight
of the column closer to the top (left) column tends to be
larger, so that the code bit closer to the top code bit
of the new LDPC code tends to be more tolerant to error.
[0309] Fig. 67 is a view showing a simulation result
of the BER/FER (bit error rate/frame error rate) of the
first new LDPC code of (16k, 6/15) measured using the
QPSK as the modulation scheme.
[0310] Fig. 68 is a view showing a simulation result
CA 02924874 20160318
74
of the BER/FER of the first new LDPC code of (16k, 8/15)
measured using the QPSK as the modulation scheme.
[0311] Fig. 69 is a view showing a simulation result
of the BER/FER of the first new LDPC code of (16k, 10/15)
measured using the QPSK as the modulation scheme.
[0312] Fig. 70 is a view showing a simulation result
of the BER/FER of the first new LDPC code of (16k, 12/15)
measured using the QPSK as the modulation scheme.
[0313] In the simulation, the AWGN channel is supposed
as the communication channel 13 (Fig. 7), and 50 times is
adopted as the number of times of repetitive decoding C
for decoding the LDPC code.
[0314] In Fig. 67 to Fig. 70, Es/No is plotted along
the abscissa and the BER/FER is plotted along the
ordinate. A solid line represents the BER, and a dotted
line represents the FER.
[0315] According to Fig. 67 to Fig. 70, as for the
first new LDPC codes of (16k, 6/15), (16k, 8/15), (16k,
10/15) and (16k, 12/15), excellent BER/FER are obtained.
Accordingly, it can confirm that a good communication
quality is ensured in the data transmission using the
first new LDPC codes of (16k, 6/15), (16k, 8/15), (16k,
10/15) and (16k, 12/15).
[0316] Fig. 71 is a view showing a minimum cycle
length and a performance threshold of the parity check
matrix H of the first new LDPC code of (16k, 10/15) shown
in Fig. 38.
[0317] The parity check matrix H of the other first
CA 02924874 20160318
new LDPC code of (16k, 10/15) has no cycle4.
[0318] The performance threshold of the first other
new LDPC code of (16k, 10/15) is 1.35.
[0319] Fig. 72 is a view illustrating the parity check
5 matrix H of the first other new LDPC code of (16k, 10/15)
in Fig. 72.
[0320] The column weight is X for first to KX1th
columns of the parity check matrix H of the first other
new LDPC code of (16k, 10/15), the column weight is Y1
10 for next KY1 columns, the column weight is Y2 for next
KY2 columns, the column weight is 2 for next M1 columns,
and the column weight is 1 for a last column,
respectively.
[0321] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
15 equal to the code length N = 16200 bits of the first
other new LDPC code of (16k, 10/15).
[0322] Fig. 73 is a view showing the numbers of
columns KX, KY1, KY2, and M, and the column weights Xl,
X2, Yl, and Y2 in Fig. 72 for the code matrix H of the
20 first other new LDPC code of (16k, 10/15).
[0323] As for the parity check matrix H of the first
other new LDPC code of (16k, 10/15), as is the case with
the parity check matrix illustrated in Figs. 12 and 13,
the column weight of the column closer to the top (left)
25 column tends to be larger, so that the code bit closer to
the top code bit of the new LDPC code tends to be more
tolerant to error.
[0324] Fig. 74 is a view showing a simulation result
CA 02924874 20160318
76
of the BER of the first other new LDPC code of (16k,
10/15) measured using the BPSK as the modulation scheme.
[0325] In the simulation, the AWGN channel is supposed
as the communication channel 13 (Fig. 7), and 50 times is
adopted as the number of times of repetitive decoding C
for decoding the LDPC code.
[0326] In Fig. 74, Es/No is plotted along the abscissa
and the BER is plotted along the ordinate. [0327]
According to Fig. 74, as for the first other new
LDPC code of (16k, 10/15), excellent BER is obtained.
Accordingly, it can confirm that a good communication
quality is ensured in the data transmission using the
first other new LDPC code of (16k, 10/15).
[0328] Fig. 75 is a view showing a minimum cycle length
and a performance threshold of the parity check matrix H
of the other first new LDPC code of (16k, 12/15) shown in
Fig. 39.
[0329] The parity check matrices H of the first other
new LDPC code of (16k, 12/15) has no cycle4.
[0330] The performance threshold of the first other
new LDPC code of (16k, 12/15) is 4.237556.
[0331] Fig. 76 is a view illustrating the parity check
matrix H of the first other new LDPC code of (16k, 12/15)
in Fig. 39.
[0332] The column weight is X1 for first to KX1th
columns of the parity check matrix H of the first other
new LDPC code of (16k, 12/15), the column weight is X2
for next KY2 columns, the column weight is Y1 for next
CA 02924874 20160318
77
KY1 columns, the column weight is Y2 for next KY2 columns,
the column weight is 2 for next M1 columns, and the
column weight is 1 for a last column, respectively.
[0333] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
equal to the code length N = 16200 bits of the first
other new LDPC code of (16k, 12/15).
[0334] Fig. 77 is a view showing the numbers of
columns KX1, KX2, KY1, KY2 and M, and the column weights
X1, X2, Yl, and Y2 in Fig. 76 for the code matrix H of
the first other new LDPC code of (16k, 12/15).
[0335] As for the parity check matrix H of the first
other new LDPC code of (16k, 12/15), as is the case with
the parity check matrix illustrated in Figs. 12 and 13,
the column weight of the column closer to the top (left)
column tends to be larger, so that the code bit closer to
the top code bit of the new LDPC code tends to be more
tolerant to error.
[0336] Fig. 78 is a view showing a simulation result
of the BER/FER (bit error rate/frame error rate) of the
first other new LDPC code of (16k, 12/15) measured using
the QPSK as the modulation scheme.
[0337] In the simulation, the AWGN channel is supposed
as the communication channel 13 (Fig. 7), and 50 times is
adopted as the number of times of repetitive decoding C
for decoding the LDPC code.
[0338] In Fig. 78, Es/No is plotted along the abscissa
and the BER is plotted along the ordinate. A solid line
represents the BER, and a dotted line represents the FER.
CA 02924874 20160318
78
[0339] According to Fig. 78, as for the first other
new LDPC code of (16k, 12/15), excellent BER/FER is
obtained. Accordingly, it can confirm that a good
communication quality is ensured in the data transmission
using the first other new LDPC code of (16k, 12/15).
[0340] Fig. 79 is a view illustrating the parity check
matrices H of the second new LDPC codes of (64k, 6/15),
(64k, 8/15), (64k, 10/15) and (64k, 12/15) in Fig. 40 to
Fig. 50.
[0341] The column weight is X1 for first to KX1th
columns of the parity check matrices H of the second new
LDPC codes of (64k, 6/15), (64k, 8/15), (64k, 10/15) and
(64k, 12/15), the column weight is X2 for next KY2
columns, the column weight is Y1 for next KY1 columns,
the column weight is Y2 for next KY2 columns, the column
weight is 2 for next M1 columns, and the column weight
is 1 for a last column, respectively.
[0342] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
equal to the code length N = 64800 bits of the second new
LDPC codes of (64k, 6/15), (64k, 8/15), (64k, 10/15) and
(64k, 12/15).
[0343] Fig. 80 is a view showing the numbers of
columns KX1, KX2, KY1, KY2, and M, and the column weights
Xi, X2, Yl, and Y2 in Fig. 79 for the parity check
matrices H of the second new LDPC codes of (64k, 6/15),
(64k, 8/15), (64k, 10/15) and (64k, 12/15).
[0344] As for the parity check matrices H of the
second new LDPC codes of (64k, 6/15), (64k, 8/15), (64k,
CA 02924874 20160318
79
10/15) and (64k, 12/15), as is the case with the parity
check matrix illustrated in Figs. 12 and 13, the column
weight of the column closer to the top (left) column
tends to be larger, so that the code bit closer to the
top code bit of the new LDPC code tends to be more
tolerant to error.
[0345] Fig. 81 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (64k, 6/15)
measured using the QPSK as the modulation scheme.
[0346] Fig. 82 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (64k, 8/15)
measured using the QPSK as the modulation scheme.
[0347] Fig. 83 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (64k,
10/15) measured using the QPSK as the modulation scheme.
[0348] Fig. 84 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (64k,
12/15) measured using the QPSK as the modulation scheme.
[0349] In the simulation, the AWGN channel is supposed,
and 50 times is adopted as the number of times of
repetitive decoding C for decoding the LDPC code.
[0350] In Fig. 81 to Fig. 84, Es/No is plotted along
the abscissa and the BER/FER is plotted along the
ordinate. A solid line represents the BER, and a dotted
line represents the FER.
[0351] According to Fig. 81 to Fig. 84, as for the
second new LDPC codes of (64k, 6/15), (64k, 8/15), (64k,
10/15) and (64k, 12/15), excellent BER/FER are obtained.
CA 02924874 20160318
Accordingly, it can confirm that a good communication
quality is ensured in the data transmission using the
second new LDPC codes of (64k, 6/15), (64k, 8/15), (64k,
10/15) and (64k, 12/15).
5 [0352] Fig. 85 is a view illustrating the parity check
matrices H of the second new LDPC codes of (64k, 7/15),
(64k, 9/15), (64k, 11/15) and (64k, 13/15) shown in Fig.
51 to Fig. 54.
[0353] The column weight is X1 for first to KX1th
10 columns of the parity check matrices H of the second new
LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15) and
(64k, 13/15), the column weight is X2 for next KY2
columns, the column weight is Y1 for next KY1 columns,
the column weight is Y2 for next KY2 columns, the column
15 weight is 2 for next M1 columns, and the column weight
is 1 for a last column, respectively.
[0354] Herein, KX1 + KX2 + KY1 + KY2 + M1 + 1 is
equal to the code length N = 16200 bits of the second new
LDPC codes of (16k, 7/15), (16k, 9/15), (16k, 11/15) and
20 (16k, 13/15).
[0355] Fig. 86 is a view showing the numbers of
columns KX1, KX2, KY1, KY2, and M, and the column weights
Xl, X2, Yl, and Y2 in Fig. 85 for the parity check
matrices H of the second new LDPC codes of (16k, 7/15),
25 (16k, 9/15), (16k, 11/15) and (16k, 13/15).
[0356] As for the parity check matrices H of the
second new LDPC codes of (16k, 7/15), (16k, 9/15), (16k,
11/15) and (16k, 13/15), as is the case with the parity
CA 02924874 20160318
81
check matrix illustrated in Figs. 12 and 13, the column
weight of the column closer to the top (left) column
tends to be larger, so that the code bit closer to the
top code bit of the new LDPC code tends to be more
tolerant to error.
[0357] Fig. 87 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (16k, 7/15)
measured using the QPSK as the modulation scheme.
[0358] Fig. 88 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (16k, 9/15)
measured using the QPSK as the modulation scheme.
[0359] Fig. 89 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (16k,
11/15) measured using the QPSK as the modulation scheme.
[0360] Fig. 90 is a view showing a simulation result
of the BER/FER of the second new LDPC code of (16k,
13/15) measured using the QPSK as the modulation scheme.
[0361] In the simulation, the AWGN channel is supposed
as the communication channel 13 (Fig. 7), and 50 times is
adopted as the number of times of repetitive decoding C
for decoding the LDPC code.
[0362] In Fig. 87 to Fig. 90, Es/No is plotted along
the abscissa and the BER/FER is plotted along the
ordinate. A solid line represents the BER, and a dotted
line represents the FER.
[0363] According to Fig. 87 to Fig. 90, as for the
second new LDPC codes of (16k, 7/15), (16k, 9/15), (16k,
11/15) and (16k, 13/15), excellent BER/FER are obtained.
CA 02924874 20160318
82
Accordingly, it can confirm that a good communication
quality is ensured in the data transmission using the
first new LDPC codes of (16k, 7/15), (16k, 9/15), (16k,
11/15) and (16k, 13/15).
[0364] Fig. 79 to Fig. 90 are data provided from
Samsung.
[0365]
<Constellation>
[0366] Fig. 91 is a diagram showing illustrative types
of the constellation used in the transmission system in
Fig. 7.
[0367] In the transmission system in Fig. 7, the
constellation expected to be specified by ATSC3.0 may be
used.
[0368] Fig. 91 shows illustrative types of the
constellation expected to be used by ATSC3Ø
[0369] In the ATSC3.0, the constellation used in the
MODCOD that is a combination of the modulation scheme and
the LDPC code is set.
[0370] In the ATSC3.0, it is expected to use five
modulation schemes, i.e.õ QPSK, 16QAM, 64QAM, 256QAM
and 1024QAM (1kQAM).
[0371] In the ATSC3.0, it is expected to use 16 types
of the LDPC codes whose code rates r of eight types of
6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15 and 13/15 for
each of two types of code lengths N of 16k bits and 64k
bits.
[0372] In the ATSC3.0, 16 types of the LDPC codes are
CA 02924874 20160318
83
classified into 8 types (not depending on the code
lengths N) by the code rates r, and it is expected that
40 (= 8 x 5) combinations of 8 types of the LDPC codes
(each LDPC code whose code rate r is 6/15, 7/15, 8/15,
9/15, 10/15, 11/15, 12/15 or 13/15) and 5 types of the
modulation schemes are used as a MODCOD capable of
setting the constellation.
[0373] Accordingly, in the ATSC3.0, the MODCOD
represents the combination of the 8 types of the code
rates r of the LDPC codes and 5 types of the modulation
schemes.
[0374] In Fig. 91, "NUC_16_6/15" described in the
column "NUC Shape" represents the constellation used in
the MODCOD corresponding to the row of the column "NUC
Shape".
[0375] Herein, for example, the "NUC_16_6/15"
represents the constellation used in the MODCOD where the
modulation scheme is 16QAM and code rate r is the LDPC
code is 6/15.
[0376] As shown in Fig. 91, if the modulation scheme
is QPSK, the same constellation is used for the 8 types
of the code rates r of the LDPC code.
[0377] Also as shown in Fig. 91, if the modulation
scheme is 16QAM, 64QAM, 256QAM or 1024QAM, different
constellations are used for the 8 types of the code rates
r of the LDPC code.
[0378] Accordingly, in the ATSC3.0, one constellation
is prepared for QPSK, and eight constellations are
CA 02924874 20160318
84
prepared each for 16QAM, 64QAM, 256QAM and 1024QAM.
[0379] There are a UC (Uniform Constellation) where a
constellation of signal points is uniform and a NUC (Non
Uniform Constellation) where a constellation is not
uniform.
[0380] Also, there are constellations called as 1D NUC
(1dimensional M2  QAM nonuniform constellation), 2D NUC
(2dimensional QQAM nonuniform constellation) and the
like.
[0381] As the constellation of QPSK, UC is used. As
the constellations of 16QAM, 64QAM and 256QAM, 2D NUC is
used, for example. As the constellations of 1024QAM, 1D
NUC is used, for example.
[0382] Fig. 92 is a diagram showing an example of the
constellation for the eight code rates r of the LDPC code
when the modulation scheme is 16QAM.
[0383] Fig. 93 is a diagram showing an example of the
constellation for the eight code rates r of the LDPC code
when the modulation scheme is 64QAM.
[0384] Fig. 94 is a diagram showing an example of the
constellation for the eight code rates r of the LDPC code
when the modulation scheme is 256QAM.
[0385] Fig. 95 is a diagram showing an example of the
constellation for the eight code rates r of the LDPC code
when the modulation scheme is 1024QAM.
[0386] In Fig. 92 to Fig. 95, each abscissa and each
ordinate are an I axis and a Q axis, Re{xl} and Im{x1}
represent a real part and an imaginary part of a signal
CA 02924874 20160318
point xl as a coordinates of the signal point xl.
[0387] In Fig. 92 to Fig. 95, the numerical values
followed by "for CR" represent the code rates r of the
LDPC code.
5 [0388] The constellations where the code rates r of
the LDPC code are 7/15, 9/15, 11/15 and 13/15 are based
on the data provided from Samsung.
[0389] Fig. 96 is a view showing a simulation result
of measurement of BER when UC, 1D NUC or 2D NUC is used
10 as the constellation in the case of the modulation scheme
of 16QAM.
[0390] Fig. 97 is a view showing a simulation result
of measurement of BER when UC, 1D NUC or 2D NUC is used
as the constellation in the case of the modulation scheme
15 of 64QAM.
[0391] Fig. 98 is a view showing a simulation result
of measurement of BER when UC, 1D NUC or 2D NUC is used
as the constellation in the case of the modulation scheme
of 256QAM.
20 [0392] Fig. 99 is a view showing a simulation result
of measurement of BER when UC, 1D NUC or 2D NUC is used
as the constellation in the case of the modulation scheme
of 1024QAM.
[0393] In Fig. 96 to Fig. 99, SNR (Signal to Noise
25 Ratio) is plotted along the abscissa and the BER is
plotted along the ordinate.
[0394] If the modulation scheme is 16QAM, 64QAM or
256QAM, as shown in Fig. 96 to Fig. 98, it can confirm
CA 02924874 20160318
86
that the BER is much improved by 1D NUC than by UC, and
that the BER is further much improved by 2D NUC than by
1D NUC.
[0395] If the modulation scheme is 1024QAM, as shown
in Fig. 99, it can confirm that the BER is much improved
by 1D NUC than by UC.
[0396] Fig. 100 is a diagram showing coordinates of
the signal points of UC commonly used for eight code
rates r (= 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15
and 13/15) of the LDPC code when the modulation scheme is
. QPSK.
[0397] In Fig. 100, "Input cell word y" represents 2
bit symbol of mapping by UC of the QPSK, and
"Constellation point zq" represents a coordinate of a
signal point zq. The index q of the signal point zq
represents a discretetime of symbols (a time interval
between one symbol and the next symbol).
[0398] In Fig. 100, the coordinates of the signal
point zq are represented by a complex number, and i
represents the imaginary unit (r(1)).
[0399] Fig. 101 is a diagram showing coordinates of
the signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
16QAM.
[0400] Fig. 102 is a diagram showing coordinates of
the signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
64QAM.
CA 02924874 20160318
87
[0401] Fig. 103 is a diagram showing coordinates of
the signal points of 2D NUC commonly used for eight code
rates r of the LDPC code when the modulation scheme is
256QAM.
[0402] In Fig. 101 to Fig. 103, NUC_2m_r represents a
coordinate of a signal point of 2D NUC used if the
modulation method is 2mQAM and the code rate of the LDPC
code is r.
[0403] In Fig. 101 to Fig. 103, as in Fig. 100, the
coordinate of the signal point zq is represented by a
complex number, and i represents the imaginary unit.
[0404] In Fig. 101 to Fig. 103, w#k represents a
coordinate of a signal point in a first quadrant of the
constellation.
[0405] In 2D NUC, a signal point of a second quadrant
of the constellation is arranged at a position where the
signal point of the first quadrant is moved symmetrically
with respect to the Q axis, and a signal point of a third
quadrant of the constellation is arranged at a position
where the signal point of the first quadrant is moved
symmetrically with respect to the origin. A signal point
of a fourth quadrant of the constellation is arranged at
a position where the signal point of the first quadrant
is moved symmetrically with respect to the I axis.
[0406] Herein, if the modulation scheme is 2m QAM, m
bits are taken as one symbol, and one symbol is mapped to
signal points corresponding to the symbol.
[0407] The symbol of the m bit symbol is represented,
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88
for example, by 0 to 2m 1 integer values. If b = 2m/4,
the symbols y(0), y(1), ¨=, y (2m1) represented by 0 to
2m1 integer values may be classified into four: symbols
y(0) to y(b1), y(b) to y(2b1), y(2b) to y(3b1) and
y(3b) to (4b1).
[0408] In Fig. 101 to Fig. 103, the suffix k of w#k
represents an integer value of 0 to b1, and w#k
represents the coordinate of the signal point
corresponding to the symbol y(k) from the symbols y(0) to
y(b1).
[0409] The coordinate of the signal point
corresponding to the symbol y(k+b) from the symbols y(b)
to y(2b1) is represented by conj(w#k). The coordinate
of the signal point corresponding to the symbol y(k+2b)
from the symbols y(2b) to y(3b1) is represented by
conj(w#k). The coordinate of the signal point
corresponding to the symbol y(k+3b) from the symbols
y(3b) to y(4b1) is represented by conj(w#k).
[0410] The conj(w#k) represents a complex conjugate of
w#k.
[0411] For example, if the modulation scheme is 16QAM,
m = 4 bit symbols; y(0), y(1), ¨=, y(15) are classified
into four; symbols y(0) to y(3), y(4) to y(7), y(8) to
y(11) and y(12) to y(15) as b = 24/4/4 = 4.
[0412] For example, as the symbol y(12) from the
symbols y(0) to y(15) is a symbol y(k+3b)y(0+3x4) from
the symbols y(3b) to y(4b1) and k = 0, the coordinate of
the signal point corresponding to the symbol y(12) will
CA 02924874 20160318
89
be w#k = w0.
[0413] If the code rate r of the LDPC code, for
example, is 9/15, according to Fig. 101, w0 of
(NUC 16 9/15) where the modulation scheme is 16QAM and
_ _
the code rate r is 9/15 is 0.4909 + 1.2007i. So, a
coordinate w0 of the signal point corresponding to the
symbol y(12) is (0.4909 + 1.2007i).
[0414] Fig. 104 is a diagram showing coordinates of
the signal points of 1D NUC used for eight code rates r
of the LDPC code when the modulation scheme is 1024QAM.
[0415] In Fig. 104, the columns of NUC_lk_r represent
values of u#k of the coordinates of the signal points of
1D NUC used when the modulation scheme is 1024QAM and the
code rate of the LDPC code is r.
[0416] u#k represents a real part Re(zq) and an
imaginary part Im(zq) of the complex number as a
coordinate of the signal point zq of 1D NUC.
[0417] Fig. 105 is a diagram showing a relationship
between the real part Re(zq) and the imaginary part
Im(zci) of the complex number as the coordinate of the
signal point zq of 1D NUC corresponding to the symbol y.
[0418] The 10bit symbol y of 1024QAM is represented
by yo, q, yi, qf Y2, GI, Y3, q, y4, (If Y5, q, Y6, q, Y7, cif Y8, q and
y9, q from the head bit (Most Significant Bit).
[0419] Fig. 105A represents a corresponding
relationship between odd numbered 5bit symbol y; yo, q, y2,
q, y4, q, y6, q and 176, q and the u#k representing the real
part Re(zq) of (the coordinate) of the signal point zq
CA 02924874 20160318
corresponding to the symbol y.
[0420] Fig. 105B represents a corresponding
relationship between even numbered 5bit symbol y; i, q,
Y3, q, ys, q, 177, q and y9, q and the u#k representing the
5 imaginary part Im(zq) of (the coordinate) of the signal
point zq corresponding to the symbol y.
[0421] If the 10bit symbol y = (yo, q, yi, q, y2, q, y3, q,
Y4, qf Y5, q, Y6, qr Y7, qf Y8, q and Yg, q) of 1024QAM is, for
example, (0, 0, 1, 0, 0, 1, 1, 1, 0, 0), oddnumbered 5
10 bits (yo, q, y2, q, 174, q, y6, q and y6, q) are (0, 1, 0, 1, 0)
and the evennumbered 5 bits (y2, q, y3, q, y5, q, y7, q and y9,
q) are (0, 0, 1, 1, 0).
[0422] In Fig. 105A, the oddnumbered 5 bits (0, 1, 0,
1, 0) are correlated with u3, and therefore, the real
15 part Re(zq) of the signal point zq corresponding to the
symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3.
[0423] In Fig. 105B, the evennumbered 5 bits (0, 1, 0,
1, 0) are correlated with ull, and therefore, the
imaginary part Im(zq) of the signal point zq corresponding
20 to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is ull.
[0424] If the code rate r of the LDPC code, for
example, is 7/15, according to Fig. 104 as described
above, as to 1D NUC (NUC_1k_7/15) where the modulation
scheme is 1024QAM and code rate r is the LDPC coding is
25 7/15, u3 is 1.04 and ull is 6.28.
[0425] Accordingly, in the real part Re(zq) of the
signal point zq corresponding to the symbol y = (0, 0, 1,
0, 0, 1, 1, 1, 0, 0), u3 = 1.04, in Im(zq), ull = 6.28.
CA 02924874 20160318
91
As a result, the coordinate of the signal point zq
corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1,
0, 0) is represented by 1.04 + 6.28i.
[0426] The signal points of 1D NUC are arranged in a
matrix on a straight line parallel to the I axis or a
straight line parallel to the Qaxis. However, spaces
between signal points are not constant. Upon transmission
of (data mapped to) the signal points, the average power
of the signal points on the constellation is normalized.
Normalization is performed by multiplying each signal
point zq on the constellation by a reciprocal 1/ (rPave) of
a square root rPave Of a root mean square value Pave, where
the root mean square of absolute values of (coordinates
of) all signal points on the constellation is represented
by Pave.
[0427] By the constellations illustrated in Fig. 92 to
Fig. 105, it can confirm that good error rates are
obtained.
[0428]
<Block interleaver 25>
[0429] Fig. 106 is a block diagram showing a
configuration example of a block interleaver 25 in Fig. 9.
[0430] The block interleaver 25 has a storage region
called as Part 1 and a storage region called as Part 2.
[0431] The Parts 1 and 2 store one bit in a row
(horizontal) direction. The number C of columns that are
the storage regions for storing the predetermined number
of bits in a column (vertical) direction are arranged.
CA 02924874 20160318
92
The number C is equal to the number of bits m of the
symbols.
[0432] When the number of bits that are stored by the
part 1 columns in the column direction (hereinafter, also
referred to as a partcolumn length) is expressed as R1,
and the part column length of the part 2 columns is
expressed as R2, (R1 + R2) x C equals to the code length
N of the target of the LDPC code to be blockinterleaved
(in the present embodiment, 64800 bits, or 16200 bits).
[0433] In addition, a part column length R1 is equal
to a multiple of 360 bits that are the number of columns
P being the unit of the cyclic structure. A part column
length R2 is equal to a remainder when the sum of the
part column length R1 of the part 1 and the part column
length R2 of the part 2 (hereinafter also referred to as
a column length) R1 + R2 is divided by 360 bits that are
the number of columns P being the unit of the cyclic
structure.
[0434] Here, the column length R1 + R2 is equal to a
value when the code length N of the LDPC code to be
blockinterleaved is divided by the bit number.m of
symbols.
[0435] For example, concerning the LDPC code whose
code length N is 16200 bits, if 16QAM is used as the
modulation method, the bit number m of symbols is four
bits, and the column length R1 + R2 will be 4050 (
16200/4) bits.
[0436] Furthermore, as the remainder when the column
CA 02924874 20160318
93
length Rl + R2 = 4050 is divided by 360 bits that are the
number of columns P being the unit of the cyclic
structure is 90, the part column length R2 will be 90
bits.
[0437] The part column length Rl of the part 1 will be
R1 + R2  R2 = 405090 = 3960 bits.
[0438] Fig. 107 is a diagram showing the column number
C of the parts 1 and 2 for a combination of the code
length N and the modulation scheme and the part column
lengths (row numbers) R1 and R2.
[0439] Fig. 107 shows the column number C of the parts
1 and 2 and the part column lengths R1 and R2 for a
combination of the code length N of the LDPC code being
16200 bits and 64800 bits and the modulation schemes of
16QAM, 64QAM, 256QAM, and 1024QAM.
[0440] Fig. 108 is a diagram for illustrating a block
interleave performed in the block interleaver 25.
[0441] The block interleaver 25 preforms the block
interleave to the parts 1 and 2 by writing and reading
the LDPC code.
[0442] In other words, in the block interleave, as
shown in Fig. 108A, the code bits of the LDPC code of one
code word are written from a top to down direction
(column direction) of the part 1 columns and from left to
right directions of the columns.
[0443] When writing of the code bits to the bottom of
the rightmost column of the part 1 columns (Cth column)
is finished, the rest of the code bits is written from a
CA 02924874 20160318
94
top to down direction (column direction) of the part 2
columns and from left to right directions of the columns.
[0444] After that, when the writing of the code bits
to the bottom of the rightmost column of the part 2
columns (Cth column) is finished, as shown in Fig. 108B,
the code bits are read in a C  m bit unit in the row
direction from all first columns of the number C of the
part 1.
[0445] The code bits for all columns of the number C
of the part 1 are read sequentially to the lower rows.
When the reading is finished for the last Rlth row, the
code bits are read in a C = m bit unit in the row
direction from all first columns of the number C of the
part 2.
[0446] The code bits for all columns of the number C
of the part 2 are read sequentially to the lower rows for
the last R2th row.
[0447] As described above, the code bits read from the
parts 1 and 2 for mbit unit are supplied to the mapper
117 (Fig. 8) as the symbols.
[0448]
<Groupwise interleave>
[0449]
Fig. 109 is a diagram for illustrating groupwise
interleave performed in the groupwise interleaver 24 in
Fig. 9.
[0450] In the groupwise interleave, the LDPC code for
one code word is divided into a 360bit unit equal to the
CA 02924874 20160318
number of columns P being the unit of the cyclic
structure from the beginning. One division, i.e., 360bit,
is considered as a bit group. The LDPC code of one code
word is interleaved in a bit group unit according to a
5 predetermined pattern (hereinafter also referred to as a
GW pattern).
[0451] Here, the i + lth bit group from the beginning
at the time of dividing the one code word of the LDPC
code to the bit group is hereinafter also described as a
10 bit group i.
[0452] For example, the LDPC code whose code length N
of 1800 bits is divided into 5 (= 1800/360) bit groups: 0,
1, 2, 3, 4. Further, for example, the LDPC codes whose
code length N of 16200 bits is divided into 45 (=
15 16200/360) bit groups: 0, 1, ..., 44. The LDPC whose code
length N of 64800 bits is divided into 180 (= 64800/360)
bit groups: 0, 1, ..., 179.
[0453] In the following, the GW pattern will be
represented by a sequence of numbers representing the bit
20 groups. For example, for the LDPC code whose code length
N of 1800 bits, the GW pattern 4, 2, 0, 3, 1 represents
that a sequence of the bit groups 0, 1, 2, 3, 4, is
interleaved (changed) to a sequence of the bit groups 4,
2, 0, 3, 1.
25 [0454] The GW pattern can be set for, at least, each
code length N of the LDPC code.
[0455] Fig. 110 is a diagram showing a first example
of a GW pattern for the LDPC code whose code length N of
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96
64k bits.
[0456] According to the GW pattern in Fig. 110, a
sequence of the bit groups 0 to 179 having the LDPC code
of 64k bits is interleaved to a sequence of a bit group
of
178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14,
165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119,
41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98,
43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112,
124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146,
34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135,
81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84,
32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73,
152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173,
153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174,
88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114,
154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15,
147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16,
175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8.
[0457] Fig. 111 is a diagram showing a second example
of the GW pattern for the LDPC code whose code length N
of 64k bits.
[0458] According to the GW pattern in Fig. 111, a
sequence of the bit groups 0 to 179 having the LDPC code
of 64k bits is interleaved to a sequence of a bit group
of
32, 84, 49, 56, 54, 99, 76, 178, 65, 48, 87, 125, 121, 51,
130, 70, 90, 2, 73, 123, 174, 20, 46, 31, 3, 89, 16, 66,
CA 02924874 20160318
97
30, 158, 19, 137, 0, 12, 153, 147, 91, 33, 122, 57, 36,
129, 135, 24, 168, 141, 52, 71, 80, 96, 50, 44, 10, 93,
81, 22, 152, 29, 41, 95, 172, 107, 173, 42, 144, 63, 163,
43, 150, 60, 69, 58, 101, 68, 62, 9, 166, 78, 177, 146,
118, 82, 6, 21, 161, 4, 169, 18, 106, 176, 162, 175, 117,
8, 128, 97, 100, 111, 23, 114, 45, 34, 165, 28, 59, 131,
143, 83, 25, 61, 105, 35, 104, 156, 38, 102, 85, 142, 164,
26, 17, 160, 109, 40, 11, 47, 72, 124, 79, 7, 136, 159,
67, 1, 5, 14, 94, 110, 98, 145, 75, 149, 119, 74, 55, 155,
115, 113, 53, 151, 39, 92, 171, 154, 179, 139, 148, 103,
86, 37, 27, 77, 157, 108, 167, 13, 127, 126, 120, 133,
138, 134, 140, 116, 64, 88, 170, 132, 15, 112.
[0459] Fig. 112 is a diagram showing a third example
of the GW pattern for the LDPC code whose code length N
of 64k bits.
[0460] According to the GW pattern in Fig. 112, a
sequence of the bit groups 0 to 179 having the LDPC code
of 64k bits is interleaved to a sequence of a bit group
of
90, 64, 100, 166, 105, 61, 29, 56, 66, 40, 52, 21, 23, 69,
31, 34, 10, 136, 94, 4, 123, 39, 72, 129, 106, 16, 14,
134, 152, 142, 164, 37, 67, 17, 48, 99, 135, 54, 2, 0,
146, 115, 20, 76, 111, 83, 145, 177, 156, 174, 28, 25,
139, 33, 128, 1, 179, 45, 153, 38, 62, 110, 151, 32, 70,
101, 143, 77, 130, 50, 84, 127, 103, 109, 5, 63, 92, 124,
87, 160, 108, 26, 60, 98, 172, 102, 88, 170, 6, 13, 171,
97, 95, 91, 81, 137, 119, 148, 86, 35, 30, 140, 65, 82,
49, 46, 133, 71, 42, 43, 175, 141, 55, 93, 79, 107, 173,
CA 02924874 20160318
98
78, 176, 96, 73, 57, 36, 44, 154, 19, 11, 165, 58, 18, 53,
126, 138, 117, 51, 113, 114, 162, 178, 3, 150, 8, 22, 131,
157, 118, 116, 85, 41, 27, 80, 12, 112, 144, 68, 167, 59,
75, 122, 132, 149, 24, 120, 47, 104, 147, 121, 74, 155,
125, 15, 7, 89, 161, 163, 9, 159, 168, 169, 158.
[0461] Fig. 113 is a diagram showing a fourth example
of the GW pattern for the LDPC code whose code length N
of 64k bits.
[0462] According to the GW pattern in Fig. 113, a
sequence of the bit groups 0 to 179 having the LDPC code
of 64k bits is interleaved to a sequence of a bit group
of
0, 154, 6, 53, 30, 97, 105, 121, 12, 156, 94, 77, 47, 78,
13, 19, 82, 60, 85, 162, 62, 58, 116, 127, 48, 177, 80,
138, 8, 145, 132, 134, 90, 28, 83, 170, 87, 59, 49, 11,
39, 101, 31, 139, 148, 22, 37, 15, 166, 1, 42, 120, 106,
119, 35, 70, 122, 56, 24, 140, 136, 126, 144, 167, 29,
163, 112, 175, 10, 73, 41, 99, 98, 107, 117, 66, 17, 57,
7, 151, 51, 33, 158, 141, 150, 110, 137, 123, 9, 18, 14,
71, 147, 52, 164, 45, 111, 108, 21, 91, 109, 160, 74, 169,
88, 63, 174, 89, 2, 130, 124, 146, 84, 176, 149, 159, 155,
44, 43, 173, 179, 86, 168, 165, 95, 135, 27, 69, 23, 65,
125, 104, 178, 171, 46, 55, 26, 75, 129, 54, 153, 114,
152, 61, 68, 103, 16, 40, 128, 3, 38, 72, 92, 81, 93, 100,
34, 79, 115, 133, 102, 76, 131, 36, 32, 5, 64, 143, 20,
172, 50, 157, 25, 113, 118, 161, 142, 96, 4, 67.
[0463] Fig. 114 is a diagram showing a first example
of a GW pattern for the LDPC code whose code length N of
CA 02924874 20160318
99
16k bits.
[0464] According to the GW pattern in Fig. 114, a
sequence of the bit groups 0 to 44 having the LDPC code
of 16k bits is interleaved to a sequence of a bit group
of
15, 23, 9, 19, 5, 29, 4, 25, 8, 41, 13, 2, 22, 12, 26, 6,
37, 17, 38, 7, 20, 1, 39, 34, 18, 31, 10, 44, 32, 24, 14,
42, 11, 30, 27, 3, 36, 40, 33, 21, 28, 43, 0, 16, 35.
[0465] Fig. 115 is a diagram showing a second example
of the GW pattern for the LDPC code whose code length N
of 16k bits.
[0466] According to the GW pattern in Fig. 115, a
sequence of the bit groups 0 to 44 having the LDPC code
of 16k bits is interleaved to a sequence of a bit group
of
6, 14, 24, 36, 30, 12, 33, 16, 37, 20, 21, 3, 11, 26, 34,
5, 7, 0, 1, 18, 2, 22, 19, 9, 32, 28, 27, 23, 42, 15, 13,
17, 35, 25, 8, 29, 38, 40, 10, 44, 31, 4, 43, 39, 41.
[0467] Fig. 116 is a diagram showing a third example
of the GW pattern for the LDPC code whose code length N
of 16k bits.
[0468] According to the GW pattern in Fig. 116, a
sequence of the bit groups 0 to 44 having the LDPC code
of 16k bits is interleaved to a sequence of a bit group
of
21, 0, 34, 5, 16, 7, 1, 25, 9, 24, 19, 11, 6, 15, 39, 38,
42, 30, 18, 14, 13, 23, 20, 33, 3, 10, 4, 8, 26, 27, 41,
40, 31, 2, 35, 37, 43, 22, 17, 12, 29, 36, 28, 32, 44.
CA 02924874 20160318
100
[0469] Fig. 117 is a diagram showing a fourth example
of the GW pattern for the LDPC code whose code length N
of 16k bits.
[0470] According to the GW pattern in Fig. 117, a
sequence of the bit groups 0 to 44 having the LDPC code
of 16k bits is interleaved to a sequence of a bit group
of
15, 25, 9, 27, 5, 38, 13, 10, 19, 16, 28, 1, 36, 0, 11,
17, 32, 35, 7, 26, 14, 21, 6, 4, 23, 22, 3, 18, 20, 24,
30, 12, 37, 2, 40, 8, 33, 29, 31, 34, 41, 42, 43, 44, 39.
[0471] For the groupwise interleave, the GW pattern
is set for each combination of the code rate r of the
LDPC code and the modulation scheme other than the code
length N of the LDPC code, thereby improving the bit
error rate for each combination.
[0472] However, if the GW pattern is set individually
for all combination of the code length N and code rate r
is the LDPC code and the modulation scheme, the GW
pattern should be changed every time the LDPC code and
the modulation scheme used in the transmitting device 11
are changed. As a result, the processing becomes complex.
[0473] For the groupwise interleave, for example, the
code rate r of the LDPC code is classified into a low
rate (e.g., 6/15, 7/15, 8/15, 9/15) and a high rate (e.
g., 10/15, 11/15, 12/15, 13/15). The GW pattern can be
set for each combination of the code length N of the LDPC
code of 16k bits or 64k bits, the code rate r of the LDPC
code of the low rate or the high rate, and the modulation
CA 02924874 20160318
101
scheme of 16QAM, 64QAM, 256QAM or 1024QAM.
[0474] When the abovedescribed combination of the
code length N, the code rate r and the modulation scheme
is expressed by (the code length N, the code rate r, the
modulation scheme), 16 combinations of the code length N,
the code rate r and the modulation scheme can be
supposed: (16k, low rate, 16QAM), (16k, low rate, 64QAM),
(16k, low rate, 256QAM), (16k, low rate, 1024QAM), (16k,
high rate, 16QAM), (16k, high rate, 64QAM), (16k, high
rate, 256QAM), (16k, high rate, 1024QAM), (64k, low rate,
16QAM), (64k, low rate, 64QAM), (64k, low rate, 256QAM),
(64k, low rate, 1024QAM), (64k, high rate, 16QAM), (64k,
high rate, 64QAM), (64k, high rate, 256QAM) and (64k,
high rate, 1024QAM), for example.
[0475] For the combination of code length N of the
LDPC code set to 64k: (64k, low rate, 16QAM), (64k, low
rate, 64QAM), (64k, low rate, 256QAM), (64k, low rate,
1024QAM), (64k, high rate, 16QAM), (64k, high rate,
64QAM), (64k, high rate, 256QAM) and (64k, high rate,
1024QAM), the GW pattern that most improves the error
rate can be applied among the four GW patterns shown in
Fig. 110 to Fig. 113.
[0476] For example, the GW pattern in Fig. 110 can be
applied to the combination (64k, high rate, 16QAM), the
GW pattern in Fig. 111 can be applied to the combination
(64k, low rate, 64QAM), the GW pattern in Fig. 112 can be
applied to the combination (64k, high rate, 256QAM), the
GW pattern in Fig. 113 can be applied to the combination
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102
(64k, low rate, 1024QAM), respectively.
[0477] For the combination of code length N of the
LDPC code is set to 16k: (16k, low rate, 16QAM), (16k,
low rate, 64QAM), (16k, low rate, 256QAM), (16k, low rate,
1024QAM), (16k, high rate, 16QAM), (16k, high rate,
64QAM), (16k, high rate, 256QAM) and (16k, high rate,
1024QAM), the GW pattern that most improves the error
rate can be applied among the four GW patterns shown in
Fig. 114 to Fig. 117.
[0478] For example, the GW pattern in Fig. 114 can be
applied to the combination (16k, low rate, 16QAM), the GW
pattern in Fig. 115 can be applied to the combination
(16k, highrate, 64QAM), the GW pattern in Fig. 116 can
be applied to the combination (16k, low rate, the 256QAM),
and the GW pattern in Fig. 117 can be applied to the
combination (16k, high rate, in 1024QAM), respectively.
[0479] According to simulation by the present
inventors, for the GW pattern in Fig. 110, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the second new
LDPC code of (64k, 10/15), the first new LDPC code of
(64k, 11/15), the second new LDPC code of (64k, 12/15)
and the first new LDPC code of (64k, 13/15) and the
modulation scheme 16QAM of which the constellation is
illustrated in Fig. 92 to Fig. 105.
[0480] For the GW pattern in Fig. 111, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the second new
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103
LDPC code of (64k, 6/15), the first new LDPC code of (64k,
7/15), the second new LDPC code of (64k, 8/15) and the
first new LDPC code of (64k, 9/15) and the modulation
scheme 64QAM of which the constellation is illustrated in
Fig. 92 to Fig. 105.
[0481] For the GW pattern in Fig. 112, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the second new
LDPC code of (64k, 10/15), the first new LDPC code of
(64k, 11/15), the second new LDPC code of (64k, 12/15)
and the first new LDPC code of (64k, 13/15) and the
modulation scheme 256QAM of which the constellation is
illustrated in Fig. 92 to Fig. 105.
[0482] For the GW pattern in Fig. 113, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the second new
LDPC code of (64k, 6/15), the first new LDPC code of (64k,
7/15), the second new LDPC code of (64k, 8/15) and the
first new LDPC code of (64k, 9/15) and the modulation
scheme 1024QAM of which the constellation is illustrated
in Fig. 92 to Fig. 105.
[0483] For the GW pattern in Fig. 114, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the first new
LDPC code of (16k, 6/15), the second new LDPC code of
(16k, 7/15), the first new LDPC code of (16k, 8/15) and
the second new LDPC code of (16k, 9/15) and the
modulation scheme 16QAM of which the constellation is
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104
illustrated in Fig. 92 to Fig. 105.
[0484] For the GW pattern in Fig. 115, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the first new
LDPC code of (16k, 10/15), the second new LDPC code of
(16k, 11/15), the first new LDPC code of (16k, 12/15) and
the second new LDPC code of (16k, 13/15) and the
modulation scheme 64QAM of which the constellation is
illustrated in Fig. 92 to Fig. 105.
[0485] For the GW pattern in Fig. 116, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the first new
LDPC code of (16k, 6/15), the second new LDPC code of
(16k, 7/15), the first new LDPC code of (16k, 8/15) and
the second new LDPC code of (16k, 9/15) and the
modulation scheme 256QAM of which the constellation is
illustrated in Fig. 92 to Fig. 105.
[0486] For the GW pattern in Fig. 117, it was
confirmed that it is especially possible to achieve good
error rate in the combination of each of the first new
LDPC code of (16k, 10/15), the second new LDPC code of
(16k, 11/15), the first new LDPC code of (16k, 12/15) and
the second new LDPC code of (16k, 13/15) and the
modulation scheme 1024QAM of which the constellation is
illustrated in Fig. 92 to Fig. 105.
[0487]
<Configuration Example of Receiving Apparatus 12>
[0488]
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105
Fig. 118 is a block diagram showing a configuration
example of the receiving device 12 in Fig. 7.
[0489] An OFDM operation 151 receives the OFDM signal
from the transmitting device 11 (Fig. 7) and performs
signal processing of the OFDM signal. The data obtained
by the signal processing by the OFDM operation 151 is
supplied to a frame management 152.
[0490] The frame management 152 performs processing of
the frame (frame interpretation) configured of the data
supplied from the OFDM operation 151 and supplies the
signal of the target data and the signal of the control
data obtained as a result to frequency deinterleavers 161
and 153.
[0491] The frequency deinterleaver 153 performs
frequency deinterleave in a symbol unit for the data from
the frame management 152 to supply to a demapper 154.
[0492] The demapper 154 demaps (performs signal point
constellation decoding) the data (data on the
constellation) from the frequency deinterleaver 153 based
on the signal arrangement (constellation) determined by
the orthogonal modulation performed at the transmitting
device 11 to perform the orthogonal demodulation thereof
and supplies the data ((likelihood) of the LDPC code)
obtained as a result to a LDPC decoder 155.
[0493] The LDPC decoder 155 performs LDPC decoding of
the LDPC code from the demapper 154 and supplies the LDPC
target data (herein, a BCH code) obtained as a result to
a BCH decoder 156.
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[0494] The BCH decoder 156 performs BCH decoding of the
LDPC target data from the LDPC decoder 155 and outputs
the control data (signaling) obtained as a result.
[0495] On the other hand, the frequency deinterleaver
161 performs the frequency deinterleave in a symbol unit
for the data from the frame management 152 to supply to a
SISO/MISO decoder 162.
[0496] The SISO/MISO decoder 162 performs timespace
decoding of the data from the frequency deinterleaver 161
to supply to a time deinterleaver 163.
[0497] The time deinterleaver 163 performs time
deinterleave of the data from the SISO/MISO decoder 162
in a symbol unit to supply to a demapper 164.
[0498] The demapper 164 demaps (performs signal point
constellation decoding) the data (data on the
constellation) from the time deinterleaver 163 based on
the signal point arrangement (constellation) determined
by the orthogonal modulation performed at the
transmitting device 11 to perform the orthogonal
demodulation thereof and supplies the data obtained as a
result to a bit deinterleaver 165.
[0499] The bit deinterleaver 165 performs bit
deinterleave of the data from the demapper 164 and
supplies (the likelihood of) the LDPC code obtained as a
result to an LDPC decoder 166.
[0500] The LDPC decoder 166 performs the LDPC decoding
of the LDPC code from the bit deinterleaver 165 and
supplies the LDPC target data (herein, the BCH code)
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obtained as a result to a BCH decoder 167.
[0501] The BCH decoder 167 performs the BCH decoding
of the LDPC target data from the LDPC decoder 155 and
supplies the data obtained as a result to a BB
descrambler 168.
[0502] The BB descrambler 168 applies a BB descramble
to the data from the BCH decoder 167 and supplies the
data obtained as a result to a null deletion 169.
[0503] The null deletion 169 deletes the null inserted
by the padder 112 in Fig. 8 from the data from the BB
descrambler 168 and supplies the same to a demultiplexer
170.
[0504] The demultiplexer 170 separates one or more
streams (target data) multiplexed into the data from the
null deletion 169 and outputs the same as output streams.
[0505] The receiving device 12 may be configured
without including some of the blocks shown in Fig. 48. In
other words, if the transmitting device 11 (Fig. 8) is
configured without including the time interleaver 118,
the SISO/MISO encoder 119, the frequency interleaver 120,
and frequency interleaver 124, for example, the receiving
device 12 may be configured without including the time
deinterleaver 163, the SISO/MISO decoder 162, the
frequency deinterleaver 161, and frequency deinterleaver
153 that are the blocks corresponding to the time
interleaver 118, the SISO/MISO encoder 119, the frequency
interleaver 120, and frequency interleaver 124 of the
transmitting device 11, respectively.
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[0506]
<Configuration Example of Bit Deinterleaver>
[0507] Fig. 119 is a block diagram showing a
configuration example of the bit deinterleaver 165 in Fig.
118.
[0508] The bit deinterleaver 165 configured of a block
deinterleaver 54 and a groupwise deinterleaver 55 and
performs the (bit) deinterleave of the symbol bit of the
data from the demapper 164 (Fig. 118).
[0509] That is to say, the block deinterleaver 54
performs a block deinterleave (an inverse process of
block interleave) corresponding to the block interleave
performed by the block interleaver 25 in Fig. 9, that is
to say, the block deinterleave to return the positions of
(the likelihood of) the code bits of the LDPC code
interchanged by the block interleave to the original
positions to the symbol bit of the symbol from the
demapper 164 and supplies the LDPC code obtained as a
result to the groupwise deinterleaver 55.
[0510] The groupwise deinterleaver 55 performs group
wise deinterleave (inverse process of the groupwise
interleave) corresponding to the groupwise interleave
performed by the groupwise interleaver 24 in Fig. 9,
that is to say, the groupwise deinterleave to return the
code bits of the LDPC code of which arrangement is
changed by the groupwise interleave illustrated in Fig.
110 to Fig. 117 in a bit group unit are rearranged in a
bit group unit to the original arrangement to the LDPC
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code from the block deinterleaver 54.
[0511] If the parity interleave, the groupwise
interleave, and the block interleave are applied to the
LDPC code supplied from the demapper 164 to the bit
deinterleaver 165, the bit deinterleaver 165 may perform
all of parity deinterleave (inverse process of the parity
interleave, that is to say, the parity deinterleave to
return the code bits of the LDPC code, the arrangement of
which is changed by the parity interleave, to the
original arrangement) corresponding to the parity
interleave, the block deinterleave corresponding to the
block interleave, and the groupwise deinterleave
corresponding to the groupwise interleave.
[0512] Note that the bit deinterleaver 165 in Fig. 119
includes the block deinterleaver 54 that performs the
block deinterleave corresponding to the block interleave,
and the groupwise deinterleaver 55 that performs the
groupwise deinterleave corresponding to the groupwise
interleave, but includes no block for performing the
parity deinterleave corresponding to the parity
interleave, and the parity deinterleave is not performed.
[0513] Therefore, the LDPC code, to which the block
deinterleave and the groupwise deinterleave are applied
and the parity deinterleave is not applied, is supplied
from (the groupwise deinterleaver 55 of) the bit
deinterleaver 165 to the LDPC decoder 166.
[0514] The LDPC decoder 166 performs the LDPC decoding
of the LDPC code from the bit deinterleaver 165 using the
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conversion parity check matrix obtained by at least
applying the column permutation corresponding to the
parity interleave to the parity check matrix H used by
the LDPC encoder 115 in Fig. 8 in the LDPC encoding and
outputs the data obtained as a result as a decoding
result of the LDPC target data.
[0515] Fig. 120 is a flowchart illustrating processes
performed by the demapper 164, the bit deinterleaver 165,
and the LDPC decoder 166 in Fig. 119.
[0516] At step S111, the demapper 164 demaps the data
from the time deinterleaver 163 (data mapped onto the
signal point on the constellation) to perform the
orthogonal demodulation and supplies the same to the bit
deinterleaver 165, then the process shifts to S112.
[0517] At step S112, the bit deinterleaver 165
performs the deinterleave (bit deinterleave) from the
demapper 164 and the process shifts to step S113.
[0518] . That is to say, at step S112, the block
deinterleaver 54 performs in the bit deinterleaver 165
the block deinterleave of the data (symbol) from the
demapper 164 and supplies the code bit of the LDPC code
obtained as a result to the groupwise deinterleaver 55.
[0519] The groupwise deinterleaver 55 performs the
groupwise deinterleave to the LDPC code from the block
deinterleaver 54 and supplies (the likelihood of) the
LDPC code obtained as a result to the LDPC decoder 166.
[0520] At step S113, the LDPC decoder 166 performs the
LDPC decoding of the LDPC code from the groupwise
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deinterleaver 55 using the conversion parity check matrix
H used by the LDPC encoder 115 in Fig. 8 in the LDPC
encoding, i.e., using the conversion parity check matrix
obtained by at least applying the column permutation
corresponding to the parity interleave to the parity
check matrix H and outputs the data obtained as a result
to the BCH decoder 167 as the decoding result of the LDPC
target data.
[0521] Although the block deinterleaver 54, which
performs the block deinterleave, and the groupwise
deinterleaver 55, which performs the groupwise
deinterleave, are separately formed also in Fig. 119 as
in Fig. 9 for convenience of description, the block
deinterleaver 54 and the groupwise deinterleaver 55 may
be integrally formed.
[0522]
<LDPC decoding>
[0523] The LDPC decoding performed by the LDPC decoder
166 in Fig. 188 is further described.
[0524] The LDPC decoder 166 in Fig. 118 performs the
LDPC decoding of the LDPC code to which the block
deinterleave and the groupwide deinterleave are applied
and the parity interleave is not applied from the group
wise deinterleaver 55 using the conversion parity check
matrix obtained by at least applying the column
permutation corresponding to the parity interleave to the
parity check matrix H used by the LDPC encoder 115 in Fig.
8 in the LDPC encoding as described above.
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[0525] Herein, the LDPC decoding capable of limiting
an operation frequency within a sufficiently feasible
range while limiting a circuit size by performing the
LDPC decoding using the conversion parity check matrix is
conventionally suggested (refer to Patent No. 4224777,
for example).
[0526] Firstly, the LDPC decoding using the conversion
parity check matrix conventionally suggested is first
described with reference to Fig. 121 to Fig. 124.
[0527] Fig. 121 illustrates an example of the parity
check matrix H of the LDPC code whose code length N is 90
and code rate is 2/3.
[0528] In Fig. 121 (also in Fig. 122 and Fig. 123 to
be described later), 0 is represented by a period (.).
[0529] In the parity check matrix H in Fig. 121, the
parity matrix has the stepwise structure.
[0530] Fig. 122 illustrates a parity check matrix H'
obtained by applying the row permutation in equation (11)
and the column permutation in equation (12) to the parity
check matrix H in Fig. 121.
[0531]
Row permutation: 6s + t + first row > t + s + first row
(11)
[0532]
Column permutation: 6x + y + 61th row > 5y + x + 61th
row (12)
[0533] In equations (11) and (12), s, t, x, and y are
integers within a range satisfying 0 s < 5, 0 t < 6,
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0 ._. x < 5, and 0 __ t < 6, respectively.
[0534] According to the row permutation in equation
(11), it is permutated such that 1st, 7th, 13th, 19th,
' and 25th rows, which leave a remainder of 1 when divided
by 6, are made 1st, 2nd, 3rd, 4th, and 5th rows, and 2nd,
8th, 14th, 20th, and 26th rows, which leave a remainder
of 2 when divided by 6, are made 6th, 7th, 8th, 9th, and
10th rows, respectively.
[0535] Also, according to the column permutation in
equation (12), it is permutated such that 61st, 67th,
73rd, 79th, and 85th columns, which leave a remainder of
1 when divided by 6, are made 61st, 62nd, 63rd, 64th, and
65th columns, and 62nd, 68th, 74th, 80th, and 86th
columns, which leave a remainder of 2 when divided by 6,
are made 66th, 67th, 68th, 69th, and 70th columns,
respectively, for the 61st and subsequent columns (parity
matrix).
[0536] The matrix obtained by performing the row
permutation and the column permutation of the parity
check matrix H in Fig. 121 in this manner is the parity
check matrix H' in Fig. 1222.
[0537] Herein, the row permutation of the parity check
matrix H does not affect the arrangement of the code bits
of the LDPC code.
[0538] The column permutation in equation (12)
corresponds to the parity interleave when the information
length K, the number of columns P being the unit of the
cyclic structure, and the submultiple q (= M/P) of the
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parity length M (herein, 30) of the abovedescribed
parity interleave to interleave the K + qx + y + 1th
code bit to the position of the K + Py + x + 1th code
bit are set to 60, 5, and 6, respectively.
[0539] Accordingly, the parity check matrix H' in Fig.
122 is the conversion parity check matrix obtained by at
least applying the column permutation that the K + qx + y
+ 1th column is permutated with the K + Py + x + 1th
column of the parity check matrix H in Fig. 121
(hereinafter, appropriately referred to as the original
parity check matrix).
[0540] By multiplying the parity check matrix H' in
Fig. 122 by the LDPC code of the parity check matrix H in
Fig. 121 to which the same permutation as equation (12)
is applied, a 0 vector is output. That is to say, when a
row vector obtained by applying the column permutation in
equation (12) to the row vector c as the LDPC code (one
code word) of the original parity check matrix H is
represented as c', HcT becomes the 0 vector from the
nature of the parity check matrix, so that H'c'T naturally
becomes the 0 vector.
[0541] From above, the conversion parity check matrix
H' in Fig. 122 is the parity check matrix of the LDPC
code c' obtained by applying the column permutation in
equation (12) to the LDPC code c of the original parity
check matrix H.
[0542] Therefore, by applying the column permutation
in equation (12) to the LDPC code c of the original
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parity check matrix H, decoding (LDPC decoding) the LDPC
code c' after the column permutation using the conversion
parity check matrix H' in Fig. 122, and applying inverse
permutation in the column permutation in equation (12) to
the decoding result, it is possible to obtain the
decoding result similar to that in a case in which the
LDPC code of the original parity check matrix H is
decoded using the parity check matrix H.
[0543] Fig. 123 shows the conversion parity check
matrix H' in Fig. 122 with an interval between the units
of 5 x 5 matrix.
[0544] In Fig. 123, the conversion parity check matrix
H' is represented by a combination of the 5 x 5 (= P x P)
unit matrix, a matrix in which one or more 1 of the unit
matrix is set to 0 (hereinafter, appropriately referred
to as a quasiunit matrix), a matrix obtained by the
cyclic shift of the unit matrix or the quasiunit matrix
(hereinafter, appropriately referred to as a shift
matrix), a sum of two or more of the unit matrix, the
quasiunit matrix, and the shift matrix (hereinafter,
appropriately referred to as a sum matrix), and a 5 x 5 0
matrix.
[0545] It may be said that the conversion parity check
matrix H' in Fig. 123 is configured of the 5 x 5 unit
matrix, quasiunit matrix, shift matrix, sum matrix, and
0 matrix. Therefore, the 5 x 5 matrices (the unit matrix,
the quasiunit matrix, the shift matrix, the sum matrix,
and the 0 matrix) constitute the conversion parity check
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matrix H' are hereinafter appropriately referred to as
constitutive matrices. '
[0546] An architecture to simultaneously perform P
check node operations and P variable node operations may
be used to decode the LDPC code of the parity check
matrix represented byaPxPconstitutive matrix.
[0547] Fig. 124 is a block diagram showing a
configuration example of the decoding device, which
performs such decoding.
[0548] That is to say, Fig. 124 shows the
configuration example of the decoding device, which
decodes the LDPC code using the conversion parity check
matrix H' in Fig. 123 obtained by at least applying the
column permutation in equation (12) to the original
parity check matrix H in Fig. 121.
[0549] The decoding device in Fig. 124 is configured
of an edge data storage memory 300 configured of 6 FIFOs
3001 to 3006, a selector 301, which selects from the FIFOs
3001 to 3006, a check node calculation unit 302, two
cyclic shift circuits 303 and 308, an edge data storage
memory 304 configured of 18 FIFOs 3041 to 30418, a
selector 305, which selects from the FIFOs 3041 to 30418,
a received data memory 306, which stores received data, a
variable node calculation unit 307, a decoded word
calculation unit 309, a received data rearrangement unit
310, and a decoded data rearrangement unit 311.
[0550] A method of storing the data in the edge data
storage memories 300 and 304 is first described.
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[0551] The edge data storage memory 300 is configured
of six FIFOs 3001 to 3006, the number of which is obtained
by dividing the number of rows 30 of the conversion
parity check matrix H' in Fig. 123 by the number of rows
(the number of columns P being the unit of the cyclic
structure) 5 of the constitutive matrix. The FIFOs 300y
(y = 1, 2, ..., 6) are formed of a plurality of stages of
storage regions and messages corresponding to five edges,
the number of which is equal to the number of rows and
the number of columns of the constitutive matrix (the
number of columns P being the unit of the cyclic
structure), may be read and written at the same time from
and to the storage region of each stage. The number of
stages of the storage regions of the FIFO 300y is set to
nine being a maximum number of 1 in the row direction of
the conversion parity check matrix in Fig. 123 (Hamming
weight).
[0552] The data corresponding to the position of 1
from first to fifth rows of the conversion parity check
matrix H' in Fig. 123 (a message vi from the variable
node) is stored in the FIFO 3001 in a form closed up in a
horizontal direction for each row (ignoring 0). That is
to say, when the jth row ith column is represented as
(j, i), the data corresponding to the position of 1 of
the 5 x 5 unit matrix from (1, 1) to (5, 5) of the
conversion parity check matrix H' is stored in the
storage region of a first stage of the FIFO 3001. The
data corresponding to the position of 1 of the shift
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matrix from (1, 21) to (5, 25) of the conversion parity
check matrix H' (shift matrix obtained by the cyclic
shift of the 5 x 5 unit matrix by three rightward) is
stored in the storage region of a second stage. The data
is similarly stored in the storage regions of third to
eighth stages in association with the conversion parity
check matrix H'. Then, the data corresponding to the
position of 1 of the shift matrix (shift matrix obtained
by replacement of 1 in the first row of the 5 x 5 unit
matrix with 0 and the cyclic shift thereof by one
leftward) from (1, 86) to (5, 90) of the conversion
parity check matrix H' is stored in the storage region of
a ninth stage.
[0553] The data corresponding to the position of 1
from 6th to 10th rows of the conversion parity check
matrix H' in Fig. 123 is stored in the FIFO 3002. That is
to say, the data corresponding to the position of 1 of a
first shift matrix configuring the sum matrix from (6, 1)
to (10, 5) of the conversion parity check matrix H' (the
sum matrix obtained by summing the first shift matrix
obtained by the cyclic shift of the 5 x 5 unit matrix by
one rightward and a second shift matrix obtained by the
cyclic shift thereof by two rightward) is stored in the
storage region of a first stage of the FIFO 3002. The
data corresponding to the position of 1 of the second
shift matrix configuring the sum matrix from (6, 1) to
(10, 5) of the conversion parity check matrix H' is
stored in the storage region of a second stage.
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[0554] That is to say, as for the constitutive matrix
whose weight is 2 or larger, the data corresponding to
the position of 1 of the unit matrix, the quasiunit
matrix, and the shift matrix whose weight is 1 (message
corresponding to the edge belonging to the unit matrix,
the quasiunit matrix, or the shift matrix) when the
constitutive matrix is represented as the sum of a
plurality of the P x P unit matrix whose weight is 1, the
quasiunit matrix in which one or more of the elements 1
of the unit matrix is set to 0, and the shift matrix
obtained by the cyclic shift of the unit matrix or the
quasiunit matrix is stored in the same address (same
FIFO out of the FIFOs 3001 to 3006)=
[0555] The data is hereinafter stored in association
with the conversion parity check matrix H' also in the
storage regions of third to ninth stages.
[0556] The data is stored in association with the
conversion parity check matrix H' also in the FIFOs 3003
to 3006.
[0557] The edge data storage memory 304 is configured
of 18 FIFOs 3041 to 30418, the number of which is obtained
by dividing the number of columns 90 of the conversion
parity check matrix H' by the number of columns 5 of the
constitutive matrix (the number of columns P being the
unit of the cyclic structure). The FIFO 304x (x = 1,
2, ..., 18) is formed of a plurality of stages of storage
regions, and the messages corresponding to the five edges,
the number of which is the number of rows and the number
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of columns of the constitutive matrix (the number of
columns P being the unit of the cyclic structure) may be
simultaneously read and written from and to the storage
region of each stage.
[0558] In the FIFO 3041, the data corresponding to the
position of 1 from first to fifth columns of the
conversion parity check matrix H' in Fig. 123 (message uj
from the check node) is stored in a form closed up in a
vertical direction for each column (ignoring 0). That is
to say, the data corresponding to the position of 1 of
the 5 x 5 unit matrix from (1, 1) to (5, 5) of the
conversion parity check matrix H' is stored in the
storage region of a first stage of the FIFO 3041. The
data corresponding to the position of 1 of the first
shift matrix configuring the sum matrix from (6, 1) to
(10, 5) of the conversion parity check matrix H' (the sum
matrix obtained by summing the first shift matrix
obtained by the cyclic shift of the 5 x 5 unit matrix by
one rightward and the second shift matrix obtained by the
cyclic shift thereof by two rightward) is stored in the
storage region of the second stage. The data
corresponding to the position of 1 of a second shift
matrix configuring the sum matrix from (6, 1) to (10, 5)
of the conversion parity check matrix H' is stored in the
storage region of a third stage.
[0559] That is to say, as for the constitutive matrix
whose weight is 2 or larger, the data corresponding to
the position of 1 of the unit matrix, the quasiunit
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121
matrix, and the shift matrix whose weight is 1 (the
message corresponding to the edge belonging to the unit
matrix, the quasiunit matrix, or the shift matrix) when
the constitutive matrix is represented as the sum of a
plurality of the P x P unit matrix whose weight is 1, the
quasiunit matrix in which one or more of the elements 1
of the unit matrix is set to 0, and the shift matrix
obtained by the cyclic shift of the unit matrix or the
quasiunit matrix is stored in the same address (same
FIFO out of the FIFOs 3041 to 304n)=
[0560] Hereinafter, the data is stored in the storage
regions of fourth and fifth stages in association with
the conversion parity check matrix H'. The number of
stages of the storage regions of the FIFO 3041 is five
being the maximum number of the number of 1 in the row
direction from the first to fifth columns of the
conversion parity check matrix H' (Hamming weight).
[0561] The data is similarly stored in association
with the conversion parity check matrix H' in the FIFOs
3042 and 3043, the length (the number of stages) of which
is five. The data is similarly stored in association with
the conversion parity check matrix H' in the FIFOs 3044 to
30412, the length of which is three. The data is similarly
stored in association with the conversion parity check
matrix H' in the FIFOs 30413 to 30418, the length of which
is two.
[0562] Next, operation of the decoding device in Fig.
124 is described.
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122
[0563] The edge data storage memory 300 is configured
of the six FIFOs 3001 to 3006, selects the FIFO in which
the data is stored from the FIFOs 3001 to 3006 according
to information (matrix data) D312 indicating the row of
the conversion parity check matrix H' in Fig. 123 to
which five messages D311 supplied from the cyclic shift
circuit 308 in a preceding stage belong, and collectively
stores the five messages D311 in the selected FIFO in
sequence. When reading the data, the edge data storage
memory 300 reads five messages D3001 from the FIFO 3001 in
sequence to supply to the selector 301 in a subsequent
stage. The edge data storage memory 300 reads the message
also from the FIFOs 3002 to 3006 in sequence after
finishing reading the message from the FIFO 3001 to supply
to the selector 301.
[0564] The selector 301 selects the five messages from
the FIFO from which the data is currently read out of the
FIFOs 3001 to 3006 according to a select signal D301 and
supplies the same as a message D302 to the check node
calculation unit 302.
[0565] The check node calculation unit 302 configured
of five check node calculators 3021 to 3025 performs the
check node operation according to equation (7) using the
messages D302 (D3021 to D3025) supplied through the
selector 301 (message vi in equation (7)) and supplies
five messages D303 (D3031 to D3035) obtained as a result
of the check node operation (message uj in equation (7))
to the cyclic shift circuit 303.
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[0566] The cyclic shift circuit 303 performs the
cyclic shift of the five messages D3031 to D3035 obtained
by the check node calculation unit 302 based on
information (matrix data) D305 indicating the value by
which the cyclic shift of the original unit matrix (or
the quasiunit matrix) in the conversion parity check
matrix H' is performed to obtain the corresponding edge
and supplies a result to the edge data storage memory 304
as a message D304.
[0567] The edge data storage memory 304 is configured
of 18 FIFOs 3041 to 30418, selects the FIFO in which the
data is stored from the FIFOs 3041 to 30418 according to
the information D305 indicating the row of the conversion
parity check matrix H' to which the five messages D304
supplied from the cyclic shift circuit 303 in the
preceding stage belongs, and collectively stores the five
messages D304 in the selected FIFO in sequence. When
reading the data, the edge data storage memory 304 reads
the five messages D3061 in sequence from the FIFO 3041 to
supply to the selector 305 in the subsequent stage. The
edge data storage memory 304 reads the message in
sequence also from the FIFOs 3042 to 30418 after finishing
reading the data from the FIFO 3041 to supply to the
selector 305.
[0568] The selector 305 selects the five messages from
the FIFO from which the data is currently read out of the
FIFOs 3041 to 30418 according to a select signal D307 and
supplies the same to the variable node calculation unit
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307 and the decoded word calculation unit 309 as a
message D308.
[0569] On the other hand, the received data
rearrangement unit 310 rearranges an LDPC code D313
received through the communication channel 13
corresponding to the parity check matrix H in Fig. 121 by
the column permutation in equation (12) and supplies the
same to the received data memory 306 as received data
D314. The received data memory 306 calculates a received
LLR (log likelihood ratio) from the received data D314
supplied from the received data rearrangement unit 310 to
store and collectively supplies the five received LLRs to
the variable node calculation unit 307 and the decoded
word calculation unit 309 as received value D309.
[0570] The variable node calculation unit 307 is
configured of five variable node calculators 3071 to 3075,
performs the variable node operation according to
equation (1) using the messages D308 (D3081 to D3085)
supplied through the selector 305 (message uj in equation
(1) and the five received values D309 supplied from the
received data memory 306 (received value uoi in equation
(1)) and supplies messages D310 (D3101 to D3105) obtained
as a result of the operation (message vi in equation (1))
to the cyclic shift circuit 308.
[0571] The cyclic shift circuit 308 performs the
cyclic shift of the messages D3101 to D3105 calculated by
the variable node calculation unit 307 based on the
information indicating the value by which the cyclic
CA 02924874 20160318
125
shift of the original unit matrix (or the quasiunit
matrix) in the conversion parity check matrix H' is
performed to obtain the corresponding edge and supplies a
result to the edge data storage memory 300 as a message
D311.
[0572] Single decoding (variable node operation and
check node operation) of the LDPC code may be performed
by single round of the abovedescribed operation. The
decoding device in Fig. 124 decodes the LDPC code a
predetermined number of times, and then obtains a final
decoding result by the decoded word calculation unit 309
and the decoded data rearrangement unit 311 to output.
[0573] That is to say, the decoded word calculation
unit 309 is configured of five decoded word calculators
3091 to 3095, calculates the decoding result (decoded
word) based on equation (5) as a final stage of a
plurality of times of decoding using the five messages
D308 (D3081 to D3085) (message uj in equation (5)) output
by the selector 305 and the five received values D309
(received value un in equation (5)) supplied from the
received data memory 306, and supplies decoded data D315
obtained as a result to the decoded data rearrangement
unit 311.
[0574] The decoded data rearrangement unit 311 applies
the inverse permutation of the column permutation in
equation (12) to the decoded data D315 supplied from the
decoded word calculation unit 309, thereby rearranging an
order thereof and outputs the same as a final decoded
CA 02924874 20160318
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result D316.
[0575] As described above, by applying any one or both
of the row permutation and the column permutation to the
parity check matrix (original parity check matrix) and
converting the same to the parity check matrix
(conversion parity check matrix) represented by the
combination of the P x P unit matrix, the quasiunit
matrix in which one or more of the elements of 1 of the
unit matrix is set to 0, the shift matrix obtained by the
cyclic shift of the unit matrix or the quasiunit matrix,
the sum matrix obtained by summing a plurality of the
unit matrix, the quasiunit matrix, and the shift matrix,
and the P x P 0 matrix, that is to say, the combination
of the constitutive matrices, it becomes possible to
adopt the architecture to simultaneously perform the P
check node operations and the P variable node operations
as the decoding of the LDPC code where P is fewer than
the numbers of the columns and rows in the parity. When
it adopts the architecture to simultaneously perform the
P check node operations and the P variable node
operations as the decoding of the LDPC code where P is
fewer than the numbers of the columns and rows in the
parity check matrix, the operation frequency may be
limited within the feasible range to perform a great
number of times of repetitive decoding, as compared to a
case that the node operations are performed at the same
time for the same numbers of the numbers of the columns
and rows in the parity check matrix.
CA 02924874 20160318
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[0576] The LDPC decoder 166, which configures the
receiving device 12 in Fig. 118, performs the LDPC
decoding by simultaneously performing the P check node
operations and the P variable node operations as is the
case with the decoding device in Fig. 124.
[0577] That is to say, in order to simplify the
description, supposing that the parity check matrix of
the LDPC code output by the LDPC encoder 115 configuring
the transmitting device 11 in Fig. 8 is the parity check
matrix H in which the parity matrix has the stepwise
structure illustrated in Fig. 121, for example, the
parity interleaver 23 of the transmitting device 11
performs the parity interleave to interleave the K + qx +
y + 1th code bit to the position of the K + Py + x + 1
th code bit by setting the information length K, the
number of columns being the unit of the cyclic structure,
and the submultiple q (= M/P) of the parity length M to
60, 5, and 6, respectively.
[0578] The parity interleave corresponds to the column
permutation in equation (12) as described above, so that
the LDPC decoder 166 is not required to perform the
column permutation in equation (12).
[0579] Therefore, in the receiving device 12 in Fig.
118, as described above, the LDPC code to which the
parity deinterleave is not applied, that is to say, the
LDPC code in a state in which the column permutation in
equation (12) is performed is supplied from the column
twist deinterleaver 55 to the LDPC decoder 166, and the
CA 02924874 20160318
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LDPC decoder 166 performs the process similar to that of
the decoding device in Fig. 124 except that this does not
perform the column permutation in equation (12).
[0580] That is to say, Fig. 125 shows a configuration
example of the LDPC decoder 166 in Fig. 118.
[0581] In Fig. 125, the LDPC decoder 166 is configured
as the decoding device in Fig. 124 except that the
received data rearrangement unit 310 in Fig. 124 is not
provided, and this performs the process similar to that
of the decoding device in Fig. 124 except that the column
permutation in equation (12) is not performed, so that
the description thereof is omitted.
[0582] As described above, the LDPC decoder 166 may be
configured without the received data rearrangement unit
310, so that a scale thereof may be made smaller than
that of the decoding device in Fig. 124.
[0583] Although the code length N in the LDPC code,
the information length K, the number of columns (the
number of rows and the number of columns of the
constitutive matrix) being the unit of the cyclic
structure P, and the submultiple q (= M/P) of the parity
length M in the LDPC code are set to 90, 60, 5, and 6,
respectively, in Fig. 121 to Fig. 125 in order to
simplify the description, the code length N, the
information length K, the number of columns P being the
unit of the cyclic structure, and the submultiple q (=
M/P) are not limited to the abovedescribed values.
[0584] That is to say, in the transmitting device 11
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in Fig. 8, the LDPC encoder 115 outputs the LDPC code of
the code length N of 64800, 16200 and the like, the
information length K of N  Pq (= N  M), the number of
columns P being the unit of the cyclic structure of 360,
and the submultiple q of M/P, for example, the LDPC
decoder 166 in Fig. 125 may also be applied to a case in
which the LDPC decoding is performed by simultaneously
performing the P check node operations and the P variable
node operations to such LDPC code.
[0585]
<Block diagram showing configuration example of block
deinterleaver 54>
[0586] Fig. 126 is a block diagram showing a
configuration example of a block deinterleaver 54.
[0587] The block deinterleaver 54 is configured
similar to the block deinterleaver 25 illustrated in Fig.
106.
[0588] The block deinterleaver 54 has a storage region
called as Part 1 and a storage region called as Part 2.
The Parts 1 and 2 store one bit in a row direction. The
number C of columns that are the storage regions for
storing the predetermined number of bits in a column
direction are arranged. The number C is equal to the
number of bits m of the symbols.
[0589] The block deinterleaver 54 preforms the block
deinterleave to the parts 1 and 2 by writing and reading
the LDPC code.
[0590] In the block deinterleave, the LDPC code (as
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the symbol) is written in an order that the block
interleaver in Fig. 106 reads the LDPC code.
[0591] Further, in the block deinterleave, the LDPC
code is read in an order that the block interleaver 25 in
Fig. 106 writes the LDPC code.
[0592] That is to say, in the block interleave by the
block interleaver 25 in Fig. 106, the LDPC code is
written to the parts 1 and 2 in the column direction and
is read in the row direction. In the block deinterleave
by the block deinterleaver 54 in Fig. 126, the LDPC code
is written to the parts 1 and 2 in the row direction and
is read in the column direction.
[0593]
<Another configuration example of bit deinterleaver 165>
[0594] Fig. 127 is a block diagram illustrating
another configuration example of the bit deinterleaver
165 in Fig. 118.
[0595] In the drawing, the same reference numeral is
assigned to a part corresponding to that in Fig. 119 and
the description thereof is hereinafter appropriately
omitted.
[0596] That is to say, the bit deinterleaver 165 in
Fig. 127 is configured in the same manner as that in Fig.
119 except that a parity deinterleaver 1011 is newly
provided.
[0597] In Fig. 127, the bit deinterleaver 165 is
configured of the block deinterleaver 54, the groupwise
deinterleaver 55, and the parity deinterleaver 1011 and
=
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performs the bit deinterleave of the code bit of the LDPC
code from the demapper 164.
[0598] That is to say, the block deinterleaver 54
performs the block deinterleave (inverse process of the
block interleave) corresponding to the block interleave
performed by the block interleaver 25 of the transmitting
device 11 for the LDPC code from the demapper 164, i.e.,
the block deinterleave to return the position of the code
bit interchanged by the block interleave to the original
position, and supplies the LDPC code obtained as a result
to the groupwise deinterleaver 55.
[0599] The groupwise deinterleaver 55 applies the
groupwise deinterleave corresponding to the groupwise
interleave as the rearranging process performed by the
groupwise interleaver 24 of the transmitting device 11
to the LDPC code from the block deinterleaver 54.
[0600] The LDPC code obtained as a result of the
groupwise deinterleave is supplied from the groupwise
deinterleaver 55 to the parity deinterleaver 1011.
[0601] The parity deinterleaver 1011 applies the
parity deinterleave (inverse process of the parity
interleave) corresponding to the parity interleave
performed by the parity interleaver 23 of the
transmitting device 11, that is to say, the parity
deinterleave to return the code bit of the LDPC code, the
arrangement of which is changed by the parity interleave,
to the original arrangement for the code bit after the
groupwise deinterleave by the groupwise deinterleaver
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55.
[0602] The LDPC code obtained as a result of the
parity deinterleave is supplied from the parity
deinterleaver 1011 to the LDPC decoder 166.
[0603] Therefore, in the bit deinterleaver 165 in Fig.
127, the LDPC code to which the block deinterleave, the
groupwise deinterleave, and the parity deinterleave are
applied, that is to say, the LDPC code obtained by the
LDPC encoding according to the parity check matrix H is
supplied to the LDPC decoder 166.
[0604] The LDPC decoder 166 performs the LDPC decoding
of the LDPC code from the bit deinterleaver 165 using the
parity check matrix H used by the LDPC encoder 115 of the
transmitting device 11. That is to say, the LDPC decoder
166 performs the LDPC decoding of the LDPC code from the
bit deinterleaver 165 using the parity check matrix H
itself used by the LDPC encoder 115 of the transmitting
device 11 in the LDPC encoding or the conversion parity
check matrix obtained by at least applying the column
permutation corresponding to the parity interleave to the
parity check matrix H.
[0605] Herein, in Fig. 127, since the LDPC code
obtained by the LDPC encoding according to the parity
check matrix H is supplied from (the parity deinterleaver
1011 of) the bit deinterleaver 165 to the LDPC decoder
166, the LDPC decoder 166 may be configured of the
decoding device, which performs the LDPC decoding by a
full serial decoding scheme to sequentially perform the
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operation of the message (check node message and the
variable node message) one node after another, and the
decoding device, which performs the LDPC decoding by a
full parallel decoding scheme to simultaneously perform
the operation of the message (in parallel) for all the
nodes, for example, when the LDPC decoding of the LDPC
code is performed using the parity check matrix H itself
used by the LDPC encoder 115 of the transmitting device
11 in the LDPC encoding.
[0606] Also, when the LDPC decoder 166 performs the
LDPC decoding of the LDPC code using the conversion
parity check matrix obtained by at least performing the
column permutation corresponding to the parity interleave
of the parity check matrix H used by the LDPC encoder 115
of the transmitting device 11 in the LDPC encoding, the
LDPC decoder 166 may be configured of the decoding device
of the architecture to simultaneously perform the P (or
submultiple of P other than 1) check node operations and
variable node operations being the decoding device (Fig.
124) including the received data rearrangement unit 310
to rearrange the code bits of the LDPC code by applying
the column permutation similar to the column permutation
for obtaining the conversion parity check matrix to the
LDPC code.
[0607] Although the block deinterleaver 54, which
performs the block deinterleave, the groupwise
deinterleaver 55, which performs the groupwise
deinterleave, and the parity deinterleaver 1011, which
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performs the parity deinterleave, are separately formed
for convenience of description in Fig. 127, two or more
of the block deinterleaver 54, the groupwise
deinterleaver 55, and the parity deinterleaver 1011 may
be integrally formed as the parity interleaver 23, the
groupwise interleaver 24, and the block interleaver 25
of the transmitting device 11.
[0608]
<Configuration example of receiving system>
[0609] Fig. 128 is a block diagram showing a first
configuration example of a receiving system to which the
receiving device 12 may be applied.
[0610] In Fig. 128, the receiving system is configured
of an obtaining unit 1101, a transmission channel
decoding processor 1102, and an information source
decoding processor 1103.
[0611] The obtaining unit 1101 obtains a signal
including the LDPC code obtained by at least the LDPC
encoding of the LDPC target data such as the image data
and the audio data of the program through a transmission
channel (communication channel) (not shown) such as
digital terrestrial broadcasting, digital satellite
broadcasting, and a network such as a CATV network, the
Internet and the like, for example, to supply to the
transmission channel decoding processor 1102.
[0612] Herein, if the signal obtained by the obtaining
unit 1101 is broadcasted from a broadcasting station
through the terrestrial wave, a satellite wave, the CATV
CA 02924874 20160318
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(cable television) network and the like, for example, the
obtaining unit 1101 is configured of a tuner, an STB (set
top box) and the like. When the signal obtained by the
obtaining unit 1101 is multicasttransmitted from a web
server such as IPTV (Internet protocol television), for
example, the obtaining unit 1101 is configured of a
network I/F (interface) such as an NIC (network interface
card), for example.
[0613] The transmission channel decoding processor
1102 corresponds to the receiving device 12. The
transmission channel decoding processor 1102 applies a
transmission channel decoding process at least including
a process to correct the error occurring in the
transmission channel to the signal obtained by the
obtaining unit 1101 through the transmission channel and
supplies the signal obtained as a result to the
information source decoding processor 1103.
[0614] That is to say, the signal obtained by the
obtaining unit 1101 through the transmission channel is
the signal obtained by at least the error correction
encoding for correcting the error occurring in the
transmission channel and the transmission channel
decoding processor 1102 applies the transmission channel
decoding process such as an error correction process, for
example, to such signal.
[0615] Herein, the error correction encoding includes
the LDPC encoding, BCH encoding and the like, for example.
Herein, the LDPC encoding is at least performed as the
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error correction encoding.
[0616] Also, the transmission channel decoding process
may include demodulation of a modulated signal and the
like.
[0617] The information source decoding processor 1103
applies an information source decoding process at least
including a process to expand compressed information to
original information to the signal to which the
transmission channel decoding process is applied.
[0618] That is to say, there is a case in which
compression encoding to compress the information is
applied to the signal obtained by the obtaining unit 1101
through the transmission channel so as to decrease a data
volume of the image and the audio as the information, and
in this case, the information source decoding processor
1103 applies the information source decoding process such
as the process to expand the compressed information to
the original information (expanding process) to the
signal to which the transmission channel decoding process
is applied.
[0619] If the compression encoding is not applied to
the signal obtained by the obtaining unit 1101 through
the transmission channel, the information source decoding
processor 1103 does not perform the process to expand the
compressed information to the original information.
[0620] Herein, the expanding process includes MPEG
decoding and the like, for example. Also, the
transmission channel decoding process might include
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descrambling and the like in addition to the expanding
process.
[0621] In the receiving system configured as above,
the obtaining unit 1101 applies the compression encoding
such as MPEG encoding to the data of the image and the
audio, for example, and obtains the signal to which the
error correction encoding such as the LDPC encoding is
applied through the transmission channel to supply to the
transmission channel decoding processor 1102.
[0622] The transmission channel decoding processor
1102 applies the process similar to that performed by the
receiving device 12 and the like to the signal from the
obtaining unit 1101 as the transmission channel decoding
process, for example, and the signal obtained as a result
is supplied to the information source decoding processor
1103.
[0623] The information source decoding processor 1103
applies the information source decoding process such as
the MPEG decoding to the signal from the transmission
channel decoding processor 1102 and outputs the image or
the audio obtained as a result.
[0624] The receiving system in Fig. 128 as described
above may be applied to a television tuner and the like,
which receives television broadcasting as the digital
broadcasting, for example.
[0625] It is possible to form each of the obtaining
unit 1101, the transmission channel decoding processor
1102, and the information source decoding processor 1103
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as one independent device (hardware (IC (integrated
circuit) and the like) or a software module).
[0626] Also, as for the obtaining unit 1101, the
transmission channel decoding processor 1102, and the
information source decoding processor 1103, it is
possible to form a set of the obtaining unit 1101 and the
transmission channel decoding processor 1102, a set of
the transmission channel decoding processor 1102 and the
information source decoding processor 1103, and a set of
the obtaining unit 1101, the transmission channel
decoding processor 1102, and the information source
decoding processor 1103 as one independent device.
[0627] Fig. 129 is a block diagram illustrating a
second configuration example of the receiving system to
which the receiving device 12 may be applied.
[0628] Meanwhile, in the drawing, the same reference
numeral is assigned to a part corresponding to that in
Fig. 128 and the description thereof is hereinafter
appropriately omitted.
[0629] The receiving system in Fig. 129 is the same as
that in Fig. 128 in that this includes the obtaining unit
1101, the transmission channel decoding processor 1102,
and the information source decoding processor 1103 and is
different from that in Fig. 128 in that an output unit
1111 is newly provided.
[0630] The output unit 1111 is a display device, which
displays the image, and a speaker, which outputs the
audio, for example, and this outputs the image, the audio
CA 02924874 20160318
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and the like as the signal output from the information
source decoding processor 1103. That is to say, the
output unit 1111 displays the image or outputs the audio.
[0631] The receiving system in Fig. 129 as described
above may be applied to a TV (television receiver), which
receives the television broadcasting as the digital
broadcasting, a radio receiver, which receives radio
broadcasting, and the like, for example.
[0632] If the compression encoding is not applied to
the signal obtained by the obtaining unit 1101, the
signal output by the transmission channel decoding
processor 1102 is supplied to the output unit 1111.
[0633] Fig. 130 is a block diagram showing a third
configuration example of the receiving system to which
the receiving device 12 may be applied.
[0634] In the drawing, the same reference numeral is
assigned to a part corresponding to that in Fig. 128 and
the description thereof is hereinafter appropriately
omitted.
[0635] The receiving system in Fig. 130 is the same as
that in Fig. 128 in that this includes the obtaining unit
1101 and the transmission channel decoding processor 1102.
[0636] However, the receiving system in Fig. 130 is
different from that in Fig. 128 in that the information
source decoding processor 1103 is not provided and a
record unit 1121 is newly provided.
[0637] The record unit 1121 records (stores) the
signal output from the transmission channel decoding
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processor 1102 (for example, a TS packet of MPEG TS) in a
recording (storage) medium such as an optical disk, a
hard disk (magnetic disk), and a flash memory.
[0638] The receiving system in Fig. 130 as described
above may be applied to a recorder and the like, which
records the television broadcasting.
[0639] In Fig. 130, the receiving system may be
provided with the information source decoding processor
1103 and the information source decoding processor 1103
may record the signal to which the information source
decoding process is applied, that is to say, the image
and the audio obtained by the decoding in the record unit
1121.
[0640]
[One embodiment of computer]
[0641] A series of processes described above may be
performed by hardware or by software. When a series of
processes is performed by the software, a program, which
configures the software, is installed on a multipurpose
computer and the like.
[0642] Fig. 131 shows a configuration example of one
embodiment of the computer on which the program, which
executes a series of processes described above, is
installed.
[0643] The program may be recorded in advance in a
hard disk 705 and a ROM 703 as a recording medium stored
in the computer.
[0644] Alternatively, the program may be temporarily
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or permanently stored (recorded) in a removable recording
medium 711 such as a flexible disk, a CDROM (compact
disc read only memory), an MO (magnetooptical) disk, a
DVD (digital versatile disc), the magnetic disk, and a
semiconductor memory. Such removable recording medium 711
may be provided as socalled packaged software.
[0645] In addition to installation from the above
described removable recording medium 711 on the computer,
the program may be transferred from a downloading site to
the computer by wireless through a satellite for the
digital satellite broadcasting or transferred to the
computer by wire through the network such as a LAN (local
area network) and the Internet, and the computer may
receive the program transferred in this manner by a
communication unit 708 to install on an internal hard
disk 705.
[0646] The computer has a CPU (central processing
unit) 702 builtin. An input/output interface 710 is
connected to the CPU 702 through a bus 701 and, when an
instruction is input through the input/output interface
710 by operation and the like of the input unit 707
configured of a keyboard, a mouse, a microphone and the
like by a user, the CPU 702 executes the program stored
in the ROM (read only memory) 703 according to the same.
Alternatively, the CPU 702 loads the program stored in
the hard disk 705, the program transferred from the
satellite or the network to be received by the
communication unit 708 and installed on the hard disk 705,
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or the program read from the removable recording medium
711 mounted on a drive 709 to be installed on the hard
disk 705 on a RAM (random access memory) 704 to execute.
According to this, the CPU 702 performs the process
according to the abovedescribed flowchart or the process
performed by the configuration of the abovedescribed
block diagram. Then, the CPU 702 outputs a processing
result from an output unit 706 configured of an LCD
(liquid crystal display), a speaker and the like, or
transmits the same from the communication unit 708, or
records the same in the hard disk 705 through the
input/output interface 710, for example, as needed.
[0647] Herein, in this specification, a processing
step to write the program to allow the computer to
perform various processes is not necessarily required to
be processed in chronological order along order described
in the flowchart and this also includes the process
executed in parallel or individually executed (for
example, a parallel process or a process by an object).
[0648] Also, the program may be processed by one
computer or distributedly processed by a plurality of
computers. Further, the program may be transferred to a
remote computer to be executed.
[0649] The embodiment of the present technology is not
limited to the abovedescribed embodiment and various
modifications may be made without departing from the
scope of the present technology.
[0650] For example, (the parity check matrix initial
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value table of) the abovedescribed new LDPC code may be
through the communication channel 13 (Fig. 7), any of
which is a satellite circuit, a terrestrial wave, and a
cable (wire circuit). Furthermore, the new LDPC code may
be used for data transmission other than the digital
broadcasting.
[0651] The abovedescribed GW patterns may be applied
to any other than the new LDPC code. Furthermore, the
modulation scheme to which the abovedescribed GW
patterns are applied is not limited to 16QAM, 64QAM,
256QAM and 1024QAM.
[0652] Effects described herein are not limited only
to be illustrative, there may be effects other than those
described herein.
Description of reference numerals
[0653]
11 transmitting device
12 receiving device
23 parity interleave
24 groupwise interleaver
block interleaver
31 memory
32 interchange unit
25 54 block deinterleaver
55 groupwise interleaver
111 mode adaptation/multiplexer
112 padder
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113 BB scrambler
114 BCH encoder
115 LDPC encoder
116 bit interleaver
117 mapper
118 time interleaver
119 SISO/MISO encoder
120 frequency interleaver
121 BCH encoder
122 LDPC encoder
123 mapper
124 frequency interleaver
131 frame builder & resource allocation
132 OFDM generation
151 OFDM processor
152 frame management
153 frequency deinterleaver
154 demapper
155 LDPC decoder
156 BCH decoder
161 frequency deinterleaver
162 SISO/MISO decoder
163 time deinterleaver
164 demapper
165 bit deinterleaver
166 LDPC decoder
167 BCH decoder
168 BB descrambler
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169 null deletion
170 demultiplexer
300 edge data storage memory
301 selector
302 check node calculation unit
303 cyclic shift circuit
304 edge data storage memory
305 selector
306 received data memory
307 variable node calculation unit
308 cyclic shift circuit
309 decoded word calculation unit
310 received data rearrangement unit
311 decoded data rearrangement unit
601 encoding processor
602 storage unit
611 code rate set unit
612 initial value table read unit
613 parity check matrix generation unit
614 information bit read unit
615 encoding parity operation unit
616 controller
701 bus
702 CPU
703 ROM
704 RAM
705 hard disk
70 output unit
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707 input unit
708 communication unit
709 drive
710 input/output interface
711 removable recording medium
1001 inverse interchange unit
1002 memory
1011 parity deinterleaver
1101 obtaining unit
1101 transmitting channel decoding processor
1103 information source decoding processor
1111 output unit
1121 record unit
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Admin Status
Title  Date 

Forecasted Issue Date  Unavailable 
(86) PCT Filing Date  20140912 
(87) PCT Publication Date  20150402 
(85) National Entry  20160318 
Dead Application  20200914 
Abandonment History
Abandonment Date  Reason  Reinstatement Date 

20190912  FAILURE TO REQUEST EXAMINATION  
20190912  FAILURE TO PAY APPLICATION MAINTENANCE FEE 
Payment History
Fee Type  Anniversary Year  Due Date  Amount Paid  Paid Date 

Application Fee  $400.00  20160318  
Maintenance Fee  Application  New Act  2  20160912  $100.00  20160815 
Maintenance Fee  Application  New Act  3  20170912  $100.00  20170825 
Maintenance Fee  Application  New Act  4  20180912  $100.00  20180823 
Current Owners on Record 

SONY CORPORATION 
Past Owners on Record 

None 