Note: Descriptions are shown in the official language in which they were submitted.
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MULTI-PORT CONVERTER STRUCTURE FOR DC/DC POWER CONVERSION
Field of the Invention
The invention relates to the field of power converters for dc systems.
Background
A two-quadrant buck converter, also known as a synchronous buck converter, is
a type of basic
switch-mode dc/dc converter that is used to regulate voltage and provide
efficient dc power transfer in
energy systems. The traditional two-quadrant buck converter cell, shown in
Figure 20 (prior art),
comprises a pair of complimentary power switches and input capacitor. An
output L-C low-pass filter is
employed when a small high frequency ripple for the output voltage is
required. For steady state
operation, switch S1 is turned "on" (i.e. switch S1 is closed) and S2 is
turned "off' (i.e. switch SI is
opened) during time interval DTs. The converter duty cycle D, which ranges
from 0 to 100%, represents
the percentage time when switch S1 is on (and thus when S2 is off) during
switching period T,. During
each time interval D=Tõ voltage 1,, at node x becomes equal to input voltage
V,õ as shown in Figure 20.
Voltage võ becomes zero when switch S1 is turned off (and thus when S2 is
turned on) for the remainder
of the switching period, due to the complimentary switching action of SI and
S2. Based on this
discussion, the voltage vx can be viewed as having an average value of D.V,õ
with a set of high frequency
switching harmonics. The L-C low-pass filter is designed such that it
attenuates the high frequency
switching harmonics of vx and allows the output voltage Vow to be equal to the
average value D.V,õ.
Assuming the output voltage is externally regulated, the inductor current //,
can be made to take on either
a positive or negative average value through adjustment of the converter duty
cycle, thus enabling
bidirectional energy transfer between input and output terminals. Therefore,
voltage regulation and
bidirectional energy transfer can be achieved easily by suitable control of
the duty cycle D in a
two-quadrant buck converter.
It should be understood that a unidirectional variant of the bidirectional
buck converter in Figure 20 can
be realized, by, for example, replacing switch S2 with a diode. The
unidirectional buck converter can be
employed for applications where only input to output power transfer capability
is needed.
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Multiple two-quadrant buck converter cells with associated filters can also be
connected in series to
form "classical cascaded buck converters". Figure 21 (i.e. prior art) shows a
classical cascaded buck
converter comprised of three individual dc/dc buck converter cells, each with
associated output filtering,
connected in series. The topology shown has three input ports and one output
port. Each of the input
ports and the output port consists of two terminals as shown. Observe each
input port has an assigned
reference terminal with its voltage defined relative to ground, i.e. vnr, vo
and vo. By chosen convention
the reference terminals are selected such that they correspond to the bottom
connection point of each
input port capacitor. To limit voltages to ground, a single reference terminal
is typically connected to
ground. In Figure 21, the reference terminal selected for ground connection is
shown by the dotted
connection from v03 to ground. However, it must be stressed this choice is
entirely arbitrary, i.e. any
other reference terminal in Figure 21 could have been connected to ground. The
classical cascaded buck
converter allows multiple input ports to exchange energy with a common output
port, wherein the output
voltage can be significantly higher than individual input voltages. This
flexibility makes the classical
cascaded buck converter suitable for a wide range of applications such as
photovoltaic systems and
battery management units.
Present state-of-the-art technology having similar application and
functionality compared to the classical
cascaded buck converter in Figure 21 is the cascaded connection of two-
quadrant buck converter cells
that share a single L-C low-pass filter, shown in Figure 22. However, with
exception of the one
ground-connected reference terminal, all other input reference terminal
voltages for this topology, i.e.
vnj and võ2, are subject to undesired high frequency switching ripple voltage.
As a result, energy sources
that are connected to these input ports, for example, solar panels or
batteries, will suffer from significant
capacitive current to ground. In contrast, the classical cascaded buck
converter with multiple low-pass
L-C filters as shown in Figure 21 can reduce the high frequency switching
ripple voltage on vo and vn2,
provided that individual L-C filter elements are sufficiently large. However,
this comes at the expense of
an overall increase in both the size and number of energy storage components
(inductors and capacitors).
The additional components increase the loss and cost of the classical cascaded
buck converter.
It is, therefore, desirable to develop a new non-isolated dc/dc converter
topology that can be designed to
have an arbitrarily small high frequency switching voltage ripple magnitude at
all input and output
reference terminals, while achieving reduced component count, cost, and loss.
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Summary of the Invention
It will be evident from the foregoing, and from a review of the detailed
description that follows, that the
multi-port converter topologies for dc/dc power conversion embodied within the
apparatus are of
significant advantage, in that, inter alia, they:
= are modular and scalable;
= can be designed to have an arbitrarily small high frequency switching
voltage ripple magnitude
at all input and output reference terminals;
= are capable of bidirectional energy exchange between input ports and
output port;
= are capable of controlling power sharing among the input ports;
= are capable of allowing multiple inputs to exchange energy with a common
output, wherein the
output voltage can be significantly higher than individual input voltages;
= have relatively low rating of components; in particular, the net rating
of energy storage
components (capacitors and inductors) are small compared to the classical
cascaded buck
converter;
= are highly flexible in that they can be cascaded with modules of the same
topology or cells of
differing topology.
Other advantages and features associated with the multi-port converter
topology will become evident
upon a review of the following detailed description and the appended drawings,
the latter being briefly
described hereinafter.
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Brief Description of the Drawings
Figure 1 Double-input single-output converter module with generalized power
switches;
Figure 2 One example of power switches realization using MOSFETs and diodes
for the
double-input single-output converter module in Figure 1;
Figure 3(a) One possible gating strategy with corresponding switching
states for double-input
single-output converter module in Figure 1;
Figure 3(b) Equivalent circuit diagram for Figure 1 corresponding to switching
state #1: switch Sib
and switch Sza turned on;
Figure 3(c) Equivalent circuit diagram for Figure 1 corresponding to
switching state #2: switch Sia
and switch S2a turned on;
Figure 3(d) Equivalent circuit diagram for Figure 1 corresponding to
switching state #3: switch Sia
and switch S2b turned on;
Figure 3(e) Equivalent circuit diagram for Figure 1 corresponding to
switching state #4: switch Sib
and switch S2b turned on;
Figure 4 Series-stacking 1-' double-input single-output converter modules
in Figure 1 to form a
2k-input single-output cascaded dc/dc converter structure;
Figure 5 Series-stacking one double-input single-output converter module of
Figure 1 with (k-1)
two-quadrant buck converter cells to form a (k+1)-input single-output cascaded
dc/dc
converter structure;
Figure 6 (k+1)-input single-output cascaded converter structure where
physical placements of the
module and switching cell plurality are interchanged relative to Figure 5;
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Figure 7 One possible cell sorting and selection scheme for cascaded
converter structures in Figure
and Figure 6 to achieve charge balancing of inputs across all possible output
voltages;
Figure 8 Simulation model for Figure 1 implemented in PLECS;
Figure 9 Simulation results for double-input single-output converter module
in Figure 1: power
transfer from inputs to output;
Figure 10 Simulation results for double-input single-output converter
module in Figure 1: power
transfer from output to inputs, where power transfer is divided evenly between
input
ports;
Figure 11 Simulation results for double-input single-output converter
module in Figure 1: power
transfer from output to inputs, where power transfer is divided unevenly
between input
ports as assigned by the user;
Figure 12 Simulation results for prior art comprising four series-cascaded
two-quadrant buck
converter cells with single L-C output filter (i.e. a four input variant of
Figure 22), to
demonstrate inability to achieve full output voltage range when only one of
the cells
utilizes switch-mode operation;
Figure 13 Simulation results for a four-input single-output cascaded
converter structure of Figure 5,
to demonstrate ability to achieve full output voltage range when utilizing
switch-mode
operation for the high/low-frequency cell stack;
Figure 14 Switch gating waveforms for simulation results in Figure 13,
where high-frequency cells
are switched at 50 kHz;
Figure 15 Finer time scale resolution (i.e. zoomed time axis) for a chosen
segment of simulated
waveforms in Figure 14, to show contrast between high-frequency and low-
frequency
switching times;
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Figure 16 Simulation results for a four-input single-output cascaded
converter structure of Figure 5
employing battery modules, to illustrate mechanism allowing equal charge
balancing
between input ports such that the average battery voltages are depleted at the
same rate;
Figure 17 Switch gating waveforms for simulation results in Figure 16,
where high-frequency cells
are switched at 50 kHz and low-frequency cells are switched at 20 Hz;
Figure 18 Finer time scale resolution (i.e. zoomed time axis) for a chosen
segment of simulated
waveforms in Figure 17, to show contrast between high-frequency and low-
frequency
switching times;
Figure 19 Double-input single-output converter module with functionally
similar output capacitor
configuration
Figure 20 Prior art: Two-quadrant buck converter with output filtering,
depicted along with
corresponding operational waveforms;
Figure 21 Prior art: Classical cascaded buck converter with multiple L-C
output filters, where three
buck converter cells are employed for ease of illustration; and
Figure 22 Prior art : Cascaded buck converter with a single shared L-C
output filter, where three
buck converter cells are employed for ease of illustration.
Detailed Description
The dc/dc converter module shown in Figure 1 has two first ports, labelled
with voltages "v1" and "v2",
and one second port, labelled with voltage "v3". In this document, an "input"
port refers to a port that
connects to a de source or load, while an "output" port refers to the port
that is operationally connected
to the de bus. Throughout this document, first ports and "input" ports are
used interchangeably, and
second ports and "output" ports are similarly interchangeable. Thus, the
converter module in Figure 1 is
referred to as a double-input single-output converter module.
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The converter module in Figure 1 is comprised of two synchronous buck
converter cells with a single
filter inductor as shown. A key topological feature of the double-input single-
output converter module is
the placement of inductor L across the two inner switches Sib and S2a as
shown. This configuration
results in the inductor being effectively "isolated" from the output port
terminals. That is, due to the
imposed connection of L across non-matching switches of the two buck converter
cells, the output port
terminals may be connected directly to input port terminals as shown. This
natural topological feature is
seen as highly advantageous in achieving an arbitrarily small high frequency
switching ripple magnitude
at all input and output reference terminals in Figure 1, as it avoids reliance
on excessively sized passive
filters to achieve this goal.
The converter module in Figure 1 employs two pairs of complimentary switches:
1) Sia, Sib and 2) S2a,
S2b. Similar to the convention illustrated in Figure 20, duty cycle command D1
controls the percentage
time that Sia is on (and thus Sib is off) and duty cycle command D2 controls
the percentage time that S2a
is on (and thus S2b is off). An interleaved operation of the two pairs of
switches is possible for this
topology, where controlling a relative phase shift, (P, between D1 and D2 can
regulate the order in
which the four switches are turned on (over each switching period T5).
However, interleaved operation
is optional, i.e. interleaved operation of the buck converter cells in Figure
1 is not required. The two
pairs of complimentary power switches can be implemented using a number of
different switching
devices or technologies; one possible example of an implementation using
MOSFETs and Diodes is
shown in Figure 2. It should be understood that there are many possible
implementations of the switches
and energy storage components shown for the double-input single-output
converter module in Figure 1.
Therefore, such variants are considered as being functionally similar to
Figure 1.
Bidirectional energy exchange between the input ports and output port in
Figure 1 is possible.
Specifically, power can be transferred either: 1) from the output port to both
input ports or 2) from both
input ports to the output port. A salient operational feature of the topology
in Figure 1 is that power
sharing among the two inputs can be achieved in a controlled manner, as will
be demonstrated in the
latter simulations section. It should be understood that a unidirectional
variant of Figure 2 can be easily
realized, by, for example, replacing two of the four MOSFET switches with
diodes.
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Double-Input Single-Output Converter Module: Theory of Operation
Due to the flexible and scalable nature of the double-input single-output
converter module shown in
Figure 1, there are many possible methods or strategies in which to operate
the converter. Therefore, the
subsequent operational analysis should not be considered to be limiting. For
demonstration purposes and
ease of understanding, the following assumptions are imposed to illustrate the
key characteristics of the
topology:
= All switching devices and energy storage components (i.e. inductors and
capacitors) are lossless;
= Dead time for switches is neglected to simplify mathematical analysis.
Reference is now made to Figure 1. Switches Si, and Sib are controlled by duty
cycle command
D1 while switches S2a and S2b are controlled by duty cycle command D2. It is
assumed the two pairs of
switches have the same switching period 7:,, however, this is done for ease of
understanding as such an
assumption is not necessary to obtain the following results. In general, four
possible switching states
exist for the converter module in Figure 1; these four states are illustrated
in Figure 3(b), Figure 3(c),
Figure 3(d) and Figure 3(e). One possible switching pattern that can generate
all four switching states is
given in Figure 3(a), where (I) is the (per-unitized) relative phase shift
between D1 and D2 commands.
Note in Figure 3(a) the order of the switching states is indicated, however,
as discussed previously, the
order and duration of switching states can vary and thus the assumed diagram
in Figure 3(a) is not
unique. The duty cycle commands for each power switch are defined in Figure
3(a), where DI = 1 ¨ D1
and 131 = 1 ¨ D2.
The inductor voltage corresponding to the four possible switching states of
Figure 1, as illustrated in
Figure 3(a), are:
State #1: vz, = VI_ + V2 ¨ V3 (I)
State #2: vi, = V2 ¨ V3 (2)
State #3: 121, = ¨V3. (3)
State #4: 19/, = V1 ¨ V3 (4)
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The principle of inductor volt-second balance (IVSB) dictates that the average
inductor voltage over one
switching period in steady state is zero. Consequently, the following voltage
relationship can be derived
when equating the average inductor voltage to zero using IVSB:
V3 = (1¨ Di)Vi + D2V2. (5)
The voltage relationship in (5) does not make any assumptions on the values of
D1, D2, CP , VI., V2 or V3 within their permissible range and is independent
of the switching period, and thus
be considered a general design equation for this topology. However, a set of
values for D1, D2, and
cto can be selected to achieve a minimum inductor ripple current and a minimum
capacitor ripple voltage.
Similar to the preceding analysis, a current relationship can also be found
using the principle of
capacitor charge balance (CCB). The principle of CCB dictates the average
capacitor current over one
switching period in steady state is zero. By equating the average capacitor
current to zero for each port,
the following current relationship can be derived
11 12
___________________________________________ ... _ (6)
1 ¨ Di D2
The polarity of currents in (6) correspond to those assumed in Figure 1.
Cascaded Topologies Formed by Series-Stacking Multiple Converter Modules
The double-input single-output dc/dc converter module shown in Figure 1 can be
extended to form
cascaded topologies by stacking multiple modules in series. Figure 4 shows one
possible example of
such a cascaded topology where k double-input single-output converter modules
are stacked to form a
2k-input single-output structure. Each of the k modules has the same topology
as shown in Figure 1, but
individual modules do not necessarily need to employ the same energy storage
components, or same
realization of the power switches. The cascaded converter structure shown in
Figure 4 enables additional
inputs (i.e. more than two) to exchange energy with a common output, wherein
the output voltage can be
significantly higher than individual input voltages.
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The stack of k modules in Figure 4 can be gated (i.e. switched) on/off at a
relatively high common
switching frequency corresponding to fs. = 11T, , as is the case with
conventional switch-mode
converters. Output L-C filter components are designed to attenuate high
frequency ripple associated with
switch-mode operation. However, in contrast to high frequency (i.e. switch-
mode) operation,
substantially lower switching frequencies can also be exploited to operate the
majority of modules in a
"voltage stacking mode". The term "voltage stacking mode" refers to where
select modules, or, select
switching converter cells within individual modules, are inserted or removed
from the cell stack for
extended periods of time. This is inherently different from conventional
switch-mode operation where
cells are switched in/out at much higher switching frequencies, typically
according to some form of
pulse-width modulation. Taking into consideration both switch-mode operation
and voltage stacking
mode, values of fs for an individual cell can be anywhere from less than 1 Hz
to several hundred kHz.
Higher switching frequencies (i.e. more than several hundred kHz) can also be
adopted. There is no
requirement the switching frequency of individual cells in Figure 4 must be
equal; in general, each buck
converter cell can employ a different L.
The converter structure in Figure 4 is only one example of how multiple double-
input single-output
converter modules of Figure 1 can be utilized to create a cascaded
architecture with increased number of
inputs. Reference is now made to Figure 5, where a single converter module
from Figure 1 is
series-stacked with (k-1) two-quadrant buck converter cells (i.e. switching
cells) to form a (k+1)-input
single-output cascaded structure. The resulting string of cascaded cells is
partitioned into a
"high/low-frequency cell stack" and a "low-frequency cell stack". The
"high/low-frequency cell stack"
comprises the two switching cells in the converter module and signifies that
these cells are capable of
operating: 1) both as high-frequency switch-mode converters, 2) both in low-
frequency voltage stacking
mode, or 3) in any combination thereof.
The "low-frequency cell stack" in Figure 5 comprises the remaining switching
cells (i.e. the cells that do
not comprise the module) and signifies that the (k-1) series-cascaded cells
operate exclusively in a
low-frequency voltage stacking mode. That is, in general, the on-off states
for each pair of
complimentary switches in the "low-frequency cell stack" do not change during
several successive
high-frequency switching periods of the neighbouring "high/low-frequency cell
stack".
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Switching frequencies employed for the "low-frequency cell stack" can be many
orders of magnitude
smaller than the associated switch-mode operating frequency of the "high/low-
frequency cell stack". It
should be stressed that on-off state durations of complimentary switch pairs
within the "low-frequency
cell stack" can be made to be arbitrarily long, i.e. there is no fundamental
constraint placed on the
maximum 'on' state duration for each pair of complimentary switches within the
"low-frequency cell
stack".
Based on the above discussion, the input port reference terminal voltages
vi,/, v,/,2 and vn2 to vn(k_o in
Figure 5 are not subject to appreciable high-frequency switching ripple
voltage. Voltages v,/,/, 17,1,2 in
the high/low-frequency cell stack achieve this by exploiting the structure in
Figure 1, while voltages vn2
to vn(k_i) achieve this by leveraging a very low frequency operation of the
low-frequency cell stack. Note
vnk is connected to ground in Figure 5 and thus does not experience any
switching voltage stress.
An advantage of the topology in Figure 5 over the structures described in, for
example, Z. Zheng, K
Wang, L Xu and Y Li, "A Hybrid Cascaded Multilevel Converter for Battery
Energy Management
Applied in Electric Vehicles," IEEE Trans. Power Electronics, vol.29, no.7,
pp. 3537-3546, July 2014.
rZheng et all is that it can be designed to have arbitrarily small high-
frequency switching ripple
magnitude at all input and output reference terminals, while simultaneously
achieving reduced
component count, cost, and loss. This is evident when inspecting Figure 5 as
only one interface inductor
and one output filter capacitor is needed.
It should be understood the cascaded structure in Figure 5 is only one example
of how the basic
converter module in Figure 1 can be arranged with series-cascaded two-quadrant
buck converter cells.
Any number of double-input single-output converter modules of Figure 1 can be
utilized (i.e. not only
limited to a single module as shown in Figure 5), as well as any number of two-
quadrant series-cascaded
buck converter cells. Other alternatives are possible, such as, for example,
the order in which individual
cells are stacked in series within the resulting string.
Reference is now made to Figure 6, where physical placement of the high/low-
frequency cell stack and
low-frequency cell stack are interchanged relative to Figure 5.
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The topology in Figure 6 remains a (k+1)-input single-output cascaded
converter structure. Apart from
the physical ordering of low-frequency and high/low-frequency cell stacks
within the string, this variant
operates in a manner substantially similar to that of the structure of Figure
5.
Full Output Voltage Range Capability
There is a practical restriction on the range of duty cycles a dc/dc converter
can achieve. Namely, a
converter is incapable of operating with a duty cycle very close to one, or
very close to zero. Duty cycle
commands within a small region above zero are in practice set to zero, while
duty cycle commands
within a small region below one are in practice set to unity. This practical
limitation in the achievable
range of duty cycles stems from the non-zero turn-on and turn-off times
inherent to any semiconductor
based power switching device. In addition, commercial PWM modules are
typically incapable of
modulating duty ratios very close to zero and one. It should be stressed the
range of non-permissible
duty cycles varies depending on many factors such as switch technology, switch
voltage and current
ratings, and switching frequency. In this work, particularly the simulations
section, duty cycle
commands less than 0.1 or greater than 0.9 are assumed to be unachievable for
switch-mode operating
cells. However, this range of values is chosen for illustrative purposes,
only, and should be not
considered as being typical.
The limitation in available range of duty cycles implies there is a range of
average output voltages near
zero, and a range of average output voltages near Vin, that a switch-mode
dc/dc converter cannot achieve.
In Zheng et al., it is explicitly highlighted that the adopted operational
strategy utilizes only one
converter cell for high-frequency switch-mode operation. The remaining
cascaded buck converter cells
operate deliberately in a low-frequency voltage stacking mode. This implies
only one cell is available to
synthesize the deficit portion of the reference output voltage not provided by
the dedicated
low-frequency buck converter cells. Thus, taking into consideration the
practical limitation for realizable
duty cycles as described above, the topology in Zheng et al.is unable to
achieve all possible average
output voltages. This stems from the fact the single dedicated switch-mode
buck converter cell cannot
achieve all duty cycle commands. This deficiency of prior art will be
demonstrated in the simulations
section.
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In contrast to prior techniques, the cascaded topologies in Figure 4 through
Figure 6 operate in such a
manner that achieves all possible average output voltages for the entire cell
stack. The effect of the
aforementioned duty cycle restriction is alleviated by allowing at least one
double-input single-output
converter module, which corresponds to at least two buck converter cells as
illustrated by Figure 1, to
operate in a switch-mode fashion as needed. The remaining cascaded cells need
only operate in
low-frequency voltage stacking mode. The key requirement is that, in order to
accommodate all possible
deficit portions of the reference output voltage not provided by the low-
frequency cell stack, at least one
module must be dedicated to switch-mode operation. Additional modules can
operate as switch-mode
converters, however, this is not required in order to achieve full output
voltage range capability. This
operational benefit will be demonstrated in the simulations section. It is
important to reiterate the
high/low-frequency cell stack is not limited to only one converter module, as
shown by Figure 5 and
Figure 6. Multiple modules can be cascaded while realizing the same benefit of
full output voltage range
capability.
Charge Balancing of Cells across all Possible Output Voltages
The cascaded converter structures in Figure 4 through Figure 6 can be used for
many applications. In
particular these topologies are well suited for battery systems. Individual
batteries can be connected to
the input ports along the entire cell stack, thus enabling their integration
with a common dc link for
bidirectional energy transfer.
An advantageous operational feature of the proposed cascaded dc/dc topologies
for battery systems is
that charge balancing of the different cells, i.e. individual batteries, can
be achieved. Moreover, recalling
the preceding discussion on output voltage range capability, the cascaded
structures in Figures 4-6 can
achieve this cell balancing across all possible output voltages. Cell
balancing is defined in this context as
a means to ensure each battery along the entire cell stack is
charged/discharged at the same average rate.
This is seen as a highly beneficial operating feature for battery energy
management systems, as unequal
charge depletion/repletion amongst the various batteries can be avoided. Cell
balancing is achieved by
suitable operation of the individual cells (ref. Figure 4) or suitable
coordinated operation of
low-frequency and high/low-frequency cell stacks (ref. Figures 5 and 6). Of
course, long term (i.e.
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average) charge/discharge rates of individual batteries can deliberately be
made unequal, if so desired.
Reference is now made to Figure 7, which shows a high level diagram
illustrating one possible
operational strategy to achieve charge balancing between cells for the
cascaded converter structures in
Figure 5 and Figure 6, across all possible output voltages. Here it is assumed
there are a total of N cells
in the entire stack, with N-2 cells in the low-frequency cell stack (i.e. two
cells in the module and N-2
cells in the switching cell plurality). As shown in Figure 7, there exists a
cell voltage sorting block and a
gating logic block. The cell voltage sorting block acts on a "slow" time
scale, corresponding to the
switching period of the low-frequency cell stack, and sorts/orders all input
ports based on their voltage
measurements. The gating logic block acts on a substantially faster time
scale, corresponding to the
high-frequency switching period of the high/low-frequency cell stack, to allow
at least one cell within
the high/low-frequency cell stack to operate in switch-mode. As a result of
this combination of slow and
fast control, individual cells can be removed and inserted as needed to meet
all possible stack voltage
demands (i.e. output port voltage references), while simultaneously ensuring
charge balancing between
cells. The "output port voltage reference" command in Figure 7 can be
generated by various means, such
as, for example, by the resulting control action of an external control logic
block. An example
application employing batteries is presented in the simulations section to
illustrate this functionality.
It should be stressed that, as previously mentioned, the implementation in
Figure 7 is not unique. There
are many other alternate implementations that can similarly achieve balancing
between cells of the entire
stack, by suitable operation of the high/low-frequency and low-frequency cell
stacks.
Deployment
The double-input single-output dc/dc converter module shown in Figure 1, along
with the embodiments
shown in Figure 4 through Figure 6, can be used to enable bidirectional (or,
if desired, unidirectional)
energy exchange between multiple inputs and a common output, wherein the
output voltage can be
significantly higher than individual input voltages. Such operation has wide
range of application in
systems such as, but not limited to, photovoltaic systems and battery
management units. For example,
individual photovoltaic panels that use centralized or distributed based
maximum power point tracking
schemes can be connected to input ports of a unidirectional variant of the
cascaded topology shown in
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Figure 4, thereby allowing maximal energy extraction from each panel (at its
respective panel voltage)
to a local load or external dc network.
Another example of application is to connect battery units to the input ports
of the converter topology in
Figure 5 and Figure 6 to enable centralized energy management of the battery
system. The bidirectional
energy exchange capability can be leveraged to allow individual battery units:
1) to supply energy to a
load/source connected at the output or 2) to be charged by a dc source
connected at the output.
Furthermore, individual battery units can be inserted or removed from the
battery stack, via appropriate
switching action, thus allowing balanced charging and/or discharging of select
battery units for all
possible output voltages.
Converter Simulations: Introduction
In subsequent sections, the double-input single-output dc/dc converter module
in Figure 1 and the
(k+1)-input single-output cascaded dc/dc converter structure in Figure 5 are
simulated using PLECS.
Specific case study scenarios are simulated to demonstrate key operational
characteristics of the
converters. In addition, an example case study comparing performance of the
converter module in
Figure 1 and prior art is carried out.
Simulation Results: Example Case Study Performance Comparison between Proposed
Double-Input Single-Output Converter Module and Classical Two-Input Single-
Output Cascaded
Buck Converter
The PLECS simulation model of the double-input single-output converter module
of Figure 1 is given in
Figure 8.
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The nomenclature used in reference to Figure 8 is summarized in Table 1.
Table 1: Nomenclature adopted for PLECS simulations involving Figure 8
Quantity Name
Vin Average voltage of input ports (i.e. average
components of
and 172)
Vout Average voltage of output port (i.e. average
component of V3)
/out Average current of output port (i.e. average
component of 13)
Switching period
D,D1,D2 Duty cycles
(/) Phase shift (per-unit) between duty cycles
LI Vout pp Peak-to-peak output voltage ripple of V3
louttu Peak-to-peak output current ripple of 13
dvc ,pp Equivalent single capacitor peak-to-peak voltage
ripple
LI iL,pp Equivalent single inductor current //, peak-to-peak
ripple
iiv Voltage ripple of reference terminal voltage vn1
Advantages of the double-input single-output converter module in Figure 1 over
the classical two-input
single-output cascaded buck converter (i.e. two cascaded buck converter cells
with associated filters)
can be quantified by comparing them in an application example. Such an
application example is now
considered, which consists of an energy management system having two equal
battery voltages of
Vin=60V (i.e. two inputs of 60V nominal rating) with an output voltage
requirement of 170,,t =90V and
iou t =10A. This corresponds to a power transfer of approx. 900 W. Equal
energy storage requirements
(of inductors and capacitors) and operating conditions are imposed on the
converter module in Figure 1
and the classical cascaded buck converter. These imposed conditions allow key
performance criteria of
the topologies to be compared directly. The performance criteria of interest
for this example case study
are: 1) losses, 2) capacitive current to ground, and 3) harmonic distortion.
The following metric is proposed to evaluate converter performance
Metric diL,pp = Ay?,
(7)
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In order to reduce converter losses, capacitive current to ground and total
harmonic distortion, it is
necessary to reduce both AiL,pp and A vr, simultaneously. In other words, a
"better" converter will
have smaller A iL,pp and A vn values, and thus a smaller metric score
constitutes a preferred converter
structure based on the considered performance criteria.
Figure 8 shows the PLECS simulation circuit for the double-input single-output
converter module in
Figure 1. In all simulations, the switching period 7:, is set equal to 16.67us
for all switches. The
inductor L is 125 H, and capacitor C3 is implemented by connecting two 0.926 F
capacitors in series
as shown. This is done to ensure fairness of the comparison, as the simulation
model for prior art utilizes
two capacitors of 0.926 F each and two inductors of 62.5p,H each. The sizing
of energy storage
components is chosen based on inductor current ripple and capacitor voltage
ripple considerations for
the prior art. Based on these parameters, the converter module in Figure 1
(and also Figure 8) and the
classical cascaded buck converter have equal inductive and capacitive energy
storage requirements.
Moreover, this also ensures equal operating conditions for both topologies.
A comparative case study is carried out for the two topologies as described
above. Reference is now
made to Figure 9, which presents simulation results for the double-input
single-output converter module
in Figure 1, where power transfer is approx. 900 W from input ports to output
port. The depicted
waveforms were obtained using the simulation model in Figure 8.
A summary of the case study simulation results comparing the two converter
topologies is tabulated in
Table 2. The classical series-cascading of buck converter cells as employed by
prior art results in equal
duty cycle commands: DI=D2=0.75. However, to achieve the same operating point,
the double-input
single-output converter module in Figure 1 employs unequal duty cycles:
D1=0.25 and D2=0.75. This is
due to the imposed switches arrangement and chosen convention of duty cycle
commands, as illustrated
in Figure 3(a).
It should be noted that a set of optimal 0, DI and D2 can be found to minimize
il iL,pp and .419, for
Figure 1 and prior art separately.
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Table 2: Summary of case study simulation results comparing performance of
double-input
single-output converter module in Figure 1 (and also Figure 8) and classical
cascaded buck
converter (prior art)
0
V0(V) /out(A) A vout,pp(V) Ajout,pp(A) Avc,pp(V) A ii,,pp(A) lv(V)
Figure 1 0 90.2 9.96 8.58 0.954 4.29 2.12
8.53
D1=0.25 0.25T 90.0 9.99 2.23 0.247 1.11 1.02
2.23
D2-0.75 0.50T 90.5 9.97 8.56 0.951 4.28 2.15
8.56
sw
Prior art 0 90.1 9.99 12.6 1.41 6.32 3.17
6.31
_ ____________________________________________________________________________
D1=0.75 0.25T5õ 90.2 9.96 8.58 - 0.953 35.4 5.68
35.3
D2-0.75 0.50Tsw 90.0 10.01 2.22 0.246 26.6 2.92
26.4
Table 3 compares the computed values of performance metric (7) for Figure 1
and prior art, based on the
case study results summarized in Table 2. It can be seen from Table 3 that the
double-input single-output
converter module in Figure 1 achieves a better metric score in comparison to
the classical cascaded buck
converter, for all values of 0. This implies Figure 1 is the preferred
topology for the considered
performance criteria.
It is important to recognize the optimal value of 0 for each converter
topology, which is defined in this
example as the 0 value corresponding to the lowest metric score in Table 3, is
2.27 for Figure 1 and
20.03 for prior art. For these optimal conditions, the double-input single-
output dc/dc converter module
has a far superior performance (as metric score is approx. 10 times lower) and
therefore outperforms the
classical cascaded buck converter.
Table 3: Summary of key simulation results for converter module and classical
cascaded buck
converter (prior art)
0 Figure 1 Prior art
0 18.2 20.03
Metric 0.257 2.27 201.07
0.50T 18.4 77.67
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It should be stressed that a case study comparison between the double-input
single-output converter
module in Figure 1 and cascaded buck converter with single L-C output filter
(i.e. Zheng et al.) is not
carried out, due to the very large high frequency switching voltage ripple
that naturally occurs with the
latter. In this case, use of Zheng et al. would result in a Avn of 60 V, which
implies computed values of
metric (7) that far exceed those summarized in Table 3.
Simulation Results: Power transfer from output port to input ports of single
converter module
The previous simulations imposed dc power transfer from inputs to output.
Additional simulations are
now performed to demonstrate the dc/dc converter topology in Figure 1 is
capable of bidirectional
energy exchange, i.e. power transfer from inputs to output and vice versa.
Moreover, power sharing
between input ports is also demonstrated via simulation.
Two additional simulations are performed for Figure 1 to illustrate dc power
transfer from output port to
input ports. Specifically, these two simulated scenarios show that an energy
source located at the output
transfers 900 W to the inputs, and power sharing among the input ports can be
controlled. Power sharing
in this context implies the total power transfer can be arbitrarily split
between input ports.
Figure 10 presents the simulated waveforms for power transfer from output to
inputs where the power is
shared equally among the two input ports. Figure 11 presents the simulated
waveforms for power
transfer from output to inputs where the power is shared unequally among the
two input ports, as
assigned by the user.
Simulation Results: Realize full output voltage range for cascaded converter
structure of Figure 5
Simulations are provided to demonstrate the achievable output voltage range
for Zheng et at. in relation
to the proposed topology in Figure 5. The simulation models are implemented in
PLECS and correspond
to: 1) four series-cascaded two-quadrant dc/dc buck converter cells with
single L-C output filter (Zheng
et al.), and 2) a four-input single-output cascaded dc/dc converter structure
of Figure 5 (i.e. k=3). Each
converter structure has four batteries connected at the input terminals, where
each battery has a nominal
potential of 10 V. Thus, the possible range of output voltages is 0 to 40 V.
It should be reiterated the
former has one buck converter cell dedicated to switch-mode operation while
the latter employs one
converter module (comprising two buck converter cells) for possible switch-
mode operation. The
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remaining converter cells in each topology operate exclusively in low-
frequency voltage stacking mode.
As stated previously, it is assumed that duty cycle commands less than 0.1 or
greater than 0.9 are
unachievable.
Figure 12 shows both the filtered and unfiltered average output voltage (i.e.
"stack voltage")
corresponding to prior art, for all possible output voltage references. Here
one converter cell operates as
a switch mode converter at any given time, while the remaining three cells are
inserted as necessary to
build up to the desired stack voltage. Observe the three regions in the lower
plot of Figure 12 that exhibit
a "flat" voltage profile. This output response is a direct result of the duty
cycle limitation of the
switch-mode operating cell as described previously. This simulation result
clearly shows that prior art is
incapable of achieving a continuous output voltage profile. The converter
cannot provide certain output
voltages as shown, and therefore its operating range must be restricted to
avoid these undesirable
operating regions. Alternatively a rapid sorting of the cell voltages could
address the problem, however,
the cells pre-designated for low-frequency operation could no longer be
considered as operating
exclusively as such.
Figure 13 shows both the filtered and unfiltered average output voltage (i.e.
"stack voltage")
corresponding to the four-input single-output structure of Figure 5, for all
possible output voltage
references. Individual cells within the high/low-frequency cell stack operate
as switch-mode converters
when needed, and cells within the low-frequency cell stack operate exclusively
in voltage stacking
mode. The lower plot in Figure 13 clearly demonstrates the topology of Figure
5 is capable of achieving
a continuous output voltage profile. Thus, in comparison to prior art, the
proposed topology can achieve
better utilization of available cell voltage in achieving the full output
voltage range.
Figure 14 shows gating signals for the individual converter cells of Figure
13. Figure 15 shows a finer
resolution time scale for a chosen segment of simulated waveforms in Figure
14, to show contrast
between high-frequency and low-frequency switching times.
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Simulation Results: Charge balancing of cells for cascaded converter structure
of Figure 5
Simulation results are provided to demonstrate the capability for cell
balancing in Figure 5 based on the
operation strategy depicted in Figure 7. These PLECS simulations utilize the
same case study system as
utilized in the previous simulation section. That is, a four-input single-
output realization of Figure 5 is
modeled in PLECS with four integrated batteries, where each battery has a
nominal potential of 10 V.
Figure 16 plots the four battery voltages as a fixed amount of de power is
transferred to the converter
output terminals. Observe the state-of-charge of all four batteries is
depleted at the same average (i.e.
long-term) rate. This charge balancing between cells is achieved by utilizing
the operational strategy
conceptualized in Figure 7. Although implemented as a case study example for
Figure 5, this same
functionality can be implemented for Figure 4 and Figure 6 (or any variants
thereof). Recall cell
balancing can be achieved across all possible output voltages, which is not
possible using prior art.
Figure 17 shows gating signals for the individual converter cells of Figure
16. Figure 18 shows a finer
resolution time scale for a chosen segment of simulated waveforms in Figure
17, to show contrast
between high-frequency and low-frequency switching times.
Variations
Whereas specific embodiments of the invention have been discussed, variations
are possible. For
example, Figure 2 shows one possible implementation of the two pairs of
complimentary switches using
MOSFETs and Diodes, however, the switches can be implemented using a number of
different
switching devices and technologies, and, similarly, energy storage components
(i.e. inductors and
capacitors) can also be implemented with equivalents. For example, the
placement of capacitors C3a and
C3b shown in Figure 19 can be employed as an alternate output capacitor
configuration. All of these
variations should be considered as functionally similar. It is also possible
to realize unidirectional
variants of the presented bidirectional topologies, by suitable implementation
of the switching devices.
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Furthermore, Figure 4 through Figure 6 are examples of cascaded topologies
derived based on the
converter module of Figure 1 and series-cascaded buck converter cells. As
there are many other possible
functionally similar realizations of cascaded converter structures using the
basic building block in Figure
1, the illustrated embodiments should not be considered as limiting.
Furthermore, the two-quadrant buck
converter cell is explicitly employed in all topologies, however, this is not
essential. Other types of dc/dc
converter cells may be employed, for example, buck or boost converter cells.
Whereas specific operating conditions and parameters are disclosed as part of
the simulations and
others, persons of ordinary skill will understand that these are included for
illustration, only, and are not
intended to be limiting.
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