Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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Background of the Invention
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(1) Field of the Invention
This invention relates to an integrated circuit
device composed of insulated gate field-effect transistors
(hereinbelow termed "MOSIC") and also to a method of manu-
facturing the same.
(2) Description of the Prior Art
In general, the MOSIC uses aluminum or silicon as
the material of a gate electrode. On the other hand, there
are known integrated circuits (IC) in which, in an inverter
stage forming one internal circuit thereof, a load MOSFET of
the enhancement mode is employed as the load of a driving
MOSFET operative in the enhancement mode Ihereinafter cal.led
"E/E type IC") and the IC in which a load MOSFET of the
depletion mode is employed (hereinafter called "E/D type IC").
Among the IC's, the silicon gate MOSIC employing the depletion
load has recently come into extensive use as a device which is
of higher performance for various uses and has a higher
density of integration.than the aluminum gate MOSIC. According
to experiments by the inventor, the occupying area of an Si
gate MOS transistor having a self-aligned gate structure is
reduced by approximately 20 to 30% as compared with that of an
Al gate MOS transistor.
As the result of the investigation of MOSIC's
commercially available as produced by several manufacturers,
however, it has been found that, in a read only memory (here-
inbelow abbreviated to "ROM") which occupies a considerable
part of a MOSIC chip, the size of the single bit of the ROM
is not always significantly smaller in the conventional Si
gate ROM structure than in the Al gate one as indicated in
the following Table 1:
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1075~0~
Table l.: Comparisons of ROM bit sizes
IC' m ~ r Si gate ROM _ Al gate ROM type of IC
A - ~m 336 ~m2 dynamic type
C 616 650 static type
D 412 _ ..
E 441 432 __ _
Summary of the Invention
It is accordingly the principal object of this
invention to provide a novel ROM structure which is conspi-
cuously smaller in occupying area than the prior-art Al gate
or Si gate ROM' S, and a method of manufacturing such novel
ROM structure.
Another object of this invention is to provide an
IC in which the occupying area of a ROM per unit function in
the prior-art MOSIC of the Si gate E/D type is conspicuously
diminished, and a method of manufacturing such IC. -
According to one aspect of this invention, there isprovided a semiconductor integrated circuit device comp-
~ising a semiconductor body having one conductivity typeand containing a plurality of insula-ted gate field-effect
transistors each having a source, a drain and a gate and
being arranged in a matrix form in which said transistors
are disposed along a plurality of rows and columns; and
wherein the gates of transistors in each column of said
matrix are formed of a common gate electrode layer and
selected ones of said transistors are depletion type
transistors.
Other aspects of this invention are claimed in our
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Canadian patent api)lication Seria1 No. 24~,274 filed on
November 24, 1975, of which the present application is a
division, and in other applications divided therefrom.
According to another feature of the invention,
at least in preferred forms, the respective tran-
sistors are formed by a self-alignment technique
which employs the polycrystal silicon layer as a
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dif:Eusi.on ~ask. The depletio!l type transistors are formed
by implanting impurity ions opposite in conductivity type
to the substrate into selected areas of the surface of the
substrate.
Brief Description of the Drawings
FIG. 1 is a fundamental circuit diagram of a prior-
art MOSROIY,
FIGs. 2(a) and 2(b) are enlarged plan and sectional
views of a part of the prior-art MOSROM, respectively,
FIG. 3 is a fundamental circuit diagram of a MOSROM
according to this invention,
FIGs. 4(a) and 4(b) as well as A(c) are enlarged
plan and sectional views of a part of the MOSROM according to
this invention, respectively,
FIG. 5 is a diagram of a circuit which uses tne
MOSROM according to this invention,
FIGs. 6(a) to 6(f) and FIGs. 7(a) to 7(d) are
enlarged sectional views and plan views of a part of the MOSROM
according to this invention for explaining a manufacturing
process of the MOSROM, respectively,
FIGs. 8(a) and 8(b) are top pattern diagrams of
LSI chips of a MOSLSI utilizing this invention and a MOSLSI
fabricated by a prior art technique for making a comparison
therebetween, respectively, and
FIG. 9(b) is a diagram showing an example of a
circuit in the case of actually employing the MOSROM of this
invention, while FIG. 9(a) is a graph showing the measured
results of operating speeds in the circuit of FIG. 9(b).
Description of the Preferred Embod _ents
Hereunder the improved ROM (MOS matrix) according
to this invention will be described in detail in comparison
1(~7~ 0~
with a prior-art Si ~3ate ROM with reference to the drawings.
FIG. 1 shows the fundamental circuit which i5 used
in the prior-art Si gate ROM. FIG. 2(a) is a plan view
showing a part of the prior-art Si gate ROM on an enlarged
scale, while E'IG. 2(b) is a sectional view of the part of the
prior-axt Si gate MOSROM as taken along a line X - X' in FIG.
2(a).
As illustrated in FIG. 1, the prior-art Si gate
MOSROM consists of MOSFET's which are arranged in parallel.
The states of the respective memory cells are discriminated
by the thicknesses of gate oxide films. A signal of low level
close to a supply voltage is applied to a selected address
line, whereas a signal of high level close to 0 (zero) volt
is applied to an unselected address line. Considering by
way of example a case where a line IN2 is selected, the MOSFET
underlying this line has a thick gate oxide film and is
usually "off," so that the output level becomes the low
level. As shown in FIGs. 2 (a) and 2(b), such prior-art ROM
is constructed of P -type diffused layers 2, 3 and 4; poly-
crystal silicon layers 7 and 8; silicon dioxide films 5 and6; phosphosilicate glass 9; a through-hole 11; and an aluminum
layer 10. The polycrystal silicon layer is used as an address
input line, while the aluminum layer is used as an output
line. The through-holes between the Al layer and the P -type
diffused layers are necessary for commonly connecting the
drain electrodes of the MOSFET's which are arranged at each
row. As apparent from the figures, the states of the memory
cells at the points of intersection between the input lines
and the output lines are determined by the thicknesses of the
gate oxide films. More specifically, where the MOSFET which
conducts the "on-off" operation by the signal voltages
4 --
1(~7~ V~
applied to the illpUt line is necessary at a certain point of
inter-section, the gate oxide film beneath the polycrystal Si
layer at that place is made thin, while at the place where the
MOSFET which conducts such operation is unnecessary, the oxide
operation is unnecessary, the oxide film beneath the poly-
crystal Si layer at that place is made thick. Thus, the ROM
having a predetermined bit pattern is constructed. The minimum
size per unit bit of the Si gate ROM of such construction is
about 410 ~m , and it is substantially equal to that of the Al
gate ROM.
As described above, the conventional ROM is character-
i~ed by the following construction:
(1) The states of the respective memory cells are dis-
tinguished by the thickness of the gate oxide films.
(2) Since the self-aligned gate structure is adopted, the
polycrystal Si layer cannot cross over the P -type diffused
layer. Therefore, the Al wiring layer is necessitated, and the
through-hole is required between the P+-type diffused layer
and the Al layer.
Accordingly, the occupying area per bit of the prior-
art Si gate ROM cannot be made small in spite of the adoption of
the self-aligned structure.
The Si gate MOSROM according to this invention will
now be explained with reference to Fig. 3, Figs. 4(a), 4(b) and
4(c), and Fig. 5.
Fig. 3 shows the fundamental circuit which is
employed in the ROM according to this invention. It is composed
of a plurality of enhancement mode and depletion mode MOSFET's
which are connected in series as driving elements. The deple-
tion mode MOSFET functions also as one resistance element. A
read-out is stably executed in such way that a signal of high
~Ot7~i~v~g
level close to 0 (zero) volt is i~pressed on a selected address
line. At this time, a signal of low level is impressed on an
unselected a~drc~s I inc.
By way of example, in case where the address line IN2
is selected, the MOSFET underlying this address line IN2 turns
"on" as it is the depletion mode MOSFET. Since the MOSFET's
associated with the other address lines INl, IN3, ..... and INn
are the enhancement mo~e MOSFET's, they turn "on" by having the
low level signal applied to their gates. Since the MOSFET
associated with the address line INn 1 is the depletion mode
MOSFET, it is "on" even when the low level signal is applied to
its gate. In this case, accordingly, all the driving elements
are substantially "on," so that an output signal of high level
close to 0 (zero) volt is produced at an output terminal OUT.
On the other hand, in case where the address line IN3
is selected, the MOSFET associated with this line becomes the
nonconductive (off) state by the input signal of high level as
it operates in the enhancement mode. Therefore, an output
signal of low level appears at the output terminal OUT.
As apparent from the above explanation, in the ROM
according to this invention, the output data line to be pre-
charged holds the low level or is shifted to the high level in
dependence on whether the enhancement or depletion mode MOSFET
is addressed, respectively.
Fig. 5 shows a ROM circuit which is constructed by
applying this invention to an actual ROM of MOSIC on the basis
of the fundamental circuit of the invention illustrated in Fig.
3, and which comprises the first address decoder MOS matrix and
the second MOS matrix receiving an output of the first MOS
matrix as its input. A flip-flop circuit 21 consists of a
plurality of stages (for example, k/2 stages) connected in
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cascade. Outputs from the respective stages are delivered
directly or through inverter circuits 22 into the first MOS
matrix 23, whose outputs are delivered into the second MOS
matrix 24. The second MOS matrix provides outputs OUT 1 to
OUT n. The matrices 23 and 24 have one MOSFET operative in
the depletion or enhancement mode in any of the places in
which input lines and output lines intersect. Such FET's
are connected in series between a supply voltage VDD and a
reference potential source (earth) at every column. Connected
to the respective matrices as loads of the driving MOSFET's
are enhancement mode MOSFET's (27, 28) which have clock
signals applied to the gates thereof. In the figure, the
driving MOSFET's with circles as indicated at 25 are those
operating in the depletion mode, while the other driving
MOSFET's are those operating in the enhancement mode. Each
of the plurality of in~erters 22 consists of a driving MOSFET
which operates in the enhancement mode, and a load MOSFET
which is connected in series therewith and which operates
in the depletion mode. As will be stated later, all the
MOSFET's in the figure have gate insulating films (for
example, Si02 films) of substantially equal thicknesses (about
500 to 1,500 angstroms) irrespective of the depletion mode
or the enhancement mode. The depletion MOSFET's in the MOS
matrices are formed simultaneously with the depletion
MOSFET's in the inverters 22 by quite an identical process.
The input lines of the first and second matrices are formed
of polycrystal silicon wiring layers, while the connection
from the output line of the first matrix to the input line
of the second matrix is performed by the use of an aluminum
wiring which connects a P+-type diffused layer and the poly-
crystal Si layer. When FIG. 5 is studied with reference to
1(~79~V~
FIG. 3, the operation of the circuit in FIG. 5 will be self-
expl.anatory. To be particularly mentioned is that clock
pulses ~1 and ~2 whose phases differ from each other are
impressed on the gates of the load MOSFET's in the first and
second matrices, respectively, and that the amplitudes of
these pulses (for example, -12 to -16 volts) are greater
than the amplitude of the supply voltage VDD (for example,
-6 volts).
Referring now to FIGs. 4(a), 4(b) and 4(c), the
device structure of the MOSROM according to this invention
will be described. FIG. 4(a) is a plan view with a part of
the MOSROM enlarged, while EIGs. 4(b) and 4(c) show X - X'
and Y - Y' sections in FIG. 4(a), respectively. In the
figures, numeral 31 designates an N-type single crystal Si
substrate; numerals 32 to 34 and numerals 47 to 49 P -type
diffused layers which are formed by being self-aligned by
Si gate electrodes; numerals 35, 36 and 43 gate insulating
films of silicon dioxide which have essentially equal thick-
nesses (about 1,000 A); numerals 37 and 38 input lines of
polycrystal Si; numeral 39 an insulating film of phosphosili-
cate glass; numerals 41 and 42 P-type channel layers which
are formed by implanti.ng P-type impurity ions into selected
areas of the surface of the substrate in order to form the
depletion MOSFET's; and numerals 44 to 46 field insulating
films of silicon dioxide which are comparatively thick
(about 1 to 2 ~). As apparent from the figures, one memory
cell is formed in any of the places of intersection between
the polycrystal Si wiring layers (37, 38) as the address
input lines and the P -type diffused layers as the self-
connected data output lines. The states of the respectivememory cel.ls are determined by the presence or absence of
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i(~'7~
the P-type channe1 formed by the ion implantation. All the
memory cells have the thin gate oxide films so as to operate
as the enhancement or depletion MOSFET.
As seen from the figures, the MOS matrix according to
this invention has the self-aligned gate structure and
needs no through-hole. It is therefore understood that the
occupying area to the single bit is remarkably smaller in
the MOS matrix of this invention than in the prior-art one.
FIGs. 8ta) and 8(b) show by comparison the semiconductor
chip sizes and the occupying areas of respective circuits
in the cases where MOSIC's for achieving the same circuit
function are formed by the technique of this invention and
by the Si gate MOS manufiacturing technique of the prior-art,
respectively. By the adoption of the MOS matrix according
to this invention, in comparison with the case of adopting
the mere self-aligned type Si gate MOSROM, the ROM part
which occupies a comparatively large area in the 1SI is
reduced by approximately 50~. As the result, it becomes
possible to lessen the whole chip size by approximately 20~.
The operating speed of the ROM according to this
invention will now be explained with reference to FIGs.
9(a) and 9(b). Since a ratioless circuit as shown in FIG.
9(b) is employed, the output level of the ROM has two
states, and as previously set forth, the precharged data
line holds the low level or is shifted to the high level.
In this case, the o~erating speed of the ROM is mainly
dependent upon the discharge time td in which the pre-
charged data line is shifted to the high level. FIG. 9(a)
illustrates the measurements of the relationship between the
discharge time of the MOSROM shown in FIG. 9(b) (the axis of
ordinates, td) and the amplitude of the clock pulse supplied
to the gate o~ the load MOSFET of the enhancement mode (the
axis of abscissas, V ), the MOSROM possessing 48 address
lines and having 48 enhancement or depletion MOSFET's con-
nected in series. Herein, the output capacitance of the ROM
is made approximately 1. 5 pF. As seen from the graph, the
discharge time is smaller than 1.5 ~s. Especially as an IC
for an electronic desk top calculator, essentially no pro-
blem is posed in practical use because an operation in the
order of 100 KHz is possible.
Description will now be made of a method of manu-
facturing the MOSROM according to this invention as shown in
FIGs. 4(a) to 4(c) and FIG. 5, reference being had to FIGs.
6(a) to 6(f) and FIGs. 7(a) to 7(d). First, an Si02 film
being about 1.4 ~ thick is formed in the surface of an N-type
Si single crystal substrate 31 whose one principal surface
is the (1 1 l)-face and which has a specific resistance of
5 to 8Qcm. Thereafter, those parts of the Si02 film on the
pr~ncipal surface of the substrate at which the MOSFET's are
to be formed are removed in the shape of narrow slots. The
exposed substrate surface is oxidized to form a thin Si02
film 30 (gate oxide film) of about 1,200 A there (refer to
FIGs. 6(a) and 7(a)). Subsequently, boron ions are implanted
into the substrate surface through the thin Si02 film 30 at
a concentration of about 1.4 x 1011 k/cm2. Further, a
photoresist material layer 50 is deposited onto that part of
the thin oxide film 30 on the substrate surface at which the
depletion MOSFET is not to be formed. Using the photoresist
layer and the thick oxide film as a mask, boron ions are
again implanted into the substrate surface through the
exposed thin Si02 film at a concentration of 6.5 x 1011 k/cm2.
Thus, the P-type region 41 which constitutes the channel of
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1(~ 7~3 ~
the D-MOSFET is formed (refer to FIGs. 6(b) and 7(b)).
Subsequently, the photoresist layer is removed. Polycry-
stal silicon is deposited on the entire oxide films to the
o
extent of about 5,000 A. Those parts of the polycrystal Si
layer which are other than parts for constructing the
address lines (37, 38) are removed (refer to FIG. 6(c)).
Subsequently, using the parts 37 and 38 of the polycrystal
Si layer left behind, the thin Si02 film 3~ is removed to
expose the substrate surface (refer to FIGs. 6(d) and 7(c)).
Subsequently, by employing the polycrystal Si layer 37, 38
and the thick Si0~ film 40 as a mask, boron is diffused into
the exposed substrate surface by the conventional vapor dif-
fusion process. Thus, the P+-type diffused regions 32, 33,
34, 47, 48 and 49 having a thickness of about 0.8 ~ are
formed (refer to FIGs. 6(e) and 7(d)). Thereafter, the
phosphosilicate glass (PSG film) 39 having a thickness of
about 0.9 to 1 ~ is deposited from vapor, to finish the
MOSROM as shown in FIG. 6(f). In this way, there is produced
the MOS matrix of the preseht invention as comprises the
combination of the enhancement mode and depletion mode
MOSFET's having the gate oxide films of substantially equal
thicknesses. As described above, in the MOS matrix of this
invention, tne respective input lines of the polycrystal Si
and the respective P -type diffused layers intersect sub-
stantially orthogonally, and all the insulating films under
the polycrystal Si layers in any place of the intersection
are made the equal thickness of about 1,200 A, so that the
transistor operation is positively carried out. Which
transistors are made the depletion type is determined by the
implantation of the boron ions as illustrated in FIG. 6(b).
Such technique of fabricating the depletion MOSFET's is not
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lo~
especially added, but in case of forming the circuit as
shown in FIG. 5 or FIG. 9(b) within the sur~ace of a single
semiconductor substrate, the aforecited MOSFET'S are fabri- -
cated by the same process as that of the other depletion
~IOSFET's, for example, the depletion load MOSFET's of the
inverters.
To sum up, the ROM according to this invention has
the following features:
(1) The ROM of this invention is constituted of the
enhancement type and depletion type MOSFET'S as the
driving elements.
(2) The size of the ROM of this invention is
remarkably small, and it is reduced by about S0~
as compared with that of the ROM of the prior-art
Si gate structure.
(3) The ROM of this invention is fabricated by a
process which is compatible with the Si gate MOSLSI
employing the depletion loads as is presently
being used extensively.
(4) The cascade ratioless circuit is applicable to
the ROM of this invention, and LSI'S with extra-
ordinarily excellent characteristics can be
realized by paying sufficient attention to the
estimation of the operating speed.
The idea of this invention as stated above can also
be applied to other complicated logical circuits such as a
programmable logic array and a four-phase ratioless dynamic
circuit. It is accordingly to be understood that the scope
of right of the present application is not restricted to
the foregoing specific aspects of performance.
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