Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
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Background~of the In~ention
This invention generally relates to digital data process-
ing systems. More specifically it relates the interconnection of
various units in such a system and the transfer of data among
t~ose units~
A dig~tal data processing system comprises three basic
elements: namely, a memory element, an input-output element and a
processor element, The memory element stores information in
addressable storage locations~ This information includes data
and instructions for processing the data. The processor element
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transfers information to an~ from the memory elem~nt, interprets
the incoming information as either ~ata or instruc~ions and
processes data in accordance with the instructions. The input-
output element also communicates with the memory element in
order to transfer input data to the system and to obtain
processed data from it.
Over the years many different types of digital d~ta
processing systems have been developed. However, this
development primari]y has been directed toward evolving new
processor e~ements with more efficient architecture, larger and
faster memory elements an~ more sophisticated input-output
elements. There has been little change in the technoloqy
involved in transferring information among the various elements
in the data processing ~ystem. In fact, all the data processing
systems of which we are aware can be classified by the basic
timing methods that they use. There are essentially two timing
categories: synchronous and asynchronous timing.
Digital data processing systems that utilize
synchronous timing usu~l]y include a master c~ock that controls
all operations in all elements. This master clock generates
timing signals that contro] operations in the processor element
and als~ in the memory and input-output elemen~s that connect to
an interconnecting bus. Ps al~ the e]ements in ~he system are
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synchronized to the master clock, the master clock frequency
must be set to operate in a way that is compatible with the
slowest element in the system. The transfer rates between
elements i~pose ulti~te limitations on the speeds with which
S the faster elements can operate. Thus a slow trOnsfer rate s]ows
the entire system so that the system runs below the theoretic~l
efficiency of many of its component units.
~ther digita~ data processing system~ utilize
asynchronous timing over their interconnections. With
asynchronous timinq eech e]ement is free to operate at its most
efficient rate. Typically two elements communicate with each
other when one element initiates a ~ata transfer over an
interconnecting bus. Then the one element controls the bus to
the excl~sion of a~] third elements in the system until the
other element acknowledges that the re~uested transfer hos been
complete~. Cystems using asynchronous timin~ tend to be somewhat
faster than their counterpart synchronous systems because they
can make some transfers at a greater rate than the slowest
ele~ent in the system, while maintaining the ability to
communcicate more s~owly with the s]ower e]ements. However,
asynchronous transfers do have ~rawbacks in some app]ications.
In some asynchronous systems, once a tr?nsfer operation has been
initiated, the entire bus is unavailable to any elements other
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than the two involved in the transfer until that transfer is
completed. ~hus transfers involving slower ele~ent~ hold up
operation of the faster elements and reduce their efficiencies
below their theoretical levels.
Despjte the ~rawbacks of both synchronous 2nd
asynchronous transfers, mo~t digital data processing systems
still are built solely around either one or the other, but no~
both ti~ing schemes. ~he selection of one over the other
apparently depends upon the predicted app]ic~tions for the
~iqital data processing syste~. ~hus, in some applications
unacceptab~e operating speeds may be encountered whi~e in others
the speeds are accept~ble.
Therefore, it is an object of this invention to
provide an interconnection for the ele~ents of a diqital data
processing system that uti!izes the desirable characteristics of
both synchronous and asynchronous timing.
Pnother ob~ect of this invention is to provi~e an
interconnection for the e]ements oF a digital data processing
system that enab]es the e]ements to communicate over the
interconnection at very high speeds.
Yet another object of this invention is to provide a
digital data processing system in which the elements exchange
information efficiently and without unduly delaying information
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exchanges among other elements in the system.
In accordance with this invention, an interconnection
for elements in a data processing system transmits timing signals
that establish timing intervals. Each element is enabled to trans-
fer information over the interconnection by an access control that
responds to those timing signals and access control signals from
the interconnection. Information is trans-ferred during a timing
interval in response to the timing signals and to the access con-
trol. Confirmation signals are transferred during a subsequent
timing interval in response to the information transfer and the
timing signals.
More particularly, according to the invention, there is
provided in a data processing system, including timing means for
generating timing signals that define successive transaction inter-
vals, and a system interconnection means including bus access con-
trol signal interconnection means for transferring bus access con-
trol signals, information slgnal interconnection means for trans-
ferring information signals, and confirmation signal interconnec-
tion means for transferring confirmation signals, a nexus means
comprising: bus access control means connected to said bus access
control signal interconnection means and to said timing means for
transferring bus access control signals and for controlling the
access of its respective nexus means to said system interconnection
means in response to bus access control signals, information trans-
fer means connected to said information signal interconnection
means, said bus access control means, and said timing means for
transferring information signals, and confirmation transfer means
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connected to said confirmation signal interconnection means, said
information transfer means, and said timing means for indicating
the status of an information transfer a predetermined interval
after the information transfer by transferring confirmation signals,
said information transfer means and said confirmation transfer
means being responsive to the timing signals from said timing means
to establish transaction sequences each comprising a plurality of
successive transaction intervals, each transaction sequence in-
cluding an information transfer interval and a subsequent confirm-
ation interval, said information transfer means transferring inform-
ation during the information transfer interval of a particular trans-
action sequence and said confirmation transfer means transferring
corresponding confirmation signals during the confirmation interval
of that particular transaction sequence, said system interconnection
means being able to transfer information signals and confirmation
signals corresponding to different transaction sequences during a
particular transaction sequence whereby plural transaction sequences
are overlapped.
According to another aspect of the invention, there is
provided a data processing system comprising timing means for gener-
ating timing signals, that define successive transaction intervals,
system interconnection means including: bus access control signal
interconnection means for transferring bus access control signals,
information signal ;nterconnection means for transferring information
signals, and confirmation signal interconnection means for transfer-
ring confirmation signals, a plurality of nexus means each including:
bus access control means connected to said bus access control sig-
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nal interconnection means and to said timing means for transferring
bus access control signals and for controlling the access of its
respective nexus means to said system interconnection means in
response to bus access control signals, information transfer means
connected to said information signal interconnection means, said
bus access control means, and said timing means for transferring
information signals, and confirmation transfer means connected to
said confirmation siynal interconnection means, said information
transfer means, and said timing means for indicating the status of
an information transfer a predetermined interval after the inform-
ation transfer by transferring confirmation signals, said informa-
tion transfer means and said confirmation transfer means being re-
sponsive to the timing signals from said timing means to establish
transaction sequences each comprising a plurality of successive
transaction intervals, each transaction sequence including an in-
formation transfer interval and a subsequent confirmation interval,
said information transfer means transferring information during the
information transfer interval of a particular transaction sequence
and said confirmation transfer means transferring corresponding
confirmation signals during the confirmation interval of that part-
icular transaction sequence, said system interconnection means being
able to transfer information signals and confirmation signals cor-
responding to different transaction sequences during a particular
transaction interval whereby plural transaction sequences are over-
lapped.
The invention will now be described in greater detail
with reference to the accompanying drawings, in which~
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Figure 1 ls a block diagram of a digital data process-
ing system eonstructed in aeeordanee with this invention;
Figures 2A through 2D picterially depict data types
that are
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utilized in conjunction with a specific embodlment of this inven-
tion;
Figure 3 illustrates the lines and corresponding signals
that constitute an interCQnnection for elements in the digital data
processing system in Figure l;
Figures 4A through 4K are graphs or timing charts, that
depict the various clocking signals and timing intervals that syn-
chronize transfers of information between the elements shcwn in
Figure l;
Figure 5 is a diagram that depicts sequences of trans-
actions that can occur between the elements shown in Figure 3;
Figure 6 is a detailed block diagram of the central pror
cessor unit 10 shcwn in Figure l;
Figure 7 is a block diagram of the data paths within the
SBI control shown in Figure 6;
Figure 8 is a detailed block diagram of relevant portions
of control logic shcwn in Figure 7;
Figure 9 is a timing diagram that is useful in understand~
ing the operation of the SBI control show.n in Figure 6 through 8
during a reading operation;
Figure 10 is a timing diagram that is useful in understand-
ing the cperation of the circuitry shown in Figures 6 through 8 dur-
ing a writing operation;
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Figure 11 is a block diagram of a m~mory controller and
mentory array as sho~ln in Figure l;
Figure 12 is a block diagram of a portion of the memDry
controller shown in Figure 11,
Figure 13 is a block diagram of another portion of the
controller shown in Figure 11; and
Figure 14 depicts registers that are utilized in the
m~ttory controller shown in Figure 11.
Descri~tion of an Illustrative Embodinten
General Discussio.n
i. Data Processing System
.
Referring to Figure 1, the basic elements of a data pro-
cessing system that embodies our invention comprises a central pro-
oessor unit 10, memory units 11 and I/O units 12. A sync~ronous
backplane interconnection (SBI) 14 interconnects the central pro-
cessor unit 10, mentory units 11 and I/O units 12.
m e central processor unit 10 comprises an operator's
console 15, an SBI interface and memory cache circuit 16, an
ctddress translation buffer circuit 17, an instruction buffer cir-
cuit 18 and a data path and internal register circuit 19. me SBI
interface and memory cache circuit 16 provides the necessary inter-
facing circuitry for transferring information over the SBI
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14 to the memory units ll and J/0 units 12. ~he circuit 16
receives all dat2 from the memory and all ~ddress trans]~tions
from the buffer circuit 17. It incl~des an associative memory,
or c~che. Fach time data is written into t~e cache memory in the
circuit lh fro~ the dat~ path an~ internal re~ister circuit 1,
th?t d~ta is a]so ~ritten into ~ corresponding ]o~tion in tke
~emory unit 11.
This specific embodiment of the central processor ~0
operates with virtua] addresses. The ~ddress tr~nslOtion buffer
circuit 17 converts the virtu~] ad~resses to physica] addresses
which the memory cache circuit 16 uses either to determine
whether it contains data from the correspondin~ location or to
initiate a transfer from the corresponding actual loc~tion in
the memory unit 11. The instr~ction buffer circuit ~P includes
~eans for storing instructions, or portions thereof, as they are
retrieved either from the cache memory directly or from the
memory unit 11.
~he operator's console 1~ serves as the operator
interface. ~t allows the operator to examine ~nd deposit data,
ha]t the operation of the central proces~or unit 10 or Ftep it
through a se~uence of program instructions. ~t also enables an
operator to initialize the syste~ through ~ bootstrap procedure
~nd perform vario~ dia~nostic tests on the entire data
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Pg. 10
processing ~yste~.
s ~ s e
~-~ In Fig. 1, the me~ory un~ 11 ~em~}s~s two memory
controllers 20A and 20B. ~ach memory control]er connects to a
plura~ity of memory arrays. Cpeci~ically, memory control]er 2nA
connects to memory arrays 21P while memory contro]]er 2~P
connects to memory arrays 7]B. ~he operation of the memory unit
ll is disclose~ in detail later .
Several types of I/~ units ]2 are shown. Pn I/~ bus
adapter 22 interconnects various input/output (I/~) devices 23,
such as teletypewriters, to the bus 14. The interconnection,
operation and transfer of signals between the I/~ ~us adapter 22
and the J/~ devices 23 ic disclosed in U.~. P~tent 3,710,~24.
Two other I/O units 12 provide a secondary storaqe
facility for the data processing system. They include a
second~ry storage bus adapter 24 a~d ~ plurality of disk drives
25. There is also shown a secondary storage bus a~apter 2fi and a
tape drive 27. ~he interconnection of the secondary storage bus
adapters ~4 and 2~ and their respective disk drives 2~ ~nd tape
drive 27 is disclosed in the foreaoing U.S. Patent 3,q99,163.
As apparen~ from Fig. 1, the SB~ ~4 interconnects the
various units in the data processing system. In accordance with
this invention, the v~rious circuits that connect to the SPI 14
interact over the SBI 14 in an extreme]y efficient manner. To
understand the transfer of information between different pairs of
units connected to the SBI 14, it will be helpful first to
establish some definitions for terms that have already been used
and that will be used throughout the remainder of this description.
"Information" is intelligence used to control and provide j
the basis for data processing. It includes address, data, control
and status information. "Data" includes information which is the
object of or result of processing.
Transfers of information between units in the data pro-
cessing system shown in Figure 1 occur over the SBI 14 and involve
transfers of discrete information items. Each information item has
a characteristic size on the SBI 14. Other elements may process
information items having other sizes. The most elementary informa-
tion item is a byte. In one specific embodiment of the data pro-
cessing system shown in Figure 1, the byte includes eight binary
digits (or bits). Figure 2A depicts a number of contiguous bytes.
The next larger data item size is a "word". A "word" as shown in
Figure 2B, comprises two contiguous bytes. As shown in Figure 2C,
two contiguous words constitute a "longword". Two contiguous long-
words constitute "quadword" as shown on Figure 2D.
The SBI 14 transfers all the information in a longword in
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parallel. Figures 2A through 2D collectively illustrate four
guadwords. In the guadword shown in Figure 2A, byte 0 is in the
least significant byte position while word 0 and longword 0 are in
the least signi-Eicant word and longwvrd positions of 2B and 2C
respectively. The following discussion assumes that ~orresponding
alignments are maintained within the data processing system. How-
ever, there is no requirement that any such alignments be maintained.
Indeed, as described in above mentioned United States Patent
4,236,206, transfers may occur without maintaining this alignment,
as when a oe ntral processor unit transfers a longword beginning at
some other byte boundary.
If two eleme~ts are to exchange informQtion over the SBI
14, at least two "SBI transactions" are necessary. During a first
SBI transaction, one element requests the information exchange and
transmits ccmmand and address information onto the SBI 14. The
other element, designated by the address information, responds and
prep æes to-oamplete the information exchange. This completes a
first SBI transaction. During a second SBI transaction the informa-
tion to be exchanged passes over the SBI 14. A third SBI trans-
action for transferring still additional information is also poss-
ible.
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Each element that connects to the SBI 14 is called a
nexus. The specific system shown in Figure l includes six nexuses.
A nexus further is defined in terms of its function during an
exchange of information. During such an exchange/ the nexus that
transmits command and address information onto the SBI 14 is called
a "commander nexus". The unit which responds to that command and
address information is called a "responder nexus". Thus, if the
central processor needs to retrieve data from the memory controller
20A, the central processor unit becomes a commander nexus and trans-
mits a read ccmmand and memory address during a first SBI trans-
action. The memory controller 20A becomes a responder nexus when
it reoeives and accepts the command and address information from
the SBI 14. During the second SBI transaction the mem~ry controller
20A transfers the requested data back to the central prooessor unit
10.
A nexus also is defined as a "transmitting" or "re oeiving"
nexus. A transmitting nexus drives the signal lines while a re oeiv-
ing nexus samples and exa~ines the signal lines during each bus
transaction. In the foregoing example, the central prooessor unit
is a transmitting nexus during the first SBI transaction and a
reoe iving nexus during the second SBI transaction. Similarly, the
~emory controller 20A is a receiving nexus during the first bus
transaction and a transmitting nexus during the second SBI trans-
action. Similar transactions occur
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Pg. 14
for information exchanges between any two nexuses. However, the
memory control]ers normally function onJy as responder nexuses
while central processor units nor~al~y f~nction only as
commander nexuses.
Typical infor~ation exchanges with the centr~]
processor unit 10 over the S~I 14 involve ~ata to be interpreted
in the central processor unit as instructions, operand
specifiers and data. Other transfers will route data from the
central processor unit back over the S~I unit ]4 for transfer to
other ele~ents, or units, connected to the SB~ 14.
Likewise, the other ~nits shown in Fig. 1 can initiate
infor~ation exchanges over the SBI 14. Typical exchanges would
include transfers between one of the disk drives 2~ or t~pe
drive 27 and one of the me~ory units 11. The I/~ devices 23 a3so
communicate with the memory control]ers 11.
Each of the memory controllers 20~ and 20B and the bus
adapters 22, 24 and 26 contain various controJ registers. At
different ti~es during the operation of the data processing
system, progra~s being executed by the central processor 10 may
transfer information directly to or fro~ one of these control
registers over the S~I 14 without involving the memory
controllers 20P or 20B. All these transactions over the SBI 14,
however, are basica]ly the same because each control register
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that connects to the ssI 14 has a memory address. More
sPecifically, the command-address information hzs the capability
of addressing a predetermined number of memory ]ocations. The
maximum va~ue of this number depends upon the number of bit
positions in the addres~, and it defines the available memory
space as a number of bytes. ~ portion of the available memory
space is reserved for the ~tora~e locations in the memory arrays
2~A and 21P. The remaining ?vailable space is reserved for these
control registers. Thus, each storage location in the data
processing system, whether it comprises a storage location in a
memory array or a control register has a unique memory address.
This feature of the ~ata processing sy~tem shown in
Fig. 1 eliminates the need for input/output instructions. ~s a
result, the SBI interface and memory cache circuit 16 or any
other element connected to the SBI 1~ can access any memory
location u~ing the ~ame basic operations a~ it would if one of
the memory units 11 were being accessed. Conseauently, a
description of information exchanges between the S~I interface
and memory cache circuit 16 of the central processor unit ln and
the memory controller 20P and one of the memory arrays 21P in
the memory units 11 essentially describes the information
exch~nqes between any other units connected to the ~I 14.
VariationE or modifications re~uired for a specific one of the
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Pg. 16
adapters 22, 24 ?nd 2fi will be based upon the specific function
of those adapters and will, based upon the following disc~ssion,
be apparent to anyone of ordinary ski]l in the art.
ii. ~he Synchronous ~ackplane Interconnect tSBI) 14
In aCCOrd?nce with one specific embodiment of this
invention, the SBI 14 conveys a number of signals to and from
the vario~s units that connect to it over corresponding
conductor positions~ These conductor positions and signals can
be listed in five c~asses:
~. arbitration;
2. information transfer,
~. response;
4. contro]
~. interrupt request;
~11 these signa]s are maintained in synchronism with
clocking signals that constitute some of the signals on the
control conductor positions. ~hese clocking signz]s are shown in
Fig. 4. Specifically, a clocking circuit utilizes signals from a
- master clock (e.g.,-~ff~ clock generator 70 in Fig. 6~ to
generate a number of signals. Figs. 4P and 4B depict
co~plementary TP signa]s th?t are de~icnate~ as a ~P~ signa~
an~ a ~P-L signal respectively. The clocking signals also
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include quadrature-phase signals at half the frequency of the TP
signals. mese are depicted as PCLK-H and PCLK-L ccmplementary
clocking signals in Figures 4C and 4D and camplementary clocking
signals PDCLK-H and PDCLK-L signals in Figures 4E and 4F. The fore-
going signals are clock signals that appear on conductors 30 of the
SBI 14 shawn in Figure 3.
Each nexus includes circuitry for deriving the timing
signals that are ne oessary to perform transactions over the SBI 14.
As shawn in Figures 4G through 4J, these signals include TOCLK
through T3CLK quadrature signals, each having a 25% duty cycle at
half the frequency of the TP signals. The leading edges of the
TOCLK through T3CLK pulses define TO through T3 clocking times as
shawn in Figure 4K. The time interval between sucoessive TO times
is called a bus cycle time. Generally, a transmitting nexus trans~
fers information onto the SBI 14 at a TO time. A receiving nexus
samples the SBI 14 at a T3 time. In one specific embodiment of
this invention, the interval between sucoessive TO times is about
200 nanoseconds.
As will ncw be apparent, each nexus that connects to the
SBI 14 can transfer information over the SBI 14. Same means to con-
trol access to the SBI 14 must therefore be provided. The arbitra-
tion signals on arbitration (TR) conductors, or lines, 31 in Figure
3 provide this control function. Each nexus has a predetermined
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P~
bus access priority assigned to it. In this specific embodiment,
there are sixteen arbitration lines that are designate~
respectively as TR~0 throuah TR15 lines. The TR0Q signal
constitu~es ~ H~ siana] and connects to every nexus. Fach of
the TR01 through T~15 lines has assigned to it a priority. The
highest priority nexus transmits an acces~ contro] signal on the
T~01 line and the second lowest priority nexus transmits another
access control signal on the TR15 line. ~he lowest priority
nexus ~oes not ~ransmit any access control signal. Each nexus
responds to access contro~ siqnals from nex~ses that have
priorities that are higher than the priority ~ssigned to that
nexus and to the HOL~ signal.
When a nexus~ other than the nexus having ~e lowest
priority, such as the nexus 32 shown in Fig. 3~desires to gain
access to the cpJ 14, it conditions an arbitration circuit 33~
to transmit its access control signal on its assigned T~ line at
a ~n time. Pt the next T' time, the arbitration circuit 33~
samples all the access control signals from higher priority
nexu~es ~n~ the HOLD signa~. If such an acces~ control signa~ or
the ~LD signal is being transmitted, the nexus 32A continues
sampling tke access control signals at each successive T~ time
until no access control signa] from a higher priority nexus or
the ~L~ signal is received. When, at a T3 time, no quch siqnals
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are re oeived, the arbitration circuit 33A enables the information
transfer circuit 56A to begin transmitting information transfer
signals at the following T0 time.
As previously indicated, the lowest priority nexus trans-
mits no ac oess control signal, but it receives all the access con-
trol signals and the HOLD signal. If this nexus wishes to gain
acoess to the SBI 14, it can do so provided at a particular T3 time
none of the access control signals and the HOLD signal is received.
It is not ne oessary for this nexus to delay its first saTrlpling of
the TR lines. Consequently, this nexus actually has shortest
acoess tlme to the SBI 14. For that reason the oentral processor
unit 10 normally is assigned the lowest priority in the digital
data processing system.
The information transfer signals and their corresponding
lines 34 are grouped in four subgroups. mey include (1) parity
check lines 35, (2) information tag (TAG) lines 36, (3) identifica-
ti~n (ID) lines 37, and (4) information lines 40.
m ere are two parity check lines 35. A P0 line carries a
parity signal for the signals on the tag lines 36, ID lines 37 and
mask lines in the information lines 40. A Pl line carries parity
for the signals on the other information lines 40.
m e tag signals are generated by a tag circuit 60A in
transmitting nexus. They control the interpretation of the
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signals on the ID lines 37 and the inf~rmation signals 40 by ~D
and information ci.rcuits ~7B and ~he. There are four general.
types of inform~tion th~t are c~rried over the information lines
40. They include read data, co~mand-address, write dat~ and
interrupt summary read information. A set of tag bit values that
correspond to each of these types control the interpretation
given to the mask signa~s on the information lines 40 by the
infor~at.ion circuit 56P. For ex~mple, if the tag signals specify
that the information is data th~t has been re~ from somP
location, the mask bits can be interpreted to indicate whether
the d~ta is actu~l data, corrected data or substituted dat2.
When the tag bits specify that the infornation on the
information lines 40 constitutes d~ta to be written into some
]ocation, the mask bits specify which of four contiguous bytes
in the addressed longword location wi~ be written~
h7hen the t2g bit value specifie~ that the information
of the information ~ines 40 constitutes a command ~nd address,
t~e information is divided into two fields. P first field is a
function fie~.~, the second, an address field. The function field
specifies different types of readinq and writing operations to
be performed by the responder. ~he m~sk bits may or may not be
used with individual ones of these operations.
There ~re six basic operations which the function
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field can define; and they include (1) a masked reading operation
(2), an interlocked masked reading operation (3), an extending read-
ing operation (4), a masked writing operation (5), an interlocked
masked writing operation and (6) an extended masked writing opera-
tion. With the exoeption of the extended reading operation, all
these operations utilize the information in the mask field.
Response lines 41 include a fault line 43 and two CNF
lines 44. Whenever a transmitter nexus transmits information on
the SBI 14 during a bus cycle, the receiving nexus decodes the
address and, two bus cycles later, trarsmits a confirmation of the
proper receipt of that information. Each nexus samples the signa]s
on the SBI at the T3 time of each successive bus cycle. merefore,
each transmitting nexus must include circuitry for distinguishing
those confirmation signals that are in response to each of its
transmissions.
me confirmation lines 44 may define one of four states:
namely an unasserted state that indicates no response or selection;
an acknowledge (ACR) state as a positive acknGwledgment to a trans-
fer; a busy state in response to a sucoessful selection of a nexus
that is presently unable to respond further to the command; and an
error state when a successful selection of a nexus has been made
but the nexus cannot execute that type of command.
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The FAULT line 43 carries a FPULT signal that in~icates
whether any information path parity error, write seauence error
or other error conditions exist.
Control lines 45 include the the clock lines 30 as well
as four other control ]ines.
An ~NJA~ ]ine 4~ in the central lines 45 carries a
signal from the central processor unit 10 that establishes an
initial condition in all the other ~]e~ents and t~e U~J~M signal
thereby constitutes a system initializing signal.
P FPIL signal on line 47 is as~erted by a neXuC if it
is an essential element in the data processing system and its
power is fai]ing. The centra] processor unit ln is the on~y
nexus that recognizes a F~IL signal.
A DF~D signal on ]ine ~Q is asserted whenever an
impending power failure in the clocking or S~I terminating
networks is detected. I~ is equivalent to a DC L~ s;gnal in a
- data processing system.
A"
~M~ INTE~LOCR signal on line 51 coordinates various
-~ nexuses responding to interlocked reading and wri~ing
operations. When a co~man~ing nexus transmits information
including an interlocked reading command during a first bus
cycle, it transmits the ~TERIOCK signal dur;ng the next bus
cycle. The responding nexus transmits the I~F~CK signal
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during the sucoeeding bus cycle. It will continue to transmit the
INTERLOCK signal until it receives an interlocked masked writing
ocmmand and transmits a corresponding a positive confirmation. The
INTER~OCK signal then is terminated.
A final group of lines 52 carries INTERRUPT REQUEST
signals. These signals are generated by nexuses which must signal
the central processing unit 10 to respond to some condition, such as
the completion of a data transfer by one of the secondary storage
bus adapters 24 or 26 in Figure 1. The INTERRUPT REQUEST lines 52
are asserted in synchronism at the T0 time. When the central pro-
cessor unit 10 responds to an INrERRUPT R QUEST signal, it trans-
mits an interrupt summary read command that designates one inter-
rupt re~uest line. A nexus that receives the interrupt summary
read ccmmand and is asserting the corresponding interrupt request
line transmits CNES in the preassigned bit positions of the long-
word in the information field at the same time that it transmits
its CNF signals. No other signals are transmitted. These signals
uniquely identify the requesting nexus and enable the cen-tral pro-
cessor unit 10 to respond. No other transactions can oc over
the SBI during such a transaction because the oentral processor unit
10 asserts the HOLD signal on the TR00 line for both the bus cycle
during which it transmits the interrupt summary read oomm~nd and
the
-23-
~3-203
1~17~
Pg. 24
fo]lowing bus cycle. The central processor unit 10 then can
respo~d to the condition that cause~ the interrupt.
If a nexus does not contain an interrupt mechanism,
such as the memory contro~]er 20Ar it may stil~ be necessary to
alert the central processing unit ln to some change in its
con~ition. If such a change occurs, such a nexus generates an
~LERT signa] on the line 54. The centra~ processing unit 10
responds to the Pl~ signa~.
With this knowledge of the vzrious signals that are
transmitted over the ~I 14, it wi]l now be possible to use
Figs. 3 and 5 to describe general!y several ~P~ transactions
that illustrate the efficiency of a data processing system
utilizing elements that connect to the S~J 14. The ~ 14 is a
time-division ~ultiplexed interconnection. As apparent from the
foregoing discussion, a memory exchange invo~ves at least two
transactions. P first transaction involves the transfer of
command and address information; a second and any following
transactions involve the transfer of ~ata. ~he same lines are
used for all transactions, and the meaning ~iven to the
information on the information lines 40 during each transaction
is determined by the signals on the tag lines 36.
Fig. 5 depicts several sequences that ~iqht occur
between severa1 nexuses including the nexus 32A and the nexus
83-203
~71~4
pg. 25
32B assuming that the nex~s 32~ includes one of the memory
controllers. The nexus 32A could be the I/O bus adapter 22 or
one of the secondary storaqe bus adapters 24 and 26.
Initially the arbitration ~ircuit 33P receives a
signal from other circuitry indicating that the nexus 32~ is
prepared to transfer data to the n~xus 32~. ~t each T3 time
thereafter the arbitration circuit 33~ samples the arbitration
lines until it recei.ves contro3 of the SBI 14. In Fig. 5 the
arbitration circuit 33A samples the arbitration ~ines 31 and
finds no access control signal of higher priority or the HOLD
signal on the ~R lines at the T3 time during bus cycle l.
~t the completion of the bus cyc~e ] circuitry
inc~uding the information circuit 56P and I~ circuit 57~ a taq
A circuit finA and a parity circuit 61~ transmits~during bus cycle
2 appropriate signa~s onto information transfer lines 34. These
include write command signals and ad~ress siqnals from the
information circuit ~6~ for identifying a location in the
information circuits 5~ signals identifying the nexus 32A from
the ID circuit 57k and signals from the tag circuit ~OA
specifying that the information ~ines 4n have command and
address information. The parity circuit 61P generates the
appropriate p~rity. If the wri.ting command is to be ~o~lowed by
data called write data during the next bus cycle the
83-203
~i~7i~
pg. 26
arbitration circuit 33~ also transmits the HOLD signal on the
TROO line during bus cycle 2 thereby to prevent any higher
priority nexus from assuming control over the information
transfer lines 34 during bUC cycle 3. During bus cycle ~,
nothing occurs with respect to SBI sequence "n". ~n the second
followina bus cycle (i.e7, bus cycle 4), a CNF circuit 63~ in
the nexus 32~ transmits a positive confirmation tdesignated as a
~EMORY ACR) over the CNF lines 44, assuming that the information
received during bus cycle 2 by the nexus 32~ was without error.
This completes SBI sequence "n" for transferrina a masked or
interlocked masked writing command and address; this transaction
required four consecutive bus cycles. ruring b~s cycle 3~ the
nexus 32~ stops transmitting the writing command znd address
information and transmits, from the information circuit 56A, the
write data. ~fter the nexus 32~ reaeivec the write data during
bus cycle 3, it waits until bus cycle 5 to transmit the
corresponding MEMC~Y ~CK. This completes SPT sequence "n~1". The
responding nexus modifies only the byte positions specified by
the byte mask transferred with the ~ommand and address.
From the foregoing description it will be apparent
that the writing operation reauires two separate transactions.
Moreover, each transaction reauires four successive bus cycles.
However, the seauencing and timing of the transactions of the
83~203
~76~;4
Pg. 27
~I 14 reducee the duration of this writing operation to five
bus cycles, rather than eight.
If the nexus 32~ were preparefl to issu~ an extended
readina command and no other nexus of higher ~riority was
transmittina its access control signa~ and the H~LD signa] wa~
not being transmitted during bus cycle 3, the nexus 32~ could
transmit the command ~nd address infor~ation on the information
tr~nsfer lines 34 during bus cycle 4. ~he MF~ORY PCK
confir~ation for this transac~ion, bus seguence,"n+~" in Fig. 5,
woulfl not be samplefl at the co~manfler nexus 32A unti] bus cycle
h. An extended reading operation causes r~sponder nexus 32~ to
obtain a auadword beginning at the location specified by the
address signa]s. However, a quadword includes two longwords, and
the information lines 34 only transfer one longword in parallel.
Thus, the nexus 32R interprets the extende~ reading command and
prepares to perform two successive transactions on the SB~14.
~t thi~ point, it wou]~ be possible to inhibi~ any further
transactions over the SBI 14 by any other nexus. ~owever, in
accordance with this invention, the nexus 32A relinguishes its
contro] of the ~BI 14, so another nexus can take control. This
release enables a secondary storage element~to contro] the S~I
14 and transmit an extendefl writing command during bus cycle 5.
As described later, this command normal]y will specify one of
~7G64
the memory controllers 20A and 20B in Figure 1. If it were
directed to the same memory controller that received the extended
reading command, the memory controller 20A would still accept the
command and subsequently acoept the transmit~ed write data because
each memory controller contains a command file which stores sucoes-
sive commands and write data items that are transferred to it as
described later.
As previously indicated, any writing operation may be
followed in successive bus cycles with the write data to be written,
so the secondaLy storage element, as a comm~nder nexus, asserts the
HOLD signal during bus cycles 5 and 6 and transmits the write data
during bus cycles 6 and 7. Thus, an extended writing operation
requires three sucoessive transactions that are shcwn as bus
sequen oes "n+3" through "n~5" in Figure 5. m ey extend only over
an interval of six bus cycles.
Assumlng that upon completion of the transfer of the writ-
ing command and address information and the write data, the nexus
32s were ready to reply to the prior extended reading command, it
would be in a position to take control of the bus and transmit the
first read data item onto the information transfer lines during bus
cycle 8 as part of SBI sequence "n~6". As an extended reading
operation is being performed, the nexus 32B asserts the HOLD signal
during bus cycle 8 to guarantee that it can send the second read
data
-28-
83-203
~176~Gi4
pg. 29
item during SPJ ceauence "n+7". The nexus 32~ decodes its I~
co~e on the Ir lines 37 and the read data function on the tag
line~ 35 an~ accepts the read data items at the T~ times during
bus cycles P and ~. The nexus 32A transmits it confir~ation,
depicted as a ~EXUS ~CX in Fig. 5, over the ~F lines 44 during
bus cyc]es ln and ll so the nexus 32e "knows" that no
trans~ission error conditions exist.
Fro~ the foregoing description, it can be seen that
the circuitey shown in Fig. ' and the operation in Fiq. ~ en~ble
transfers over the ~BI to be conducted very efficient]y. ~s can
be seen by ~ooking at any specific one of the bus cycles l
through ll, different groups of lines that constitute the ~I 14
are involved with different bus sequences or transactions at the
same time. For example, during bus cycle ~ the HOL~ signal is
asserted for bus seauence "n~5". ~imultaneously, the information
tr~nsfer lines 34 are conveying the write data for ~P~ seauence
"n+4", and the response lines 41 are conducting confirmation
signals for ~RI sequence "n+2". ~oreover, the control of the S~I
14 en~b]es eight transactions, that eack req~ire four bus cycles
to complete, to be completed within ll bus cycles~ rather than
t~irty-two bus cycles. It is the foregoing ti~ing and sequencing
of signals on the S~I which enable it to transfer data among the
e~ements in a digita~ data processing system in a highly
1~17669~
efficient manner.
Although the extended reading operation begun in bus
cycle 3 was not ccmpleted until bus cycle 11, the associated re-
lease of the SBI 14 allowed a ccmpletely different transaction
during bus cycle 5. me reading operation thexefore did not
inhibit other transfers over the SBI 14 while the nexus 32B was
retrieving the read data. It was only when the nexus 32B had the
data items ready for transfer that it took control of the SBI 14.
Specific Description
i. Central Processor Unit 10
As shown in Figure 6, the central processor unit 10 in-
cludes the operator's console 15, the SBI 14 and the other circuits
that constitute the SBI interface and memory cache circuit 16, the
address translation buffer circuit 17 and the instruction buffer
circuit 18 of Figure 1. More specifically, the central processor
unit 10 operates under timing established by a clock generator 70
that not only provides the internal clocking signals but produces
the TP, PCLK and PDCLK clocking signals of Figure 4 that are trans-
mitted onto the SBI 14. The SBI interfaoe and memory cache circuit
16 camprises an SBI control circuit 71 that connects to the SBI 14
and to a physical address (PA) bus 72. The PA bus 32 connects to a
data cache circuit 73 and to a
-30-
,, ,
,
,, . ~ .,
~17~4 ~3-203
Pg. 31
translation buffer 74. The translation buffer 74 converts
virtual address (VA) information and other control infor~ation
into a physica] addres~ that is transmi~.te~ ~imu]taneously to
the SBI control 71 and data cache 7~. Data from the data cache
73, or from any other location on the SBI 14 th~t passes throvgh
the SBI control 71, is conveyed to other elements in the central
processor unit l~ over a ~emory data (~D~ b~s 75. These units
inc~ude a data paths circuit 7~ and an instruction buffer and
decode circuit 77.
~ microprogram contro] (UPC) bus 7P conveys signals
fro~ the instruction buffer and decode circuit 77 to a program
control store sn. The progra~ control store 80 then generates
various control signals onto a C~ bus 8~, and this bus conveys
signals to the trznslation buffer 74, the data paths 76, the
instruction buffer and decoder 77 and a traps-interrupts
ar~itrator circuit P2. These circuits and the oper~tor's console
15 com~unicate over an instruction data (Ir) bus ~3 with a
~icrosequencer 84 that controls the seq~ence of oper~tions in
response to microinstructions stored in the pragram control
store 80.
The microsequencer 84 establishes a retrieval st~te
for obtaining an instruction. ~ program counter, which
specifies the address of the next instruction to be retrieved
83-20~
7~
Pg. 32
from one of the memory units 11, passes fro~ data paths circuit
76 through the translation buffer 74 onto the PA bus 72. If the
data cache 73 contains valid information in a location
corresponding to the specified physical 2ddress, it ~.ransmits
data over the MD b~s 75 to the instruction buffer and decode
circui.t 77. ~he microseauencer R4 establishes other data paths
that transfer other information to the translation buffer 74
thereby to transfer other data into registers in the data paths
circuit 76 from either the data cache 73 or, after a retrieval
from the me~ory uni~s ll or other ~emory locations on the S8I
14, the 5~I control 71. If the instruction reauires datz to be
transferred to a physical]y addressed location, the
microseauencer ~4 establishes the data paths that are necessary
to transfer signals to the translation buffer 74 thereby to form
the physical address and to transfer the data simultaneously to
the dat~ cache 73 and to the ~BI control 7]. During any such
transfer the ~I control 71 initiates an exchange with the
specified memory location.
As skown in Figs. ~ and 7, the ~BI control 7~. connects
to the PP bus 72, the ~ bus 75, the I~ bus ~3 and t~e SBI 14.
Jf access is made to the data c~cke 73 in Fig. ~ and the data
cache 73 does not contain the requested data, a "miss" condition
exists. P read-write condition circuit 9~, shown in Fig. ~,
~7t;6~
asserts a STALL and conditions a R~ISE TR flip-flop 92 to be set at
a subsequent SBIT1 time. This signal is shcwn as a zero assertion
signal in Figure 9. The general relationship between the timing of
the oentral prooessor unit 10 and of the SBI 14 is shcwn in Figures
9 and 10. In the following discussion, the prefix "SBI" designates
SBI times; the prefix "CP", oentral processor unit times. Figure 9
discloses cycle times bounded at CPT0 times.
D~ring the first cycle time, the microword from the micro-
sequenoe r 84 prcduces a reading signal and places the physical
address on the PA bus 72. If the data cache doe s not contain the
information, the flip-flop 92 sets at the next SBITl time and
generates the R~ISE TR FF signal. After a short time delay, an OR
gate 93 generates a BUFFER FULL signal which can also be generated
in reSpQnSe to other signals such as the assertion of a READ DATA FF
signal by flip-flop 94 when the nexus is in a re oe iving mode or an
EXPECT READ signal from a shift register 95 after a read data item
has been received. So long as a BUSY flip-flop 96 is cleared, the
R~ISED TR FF signal energizes an 2ND gate 97 and an OR gate 100
thereby to generate a R~ISE TR signal.
A priority arbitration circuit 101 asserts an ARB OK
signal at an SBIT3 time so long as (1) no incoming higher priority
access control or HOLD signals on the TR lines are
-33-
1~7~ 3-203
Pg. 34
asserte~ the A~?D g3te 102 is energized by the ~AISF TR
signal from the ~R gate ]00 and (3) the PRB ~ signal is not
then asserted. The arbitration circuit 101 clocks the inco~ing
signal from the ~ND qate In2 in coincidence with the 5~l~0 and
transmits a ~Y TR signal.
~t the S~2 time, a latch ln3 is set if th~ RPISF~ TR
signa] is asserted thereby to energize an ~ND gate 104 and
generate a TRAN~MIT CA signal. The TRA~S~IT CP ~ignaJ indicates
tha~ command-address infor~ation is to be sent, and this signal
is applied to severa] other circuits. For example, this signal
controls the transfer of the address from an ad~ress register
120 in Fiq. 7 through a transmitting m~ltip]exer 121 and data
A transceivers 1]~ ~ onto the SPI 14. The P~SY flip-flop ~
responds to the TRP~S~ P signal by settina at the next SPIT]
time which disables the OP gate 100 and RAISE ~ signal. Then
the f]ip-flop ]0~ is c~eared zt t~e next S~IT3 time and
terminates the TR~N~MIT ~ signal. The ~USY signal and ~ RESFT
~USY siana] energize reset loaic 10~ that estab]ishes an initial
condition in a timing shift re~ister 107 that produces TIMING
20 PUL5F 0, 1 and 2 during successive cyc]es, the timing pu]~es
changing at the SBIT2 times. This completes the transmission of
the com~an~-ad~ress information.
The shift register 107 acts as a sta~e cont~o] and
~17664
enables the CNF circuit 63 to mDnitor the CNF lines 41 at the
appropriate time or times. When a positive confirrnation is
received, the shift register 95 is loaded with an ANY RFAD output
rrom a sequen oe decoder 108 that responds to a sequencer (SEQ) IO9
by generating the ANY ~EAD signal when the ccmmand-address informa-
tian defines any of the reading operations. m us, at the next
SBITl time, the shift register 95 will assert an EXPECT READ signal
that energizes the OR gate 93 thereby to maintain the BUFFER FVLL
signal at an asserted level.
When the .responder nexus has retrieved the requested data
items and gains control of the SBI 14 and transmits the data item
and other info~mation, a co~nparator 110 and nexus ID circuit 111,
that form part of the ID circuit 57, coact to generate a MY ID signal
when the incoming ID signals on the SBI 14 correspond to the signals
from the NEXUS ID circuit 111. If the (TAG) signals indicate that
the info~mation is read data, no parity errors are detected and the
ccmmander nexus has not timed out waiting for a response, an AND
gate 112 generates an ANY READ DATA signal. At the next SBITl time,
the flip-flcp 94 generates the KEAD DATA FF signal that energizes
the OR gate 93 and conditions a flip-flop 113 to be set at the next
SBIT2 time thereby to enable a decoding circuit 114 to pro~u oe a
W~NTED DATA signal. The WPNTED DATA signal enables the cDnditiQn
6~
circuit 91 to disable the STALL signal at the next SBIT0 time.
At the time that the R~D DATA FF signal shifts to an
asserted state, it also enables the control logic 90 in Figure 7 to
control the transfer of data from a data transceiver 115 and read
data register 116 to be diverted to the MD bus 75 through a driver
circuit 117. It also will be apparent that the incoming data could
be routed through the data transceiver 115, an SBI silo circuit 122,
an ID bus multiplexer 123 and a driver circuit 124 onto the ID bus
83 for diagnostic purposes.
Figure 9 depicts the timing for an extended reading o~era-
tion. As shown, the responder nexus initiates a bus transaction
during the cycle designated "MEMORY TR" and transfers a read data
item during the next bus cycle. The responder nexus also transmits
the H~LD signal during the same bus cycle that it transmits the
first read data item so it can transfer the second read data item
on the subsequent bus cycle.
Figure 10 depicts the timing seq~ence for the signals
that æe generated during a ~7riting operation. For this transfer
the microsequencer 44 issues a writing command and provides the
address and data items over the PA bus 72 and MD bus 75 respect-
ively. The flip-flop 92 then asserts the R~ISE TR FF signal and
causes the OR gate 93 to assert the BUFFER FULL signal. At the
next SBITl time, the BUSY flip-flop 96 sets and the reset logic 106
-36-
1~76f~i4
then enables the state counter 107. Four timing pulses are
generated for a writing cperation involving only one longword.
These pulses define the command-address time, write data time and
two acknowledgement ti~es respectively. When the second acknow-
ledgement signal is received over the CNF lines 44, the R~ISE TR FF,
BUFFER FULL and BUSY signals are terminated. It will also be
apparent fm m Figure 10 that the data item is simultaneously
written into the cache memory at the beginning of the operation.
ii. Memory Units 11
-
With ~is understanding of the basic construction and
operatian of an SBI control circuit, such as the SBI control cir-
cuit 71 in Figure 6, operating as a commander nexus in both the
transmitting and receiving states, we now will describe the Gpera-
tion of a memory controller as a responder nexus.
Memory controller 20A and one array 21~ are shc~n in
Figure 11 as a typical memory unit. me memory controller 20A in-
cludes a memory-SBI interface circuit 200 that contains many of the
circuits shown in the nexus 32B in Figure 3. This interfaoe 200
connects through a FILF bus to a control and timing circuit 201 and
a data pa~h circuit 202. A OCNTRDL bus fm m the control and timing
circuit 201 interconnects various mem~ry array
-37-
~3-203
~176f~4
Pg. 3~
sections 203 while a DP~ bus interconnects the memory array
sections 203 and the data path circuit 202.
Referring to ~ig. 12, the ~l interface circuit 20n
comprises a number of drivers and receivers in an ~I interface
2n4 th~t connect to the ~BI 14 directly. ~ther ~ortion~ of the
memory ~I interface 20~ include circuits for responding these
signa]s and for generating appropriate signals onto the SB~ 14c
~ efore describing the operation of this memory
controller ~nd array, it wi]l be helpful to describe the
function of specific circuits that are shown in Figs. 12 throu~h
14. Sti]l referring to Fig. 12, a parity check circuit 205,
included in the parity circuit 61~ ass~ming the nexus 32~
corresponds to this memory contro]ler, receives the parity and
~11 other signals from the ~I interface 204 and monitors for
~e ~.f o ~ 5 e
~ny parity errors.-~he respo~ ]ogic circuit 20~ corresponds to
the C~IF circuit 63B and the FAULT circuit 62~; it transmits a
responC-e in the form of a confirmation or error, as previously
described, no more than two bus cycles after the memory receives
2 command-address or write data.
The arbitration logic circuit 207 corresponds to the
arbitration circuit 33~ and it, ]ike the circuitry shown in
connection with the central processor unit, determines when the
memory controller 20~ ~ains control of the S~I 14. This circuit
~17~;4
connects directly to the SBI 14.
Tag decode circuit 210 corresponds to the tag circuit 60B
in Figure 3. It deoodes the tag field of re oeived information on
the tag lines 35 thereby to determine the nature of the signals on
the information lines 40. The decoded tag is routed to an address-
data validity checking circuit 211 and the tag field is routed to a
command file 212.
A function deccde circuit 213 decodes the function signals
~len command-address information is received from the SBI 14. This
circuit determines the validity of the functiQn signals by compar-
ing them against the allowed function signals. The functions bits
also are transmitted to the address/data validity check circuit 211
and the ccmnand file 212.
The address-data validity checking circuit 211 generates
a UAL DA~ signal when the parity check circuit 205 indicates that
no parity errors exists, when the function decode circuit 213
indicates that the function bits are valid and when the d~stination
address, function and other information all indicate that the cpera-
tion can be perfonmed in the memory. Circuitry in file control
logic 214, associated with the comm~nd file 212, enables the informa-
tion on the SBI interfaoe 204 to be transferred into the command
file 212 and a write counter 252 to be incremented in response to
the V~L D~ signal.
-39-
1~7~64
An array address checking circuit 215 determines whether
the received address on the information lines 40 falls within the
range of memory locations that is associated with the particular
memory controller. The circuit 215 also receives signals fron a
memory size encoding network 220, a chip-size correcticn circuit
221 and an inter~eaving address correction circuit 222. Circuits
for checking incoming addresses against valid ranges of memory
locations are well known in the art.
An I/O address validity checking circuit 223 determines
if the address and selected function are valid for any control
registers that are included in the memory controller. In one
specific embodiment a memory controller includes three configura-
tion registers, that are shown schematically in Figure 14, and a
read-only memory.
Configuration register A in Figure 14 includes an inter-
leaving information field 230, a subsystem field 232 that indicates
the size and type of memory and an enable write interleave field
233 that enables the interleave field to be written. A size field
234 indicates the size of memory storage connected to the memory
controller. A power up flag 235 and a power down flag 236 indicate
whether the memory is undergoing either one of the corresponding
sequenoe s. Fault condition flags 237 including a transmit fault
(TF), m~ltiple transmitter fault (M~F), interlock comm~nd sequen oe
-40-
1~17~
fault (ICS), write data sequence Eault (WDS) and bus parity (PP~
fault also are included. The TF signal is generated if the memory
was cperating as a transmitting nexus when a fault occurred. m e
MTF signal indicates an ID check circuit 238 (Figure 12) detects ID
signals on thR lines 37 (Figure 3) that differ from the ID signals
being transmitted by an ID latch 239 at the time that the memory
oontroller acts as a transmitting nexus. The ICS signal is
asserted when an interlocked masked writing ccmmand is received,
but the INrERLOCK signal on the control line 51 is not asserted.
Interlocked exchanges require that the commander nexus issue a
interlocked masked reading command before the interlocked masked
writing command is sent. me first command causes an interlock
flip-flcp in the commander nexus to be set thereby to assert the
INTE~LOCK signal. The WDS signal is asserted whenever any of the
writing commands is sent and not immediately followed by write data
during the subsequent bus cycle. me PP signal is asserted whenever
a parity error is detectedO
Still referring to Figure 14, configuration register B
contains information for testing the error checking logic and
me~ory status. It includes a foroe check bits field 240 used for
forcing error corrections and a FOR field 242 to force an error at
a predetermined address. An EOC field 241 is used to disable the
-41-
~7~ 4
ECC circuit. An INIT STAT field 243 indicates whether the mEmory
data is valid, the memory is in the process of initializing or
initialization is ccmplete. An EWSA field 244 enables a mem~ry
starting a~ress field 245 to be altered. me memory starting
address, as the name implies, identifies the first lw ation in the
memory. A file fullness field 246 indicates whether the command
file 212 in Figure 11 is full.
Still referring to Figure 14, configuration register C
contains error syndrome, error address and other fields that are
used in indicating corrected data if certain types of errors occur.
Referring again to Figure 12, an MR 250 address generator
250 generates memory referen oe addresses in response to the
addresses received from the SBI 14 and the starting address signals
from configuration register B, identified by referen oe number 247
in Figure 13.
A ccmmand/address destination decode circuit 251 uses the
inocming address signals from the SBI 14 to select the appropriate
section in the memDry. As previously indicated, these address
signals may identify a location in an array section 203 (Figure 11),
one of the configuration registers (Figure 14) or read-only memory
248 in Figure 13 that is used to initialize the system. me cir-
cuit 251 decodes the incoming address signals to select one of
these storage locations.
-42-
~17~
Still referring again to Figure 12, the file control logic
214 monitors the amount of space in the command file 212. It in-
cludes a write counter 252 and a read counter 253. A differenoe
decoder 254 monitors both counters 252 and 253. As described later,
a room-in-file comparator 255 indi Qtes whether additional informa-
tion can be loaded into the command file 212 in response to signals
from the difference decoder 254 and the function decoder 213.
The circuitry in Figure 12 also includes clock logic 256.
This logic receives a clocking signals on the lines 30 and produces
the necessary timing pulses in synchronism with the clocking
signals on the SsI 14.
When data is transmitted onto the SBI 14, a parity
generator 257 responds to the information in the data, ID, TAG and
other fields to produce the appropriate parity signals.
In addition, the memory controller contains circuitry for
controlling memory cycles during which data is transmitted into or
retrieved from a memory array 21A. This circuitry is shown in
Figure 13 and includes an address register 260 that reoe ives the
address for the location in an array that is derived from the
address information in command-address signals from the lines 40.
These signals are directed through an address multipleæ r 261 to
-43-
1~76f~q~
the men~ory array, to the read-only memory 248, or to the configura-
tion registers. The other input to the address multiplexer 261 in-
cludes address signals from memory timing and refresh logic 262
that maintains the data in a volatile mem~ry in a valid state.
Refreshing of such memories is well kncwn in the art.
Cycle decode and control logic 264 in Figure 12 receives
information from the command file and generates control signals
that are utilized in the circuitry shown in Figure 13.
Still referring to Fiyure 13, a I/O data multiplexer 265
selects data from one of the configuration registers 247, 266 and
267 or the read-only memory 248 for transferring the data onto the
FILE bus if the incomlng address identifies one of those specific
registers. Data receive latches 268 receive a longword of data
from the FILE bus and store it temporarily until it is ready to be
transferred over the DATA bus into the memory 21A. m is data is
also loaded into latches 269 and 270 which serve as inputs into an
error checking circuit 271 that is not described in any further de-
tail.
A read data tag generator 272 encodes the tag field in
accordance with any errors that may exist or not and energizes a
tag transmitter 273 when the data is transmitted onto the SBI 14.
-44-
1~176~4 83-2n3
P~. 45
~urinq operation of the data peocescing system, the
clock logic 3n monitors the timing signals on the ceI 14. ~t ~I
time ~3, al~ infor~ation on the SB~ ]4 is transferred into
a~propriate latches of all receiving nexuse~. ~nitially, all
siqnaJs on the ~ 14 are teste~ for parity. ~f a parity ~rror
is detected, various flags are set and cleared and a parity
fault is indiated. Jf write data is being received, it is
placed in the command file aJonq with an indicator that will
abort the write cycle and the write co~nter 252 is advanced. ~f
command-address information is received, it is placed in the
command file 212, but the write counter 252 is not advanced.
kss~me that command-address information is received
without error, ~he ta~ d~code circuit ~] n ~ecodes the f~nction
signals. If the address signals specify a location in a memory
array, the address is tran~ferred into the ~om~and file 212.
The memory array can be accessed by any of the valid functions;
if an invalid function is ~etec~ed, ~he ~F siqnals wiJl be set
to an error state.
~he foregoing description is limited to a specific
embodiment of this invention. It will he apparent, however,
that this invention can be practiced in data processin~ systems
havin~ diverse basic construction or in systems that use
different interna] circuitry than is describe~ in this
1~17~
specification with the attainment of scme or all of the foregoing
objects and advantages of this invention. Therefore, it is the ob-
ject of the app~ded claims to oover all such variations and modi-
fications as ccme within the true spirit and scope of this inven-
tion.
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