Note : Les descriptions sont présentées dans la langue officielle dans laquelle elles ont été soumises.
1 17~7~33
This is a divisional of copending Canadian Patent Application
Serial No 367J739 filecl on December 30, 1980 in the name of Fairchild Camera
and Instrument Corporation.
This invention relates to integrated circuits, and in particular
to a method for manufacturing integrated injection lo~ic devices having self-
aligned base contacts.
Integrated injection logic devices and circuits are known in the
art and have been the subject of numerous patents~ and publications. See,
example United States Patent 3,962,717 to O'Brien. This patent discloses an
integrated injection logic often referred to as I2L device formed in an oxide
isolated region of an epitaxial layer of semiconductor material. Also known
is the use of boron doped polycrystalline silicon as a difusion source for p-
type regions of I2L devices. See, example, "Polycrystalline-Silicoll as a
Diffusion Source and Interconnect Layer in I2L Realizations" by Middlehoek and
Kooy, IEEE Journal of Solid State Circuits, Vol. SC-12l No. 2, April 1977.
`~ Prior art I2L circuits, however, suffer from certain disadvantages
;~ relating to speed, density, number of fan-outs permitted, and the crossing ot`
such structures by~metal interconnecting lines. One goal in designing
-~ injection logic structures is to maintain the resistance of the base region
~ 20 while increasing the beta of the transistor. In prior structures, this has
been accomplished by scaling of the structure in a horizontal or vertical
direction. At a certain point, however, scaling does not provide further
mprovements in beta because the P~ collar which surrounds the N~ collectors
determine the base resistance and beta.
An integrated injection logic structure is disclosed which offers
~- improvements in speed, density, number of interconnects, number of fan-outs
and layout design over prior art structures.
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According to the present invention, there is provided a method of
making an integrated injection logic device in an electrically isolated pocket
of first conductivity type material underlaid by a buried region of first
conductivity type, the method comprising: introducing opposite conductivity
type impurity into a first portion of the pocket; depositing a layer of first
material which includes opposite conductivity type impurity over all of the
pocket; forming a layer of silicon oxide over the layer of first material;
patterning the oxide layer and the layer of first material such that first
material remains over a second portion of the pocket which second portion
includes at least part of the first portion and such that a third portion of
the pockek is exposed which third portion includes at least part of the first
portion and none of the second portion; forming silicon oxide ove:r all of the
remaining first material except where the first material is in contact with
the pocket; patterning the silicon dioxide to expose parts o the third portion
which are within the first portion; introducing first conductivity type impurity
into the exposed parts of the third portion; and treating the remaining first
material to cause at least some of the opposite type impurity to enter the
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second portion of the pocket.
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.. The invention and that of copending Canadian application S.N. 367J739
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~;~ 2~ will now be described in greater detail with reference to the accompanying
dr Nings, in which:
Figure 1 is a cross-sectional view of an early step in the fabrication
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of I L devices, showing the semiconductor su~strate, the buried layer, the
epitaYial layer, and the oxîde isolation;
Figure 2 is a cross-sectional view showing the appearance of such a
- structure after layers of polycrystalline silicon and oxide are formed over
selected portions of the epitaxial layer;
Figure 3 is a cross-sectional view after removal of some of the poly-
crystalline silicon;
. Figure 4 is a cross.-sectional view after additional oxide is formed;
Figure 5 is a cross-sectional view after removal of some of the oxide
previously added and the introduction o n type impurity;
Figure 6 is a top view o the structure of Figure 5;
Figure 7 is a cross-sectional view tak~n on line 7-7 in Figure 6;
~ Figure 8 is a schematic diagram of the I2L circuit ormed according
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to the proccss of Fi~ures 1-7;
Figure 9-11 depict an alternate technique for making an I2L device
usillg thermally grown oxide layers and plasma etching; and
Figure 12 SJIOWS an extended I2L structure ma~e possible as a result
of th s inventiol-.
~igures 1 through 6 depict one method Eor fabricating the integrated
injection logic structure of this invention. As shown in Figure 1J using well-
kn~wn integrated circuit technology~ a buried layer 12 of N+ conductivity type
material has been ormed between a substrate of P type material and an epitax allayer 15 of N- type material. Epitaxial layer 15 is electrically isolated
from other portions of the integrated circuit structure ~not sho~n) by a ring
of oxide isolation 18, typically silicon dioxode, whicll surrounds epitaxial
layer lS. Using well-kno~n ion implantation techniquas P type impurity 20
has beell introduccd into region 21 of the epitaxial layer 15. Substrate 10
will usually be monocrystalline silicon having a resistivity of 2 to 5 ohm-
centimeters. Buried layer 12, which ~ill form the collectors o the integrated
injection logic transistors will have an impurity concentration of 2 x 1019
atoms per cubic centimeter, while a dose of P type material of approximately
- 1012 atoms per square centimeter at 190 kev is introduced into epitaxial layer
~` 20 15 to collvert portions of it to P conductivity type.
Next, as shown In Figure 2 a layer of polycrystalline silicon 22
is deposited across the upper surface of the integrated circuit structure.
Polycrystalline silicon 22 may be deposited using any well-known techni~ue, for
example, by chemical vapor deposition. In one embodiment polysilicon 22 is
5000 Angstroms thlck.
Polycrystalline silicon 22 will also include the desired concent-
ration of P type 1mpurity for use as a diffusion source during later processing.
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In one embodiment of the invention, 1015 atoms per square centimeter of
boron is added to the polycrystalline silicon. Next as also shown in Figure
2, a layer of silicon dioxide 24 approximately 5000 Angstroms thick is depositedon the surface of polycrystalline silicon 22, for example, by chemical vapor
deposition. Next, silicon dioxide 24 is suitably patterned using well-known
photolithographic techniques.
The openings in oxide layer 24 are then used as a mask for removal
of regions of polycrystalline silicon layer 22. The polycrystalline si.licon 22
may be removed using any well-known chemical etching process, for example, by
etching with a mixture of hydrofluoric and nitric acids. The appearance of
the structure after removal of the thereby exposed portions of polycrystalline
silicon layer 22 is shown in Figure 3. The chemical etching results in under-
cutting, that is, the width-tf the sillcon dioxide layer 24 will be slightly
~ greater than the width of the underlying polycrystalline silicon 22, ~See
-~ Figure 3). As will be discussed, the undercutting, typically consldered
undesirable, is used to advantage in one embodiment of the invention.
Next as shown in Figure 4 the integrated circuit structure is therm-
ally oxidized by heating to 1000C to create regions of silicon dioxide 26 be-
~- ~ tween the polysilicon regions 22. Oxide 26 is typically 1000 Angstroms thick
and the tbermal process will also slightly thicken oxide 24.
Then, as shown in Figure 5, some of the silicon dioxide regions 26
are etched, typically using any well-known plasma etch process to prevent under-cutting. A plasma comprising chlorine is typically used. The oxide 26 over-
' lying the portion of epitaxial layer 15 which was not doped from N to P in not
- etched. As will be shown this portion of the epitaxial layer 15 functions as
~; ~ the base of the PNP translstor. The appearance of the remaining oxide 26 is
shown in Figure S. Note that reglons of oxlde 26 remain on the ends of each
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regioll of polycrystalline silicon 22. Openings throu~h this oxide 26 re-
maining on the cnds of polysilicon 22 may be made later in the process to allow
ohmic connections to be made to polysilicon 22. N type impurities 28 are then
implanted through the openings in the oxide 24 and 26. In one embodiment
arsenic or phosphorus is used to provide the N type impuri',ies and a concentra-
tion of 1021 atoms per cubic centime.er is created in the epitaxial layer 15.
The wafer is then heated to 1000C to drive in the N type impurities, an~ at
this time the boron in polycrystalline silicon regions 22 will also diffuse in-
to the single crystal silicon beneath regions 22 as shown in Figure 5.-
An alternative processing technique is to create silicon dioxide
layer 24 is thermally oxidizing the polysilicon, rather than using chemical
vapor deposition. If this technique is selectedJ the oxide 2~ grown on poly-
crystalline silicon 22 cannot be as thick as if ~ormed using chemical vapor
deposition because the elevated temperatures may clifuse the boron from the
polysilicon 22 into the single crystal silicon lS too quickly and thereby con-
vert the PNP base region from N type to P type. Hence, a relatively thin ~3000
Angstroms) layer of oxide 24 is grown at a low temperatureJ for example, 900C.
After this layer is patterned and the underlying polysilicon 22 removed as shown
in Figure 3~ oxide 26 is grown to approximately 1000 Angstroms thickness~ and
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-- 20 this layer is then plasma etched also with a plasma containing chlorine, with
the remaining process following the description associated with Figure 5.
Figure 6 is a top view of the structure shown in Figure 5. Note
that the polycrystalline silicon region 22 is divided into two portions, region
22a which serves as a contact to the emitter of a PNPcransistor 45 ~see Figure
- 8), and region 22b which serves as a contact for the base regions of thc NPN
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~ transistors 50-53 (see Figure 8). Note that polycrystalline silicon 22b over_
lies P type regions 25, with N type regions 28 being formed in the gaps between
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the P type regions 25.
Figure 7 is a cross sectional view taken through Figure 6 as shown.
Figure 7 shows the po]ycrystalline silicon interconnection 22b displaced away
from N type regions ~S which are ~ormed between P type regions 25.
Figure 8 is a schematic diagram sho~ing the circuit created by the
structure depicl~cl in Figures 5, 6, and 7. Note that the components of Figure
~ are given numericai designations corresponding to ~he appropriate regions
shown in Figures 5) 6 and 7.
An alternative technique for fabricating an I2L structure using
this invention is shown in Figures 9 ~hrough 11. The structure shown in Figure
9 is obtained by following the same process steps depicted in Fi~ures 1, 2 ancl
3, except that instead of forming oxide layer 2~ by chemical vapor deposition
i~ is created by thermal oxidation. Because it is formed using thermal o~ida-
tion, oxide layer 30 in Figure 9 is given a different designation than oxide
layer 24 in Figure 2, although it should be understood both layers are comprised
of silicon dioxide and perform the same function. Because the necessary pro-
longed elevated te~pera-ture required to generate oxide as thicX as layer 24
would diffuse boron out of polycrystalline silicon layer 22 and into the under-
lying single crystal silicon too quickly, thereby lowering the base to buried
Iayer breakdown ~oltage, a thinner layer of oxide 30 is grown at a lower temp-
erature. Typically, oxide 30 will be approximately 3000 Angstroms thick
and will be created by thermal oxidation at 900C.
After the silicon dioxide layer 30 and polycrystalline layer 22 are
etched as described in conjuction with Figure 3, a thinner layer of silicon
dioxide 27 is grown at approximately the same temperature as layer 30.- Layer
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, 27 will typically be approximately 1000 Angstroms thick. The appearance of the
structure at this step in the process is depicted in Figure 10.
Next, as shown in Figure 11, a plasma etching process lS used to
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create an opening in layer 27 through which N type impurities may be intro-
duced to form region 28. I~hen the wafer is heated to drive in the impurities
to form region 2~, boron or other P ty~e dopant will diffuse out of poly-
crystalline silicon 2~ to form underlying P type regions 25, also as shown in
Figure 11. The resulting structure will have the same surface appearance as
that depicted in Figure 6.
One further advantage of the I2L structure of this invention is
sho~nn in Figure 12. Because the polycrystalline silicon region 22b is self-
aligned over the base regions of the NPN transistors, the base resistance be-
tween the NPN bnses will be extremely low, on the order of 100 ohms. These
resistances are designa~ed 31a~ 31b, and 31c ln Flgure 8. The low resistance
allows thc structure to be divided and extended as shown in Figure 12 to allow
one or more conducting lines 33 to traverse the structure. I~ith prior art
I2L structures, such a~ extension created unacceptahly high base resistances,
; and there~ore necessitated complicated and long intercomlecting lines having
many turns to avoid crossing the I2L structure.
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