Note: Descriptions are shown in the official language in which they were submitted.
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PLANAR AVALANCHE PHOTODIODE
BACKGROUND
[0001] The present invention relates to photodetectors. More specifically, the
present invention relates to avalanche photodiodes.
[0002] Owing to the known interaction between photons and electrons,
advances have been made in the field of photodetectors in recent years,
particularly
in those photodetectors that utilize semiconductor materials. One type of
semiconductor-based photodetector known as an avalanche photodiode includes a
number of semiconductive materials that serve different purposes such as
absorption and multiplication.
[0003] The avalanche photodiode structure provides a large gain through the
action of excited charge carriers that produce large numbers of electron-hole
pairs in
the multiplication layer. In order to prevent tunneling in the absorption
layer, the
electric field is regulated within the avalanche photodiode itself, such that
the electric
field in the multiplication layer is significantly higher than that in the
absorption layer.
[0004] A particular type of avalanche photodiode know as a mesa avalanche
photodiode exposes high field p-n junctions and large numbers of exposed
surface
and interface states that make it difficult to passivate using a layer of
insulating
material. Therefore, conventional InP/InGaAs avalanche photodiodes use
diffused
structures which bury the p-n junction. However, these InP avalanche
photodiodes
require extremely accurate diffusion control of both the depth and the doping
density
of the p-type semiconductor regions as well as accurate control of the n-doped
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region into which this diffusion occurs. This critical doping control is
essential, since
the diffusion controls the placement of the p-n junction, the magnitude of the
electric
field in the multiplication region, the length of the avalanche region, as
well as the
total charge in the charge control layer which determines the values of the
electric
fields in both the high field InP avalanche region, which must be large enough
to
produce multiplication, as well as the low field InGaAs absorbing region,
which must
be small enough to avoid tunneling. In addition, accurately placed diffused or
implanted guards rings are used in this type of arragnement, to avoid
avalanche
breakdown at the edges of the diffused p-n junction. This combination of guard
rings
and critically controlled diffusions increases the capacitance, lowers the
bandwidth,
and reduces the yield, thus increasing the cost of these APDs.
[0005] For ultrahigh speed performance detectors, InAlAs can be used as the
avalanche layer rather than InP, since the higher bandgap reduces tunneling
and
thus allows thinner avalanche regions to be used leading to higher speeds and
higher performance receivers. However, a diffused structure is even more
difficult to
achieve in InAlAs since the larger electron avalanche coefficient (relative to
the
holes) makes it desirable to multiply the electrons rather than the holes as
in
standard InP based APDs. Moreover, simply reversing the standard p-doped
diffused structure is not sufficient, since n-dopants do not diffuse fast
enough.
SUMMARY OF THE INVENTION
[0006] The present invention provides a planar avalanche photodiode
including first and second contact layers, a semiconductor layer with a
diffusion
region, a semiconductor multiplication layer, and a semiconductor absorption
layer.
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The diffusion region has a smaller area than the semiconductor layer and is
positioned adjacent to the first contact layer, and the semiconductor
multiplication
layer is positioned between the first and second contact layers.
[0007] In another aspect of the invention, a planar avalanche photodiode
includes first and second contact layers, a semiconductor absorption layer,
and a
semiconductor multiplication layer. The first contact layer has a smaller area
than
that of the semiconductor absorption layer. The semiconductor absorption layer
is
positioned between the first contact layer and the semiconductor
multiplication layer,
and the semiconductor absorption layer and the semiconductor multiplication
layer
are positioned between the first and second contact layers.
[0008] Various embodiments of the invention provide a photodiode with a low
capacitance and a low field near the edges of the absorption and
multiplication
layers.
[0009] Other features and advantages will be apparent from the following
description and from the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 is a cross-sectional view of a planar avalanche photodiode in
accordance with the present invention.
[0011] Figure 2 is a cross-sectional view of an alternative planar avalanche
photodiode in accordance with the present invention.
[0012] Figure 3 is an experimental plot of the capacitance of the planar
avalanche photodiode.
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[00131 Figure 4 is an experimental plot of the capacitance of the planar
avalanche photodiode above punch-through as a function of the p-contact size
and
the isolation mesa size.
[0014] Figure 5 is a schematic plot of the results of a calculation of the
electric
field profile through the multiplication layer showing that the field is a
maximum in
the center.
[0015] Figure 6 is an experimental plot of the photocurrent gain as a function
of distance across the device.
[0016] Figure 7 is a schematic plot of the results of a calculation of the
electric
field profile through the absorption layer showing that the field is a maximum
in the
center and drops to a negligible value at the mesa edge.
[0017] Figure 8 is a schematic plot of the results of a calculation of the
electric field profile through the center of the device, showing the field is
high in the
multiplication layer and low in the absorption layer.
[0018] Figure 9 is a cross-sectional view of the planar avalanche photodiode
of Figure 1 with additional field control structures in accordance with the
present
invention.
[0019] Figure 10 is a cross-sectional view of the planar avalanche photodiode
of Figure 2 with additional field control structures in accordance with the
present
invention.
[0020] Figure 11 is a cross-sectional view of a planar avalanche photodiode in
accordance with another alternative embodiment of the present invention with
the
diffusion region extending into the absorption region.
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[0021] Figure 12 is a cross-sectional view of a planar avalanche photodiode
in accordance with yet another alternative embodiment of the present invention
with
additional oxidized field control structures.
DETAILED DESCRIPTION
[0022] Referring now to Figure 1, a photodetector structure, in particular, a
planar avalanche photodiode ("APD"), embodying the principles of the present
invention is illustrated and designated at 10. As its primary components, the
APD 10
includes a p-type contact layer 12 and a first n-type semiconductor layer 28
that
defines a second n-type contact layer. The avalanche photodiode 10 is
optimized
for increased performance through diffused p-type doping creating a p-n
junction
and a p-contact. Specifically, the p-type contact layer 12 is positioned on a
second
n-type semiconductor layer 16, which includes a p-type diffusion region 14 to
form a
p-n junction and create a p-contact to the second n-type semiconductor layer
16.
Alternatively, the semiconductor layer 16 can be a p type so that a p-p+
junction is
formed by the diffusion. The semiconductor layer 16 can be undoped or low
doped
to facilitate forming a depletion region under a bias voltage.
[0023] The planar avalanche photodiode 10 further includes an undoped or n-
or p-type semiconductor absorption layer 20. This absorption layer can be
separated from the semiconductor layer 16 by a first grading layer 18a to
increase
the speed of the photodiode. The absorption layer 20 is located between the
semiconductor layer 16 and a semiconductor multiplication layer 24. In certain
embodiments, the semiconductor absorption layer 20 is separated from the
multiplication layer 24 by a p-type semiconductor charge control layer 22 and
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second grading layer 18b. An n-type contact layer 26 collects electrons and is
shown positioned on the first n-type semiconductor layer 28.
[0024] The first n-type semiconductor layer 28 is selected from a group
including tertiary semiconductors, or group III-V semiconductors. Accordingly,
the
first n-type semiconductor layer 28 is either two elements from group IIl
combined
with one element from group V or the converse, two elements from group V
combined with one element from group Ifi. A table of representative groups of
the
periodic table is shown below.
GROUP II GROUP III GROUP IV GROUPV
Zinc (Zn) Aluminum (Al) Silicon (Si) Phosphorus (P)
Cadmium (Cd) Gallium (Ga) Germanium (Ge) Arsenic (As)
Mercury (Hg) Indium (4n) Antimony (Sb)
[0025] In certain embodiments, the first n-type semiconductor layer 28 is
InAlAs. However, it is understood that the first n-type semiconductor layer 28
may
be any binary or tertiary semiconductor that provides the bandgap for
optimized
operation of the planar avalanche photodiode 10.
[0026] The semiconductor multiplication layer 24 is also selected from a group
including tertiary semiconductors, or group III-V semiconductors. In the
preferred
embodiment, the semiconductor multiplication layer 24 is InAlAs. Preferably,
the
semiconductor absorption layer 20 is also selected from a group including
tertiary
semiconductors, or group Ill-V semiconductors. In the preferred embodiment,
the
semiconductor absorption layer 20 is 1nGaAs. However, it is understood that
both
the semiconductor absorption layer 20 and the semiconductor multiplication
layer 24
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may be any binary or tertiary semiconductor that provides the bandgap for
optimized
operation of the planar avalanche photodiode 10.
[0027] The second semiconductor layer 16 is also selected from a group
including tertiary semiconductors, or group Ill-V semiconductors. As before,
the
second semiconductor layer 16 is either two elements from group III combined
with
one element from group V or the converse, two elements from group V combined
with one element from group III. In the preferred embodiment, the second
semiconductor layer 16 is InAIAs. However, it is understood that the second
semiconductor layer 18 may be any binary or tertiary semiconductor that
provides
the bandgap for optimized operation of the planar avalanche photodiode 10.
[0028] As noted previously, the semiconductor layer 16 defines in part a p-
type diffusion region 14 near the junction between the former and the p-type
contact
area 12. The small area of the localized p-type diffusion region 14 determines
the
capacitance of the planar avalanche photodiode 10 at the aforementioned
diffusion
junction, rather than that of the larger area outer mesa, thereby increasing
the
overall speed of the structure.
[0029] A feature of the planar avalanche photodiode 10 is that all the
critical
layer thicknesses and doping concentrations are regulated in the initial
crystal
growth, and thus are under control, such that they can be reproducibly grown
and
are uniform over the entire wafer. Accordingly, difficulties associated with
process
control during fabrication, particulariy those related to the diffusion step,
are not
manifest.
[0030] An alternative embodiment as shown in Figure 2 as a planar avalanche
photodiode 110 includes a mini-mesa structure 32. For the photodiode 110, the
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diffused semiconductor region 14 described above is replaced with a p-type
semiconductor layer that is epitaxially grown into the mini-mesa structure 32.
The p-
type semiconductor layer 32 may be InAIAs, or any other type Ill-V
semiconductor
that provides a suitable bandgap for optimized performance.
[0031] Similar to the structure 10 shown in Figure 1, the planar avalanche
photodiode 110 also includes the p-type contact layer 12, a contact and
passivation
layer 16, made of, for example, InAlAs, and the first n-type semiconductor
layer 28
providing another contact area. The p-type contact layer 12 is positioned on
the p-
type semiconductor layer 32. Passivated regions 34 are positioned surrounding
the
p-type semiconductor layer 32 and the remaining structure of the planar
avalanche
photodiode. Suitable passivation materials include BCB (benzocyclobutene),
silicon
dioxide, silicon nitride, or polyimide.
[0032] To fabricate the photodiode 110, the full structure is grown initially
including the p-type semiconductor layer 32, and then it is etched down to the
high
bandgap passivation layer 16 using a stop etch layer, which is positioned
above the
passivation layer. The foregoing process defines a localized p- contact region
32,
which controls the relevant capacitance area, thus resulting in a low
capacitance and
a high speed avalanche photodiode. Moreover, the entire planar avalanche
photodiode 110 is epitaxially grown and does not require p-type diffusion.
[0033] Another approach to form the passivated region 34 is to utilize wet
oxidation. The p-type semiconductor layer 32 can be oxidized through to the
passivation layer 16 or the first grading layer 18a. Similarly, the sides of
the outer
mesa, which includes the n-type semiconductor multiplication layer 24, the p-
type
semiconductor charge control layer 22, and the second grading layer 18b, can
be
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oxidized as indicated, for example, in Figure 12 as a photodiode 510. Finally,
it is
possible to oxidize the first n-type semiconductor layer 28 so that there is a
gradual
interface between the unoxidized and oxidized layers. This reduces the field
at the
interface between the first n-type semiconductor layer 28 and the n-type
semiconductor multiplication layer 24 leading to enhanced passivation.
[0034] The passivation approach may be combined with proton or oxygen
implantation to additionally control the p-type semiconductor charge control
layer 22
and reduce the field at the edge of the outer mesa to further improve
passivation.
[0035] Additionally, the entire structure may be passivated by a suitable
passivation technique such as BCB.(benzocyclobutene). Alternatively, other
surface
passivation materials such as silicon dioxide, silicon nitride, or polyimide
could be
used to passivate the outside of the planar avalanche photodiode 210.
[0036] The planar avalanche photodtiode 110, as well as photodiode 10, is
high speed since the capacitance is low, due to the small area of the p-n
junction,
since the capacitance is not determined by the large noncritical isolation
mesa. Note
that these structures are reversed from the usual lnP/lnGaAs APD geometry
since
electrons are being avalanched in the InAlAs rather than holes as in InP. This
reversal allows the depletion field region in the InGaAs absorption region to
be at the
top of the device (i.e. near the surface of the wafer) rather than the as in
the
conventional InP APD. That is, these structures 10, 110 allow the high field
multiplication region to be buried under the low field absorption region. This
feature
means that the electric fields at the top surface look like those in a low
field PIN
detector, and thus guard rings are not needed, although, if desired, they can
be used
for additional field control.
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[0037] Figures 1 and 2 show that the p+ charge control layer 22, which can be
grown using carbon or Be as the p-dopant, extends across the entire isolation
mesa.
In spite of the large area of the p-n junction in this isolation mesa, the
capacitance
above punch-through is not substantially increased. This occurs because the
device
capacitance is (after charge punch-through and depletion) determined mainly by
the
area of the small diffused region (photodiode 10) or etched p+ region
(photodiode
110) and not the isolation mesa, thus leading to a low capacitance, high speed
APD.
[0038] Figure 3 shows the capacitance versus bias voltage for the structure
shown in Figure 2. The low capacitance occurring after the punch-through
voltage is
reached can be seen in Figure 3. Specifically, the capacitance starts out at
low bias
with a value corresponding to the area of the large isolation mesa together
with a
thickness of the multiplication layer. However, at high bias after punch-
through (that
is, when the charge control and absorption layers are depleted), the
capacitance
drops to a value corresponding to the area of the small p-contact 12 together
with a
thickness corresponding to the total depletion region between the p- and n-
contacts.
In addition, Figure 4 shows that ,the value of the capacitance above punch-
through
increases with the area of the p contact, but is independent of the area of
the large
isolation mesa as expected. For diameters less than 50 microns the mesa
diameter
along the abscissa corresponds to the mini-mesa (with the isolation mesa fixed
at 50
microns), and for diameters greater than 50 microns the mini-mesa is fixed at
40
microns while the isolation mesa is increased.
[0039] Furthermore, because of the electric field is a maximum in the center
of the InAIAs avalanche region, and low at the edges of the avalanche region,
guard
rings are not necessary although they may be used for fine control of the
fields. This
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is shown schematically in Figure 5 where the calculated field in the avalanche
region
24 is only large in the center of the APD directly under the p-contact. Thus,
the
avalanche gain, which depends exponentially on the field is only large in the
center
of the APD. This is experimentally confirmed as shown in Figure 6,
illustrating the
measured photocurrent gain as a function of the distance from the center of
the
device.
[0040] Similarly, as shown in Figure 7, the field in the low band-gap
absorption layer 20 is negligible at the edge of the isolation mesa in sharp
contrast
to a conventional mesa APD where the field is large at the mesa edge.
Furthermore,
since the current is also reduced at these surfaces, any charging of surface
or
interface states at these boundaries is reduced. Thus, this device design
effectively
passivates this low band-gap layer. This field reduction and passivation
results in a
device with improved lifetime and aging characteristics. In some
implementations,
the lifetime can exceed 2000 hours at about, for example, 150 C (that is, the
device
has a dark current that is substantially constant relative to an initial value
over a time
period greater than 2000 hours at about, for example, 150 C), which
corresponds to
a lifetime that is greater than 20 years at normal operating temperatures,
such as,
for example, 70 C.
[0041] Finally, Figure 8 shows the field as a function of distance from the p-
contact down to the n-contact in the center of the device. This plot shows
that the
charge control layer is effective in reducing the field in the absorption
layer to a very
low value, while simultaneously producing a high field in the avalanche layer
for
carrier multiplication.
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[0042] Thus, to obtain the localized p-contact for the field localization,
several
approaches are possible, for example, using an etched mini-mesa p-contact
(Figure
2) or a diffused p-contact (Figure 1). For the diffused p-contact, the InAlAs
contact
layer 16, into which the p-diffusion occurs, is grown low doped (either n- or
p-) in
order to reduce the electric field at the surface. The absorption and
multiplication
layers can be grown low doped to reduce the voltage required to deplete them.
[0043] Further note that although this contact is diffused it is different
than the
usual diffused p-contact for which critical doping control is essential, since
for the
standard diffused APD, this diffusion process controis the placement of the p-
n
junction, the magnitude of the electric field in the multiplication region,
the length of
the avalanche region, and the total charge in the charge control layer which
determines the values of the electric fields in both the high field avalanche
region, as
well as the low field InGaAs absorbing region. In contrast, for the APD 10
this p-
diffusion is only a p-contact requiring only noncritical process control.
[0044] As discussed previously, Figure 2 illustrates achieving a localized p-
contact region by etching a "mini-mesa" rather than using p-diffusing. That
is, the
full structure is grown initially including the p+ contact and then is etched
down (stop
etch layers can be used) to the low doped high bandgap InAlAs passivation
layer.
This defines a small localized p- contact region which controls the relevant
capacitance area, thus resulting in a low capacitance, and a high speed APD.
The
advantage of this structure is that it is completely grown initially and does
not require
any p diffusion. This structure has a low capacitance (Figure 3), a high speed
response, a high gain-bandwidth, optical response localized in the center of
the
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device (without the need of guard rings), and an extremely high sensitivity
when
used in a receiver.
[0045] In a particular implementation, a set of parameters for such a mini-
mesa APD is for example: a 50A p-doped cap layer of 1nGaAs followed by a 2000A
p-doped layer of InAIAs and a 100A stop etch layer of InGaAs all doped 5x1019
cm"3
This is followed by a 500A passivation layer of undoped InAlAs, a 180A undoped
digital grading layer, 8000A absorption layer of undoped InGaAs, another 180A
undoped digital grading layer, a p-doped charge layer with a sheet charge of
4.5x1012 cm"2, a 1300A undoped InAlAs multiplication layer, and a 7000A n-
doped
1019 cm"3 contact layer. An advantageous mini-mesa diameter is 33 microns, and
an
advantageous outer contact mesa is 60 microns. The capacitance of such an APD
is shown in Figure 3. These parameter values are only one possibility, other
doping
and thickness values and other materials such as InP can be implemented in the
APD. For instance, a contact layer can be an n-type contact layer using InP to
minimize or eliminate the increase in resistance caused by the diffusion of,
for
example, Fluorine in InAlAs contact layers.
[0046] Since, as discussed above, the photodiodes 10, 110 substantially
reduce the mesa electric field at the isolation mesa edge, compared with the
standard APD, guard rings are not necessary. However, if desired, additional
field
control can be obtained by the use of guard rings or a double diffused shaped
p-
diffusion front at the p contact. This may also be accomplished, for example,
by
implanting an n=dopant (e.g. Si) or a deep donor (e.g. 0) at the mesa edge, by
implanting an ion to create a semi-insulating region (e.g. H, He) at the mesa
edge, or
by hydrogen passivation at the edge. AII these methods reduce the magnitude of
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the p+ charge control layer at the mesa edge, and thus further reduce the
electric
fields. These modifications are shown schematically in Figures 9 and 10.
[0047] A planar avalanche photodiode designated as 210 in Figure 9 includes
a field control structure 30, such as an additional diffused region, an
implanted
region which can produce a doped or insulating region, or hydrogen
passivation.
The field control structure 30 is shown schematically as a pair of intrusions
into the
pianar avaianche photodiode 110. Figure 10 shows a planar avalanche
photodiodoe
310 with the mini mesa structure 32 and the intrusions 30. The photodiode 310
may
passivated by any of the other methods discussed above.
[0048] As described, various implementations of the present invention provide
numerous advantages, for example, the structure of the planar avalanche
region.
Moreover, the structure of the planar avalanche photodiode 10 and 110 shown in
Figures 1 and 2, respectively, or 210 and 310 shown in Figures 9 and 10,
respectively, is reversed from a typical InP/InGaAs avalanche photodiode
geometry
since electrons are being avalanched in the n-type semiconductor
multiplication
layer 24 as opposed to the avalanching of holes in an InP multiplication
region, as
found in conventional avalanche photodiodes. This structural inversion allows
the
low field region in the InGaAs absorption region to be at the top of the
device rather
than the high field avalanche region as in a standard InP avalanche
photodiode.
[0049] Thus, in the various implementations of the invention describe above,
the high field avalanche region is at the bottom (i.e. buried below several
semiconductor layers). Fabricating such a structure avoids the difficulty of
precisely
controlling the diffusion, etching or implantation steps, since all the layer
thicknesses
and dopings, including, in particular, the multiplication and the charge
control layers,
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are produced by the initial crystal growth, Thus, all these parameters are
under
excellent control, can be reproducibly grown, and are uniform over the entire
wafer.
The high field critical part of the structure is truly planar, is buried and
thus well
passivated, and the diffusion or alternatively the mini-mesa etching step
(which are
used for producing a small area contact) do not require any difficult
processing
control.
[0050] Because of the high uniformity of these APDs, and further because of
the simple processing required, all critical parameters grown in these devices
are
extremely uniform and have very high yield similar to PIN detectors. Thus,
large
uniform arrays of high performance APDs can be fabricated which are not
readily
achievable with standard APD technology.
[0051] The APD design in accordance with the invention can be combined
with enhanced PIN detectors to make an APD 410 as shown in Figure 11. By
controlling the shape of the diffusion profile 14 as it progresses into the
absorption
region 20, a pseudo field can be created which speeds up the carrier fransport
similar to a high speed PIN detector. The p- diffused region 14 is most
heavily
doped near the top of the contact 12 and is progressively less doped as the
diffusion
proceeds into the absorption region. Accordingly, the p-doped, hole
concentration
extends into the absorption layer and decreases as it progresses in the
absorption
layer, creating the pseudo filed and enhancing the electron transport, as well
as
decreasing the hole collection time. This permits a thicker absorption layer
and thus
improves sensitivity. Details of PIN detectors with the above described
features can
be found in U.S. Provisional Application No. 60/467,399, filed May 2, 2003,
and
International PCT Application entitled PIN Photodector, Attorney Docket No.
10555-
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068, filed herewith, the entire contents of which are incorporated herein by
reference.
[0052] The photodetectors described above can be implemented as
waveguide photodetectors or as single photon detectors. The photodetectors may
have an integrated lens for improved light collection.
[0053] The forgoing and other implementations are within the scope of the
following claims. For example, all n and p doped semiconductors may be
interchanged. That is the n and p doping may be reversed to provide a top mini
mesa of n type semiconductor and a lower contact of a p type.
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