Note: Descriptions are shown in the official language in which they were submitted.
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to data transmission systems, and more
particularly to a bifrequency encoded binary data transmission system
wherein the transmitted signal is predistorted to eliminate the need
for equalization at the receiving end.
Descrjption of the Prior Art
The distance over which an information carrying signal can be
transmitted by a transmission line is limited primarily by two factors:
(1) the signal to noise ratio of the transmission, and (2) the phase
distortion introduced by the transmission line. Increasing the signal
to noise ratio of the transmission is relatively easily accomplished.
On the other hand, transmission line induced phase distortion is a more
difficult problem since, even
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with a good signal to noise ratio, detection of the information may be
possible only after complex transformation of the received signal. In a
bifrequency encoded binary data transrnission sy~tem, an oscillograph of the
transmitted signal reveals a characteristic pattern of two repeating small
"eyes" each of which represents a half-bit period. The receiver gates on
the center of these "eyes" for detection of the signal and on the level trans-
itions for synchronization. Phase distortion which is a function of increas-
ing line length has the effect of closing or causing the disappearance of
these "eyes" with the result that detection of the signal is impossible.
In order to overcome the effects of phase distortion over long lines,
it is known to provide an equalizer or filter at the end of the transmission
line. The purpose of the equalizer is to introduce an inver~e distortion to
compensate for the transmission line distortion. But, since the line distor-
tion is a function of line length or distance, the equalizer must be tuned to
the distance. This means that any change in line length effectively requires
a redesign of the equalizer or an automatic equalizer. In addition to the
inflexibility ~f equalizers, they have the additional disadvantage of being
expensive to fabricate.
SUMMARY OF THE INVENTION -
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It is therefore an object of this invention to eliminate the need for
equalization at the receiving end of a binary data transmission system.
It i8 another object of the invention to generate a bifrequency encoded
binary data signal which can be readily detected at any distance up to a given
maximum without any change in the sending or receiving circuitry.
It is a further object of the invention to extend the distance over
which bifrequency encoded binary data signals can be transmitted without
sacrificing short distance or direct-coupled transmission performance which
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is both very inexpensive and easily fabricated.
2 According to the present invention, the foregoing and other objects
3 are attained by reducing the low frequency content of the transmitted signal
4 in the line driver. This is done by lowering the amplitude of the second half
of the long pulses to a value typically about one quarter or less of peak value.
6 Since each frequency propagates at a different speed and each has different
7 amounts of attentuation per unit distance of transmiæsion line, the resulting
8 narrowing of the band width has the effect of reducing distortion due to phase
9 shift error. This does not significantly affect signal detection on short lines
¦ and drastically reduces signal distortion on longer lines thereby simplifying
11 ¦ receiver design.
12 Implementation of the invention is quite simple and inexpensive using
13 ~ the techniques of modern technology. Logic circuitry is used to detect
14 I whether two consecutive half-bit intervals are equal. Two equal half-bit
intervals represent a long pulse, and the logic causes the drive level to be
16 lowered in the Yecond half of the long pulse.
17 ¦ ERIEF DESCRIPTION OF THE DRAWINGS
18 The specific nature of the invention, as well as other objects, aspects
19 uses and advantages thereof, will clearly appear from the following descriptior '
and from the accompanying drawings, in which:
21 Figur~ 1 illustrates a bipolar waveform consisting of short and long
22 pulses;
23 Figure 2 illustrates a predistortion of the bipolar waveform wherein
2~L the second half of all long pulses is transmitted at a reduced level;
Figures 3 and 4 illustrate bipolar waveforms predistorted so that the
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1 trailing end of every pulse is lowered, the difference in the pre-
d;stortion illustrated in the two Figures residing in the time at
which the amplitude level of the pulses is lowered~
Figure 5 is a logic and schematic diagram illustrating one
embodiment for implementing the predistortion of a bipolar waveform
according to the invention;
Figure 6 shown on the sheet of drawings bearing Figure 1 is a
timing diagram useful in understanding the operation of the logic
and circuit diagram of Figure 55
Figures 7(a) through 7(f) are illustrations of oscillographs of
a bipolar waveform without predistortion along varying lengths of a
transmission line; and
Figures 8(a) through 8(f) are illustrations of oscillographs of
a bipolar waveform predistorted according to the teachings of the
present invention at various lengths of a transmission line.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In a bifrequency encoded binary data transmission system, the
suitability of a received signal is judged based on two main aspects: ~.
1. At the receiving end the eye of the signal must open enough
to allow reliable determination of the signal polarity, since the ~ .
signal is sampled near the center of the eye. .
2. Pattern dependent timing jitter in the received signal should .
be as small as possible; that is, the transitions through the zero level
in the received signal should occur within a small time interval for
both short and long pulses.
Figure 1 of the drawings illustrates a typical bipolar waveform ~
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consisting of short and long pulses. For purposes of illustration, the long
2 pulses are considered to have a period 2T and the short pulses have a
3 period equal to T. Figure 1 illustrates two possible code as~ignments.
4 Thus, for example, two short pulses may represent a binary 1, and one
long pulse may represent a binary 0. On the other hand for what is commonly
6 referred to as the biphase code, a binary 1 may be represented by the
7 transition frorn a positive to a negative pulse level in the middle of a bit
8 period, while a binary 0 may be represented by the negative to positive
9 transition of the pulse level in the middle of a bit period. The code assign-
ment is, however, irrelevant with respect to the present invention since
11 the waveforms have identical features.
12 Given the bipolar waveform of Figure 1, it may be predistorted
13 before tran~mission over a transmission line according to any one of the
14 waveforms shown in Figures 2, 3 or 4. In the waveform shown in Figure 2,
the second half of all long pulses is tran~mitted at a reduced level indicated
16 in the Figure by the drop in amplitude at the reference numerals 10. In the
17 waveforms illustrated in Figures 3 and 4, the trailing end of every pulse is
18 lowered. In the waveform of Figure 3, the transition from the high level 11
19 to the low level 12 occurs at every time T/2 after a polarity change in the ~-
original waveform illustrated in Figure 1. In the waveform illustrated in
21 Figure 4, the ls~vel change occurs at time 3T/4.
22 In general, the waveforms of Figures 2, 3 and 4 are more costly
23 to implement in the order described. Selection of any one waveform depends
24 on the application. The bipolar waveform illustrated in Figure 1 is suitable
only for relatively short distances. The waveform of Figure 2 roughly double
26 the range; however, both of the waveforms illustrated in Figures 1 and 2
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generate con~iderable pattern dependent timing jitter at most distances.
2 Thus, in applications with chains of repeaters, the waveforms illustrated
3 in Figures 3 and 4 are preferred choice~, since they ~how very little timing
4 jitter at any distance up to the maximum. The relatively narrow peak pulse
of the waveform illustrated in Figure 3 suffers slightly more attenuation
6 than wider pulses, but the waveform illustrated in Figure 4 is a little more
7 complex to implement.
8 Once a waveform has been selected, the optimum high and low
9 levels may be determined from the following procedure. The peak amplitude
is chosen such that a sequence of all short pulses re~ults in a readily detect-
11 able signal at the end of a maximu~n length of tran~mission line. Since
12 attenuation on normal transmission lines is proportional to the square root
13 of the frequency, the wide pulses ~uffer le~s attenuation due to their lower
14 frequency spectrum. These wider pulses are weakened at the sending end
by lowering their trailing a~plitude enough, such that the amplitude of the
16 wide pulses at the end o$ the maximum length line exceeds the amplitude
17 of the short pulses by no more than about 20 to 50%O
18 In many cases it is desirable to adjust the amplitudes for minimum
19 timing jitter. For predistorted waveforms the trailing transition of
a wide pulse leads other tran~itions at distances up to a certain cross-
21 over distance, where the two tgpes of transitions coincide exactly. At
22 distances beyond the cross-over point, the trailing tran~ition of a wide
23 pulse lags the other transitions. A higher peak to low amplitude ratio
24 at the sending end will increase the timing lead for the short distances
and decrease the lag for the maximum di~tances. The ratio could,
26 therefore, be considered optimum if the maximurn timing
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1 lead equals the maximum timing lag. 1 ~ 3 9 6 6 0
An apparatus for generating the waveform illustrated by Figure 3,
for example, is shown in Figure 5. The bipolar waveform of Figure 1,
which may be denoted as code Q, is applied to the input terminal 21
which is connected to the enable or set input of flip-flop 22 and also
to AND gate 23. A clock signal at a frequency of 2fo is applied to ter-
minal 24 which is connected to the trigger input of flip-flop 22. To
initiate operation, a clear and preset signal can be applied to ter-
minal 25 which is connected to the reset input of flip-flop 22. The -
true output of flip-flop 22 designated as Q is connected to the other
input of AND gate 23. A second AND gate 26 is connected to receive
the NOT true output of flip-flop 22 designated as ~. AND gate 26 also
receives as an input the code ~ applied at terminal 27. The NOT or
inverted outputs of AND gates 23 and 26 are applied as inputs to a third
AND gate 28 which also receives the clock signal as an input.
Referring to the timing diagram of Figure 6, the clock signal at a
frequency 2fo which is applied to the trigger input of flip-flop 22 and
one input of AND gate 28 is illustrated at the top of the Figure. Code
Q which is applied at terminal 21 to the set input of flip-flop 22 and
AND gate 23 is illustrated as the second waveform. The opposite or in-
version of code Q designated as code ~ is illustrated just below. The
operation of flip-flop 22 is such that it is set in coincidence with
the clock pulses when the bipolar code Q is at a high level or on the
trailing edge of the bipolar code. The flip-flop 22 is reset in co-
incidence with the clock pulses when the bipolar code is at a low level
Or on the leading edge of the bipolar code. This operation is illus-
trated by the waveforms designated as FFQ and FFQ representing the -
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true and not true outputs of flip-flop 22. The outputs of flip-flop 22 are used
2 to gate the code and its inverse in AND gates 23 and 26. Specifically, the
3 code Q and the true output of flip-flop 22 produce a negative going gating
4 signal 29 at the output of AND gate 23. Note that this is the inversion of the
true output of AND gate 23. In a similar manner, the inversion of the code
6 Q, that is, code Q, and the not true output of flip-flop 22 produce the output
7 gating signals 31 of the AND gate 26. Note again that these are negative
8 going or the not true outputs of AND gate 26. The negative going signals 29
9 and 31 from AND gates 23 and 26, respectively, may be considered as
inhibiting signals which control the passage of the clock signal through AND
11 gate 28. The effect of this is illustrated in Figure 6 which shows the output
12 of AND gate 28.
13 The output of AND gate 28 is connected to one side of a collector
14 resistor R2. Transistors T10 through T16 represent a switchable current
source. Such current sources are in common use in today's integrated
16 1 circuits. The collector and base of transistor T16 are connected in co~nmon
17 to the junction of AND gate 28 and the collector resistor R2. The emitter of
18 transistor T16 is connected to ground through re~istor R16, while the emitters
19 of transistors T10 through T15 are connected to ground through resistors ;~
R10 through R15, respectively. If a current I flows through the diode-
21 connected transistor T16, nearly equal currents I flow through each of the
22 other six transistors, all of which have a common base with transistor T16.
23 Thus the common collector junction 32 of transistors T10 through T15 will
24 sink a current approximately six times the current of transistor T16. The
amount of current flowing through T16 is determined by the value of the
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¦ resistor R2, and this current is switched by the output of AND gate 28.
2 The operation of AND gate 28 is such that when the output i~ at a low level,
3 it will divert essentially the entire R2 current to ground by-passing transistor
4 Tl6.
The current source comprising tranYistors TlO through T16 drives
6 a push-pull line driver. The current drive provided by the transistors TlO
7 through Tl6 is the peak current as will be clear from the description of the
8 driver operation. In addition to the peak current source, there is a parallel
9 steady-state current source represented by the transistors TS, T6 and T7.
The base of transistor T5 is connected in common with its collector through
11 resistor Rl to a source of positive potential. The emitter of transistor T5
12 is connected through resistor R3 to ground, while the emitters of transistors
13 T6 and T7 are connected through resistor R4 to ground. The collectors of
14 transistors T6 and T7 are connected in common to the co~nmon junction 32.
As in the peak current source, the bases of transistors T6 and T7 are commo~
16 with the base of transistor T5. The common junction 32 is connected to the
17 emitters of transistors Tl and T2 which are current steering transistors.
18 The collectors of transistors Tl and T2 are connected to opposite ends of a
19 center tapped primary winding of transformer 33. The center tap of the
primary winding of transformer 33 is connected to a source of positive voltage
21 and through a decoupling capacitor C2 to ground. If the base voltage on
22 transistor T2, for example, is sufficiently higher than on the base of trans-
23 istor Tl, all the current, both peak and steady-state, will flow through
24 transistor T2 and the left section of the transformer primary, generating a
more positive voltage on the output terminal 34 when referenced to output
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1 terminal 35 of the secondary winding of transFormer 33. With transis-
tor Tl conducting and transistor T2 off, the output polarity at out-
put terminals 34 and 35 is reversed.
The bivalue code wave Q and Q is connected to the circuitry which
drives the bases of transistors Tl and T2. More specifically, the code
Q applied at input terminal 21 is connected to the emitters of trans-
istors T9 and T18, and the inverse of the code Q is applied to the ~;
emitters of transistors T8 and T17. Each of the transistors T8, T9,
T17 and T18 is diode-connected, i.e., their base and collector junctions
are connected in common. The collector of transistor T9 is connected ~
to the base of transistor T4 and through a collector resistor R6 to a ~-
common junction 34. In a similar manner, the collector of transistor T8
is connected to the base of transistor T3 and through a collector re-
sistor R7 to the common junction 34. The collector of transistor T18 is
connected in common to the base of transistor T2 and the emitter of
transistor T4, while the collector of transistor T17 is connected in com-
mon to the base of transistor Tl and the emitter of transistor T3.
The collectors of transistors T3 and T4 are both connected to a source
of positive potential. The common junction 34 is connected also to a
source of positive potential through series connected resistor R5 and
diode-connected transistors Tl9 and T20. Diode connected transistors
Tl9 and T20 and resistor R5 are used to limit the maximum positive swing
at the base of transistors Tl and T2 in order to avoid saturation.
Transistors T3 and T4 are emitter followers and provide the considerable
base drive current required for the current steering transistors Tl and
T2. Transistors T8 and T9 in diode connection disconnects the emitter
followers in the output of the code source from the
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driver. This may be required where the code source up-level is not well
Z controlled and may rise too high. Transistors T17 and T18 provide a
3 sufficient voltage drop to avoid shunt currents from transistors T3 and T4
4 into the code source outputs at the down level. Resistors R8 and R9 con-
nected across the secondary winding and the primary winding, respecti~ely,
6 provide a match for the external transmission line. The capacitor Cl
7 connected across the primary winding is u~ed to ~mooth the waveform
8 and reduce possible radiation.
9 In operation, the code and its inverse Q and Q control steering
transistors Tl and T2. The output of AND gate 28 controls the peak current
11 source comprising transistor~ T10 through T16 when the Code Q iB at a high
12 level, transistor T2 will conduct a peak current for the duration of one clock
13 pulse. The steady-state current source comprising transistor T5 through T7
14 p~4~ides the low le~rel pedestal for the duration of the output signal. When
the inverse of the code Q is at a high level, transistor Tl will conduct a
16 peak current for the period of one clock pulse and thereafter the steady-state
17 current source provide the low pedestal for the duration of the output signal.
18 This operation is illustrated by the waveform at the bottom of Figure 6.
19 Figures 7(a) through 7(f) illustrate the line driver output without
predistortion of a 1. 39 Mbit/sec signal over varying lengths of 24 gauge
21 twisted pair transmission line. Notice that at the end of 4, 000 feet of
22 transmission line as illustrated in Figure 7(e), one of the two small eyes
23 has disappeared for the regular unequalized signal. In comparison,
24 Figures 8(a) through 8(f) illustrate the signal on the transmission lines
when subjected to predistortion according to the teaching~ of the invention.
.
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At all lengths of transmission line, the predistorted signal illustrated in
2 Figures 8(a) through 8(f) does not need any further equalization. Heavier
3 gauge wire like the common AWG22 in telephone exchange areas will, of
4 course, allow transmission over longer distances,
It will be apparent that the embodiment æhown i9 only exenlplary
6 and that various modification~ can be made in construction and arrangement
7 within the scope of the invention as defined by the appended claims. For
8 example, while the circuit ~hown in Figure 5 is intended to generate the
9 waveform shown in Figure 3, those skilled in the art will recognize that
simple logic circuits can be implemented which generate the waveform
11 shown in Figures 2 and 4 or, for that matter, any variation thereof de-
12 pending upon the desired application.
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