Note: Descriptions are shown in the official language in which they were submitted.
16Background of the Invention
17Field of the Invention
18~he present invention relates to an arrangement for
19 stabilizing the input circuit of a bipolar semiconductor
device used in emitter follower or current switching
21 configuration. More particularly, the invention concerns
22 an arrangement for stabilizing the input circuit of such
23 a semiconductor device by the addition of lumped capaci-
24 tance between the base of the semiconductor and ground.
25Description of the Prior Art
26It is well known that the input impedance of bipolar
27 transistors utilized in current switching and emitter
28 follower configurations often exhibit a negative real
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1 part over a usual range of operating frequencies of
2 such devices. This is particularly true of certain
3 bipolar transistors fabricated by larqe scale integration
4 techniques and specifically those utilizing recessed
oxide isolation since the base collector feedback
6 capacitance of such transistors is greatly reduced as
7 compared to the feedback capacitance of other types of
8 bipolar transistors.
9 When such LSI bipolar transistors are driven by a
circuit having a driving point impedance that is primarily
11 inductive, such as commonly occurs when the devices are
12 utilized in current switching and emitter follower type
13 configurations, the transistors are subject to instability
14 and under certain conditions may develop sinusoidal steady
state oscillations within the input circuit. It should
16 be noted that this is a problem unique to bipolar
17 transistor circuits, i.e. it is usually not encountered
18 in connection with FET circuits.
19 Various approaches have been utilized in the prior
art to eliminate or mini~ize such instabilities, usually
¦ 21 based upon an effort to reduce or eliminate the negative
22 real part of the input impedance of the semiconductor
23 to be stabilized. One method of reducing the negative
24 resistance is to add a series base resistance within
the circuit which, in effect, reduces the negative real
26 part of the input impedance by an amount e~ual to the
! 27 added resistance. This in turn causes thesZin plot of
1 28 the device for a given frequency to move from the third
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1 quadrant toward the fourth quadrant of a nyquist diagram,
2 in well known fashion. This method of stabilization
3 works satisfactorily in certain instances. However,
¦ 4 the magnitude of the added series based resistance must
be equal to or greater than the magnitude o the negative
6 real part of the transistor input impedance in order to
7 achieve stability. In many cases, therefore, the required
8 stabilizing resistance would necessarily be so large that
9 the noise tolerance of the circuit would become unsatis-
factory, due to base current IR drop across the added
11 resistance. Furthermore, the addition of large base
12 stabilizing resistance values to emitter follower type
13 circuits generally has the effect of reducing switching
14 time to unsatisfactory levels.
Consequently, in order to achieve stability of
16 emitter follower configurations, other methods have been
17 attempted in conjunction with the addition of series
18 base resistance to move the Zin plot to the right toward
19 the fourth quadrant. Such methods have included in-
creasing the collector base capacitance of the transistor,
21 as well as increasing the collector resistance to provide
22 more negative feedback within the circuit.
23 Again, such methods have proved satisfactory in
z 24 certain instances to achieve stabilization of emitter
follower type circuits. However, many applications of
26 emitter follower circuits have been found to require the
27 addition of excessive series base resistance to achieve
28 stability even in the presence of added collector base
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1 capacitance and increased collector resistance. Accord-
2 ingly, a need exists in the art for an axrangement for
3 satisfactorily stabilizing emitter follower and current
¦ 4 switching type transistor circuits without reducing the
1 5 switching time and eliminating satisfactory noise toler-
¦ 6 ance.
7 Summary of the Invention
1 8 Accordingly, the pres`ent invention is directed
9 toward an arrangement for stabilizing a bipolar semi-
~¦ 10 conductor device such as might be commonly used in
` 11 emitter follower or current switching configuration by
12 the addition of lumped capacitance between the base of
j 13 the semiconductor device and ground. In one preferred
,1 14 embodiment the lumped capacitance is derived from a
~I 15 flared or enlarged end of a base stabilizing resistor
ij 16 connected to the base of the semiconductor device, and
¦! 17 in an alternative embodiment the capacitance is derived
18 from a base collector junction of another unconnected
~¦ 19 semiconductor device located upon a common substrate
with the semiconductor to be stabilized. The effect of
21 the lumped capacitance, when added to the circuit, is
22 to move the Zin plot of the transistor toward the fourth
23 quadrant of a nyquist diagram without the addition of
, 24 a large series base resistance. The addition of the
lumped capacitance is preferably utilized in conjunction
i ~ 26 with a small base stabilizing resistor in order to
27 achieve stability in the input of the semiconductor.
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1 Brief Description of the Drawings
2 The above advantages and certain other features
3 and advantages of the invention will hecome more clearly
4 apparent in view of the following detailed description
S of the invention taken in conjunction with the accompany-
6 ing drawings wherein:
7 FIGURF. 1 comprises an electrical equivalent circuit
8 of a typical bipolar semiconductor utilized in a common
9 emitter configuration with lumped capacitance added in
accordance with the invention;
11 FIGURE 2 is a schematic top view of a monolithic
12 chip of semiconductor material supporting a bipolar semi-
13 conductor device having base, emitter and collector
14 terminals, the semiconductor device being associated
with a base stabilizing resistor hàvin~ a flared or
16 enlarged end portion providing lumped capacitance; and
17 FIGUR~ 3 is a schematic representation in vertical
18 cross-section of a device similar to that illustrated in
19 FIGURE 2.
Detailed Description o the Invention .
21 Referring now to the drawings, and particularly to
22 FI,URES 1-3, one preferred embodiment of the invention is
23 illustrated wherein a bipolar semiconductor device is
24 stabilized by the addition of lumped capacitance electri-
cally connected between the base of the semiconductor
26 and ground. More particularly, FIGURE 1 illustrates an
27 electrical schematic diagram of a bipolar transistor 12
28 adapted to be deposited or fabricated upon a monolithic
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1 chip of semiconductor material, such as that indicated
1 2 by numeral 10 in FIGURE 2, for example, by conventional
3 means such as large scale integration techniques. Tran-
4 sistor 12 is illustrate~ as including at least a collector
14 having a collector resistor 16 associated therewith,
6 an emitter 18 having an emitter resistor 20 associated
7 therewith and a base 22 having a base stabilizing resistor
8 24 associated therewith. As shown, resistor 24 has one
9 end 2S electrically connected to a circuit input terminal
10 27 and its other end 26 electrically connected to base 22.
11 The transistor is connected in typical emitter follower
12 configuration and has associated therewith a capacitor 28
13 which is electrically connected between base 22 o the
14 transistor and ground terminal 30.
In one preferred embodiment of the invention, such
16 as will become apparent from the following description
~l 17 of FIGURES 2 and 3, capacitor 28 comprises the lumped
i 18 capacitance associated with a flared or enlarged end of
19 a diffused resistor which forms or corresponds to
~! 20 resistor 24 of FIGURE 1. More particularly, FIGURES 2
1 21 and 3 illustrate a monolithic chip 10 generally comprising
22 a substrate 40 of P negative material having an epitaxial
23 layer 42 of N negative material overlying it. A bipolar
1, 24 transistor such as transistor 12 is illustrated on the
l~ 25 left side of the substrate including a subcollector
~, 26 region, of N+ material designated by numeral 43, which
27 is covered by a portion of epitaxial layer 42, and a
~i 28 P diffusion layer 44 formed within layer 42 in well ;
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1 known fashion. The subcollector region is bounded on
2 the right and left sides by recessed oxide isolation
3 channels 47, 48 overlying P positive isolation regions
4 51, 52 respectively.
Subcollector 43 is exposed to the surface of the
6 chip via collector region 53 having a collector terminal
7 14 associated therewith, and an emitter region 55 is
8 formed, again in conventional fashion, in diffusion
9 layer 44 and has an emitter terminal 18 associated
therewith. P diffusion layer 44 comprises the base of
11 the transistor and has base electrode 22 associated
~ 12 therewith, again in conventional fashion. The chip
¦ 13 otherwise includes a recessed oxide isolation region
! 14 58 utilized to isolate the base region of transistor
12 from the collector electrode region.
16 On the right side of FI~URE 3, a resistor 24 is
17 schematically illustrated, formed by a P diffused layer
18 60 formed within epitaxial N- layer 42 separated from P
~! 19 negative substrate 40 by the N+ subcollector region 43,
again in well known fashion. The resistor is completely
21 bounded by recessed oxide isolation regions 48, 65
22 respectively and is otherwise provided with resistor
' 23 electrodes 25, 26. As shown electrode 25 is electri-
24 cally connected to input terminal 27 and electrode 26
Ij 25 is electrically connected to base 22 of the transistor.
i3 26 Silicon dioxide regions 70, 71, 72 are illustrated as
27 covering and completing the structure of the bipolar
28 transistor and its associated stabilizing resistor.
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1 Referring now to FIGURE 2, region 29 of P diffused
2 layer 60 that exists between electrodes 25, 26 comprises
3 the resistive re~ion of resistor 24. Furthermore, the
4 PN junction capacitance of the diffusion bed of the
resistor extending between electrodes 25, 26 comprisies
6 a capacitance distributed along the length of the resistor.
7 In addition, the PN junction of the diffusion bed of the
8 portion of resistor 24 which exists at the left side of
9 the resistor in FIGURES 2 and 3 and corresponds to the
enlarged or flared end 80 of the resistor visible in
11 FIGURE 2 comprises a lumped capacitance which is electri-
I2 cally associated or connected between the base of
13 transistor 12 and a ground terminal associated with the
14 substrate. Accordingly, the capacitance of flared end
80 of resistor 24 corresponds to capacitor 28 in FIGURE
16 1 and provides a stabilizing influence upon the bipolar
17 transistor as explained hereinbefore.
18 In general it is preferred that capacitance
19 provided by an enlarged area having a cross section of
about 20~i greater than the width of the narrow portion
21 of the diffused resistor be added to enable stabilization
22 of an emitter follower utilized bipolar transistor,
23 without degradation of its operating parameters. However,
24 it should be apparent that more or less capacitance can
be utilized if desired.
26 In an alternative form of the invention the capac-
27 itance associated with the base of transistor 12 is
28 derived from a PN junction of an otherwise uncon~ectod
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1 device also located on chip 10. The capacitance of
2 the PN junction is electrically connected to base 22
3 of the transistor by means of an electrical lead in
4 well known fashion. In general, the capacitance
associated with such a PN junction is suitable for the
6 stabilizing function described herein. The alternative
7 embodiment of the invention can be utilized where
8 connected semiconductor junctions or devices exist upon
9 the same monolithic chip, and where the architecture
of the chip permits the use of an external connecting
11 strip. However, the preferred embodiment has certain
12 advantages where emitter follower configurations are
13 used on isolated chips or where other PN junctions are
~' 14 not available. Furthermore, the extra area required
for flaring or enlarging the end of resistor 22 to
16 provide a lumped capacitance is a parameter which can
~, 17 usually be designed into a circuit in much more economic~, 18 fashion than a connecting strip.
' 19 It has been found that the arrangements described
in FIGURES 1-3 result in an improved stabilizing arrange-
21 ment for bipolar transistors when utilized in emitter
22 follower or current switching applications. Thus, the
23 use of lumped capacitance between base and ground of the
~ 24 transistor, whether the capacitance is provided by a
-~ 25 flared end of a series base stabilizing resistance or
! 26 provided by other means such as the PN junction of
27 another semiconductor device, permits stabilization of
28 the transistor through the use of a series base resistance
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1 of much lower magnitude than was heretofore possible.
- 2 This in turn allows the transistor to be operated
3 without significant loss of switching speed and without
4 objectionable loss of noise tolerance.
While the invention has been described in detail
6 with reference to specific embodiments thereof, it
7 will be apparent to one skilled in the art that various
8 changes and modifications can be made therein without
9 departing from the spirit and scope thereof.
What is claimed is:
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