Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
This invention relates to an automatic common control
switching system for local and/or toll tandem switching. More
particularly, it relates to an arrangement for alternately
assigning a marker to two translator assigners of the system.
In co-pending U.S. Patents No. 3,830,984, issued
August 20, 1974, titled "An Automatic Common Control Switching
System" and No. 3,806,717, issued April 23, 1974, titled "A
Method and Means for Simultaneously Testing Counter Check Circuit",
there is disclosed an automatic common control switching system
for local and/or toll tandem switching. In this system, two
translator assigners are used to recognize requests from the
register/senders for one of the two translators of the system.
The translator assigner connects the translator to the requesting -
register/sender, and upon receiving a "call for marker" signal
from the translator, searches for an idle marker and assigns
the latter to the translator. There are up to ten markers
in the system which communicate over a highway which is common ;
to the two translator assigners.
SUMMARY OF THE INVENTION
In small offices, where traffic considerations require
only two or three markers, the condition where only one marker
is functioning can arise. In such a case, both of the trans- ~;
lator assigners will try to seize the marker, and one trans- ~ -
lator assigner may access the marker several times while the
other translator assigner is denied access, times out, and
reports on "all marker busy" status. `
The arrangement of the present invention detects the ~ ~ -
condition when only one marker is "on line", and then alternates
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the assignment of the marker between the two translator assigners.
More particularly, each translator assigner in the
system includes a detection circuit which monitors up to ten
"marker busy" leads. Whell only one marker is "on line", and
S providing that both translator assigners are functioning and
"on line", the detection circuit of both of the translator
assigners will start the sequence of alternating the assignment
of the marker. If the condition changes, i.e., more than one
marker becomes available or one translator assigner is removed
from service, the arrangement will release. Thereafter, the
assignment of the markers by the translator assigners will be
accomplished via its normal sequence.
Accordingly, it is an object of the present invention
to provide an improved automatic common control switching system
fox local and/or toll tandem swltching.
More particularly, it is an object to provide within
,
such a system an arrangement for alternately assigning a
marker to the system's two translator assiyners.
- Other objects of the invention will in part be obvious
and wlll in part appear hexeinafter.
BRIEF DESCRIPTION OF THE DR~WINGS
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For a fuller understanding of the nature and objects
of the invention, reference should be had to the following
detailed description taken in connection with the accompanying
drawings in which:
FIG. 1 is a block diagram schematic of the automatic
common control switching system; and
FIG. 2 is a block diagram schematic of the arrange-
ment for alternately assigning a marker to the system's two
translator assigners.
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Similar reference characters refer to similar parts
throughout the several views of the drawings. -
DESCRIPTION OF T~IE PREFERRED EMBODIMENT
Referring now to Fig. 1, the automatic common
control switching system, or crosspoint tandem system as it
is commonly referred to, is illustrated in a block diagram
schematic. The maximum capacity of the crosspoint tandem
system is 6000 incoming trunks, however, the 6000 trunks are
divided into groups of 1000 trunks with each group of 1000
trunks being served by a register-sender access subsystem
RAC (hereinafter RAC units). The trunk circuits are given access
to the register senders by means of a two-stage register-
access network (hereinafter RAN units) which employs 1 x 50
crosspoint switches arranged in back-to-back configuration. ~ -
The RAN units are controlled by the RAC units, and
the latter are configured in pairs such that each RAC unit
normally controls the connection of up to 500 trunks with up
to 50 register senders. These RAC units are electronic sub-
systems using electromechanical interfaces to communicate with
the adjoining electromechanical subsystems. Functionally, the
RAC units can be divided into two major logic blocks: the
common control logic block which is basically a sequence state
controller SSC and the peripheral logic block comprised of ~; -
a trunk identifier, a link selector, a register sender selector,
a trouble recorder access, a register sender access encoder, and
a transfer circuit.
The~sequence state controller SSC determines the order
of events and the major tasks to be performed by the subsystem.
The subsystem is "wire programmed" for that purpose. The ;
circuits of the peripheral logic block execute the commands
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given by the sequence state controller SSC and receive informa-
tion signals from and extend commands to the adjoining subsystems.
When a connection has been setup between a trunk and
a register sender, the register sender receives the called
address in either dial pulse or MF mode from the trunk circuit.
The originating class is transmitted to the register sender by
the RAC unit, coincident with setting up the trunk to register-
sender connection.
After sufficient called address digits have been
received, the register sender calls for a connection to a
translator TSL. This connection is effected by one of a
duplexed pair of translator assigners ASG which also controls
connections between the translators and markers, between markers
and the automatic trunk routiner, and between markers and the
marker test panel.
When the connection with the translator TSL has been
effected, the register sender loads the called address infor- `~
mation and the originating class information into the translator -~
TSL. The translator TSL processes this information.
After the translator TSL has derived call switching ~-
data from the data input from the register senders, it calls
for the services of one of the markers through the translator
assigner ASG. Upon finding and assigning an idle marker, the
translator assigner ASG controls the transmission of call
25 switching data from the translator TSL to the selected marker. `~
The call switching data includes enough information to enable
a marker to make a second attempt to complete the call across
the transmission matrix, should there be no cross matrix paths
or trunks in the selected sub-group available on the first
attempt.
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Having received the identity and location of the
incoming trunk and the location and identities of the outgoing
trunk sub-groups to the desired destination~ the marke~ performs
the function of connecting the calling inlet to an appropriate
out~et. It then seizes the outgoing trunk, and checks for
path integrity from the register sender through the matrix
and outgoing trunk. Having successfully completed the path
integrity check, the marker transfers control to the register
sender and releases, ready to serve another call.
After the register sender has transmitted called
address information to the next switching machine, it releases
from the connection and transfers holding control to the incoming
trunk.
As indicated above, the circuits and the descriptions
of the same in establishing a connection through the crosspoint
tandem system are more fully disclosed in the above-identified -~
U.S. Patent Nos. 3,830,984 and 3,806,717 and reference may be ;~
made to these patents for the detailed description of the ;
operation.
As indicated above, and as more fully set forth in -;~
the above-identified U.S. patents, two translator assigners ASGA
and ASGB are used to recognize requests from the register/senders
for one of the two translators TSLA and TSLB of the system.
The translator assigner ASGA ~or ASGB) connects the translator
25 TSLA (or TSLB) to the requesting register sender, and upon `~
receiving a "call for marker" signal from the translator TSLA
(or TSLB), searches for an idle marker and assigns the latter
to the translator TSLA ~or TSLB). The markers communicate
over a highway which is common to both the translator assigners
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ASGA and ASGB. The operation of the translator assigners ASGA
and ASGB are asynchronous in operation, under the control of
their respective sequence state controllers SSCA and SSCB.
As previously explained, the various different modes of operation
are effected during various different sequence states SS0-SS9.
Output signals SS0-SS9 representative of each of these respective
sequence states are outputed by the respective sequence state
controller SSCA and SSCB.
In FIG. 2, there is disclosed an arrangement for
detecting the condition when only one marker is "on line",
and for alternatley assigning the marker between the two trans-
lator assigners ASGA and ASGB. As explained above, such a
condition can occur in small offices, where traffic conditions
require only two or three markers. The arrangement includes
detection circuits 10 and 20 which are incorporated within
each of the translator assigners ASGA and ASGB. These detection
circuits 10 and 20 may be "one-out-of-ten" checking circuits
of the type disclosed in the above-mentioned U.S. patents.
These detection cirucits 10 and 20 are used to monitor the
"marker busy" leads 30 of up to ten markers. These leads 30
are coupled from the "marker busy" leads 40 forming part of
the common highway between the markers and the translator
assigners ASGA and ASGB, and which normally are coupled to -~
the marker seizure circuits MSLA and MSLB of the respective
translator assigners. The availability of an on line marker, -
i.e., busy or idle, normally is indicated to the marker seizure
circuits MSLA and MSLB via the "marker busy" leads 40, and
is seized via the marker seizure leads SZMKR 50.
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For the purpose of explaining the operation o~ the
arrangement of Fig. 2, assume first of all that there is more
than one marker on line and that both the translator assigners
ASGA and ASGB are on line. Under these conditions, the checking
circuits 10 and 20 are operative to output, in this particular
case, a logic level one signal to the respective inverters
13 and 14, since in this particular described embodiment, NAND
logic is used. The logic 1 level signal outputs from the
checking circuits 10 and 20 indicate that more than one marker
is on line and available for service, as more fully described
below. Also, the translator assigner ASGA and ASGB via the
respective sequence state controllers SSCA and SSCB associated
with them each output a logic 1 level signal to the NAND gate
15, and to the respective AND gates 27 and 28. At this time,
15 both the latches 25 and 26 are reset and, therefore, output a -
logic 1 level signal to the AND gates 28 and 27, respectively. --
These inputs to the AND gates 27 and 28 in coincidence with
logic 1 level signals from the latches 25 and 26 enable them
to output a logic 1 level signal to the respective AND gates
31 and 32. When the AND gates 27 and 28 are enabled, during
normal operation, the AND gates 31 and 32 are enabled via the
signals on the control leads CONT from the respective sequence
state controllers SSCA and SSCB to, in turn, enable the marker
seizure circuits MSLA and MSLB to seize a marker, via the
marker seizure leads SZMKR. Under these conditions, normal
system operation is established.
As indicated above, output signals representative
of each of the respective sequence states are generated by
the sequence state controllers SSCA and SSCB, and, in this
particular case, the signals representing the sequence states
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SS0, SS4 and SS5-SS8 are coupled to the arrangement of Fig. 2.
In sequence state 4, the signal SS4 is coupled to the AND gate
17, and 18, to perform a test to see if there is only one marker
on line. During normal operation, as described above, neither
the AND gate 17, or 18, is enabled.
Assume, now, however, that a condition arises that
only one marker is on line and operable. Under such circum-
stances, each of the checking circuits 10 and 20 now will output
a logic 0 level signal to the respective inverters 13 and 14,
which in turn, then output logic 1 level signals to the
respective AND gates 17 and 18. With both of the translator
assigners ASGA and ASGB on line, the NAND gate 15 is enabled to -
output a logic 0 level signal to the inverter 16, which in
turn, then outputs a logic 1 level signal to the AND gates 17- ~
15 and 18. Now, during sequence state 4 of the sequence state -
controller SSCA, the signal SS4 is at a logic 1 level and all ~ ~-
of the inputs to the AND gate 17 are at a logic 1 level. The -
AND gate 17 therefore is enabled to output a logic 1 level
signal to the AND gate 23. This signal in conjunction with the
logic 1 level signal from the latch 26 which is at this time
reset enables the AND gate 23. The AND gate 23 outputs a logic ~ -
1 level signal to the latch 25 to set it. The latch 25, upon
being set, outputs a logic 1 level signal to the AND gate 19,
and a logic 0 level signal to the AND gate 28 and to the AND
gate 24. This logic 0 level signal to the AND gate 28 disables
this gate to prevent the translator assigner ASGB from seizing
the marker, by effectively disabling the AND gate 32, and hence
the marker seizure circuit MSLB. This logic 0 level signal also
disables the AND gate 24, to prevent the latter from outputing
a signal to set the latch 26.
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-- Durinc3 the sequence states 5-8 of the sequence state
controller SSCA, the latch 25 is reset, by the signals SS5-SS8
which are coupled through the OR gate 11 or the OR gate 21 to
enable the latter to output a logic 1 level siynal to reset the
latch 25. The signals SS5-SS8 provide a timing interval duriny
which the latch 25 is reset. With latch 25 reset, a logic 1
level signal again is coupled to the AND gates 28 and 24, and
a logic level 0 signal is coupled to the AND gate 19. The
arrangement therefore is effectively restored to its original
configuration, and is ready to now assign the marker to the
translator assigner ASGB, when a request is received. This is
as follows.
During sequence state 4 of the sequence state controller
SSCB, the operation of the latter being out of synchronism with
- the sequence state controller SSCA, the signal SS4 will enable the
AND gate 18, and the latter outputs a logic 1 Ievel signal to the
AND gate 24. Since latch 25 now is reset and therefore outputing
a logic 1 level signal to the ~D gate 24, the latter is enabled
to output a logic 1 level signal to the latch 26 to set it. The
latch 26, upon being set, outputs a logic 1 level signal to the
AND gate 19, and a logic 0 level signal to the AND gate 27 and
to the ~D gate 23. These AND gates 27 and 23 inhibit the AND
gate 31 and prevent the latch 25 from being set, respectively, in
the manner described above in the case of the AND gates 28 and
24. Under these conditions, the next call for a marker there-
fore will be processed by the translator assigner ASGB.
When the sequence state controller SSCB advances to
sequence state 5-8, the signals SS5-SS8 are coupled through the
OR gate 12 to the OR gate 22, to enable the latter to, in
turn, output a logic 1 level signal to the latch 26 to reset it.
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The latch 26, upon being reset, again removes the disabling
signals coupled to the AND gates 27 and 23. ~-
When the sequence state controller SSCA advances to
the sequence state 0, the signal SS0 is coupled to the OR gate
21 to enable it to output a logic 1 level signal to the latch
25, to again reset it, in the event it was not reset during the
normal sequence of operation. The same is true with respect ~ .
to the sequence state controller SSCB. When the latter advances
to sequence state 0, the signal SS0 is coupled through the OR
gate 22, to make sure that the latch 26 was reset.
If for any reason, both latches 25 and 26 are set,
both will output a logic 1 level signal to the AND gate 19.
The AND gate 19 therefore will be enabled, and will output a
logic 1 level signal through the OR gate 22 to reset the latch
26. Accordingly, only one of the latches 25 and 26 can be set ~
~and .remain set, with preference being given to the latch 25 .
in the:event both should be momentarily set for any reason. .
Provision also is made for manually resetting each or both of
the latches 25 and 26, by signals applied to the MAN RST .~ ~ .
leads of both latches.
Accordingly, from the~above description, it can be ~ :
seen that during sequence state 4 of the res:pective sequence state .~ :
controllers SSCA and SSCB, the AND gates 17 and 18 are enabled
to check to .s.ee if there is only one marker on line. If there
is only one marker on line, since the sequence state controllers
are operating as.ynchronously, one or the other of the latches
25 and 26 will be set to inhibit the enable marker signal from
the AND gates 28 and 27, respectively. At the end of the cycle, ~ .
the latch inhibiting the enable marker signal is reset and,
30 thereafter, during the course of operation, the opposite one ~ ~:
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of the latches is set to inhibit the enable marker signal from
its associated AND gate 27 or 28.
This alternate processing of calls by both of the
translator assigners ASGA and ASGs will continue until a second
marker becomes available, or one translator aSsigneT is taken
out of service. In the former case, the AND gates 17 and 18
effectively are disabled, by the removal of the logic 1 level
signals from the inverters 13 and 14, thus permitting the opera- -
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tion to proceed in the normal course of events. In the latter
case, the signal from the "out-of-service" one of the translator
assigners ASGA and ASGB to the NAND gate 15 is removed, thus
effectively disabling the AND gates 17 and 18 to thereby prevent
the latches 25 and 26 from being set. With both latches 25
and 26 reset, these latches output logic level 1 signals to the
AND gates 28 and 27, respectively, so that normally these gates
would be enabled by the signals from the on line translator
assigners ASGA and ASGB. However, in this case, only the AND gate
27 or 28 will be enabled, since one of the translator assigners
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now is not in operation. Therefore, only the AND gate 31 or 32
associated with the on line translator assigner will be enabled,
in the manner described above to permit the marker seizure
circuit MSLA or MSLB to seize the marker. When the translator
assigner is put back into service, the operation automatically
reverts to normal operation.
It will thus be seen that the objects set forth above
among those made apparent from the preceding description, are
efficiently attained and certain changes may be made in carrying -
out the above method and in the construction set forth. Accord-
ingly, it is intended that all matter contained in the above
description or shown in the accompanying drawings shall be
interpreted as illustrative and not in a limiting sense.
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Now that the invention has been described, what is
claimed as ~ew and desired to be secured by Letters Patent is:
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