Note: Descriptions are shown in the official language in which they were submitted.
9653
Cross Reference to Related ~pplications
This application was filed concurrently with
both Canadian application Serial No. 21~,081 entitled
"Charge Transfer Logic Gate" and application Serial No.
218,082 entitled "Charge Transfer Delay Line Filters"
on January 17, 1975.
Background of t_e Invention
This invention relates to charge transfer devices
and, more particularly, to charge coupled devices (CCDs)for
perorming a binary counting function.
The recent emergence of charge coupled
technology has brought with it the advent of shift register
and memory devices now well known in the art. In order to
fabricate complete systems, other circuit functions are
frequently utilized. By way of lllustration, such
supplementary functions often include loglcal AND and OR,
binary counting, and slgnal filtering. Advantageously,
if all of -the circuits performing the various functions o~
the system are charge coupled devices, the manufacture of ~-
the system is simplified. A shift register and an AND gate,
for example, could be fabricated on a single chip by well-
known integrated circuit technology. Moreover, interface
problems, such as impedance matching and loading due to
stray capacitance, would be alleviated.
Summary of the Invention
The invention is a charge transfer binary
counter capable of counting the number (from 0 to 2n _ 1) ;
of charge packets in a particular time interval. The -
charge packets might, for example, be generated from
signal pulses in a PCM system and the time interval might
-- 1 --
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constitute a "word" or frame in PCM terminoloyy. In an
illustrative embodiment the binary counter comprises a charge
storage medium in which is formed at least one charge storage
"Q-cell" adapted to quantize each signal pulse into a packet
of charge Q. In tandem with the Q-cells are _ one-bit shift
registers each of which, except perhaps the last, comprises
first and second charge storage cells connected in series.
Adjacent cells of the same shift register are separated
from one another by a threshold potential barrier of
magnitude VT which permits only partial transfer of
charge thereacross. On the other hand, adjacent cells
of consecutive shift registers are separated from one
another by a smaller potential barrier of magnitude VB
which permits virtually complete charge transfer there-
across. In a preferred embodiment, VT is approximately
equal to 1.5 VB if the Q-cells are of area A and at least
the first cells of each shift register each have an area
equal to 2A. Adjacent cells of the device are connected
to opposite phases of a two-phase clock. A feedback
path is established between adjacent cells of the same
shift register in order to clear residual charge from
the first cell whenever charge is transferred across its
threshold barrier. At the end of the particular time
interval (e.g., word or frame), however, a quasi-steady
state is reached; that is, charge transfer ceases until
a read operation is performed or the next word arrives.
In the quasi-steady state, charge packets residing in
-- 2 --
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the first cells of -the shift registers correspond to the
binary equivalent of the number of signal pulses in the
word.
In accordance with one aspect of the present
invention, there is provided in a charge transfer binary
counter for counting the number of signal pulses in a
particular time interval up to a maximum of 2n _ 1 pulses
in the interval, a device comprising: a charge storage
medium, a quantizer comprising first electrode means for
forming in said medium at least one charge storage cell
adapted to generate a predetermined packet of charge in
response to each of said signal pulses, second electrode
means for forming in said tandem medium a plurality _ of
charge storage threshold cells coupled in tandem with one
another and at least one of which is disposed to receive
charge transferred out of said quantizer, means for
applying clock voltages to said first and second electrode
means, each of said threshold cells having at its input
a first potential barrier across which virtually all charge .
transferred out of a precediny cell will transfer into said
threshold cell upon the application of clock voltage from
said applying means to said second electrode means and
having at its output a second potential barrier, the area
of each threshold cell and the height of its second barrier
being mutually adapted in relation to the clock voltage so
that charge transfer across the second barrier occurs only
when two of said charge packets are transferred into said
threshold cell, and feedback means responsive to charge
transferred across any of the first (n-l) of said second ~ .
barriers for removing residual charge remaining in the cor-
responding threshold cells.
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srief ~ n of the rawing
The invention, together with its various ~eatures
and advantages, can be easily understood from the following
more detailed description taken in conjunction with the
accompanying drawing, in which:
Fig. 1 is a plan view of a binary counter in -
accordance with an illustrative embodiment of my invention;
Fig. 2 is a schematic plan view of the binary
counter of Fig. 1 in which the electrodes have been omitted
for convenience and the barrier lattice configuration
is shown by solid lines; and
Fig. 3A shows schematically the quantizer and
the first shift register of Fig. 2, whereas Figs. 3B-F
show the surface potential of the various cells of Fig. 3A
at different times during the clock cycle. It has been
assumed for convenience that the voltage drop across the
insulating layer (oxide) of the storage medium is negligible
so that the surface potential(s) is nearly equal to applied ~-
voltage.
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Deta _ed Description
Turning now to FIG. 1, there is shown a plan
view of a binary counter in accordance with an illustrative
embodiment of the invention. The counter 10 comprises a
storage medium lO.I illustratively a p -type semiconductor
substrate such as silicon on which is formed an insulative
layer (not shown) typically thermally grown silicon dioxide.
In the substrate are a plurality of rectangular charge
storage cells, the boundaries of which are designated by
1~ dashed and dot-dashed lines. These boundaries, termed a
barrier lattice, are illustratively established in the
substrate by ion implantation or diffusion of stripes of
immobile charge carriers (i.e., impurity centers) in the
fashion taught in U.S. Patent No. 3,789,267 (Case 7-3)
issued on January 29, 1974, to R.H. Krambeck and myself.
The barrier lattice is composed of stripes of
charge with three different potential heights:
(1) chanstop barriers (dashed lines) which are designed
to prevent charge transport across them. The object of
chanstop barriers, as described in U.S. Patent No. 3,728,161
(R.A. Moline Case 8), issued on April 17, 1973, is to
eliminate spurious inversion of the surface of a semi- ;~
conductor integrated circuit chip due to capacitive coupling
between metallization and/or field o~ide in the semiconductor
substrate. If such coupling were strong enough to invert
the surface of the semiconductor, current might leak between
adjacent devices or might even short elements of a single
device; (2) transfer barriers (dot-dashed lines) which have
a height typical of an n-channel device; i.e., the applica-
3a tion of most positive clock voltage to the barrier region
,~ _ ~
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should permit complete transfer of charge. Each transfer
barrier is asymmetrically positioned with respec-t to the
center of the overlaying electrode in order to cause charge
to flow in a predictable direction; and (3) threshold
barriers tdot-dashed double lines) which have a height such
that charge is transferred thereacross only if two packets
of charge have been transferred into the preceding cell.
In addition, ~he boundaries of diffusion zones for diodes,
IGFETs, and the like are shown by dotted lines.
The three types of potential barriers in the
lattice define a quantizer 12 and three (n - 3) one-bit
shift registers 14, 16 and 18 capable of counting the number
of charge packets in a particular time interval up to a
maximum of 2n _ 1 = 7. In binary notation the outputs of
the shift reaisters 14, 16 and 18 correspond to the powers
of two as follows: 2, 21 and 22, respectively.
The quantizer 12 comprises at least one charge
storage cell (hereinafter a "Q-cell") of area A having
a charge carrying capacity Q. Thus, each signal pulse
to be counted produces a quantum of charge Q in the Q~cell.
For reasons discussed later, the quantizer of FIG. 1
comprises first and second Q-cells 12.1 and 12.2 each
having an area A and arranged in series relationship. -
Transfer barriers are located at 12.4 between the
first and second Q-cells 12.1 and 12.2, respectively,
and at 12.5 between the second Q-cell 12.2 and the
first shift register 14. A transfer barrier may also ;
be located at 12.3 if the input de~ice 11 is a charge ~ .
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storage cell of a preceding CCD device. However, if
3a the input device 11 is a diode, as shown, then the interface
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at 12.3 would designate one edge of an n~-diffusion ~one.
On th~ other hand, chanstop barriers are located at 12.7
and 12.8. In addition, a pair of electrodes 12.9 and
12.10 overlay the first and second Q-cells 12.1 and
12.2, respectively, and are connected to opposite phases
of two-phase clock means 100.
In a similar fashion the first shift register 14
comprises first and second charge storage cells 14.1 and
14.2 arranged in series relationship. The transfer
barrier 12.5 mentioned previously is locat`ed between
the first cell 14.1 of shift register 14 and the second
Q-cell 12.2 of the quantizer 12. A threshold barr-ier
is located at 1~.3 between the first and second cells
14.1 and 14.2 Overlaying cells 14.1 and 14.2 are a pair
of electrodes 19.7 and 14.8, respectively, connected to
opposite phases of clock means 100.
As described more fully hereinafter, in order ~.
to clear residual charge from the first cell 14.1 in
response to charge transferred across threshold barrier
14.3 9 a feedback path is established between the first
and second cells 14.1 and 14.2. Illustratively, this
.- path includes a conventional grounded source IGFET 17
having its gate electrode 17.1 in contact with an
n -diffusion gate zone 14.6 which is partly overlapped
by electrode 14.8. The drain electrode 17.2 actuates
a dump gate 15 coupled to the first cell 14.1.
The dump gate 15 comprises a charge storage
cell 15.1 adjacent the first cell 14.1 and includes
a transfer barrier 14.5 at the interface therebetween.
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An electrode 15.3 overlays cell 15.1 and is connected to
the drain 17.2 of IGFET 17. Charge transferred into
the second cell 14.2 of first shift register 14 causes
a voltage to be applied to dump gate electrode 15.3
via IGFET 17 and, in turn, causes residual charge to
be drained from the first cell 14.1 into dump gate
cell 15.1. In order to remove the residual charge from
the dump gate, an IGFET diode 25 is utilized as described
hereinafter.
In addition, a charge-sensing IGFET has its
gate electrode 19.1 connected to the n+-diffusion zone
15.2 which extends under electrode 15.3. The drain of
IGFET 19 is connected to a load schematically designated
by resistor 20. The voltage at output terminal 20.1,
when read at a prescribed time such as the end of a word,
corresponds to the first digit of a three-digit binary
number. That is, the presence of a voltage at terminal
20.1 corresponds to binary digit 2. -
In the interest of brevity a detailed description
of the second and third shift registers 16 and 18, and
their respective feedback paths, will not be given. It is
to be understood that the structure of these components, as
well as the circuit connections, are with one exception ;~
substantially identical to those previously described with
. -: .
respect to the first shift register 14. The exception is
that the third shift register, and in general the nth shift
register, need not include a second cell inasmuch as no
; charge can be transferred across the last threshold barrier
if the maximum number of signal pulses in any given word is
2n _ 1. Accordingly, the nth shift xegister also need not
include a feedback path of the type described.
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~s mentioned previously, in the quasi-steady state,
such as the end of a word, charge reslding in the first cell
Of each shift register is the binary equivalent of the number
of pulses in the word. In order to obtain the desired count,
a read control 110 ls connected to each dump gate. Read control
110 is shown, for simpllcity, as a single IGFET device 111
connected by means of a trunk to each of the dump gates. The
trunk represents separate leads from read control 110 to each
of the dump gates, and 9 in practice, more than one IGFET 111
may be used, for example, one for each dump gate, connected
individually thereto. ~ clock cycle counter 120 is connected ;
to clock means 100, and, after a predetermined number of clock
cycles, activates the read control 110. The latter applies a
suitable voltage to the dump gate electrodes effective to
transfer charge, if any, from the first cells of the shift
registers into the dump gate cells. Thereupon, voltages appear
at the drains of IGFETs 19, 21 and 23 (i.e., at output terminals ~ ~
20.1, 30.1 and 40.1) depending on which of the first cells
contained charge. IGFET diodes 25, 27 and 29 have their sources
connected to the diffusion zones adjacent the dump gate cells -
of the first, second and third shift registers, respectively,
in order to provide a path for the charge in the dump gate cells
to flow to the substrate (ground). In conventional fashion,
- each IGFET diode has its gate and drain shorted to one another
and connected to a bias source 130. Thus, reading the presence
of charge in the first cell of each shift register also clears
these cells in preparation for the next counting operation
(e.g., the arrival of the ne~t word). The read and clear
operations are described more fully hereinafter. ;
Assuming that the duration of a clock cycle is equal
to the time spacing of adJacent pulse positions, the read
operation, performed under the control of counter 120 and
read control 110, occurs
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after an integral nu~ber of clock cycles if an even
number of Q-cells are used in quantizer 12, but occurs
after an integral number of half-cycles if an odd
number of Q-cells are used. The precise number of
clock cycles after which each read operation is performed
depends on design considerations such as the maximum
number of pulses in a ~ord, which in turn determines the
number _ of shift registers required in the counter. In
any event, however, the outputs 20.1, 30.1 and 40.1 correspond
in binary notation to powers of two as follows: 2, 21 and
2 , respectively. Thus, output voltages read on terminals
20.1 and 30.1 ~ut none on terminal 40.1 corresponds to the
binary number 110 which equals decimal 3; i.e., the word
detected has three pulses.
Operation of the invention will now be described
with refe~ence to the schematic drawing of FIGS. 2 and 3.
.: :
In the interests of clarity of illustration the electrodes ~ ~
.
have been omitted and the barrier lattice has been shown
by solid lines. Corresponding components have been given
identical numerical designations in FIGS. 1 and 2. Although
the clock means is not shown, it is to be understood that
adjacent cells of each shift register are connected to
opposite clock phases as in FIG. 1. Note the last shift
register 18' has only a first celi 18.1; no second cell or
feedback path is required as discussed above. In addition,
~ understanding of the operation of my invention will be
- facilitated by assumlng a preferred embodiment in which
the Q-cells of the quantizer each have an area equal to A,
~ the cells of the shift registers have an area equal to 2A,
; 30 the threshold barriers VT are equal to 1.5 VB approximately,
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and the voltage swing oE the clock voltage is equal to VB,
approximately (FIG. 3A).
Assume that the input signal is a PC~ word
having a maximum of seven pulse slots, three of which
contain signal pulses. During phase one of the clock
cycle, the first signal pulse is applied to quantizer 12
which generates a packet of charge Q in the first Q-cell.
By two-phase clocking the packet Q is transferred across
transfer barrier 12.4 into the second Q-cell and then
across transfer barrier 12.5 into the first cell 14.1 of
the first shift register 14. This first packet is
temporarily inhibited from ~urther transfer by the
threshold barrier 14.3; ie.., due to the larger area (2A?
of cell 14.1, the charge Q only half fills the cell~ `
More specifically, an amount of charge Q in a cell of
area A decreases the sur~ace potential thereof by an
amount equal to VB, whereas the same amount of charge Q
in a cell of area 2A will decrease the surface potential
by only 0.5 VB. Consequently, during phase two when
the threshold barrier is reduced from 1.5 VB to 0.5 V
which is equal to the surface potential of cell 14.1,
no charge is transferred into cell 14.2 (FIG. 3C). -~
Subsequently, the second signal pulse is
applied to quantizer 12 which generates another packet
- of charge Q in the first Q-cell. By two-phase clocking
; this s4cond packet of charge Q is similarly transferred
through the second Q-cell into the first cell 14.1 where,
it will be remembered, the first packet of charge Q is
. . .
waiting. Charge in the amount of 2Q is now present in the
3Q first cell 14.1. This charge decreases the surface potential
-- 10 -- .
~9~;53
of the first cell 14.1 by approximately VB ~FI~. 3D).
Consequently, during phase two of the clock cycle, when
the surface potential under the second cell 14.2 of the
first shift register increases by an amount equal to VB
(the clock voltage swing), the effective threshold barrier
is reduced from 1.5 VB to 0.5 VB. Bec~use the surface
potential in the irst cell 14.1 is smaller by 0.5 VB than
the reduced threshold barrier, half of -the 2Q charge
(i.e., Q) will transfer into the second cell 14.2 (FIG. 3E)
and subsequently in~o cell 16.1 ~FIG. 3F). Therefore, the
second cell 14.2 receives charge only after two packets of
charge are transferred into the first cell 14.1.
When this process is completed, the first
cell 14.1 of the first shift register 14 is still half
fulli i.e., it contains an amount of charge Q (FIG. 3F).
This excess charge is drained of before the next pulse
arrives at the first cell 14.1 by means of a feedback path
which includes the dump gate 15 and the IGFET inverter 17
(FIG. 2). Briefly, the IFGET inverter 17 is open-circuited
by the presence of charge in the second cell 14.2. The
resulting increase in its drain voltage opens the dump
~` gate 15. Excess charge in the first cells of the other
shift registers, except the last one 18', is cleared in a
similar fashion.
; During the next half clock cycle, the packet
of charge Q in the second cell 14.2 is transferred into
the first cell 16.1 of the second shift register where it
awaits the arrival of another charge packet. This counting
process continues as subsequent charge packets are generated
by the quantizer in response to applied signal pulses in the
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PCM word. Thus, a third charge packet is propagated along
the device in the same ~anner as the first and second charge
packets until it reaches the first cell 14.1 where the
threshold barrier 14.3 causes it to await the arrival
of the next charge packet, if any. Inasmuch as it has
been assumed that the word contained only three signal
pulses, a quasi-steady state is reached (i.e., no further
charge propagation occurs). At the end of the word, which
may be sensed by counting clock cycles (viz., counter 120,
FIG. 1), the read control activates all of the dump gates so
that voltages appear on output terminals 20.1 and 30.1 but no
voltage appears on terminal 40.1. Thus, the binary output
is 110 which equals decimal 3, the number of pulses in the
PCM word. After the reading operation is completed, the
first cell of each shift register is cleared so that the -
counter is in condition to count the number of pulses in
the next word to arrive.
In a similar fashion, any number of charge
packets from 0 to 7 in a given word can be counted by the
structure of FIG. 2. In general, a large number of
charge packets, up to a maximum of 2n _ l, can be counted
by utili~ing a plurality _ of shift registers of the type
described.
The reading and clearing operations are described
more particularly as follows. The read control llO includes
an IGFET lll which has its drain connected to source 130
of bias voltage VB, its source ~
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separately connected to each dump ~ate electrode and its gate
connected to the clock cycle counter 120. In practice the
IGFET 111 may b~ fabricated on the same chip as the binary
counter and, as pointed out before, may include several IGFETs.
Depending on whether a clearing or readlng function is to be
performed, the clock cycle counter 120 applies one of two
voltages VR = Va or VR - Vb > Va to the gate of IGFET lll.
For clearing VR = Va so that the conductance of IGFET 111 -
has a value gR = g < < gI where gI is the conductance of the
IGFET 17, for example, when no charge is present in cell 14.2.
Consequently, the potential on the dump gate 15 is nearly
zero and no clearing occurs. When, however, a quantum of
charge Q is transferred across threshold barrier 14.3 into
cell 14.2, the IGFET 17 is cut-off and the potential on
the dump gate 15 is approximately VB so that clearing of cell
14.1 is accomplished. For reading, on the other hand, in ~;
the quasi-steady state no charge is present in cell 14.1 so
that IGFET 17 is conducting and has a conductance equal to
gI. To read the clock cycle counter 120 sets VR = Vb > V
so that the conductance of IGFET 111 now has a value ;
gR = gb > > gI. Hence, the potential on the dump gate 15
- is approximately VB and charge in cell 14.1 flows through
the channel under the dump gate onto the gate of IGFET 19
producing a signal at output terminal 20.1. In a similar
fashion the first cells of the other shift registers are
cleared and read.
It is to be understood that the above-described
arrangements are merely illustrative of the many possible
specific embodiments which can be devised to represent
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~4~3~53
application of the principles of the invention. Numerous
and varied other arrangements can be devised in accordance
with these principles by those skilled in the art without
departing from the spirit and scope of the invention. In
particular, although it has been pointed out that the last
shift register need not include a "second cell" or a feedback
path, it should be noted that in some cases, where the pulse
count is high enough, 2Q ~harge will reach the last cell and
Q will be transferred over the last threshold barrier.
Thus, it may be desirable to dissipate this transferred
charge by coupling a diode, for example, to the last cell
of the last shift register.
In addition, in order to provide a path from the
read control 110 through the electrode of the last dump gate
(e.g., 45 of FIG. 2) to ground, an IGFET 112 has its drain
connected to that electrode, its source grounded and its gate
connected to the bias source (i.e., VB). Thus, IGFET 112 is
always conducting, but function substantially in the same
manner as inverters 17 and 37 in providing continuity to
2~ ground.
Moreover, it will be appreciated that the invention,
when viewed from a slightly different standpoint, can be
co~sidered as comprising a quantizer 12, a plurality _ of
threshold cells (14.1, 16.1 and 18.1) each of which has a
transfer barrier (12.5, 14 4 and 16.4) at its input and a
threshold barrler (14.3, 16.3 and 18.3) at its output. Feed-
back means (storage cells 14.2 and 16.2, IGFET inverters 17
and 37, and dump yates 15, 35 and 45) are responsive to
charge transferred across each threshold barrier for removing
residual charge in the threshold cells.
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