Note: Descriptions are shown in the official language in which they were submitted.
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Flelt of the Invention
,
This invention relates generally to postage meter-
lng, and particularly concerns secured electronlc calculating
and postage printing equipment for achieving postage meter-
ing security in a computer-controlled high volume mailing
operation.
Background and Summary of the Invention
,
It is conventional for high volume mailers to
avall themselves of the high speeds offered by modern electronic
digital computers and chain printers, in orter to reduce
costs ant increa~e thelr output.- A typical prior art
installation inclutes a computer which receives information
as to the weight and destination of a package, and i8
programmet to calculate the required postage. A high speet
computer output printer is slaved to the computer to print
out the destination information on an address l-bel which
18 subsequently affixed to the package.
The computer also provites the calculatet postage
amount information to shipping department employees in
~ome form which enables them to afflx the proper amoont of
postage to the package. The most common way of accomplish-
lng thls ls for the hlgh speed printer to recei~e the postage
mount lnformatlon from the computer, ant print lt dlrectly
on the address label for the lnformatlon of the employees
who subsequently afflx postage. Thls prlnting i9 not an
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actual government-authorlzet postage lmpres~lon of the ~ -
klnd provlded by a postage meter. The print impression mate
ln a prlor art lnstallation as described above inclutes
only the postage amount without any authorized postage
validation 8ymbols, and iæ provided for information only.
Thereafter authorized postage of like amount must be affixed
by an employee by affixing postage stamps or using a con-
ventional manually controlled mechanical postage meter.
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The intervention of a human being, or of a
mechsnical postage metering device, slowg town a high volume
mailing operation of the kind tescribèd. Therefore it is
.
.desirable to have the authorized postage impression printed
~; automatically in response to the computer-generated postage
calculation. It is not enough, however, simply to connect :
.~ the data output lines of the computer to the input of
some insecurely housed apparatus capable of printing authoriz-
ed postage impresslons, as suggested by U. S. Patent No.
3,255, 439 of L. G. Sim~ian. In accordance with applicable
po8tal security regulations, there must be some secure
means of accounting which assures.postal officials that
ll the postage used is paid for. Normally a descending
~egister is filled wlth a pre-paid postage credit
balance, the register 18 decremented by
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the amount of postage dlspensed, and the postage dispenser is
locked when the postage balance falls too low. Subsequently
the register can be recharged under secured conditions. It
is also possible to extend postage credit to the user, keeping
track of a debit balance which increases by the amount of the
postage used, and billing the user subsequently. Those skilled
in the computer arts will readily appreciate that it i~ possible
to program the computer itself to take care of either type
of bookkeeping described above. Such a solution is unsatis-
factory, however, because digital computers are so easily re-
programmed that an unscrupulous individual could thereby
accomplish postal fraud.
This invention contemplates, therefore, that the desired
computer control of postage printing be achieved in conjunction
with some form of secure, fixed-program postal accounting
equipment. One approach which is within the contemplation of
t- :.
this invention is to use a mechanical postage meter which com-
prises a secure housing containing authorized postage printing
means, a mechanical descending register for storing the postal
credit balance, and mechanical guaranteeing for guaranteeing
that all printed postage amounts are decremented from the
register, all of which is conventional. The mechanical meter
is mcdified in accordance with this invention, however, to
provide it with an electrically actuated meter controller device
connected to respond to electrical signals from the computer, and
to translate those signals into a mechanical input for controlling
all meter functions. (A system using a lever and clutch
mechanism in an electrically actuated meter is shown in U.S.
Pat. ~o. 3,692,988.)
The latter approach meets all security requirements, but
is considered too slow to meet the speed requirements of some
high volume mailing operations. When used in conjunction with an
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electronlc digital computer and hlgh ~peet prlnter, lt may
be necessary for the postage printer to produce approxlmately
two or three po~tage impressions per second, and mechanlcal
postage meters do not appear capable of withstanding such
operatlng rates over a reasonable llfetime.
In order to achieve longer operating llfetimes
and/or higher operating speeds, a preferred form of the
invention employs fast-acting electrically driven printing
means, electrical means for storing the postage balance,
and electrical calculating means for changing the postage
balance in accordance with the amount of postage printed.
The postage printing means is enclosed within a secure
housing, and the electronic control circuitry, or at least
that portion of it which bears the responsibility for postal
security, is enclosed within the same housing or alternatively
isin a separate secure housing and connected to the postage
printer by means of secure electrical cable-and connector
devices.
Equipment in accordance with this aspect of the
lnvention can be used for printing various different kinds
of numerlcal indicia under computer control. For example
it 18 adapted for various non-postage applications having
8imilar securlty problems, e.g. printing paychecks.
It is also within the contemplation of this invention
to provide appropriate security measures which make it practical
to u~e a high speed printer directly for postage printing,
after appropriate modlflcations such as replacing standard -~
~print characters by special authorized postage symbols.
That spproach, however, has a number of disadvantages,
one of which relates to the character ~ize limitation of
~tantart hi8h speet printlng equlpment. It also lnvolves
unteslrab1e lnterference with the electrical lnterface between
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the computer and the high speed printer, l.e. breakin8 into
the electrical cable which connects the co~puter and the high
speed prlnter ln order to lnsert speclal clrcultry for per-
formlng postal securlty functlons.
Therefore a preferred form of this lnvention pro-
Vides a separate auxiliary prlnting mechanlsm which 18 arranged
in one of several ways to prlnt authorlzed postage impreYsions
upon the address labels that are fed through the high speed
printer. The high speed printer and the postage printer are
both controlled ultimately by the computer, but they have
individual electrical connections thereto, and therefore,
only the connection to the postage printer need be designed
with postal security problems in mind.
Brief Description of the Drawings
Figure 1 is a block diagram of a computer-responsive
authorized postage printing syst$m in accordance with one
embodiment of this invention, wherein an otherwise conventlonal J
high speed computer output printer is modified to print an
authorized postage symbol,-and is connected to so under control
of an electronic postage metering circuit co~nected between
the computer and the printer.
Figure lA is an illustration of an authorized
postage inpression mate by the apparatus of Figure 1.
Figure 2 is a block tlagram of an alternative embodi-
ment of a computer-responsive authorlzet postage printin~
~tem in accordance with this invention, in which a self-
containet mechanical postage meter is arranged to prlnt upon
the same paper web a& a computer-triven high speet prlnter,
and an automatlc meter controller accepts computer lnstructlons
~n elcctrIcal form and translates them into a mechanlcal
~nput to the po~tage meter.
Flguro 3 18 a block diagram of another alternative
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embotiment of a computer-responsive authorlzet po~tage prlnt-
lng system ln accordance wlth thls lnventlon, whlch uses a
separate electrlcally actuated postage prlnter and electrlcal
postal accounting equip~ent. Both the pogtage prlnter ant
at least that portion of the electronic circuitry whlch has
responsiblllty for postal accounting are contained within
a common secure housing.
Flgure 4 i9 a block diagram of still another alter-
natlve embotiment of a postage printing system in accortance
with this invention, in which electronic metering circuitry
ant an electrically actuatet authorizet postage prlnter
are-encloset in separate securet housings and connectet by
a securet cable ant securet electrical connector means.
The postage printer is mountet piggy-back fashion upon a
high speet computer output-printe-r.
Figurè S is a perspective view of an exemplary
physical realizatlon of a high speet printer ant piggy-back
postage prlnter mountet thereon, as illustrated in Figure 4.
Flgure 6 is an enlarget perspective viéw of the
plggy-backpostage printer and the supporting structure for -
mountlng it on the high speed printer.
Figure 7 is another perspective view of the piggy-
back postage printer.
Figure 8 is a perspective view of the printing
mechanlsm of the piggy-back postage printer.
Flgure 9 is a top plan view, with parts broken
awa~ and sectionet for clarity of lllu~tration, of the
piggy-back prlnter.
Flgure lO 18 an elevatlonal view of the rlbbon
atvance mechanlsm of the plggy-back prlnter.
Figure 11 18 a front elevatlonal vlew of the
control panel of the electronic meter of Flgures 3 or 4.
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Plgure 12 lo a slmplified block diagr~m of the clr-
cultry of the electronic ~eter,
Flgures 13A through 13D comprise a more detalled
block diagram of the same circultry, when fitted together a~
shown in Figure 13E.
Figures 14 through 34 depict a more detailed Yiew
of the clrcultry of Figure 13, and associated timing and
addressing diagr~ms for this circuitry.
Flgure 14 shows a diagram including a plot of the
10- clock, gray code counter and the polling signals with respect
to time.
Flgure 15 depicts a diagram of the addressing signals
plotted with respect to time.
Figure 16 illustrates a table of address allocation
ant arithmetic unit functions. ~-
Figure 1~ shows a circuit diagram for the gray ~ode
counter and the memory addressing counter.
Figure 18 depicts a circuit diagram for the polling
circult, the la~t address decoder and the combination lock
swltch.
Figure 19 illustrates a diagram of part of the con-
trol logic circuitry.
Flgure 20 shows a diagram of the memory circuit.
Figure 21 depicts a diagram of the memory address
decoder and memory ~nput buffer circultry.
Figure 22 illustrates 8 dlagram for the arithmetic
'- unit circult and memory output buffer circuitry.
- Figure 23 ~how~ a ttagram for the lnsufficient post-
age decoder circuit, part of the interrupts ant status indicator
circuit and the arlthmetic contrdl circuit.
Pigure 24 depicts a diagram for postage ~uffer
clrcuitry.
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Flgure 25 illustrate~ a tiagr~m of the print buffer
clrcuitry.
Figure 26 shows a diagram for varlable prlnt module
control circultry and Binary Coded Decimal error detection
clrcultry.
Figure 27 tepicts a dia8ram of the print wheel logic
circuitry.
Figure 28 illustrates a diagram of the interfaclng
clrcuitry of the computer for this system.
Figure 29 shows a diagram of the meter status cir-
cuitry.
Figure 30 depicts a diagram for the memory power
supply and voltage sensing circuits.
Figure 31 illustrates a tiagram of the control power
supply and initiallzation circuitry.
Pigure 32 shows a diagram of the display switching
control circuit.
Plgure 33 deplcts a diagram of the dlsplay logic-
control circuitry; and
Plgure 34 illustrates a diagram of the direct
memory read control logic circuitry.
Detailed Description of the Preferred Embodiment
In Pigure 1 reference numeral-10 generally designates
a high speed computer outpué- printer, for example a chain
pr~nter such as the IB~ Model 1403. The printer 10 i9 conven-
t~onal in ever~ respect, except that it is modified to include
type element for printing an authorized postage valitation
symboi, A ~eb of mailing label paper 14 is pullet through the
h,igh ~peet printer turlng printlng by means of the conventlonal
paper tractor mechanlsm ~not lntlcatet), ant the prlnter 18
capable of printlng thereon both conventlonal alphanumerlc
~ymbols and the authorizet postage symbol on command of a
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conventlonal programmable electronic tigltal computer 16.
In modlfylng the hlgh speet prlnter 10 to lnclude
the authorized pogtage v~lidation symbol, one of the less
frequently used conventional symbol print elements may be
easlly removed from the printing chain and replaced by a vali-
dation symbol print element. Ag printet by the modified chain
printer 10, an authorized postage impression would appear as
illustrated in Figure lA. This postage lmpression includes a
dollar postage amount 11 and a pair of authorized postage
symbols 12 before and after it. The postage amount 11 is printed
by the conventional type elements used for general electronic
data processing print-out purposes, and the validation symbols
12 are printed by the special substitute type element. ~-
The computer 16 is programmed to receive destination
and package weight information, and from that information to cal-
culate the amount of postage ll. Then the computer 16 transmits
slgnals to the high speet printer lO whi-ch cause it to print
the address (not shown) ant the calculated amount of postage
11 on the paper web 14, using conventional alphanumeric type
elements. In addition, the printer 10, upon receiving an
appropriate signal from the computer 16, prints the postage
symbols 12 ad~acent the postage amount 11 to validate the
latter as an authorized postage impression.
The paper web 14 is designed to be separated into
intividual mailing labels and then attached to individual pack-
ages for mailing purposes, as is presently conventional in
high volume mailing operations.
The high speed printer 10 is enclosed within a secured
housing 18, along with an electronic postage meterlng circult
20 which stores postal accounting information, recognizes the
mount of postage calculated by the computer, and-makes sure that
the po8tage balance iB alteret by the amount of po8tage ll
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every time that ~ computer ln~truction 19 ~ent to printer 10 for
prl~ting of the authorized postage val~tating ~ymbol 12. The
purpose of secured houslng 18 is to make ~ure that no such
command can reach the high speed printer 10 to cause lt to
; prlnt the authorlzed postage valldating symbol 12 wlthout
an appropriate change in the postal accounting balance of
clrcult 20. To accompllsh thls, the secured houslng 18 pre-
vents access to the metering circuit 20 and the hlgh speed
printer lO.
The term "secured housing" as used herein means a
housing which either cannot be opened by unauthorized persons
or cannot be opened by such persons without detection, or with-
out engaging in counterfeiting. An example of a secured housing
whlch is preferred ~or use wlth the present invention is the
type which is currently employed in conventional mechanical
postage meters. Such a housing cannot be opened without
cutting a security closure which i8 protected by a lead seal
having an authorized government impression thereon. Therefore
ln order to hsve access to the postage balance reglster of such
a postage meter, a postage thief would either have to counter-
felt the seal or leave behlnd telltale alterations of the
security closures.
The electronic meter 20 must be inserted lnto the
electrical path between the computer 16 and high speed printer
10, because the computer must not be permitted to send any
control signals to the high speed printer which are not monitor-
ed by the postage metering circuit 20. Otherwise, a dishonest
computer programmer could easily redesign ~oftware 80 that
computer 16 could access the authorized postage valldatlng
symbol 12 on the high speed printer 10 without causing the
meter 20 to slter the postage balance by the proper amount.
If every computer instruction reaching the high speed printer
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10 passes through the meter 20, however, there wlll be sn
appropriate change in the postage balance for every postsl
amount printed.
The need for splicing the electronic meter 20 into
; the cable 28 leading to the high speed printer 10 i8, however,
a di~advantage of the embodiment of Figure 1. Both the manu-
facturersand renters of computer installations frown upon
the splicing of foreign circuitg into the data cables between
computers and peripheral equipment. Such splicing might also
void various performance guarantees, since the manufacturers do
not wish to be responsible for malfunctions that could conceiv-
ably have been caused by the foreign circuits.
Another disadvantage of the approach illustrated in
Flgure 1 Is the fact that it causes difficulties for service ;-
-personnel who maintain the printer 10 and meter 20. When
repairs are required which necessitate opening the secured
housing 18, special arrangements must be made with the postal
authorities. The housing 18 ma~y be designed to permit loading
of paper 14, however, and other normal operating procedures,
without the need for opening the housing or special supervision
by postal authorities. For example, the paper 14 may be fed
in through an opening in the housing 18 which is too small to
permit tampering with the metering circuit 20 and electrical
connectlon 22.
Another disadvantage of the Figure 1 embodiment
relate~ to the fact that conventional high speed printer
tesign places an upper limit on the size of type elements
whlch can be used therein. Consequently the special postage
valldatlng symbol 12 may be too small for maximum vlsibllity
to pogtal employees handling the mail.
An alternative embotlment of the invention whlch
avoits these problems i9 seen in Figure 2. There a computer
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116 18 connectcd by an uninterrupted cable 128 dlrectly to a
totally conventional, unmodifled hi8h speed prlnter 110.' No
foreign equlpment i5 connected electrlcally to the printer, and
there are no change~ in it~ type elementg, A conventional
mechanical authorlzed postage meterlng and prlnting device 111`
slmilar in internal design to mechanical postage meter devices
that are in common use today, is installed near the high ~peed
printer 110, and is arranged to p,rint on the same continuous
web of paper 114 as the high speed printer. The device 111
includes a mechanical postage printer 112 and mechanical postage
registers 120 enclosed in a conventional secured housing 118.
Thé mechanical postage meter ant printing device 111
may be located either upstream or downstream from the high
speed printer 110, relative to the direction of paper motion.
The placement of the mechanical postage meter 111 in relation
to the dlrection of paper motion determines whether the'postage
lmpression is printed before or after the address information
printed by the hlgh speed printer 110. In either case, the
computer 116 is programmed to take account of the difference in
locatlon between the high speed printer and the postage printer,
ant actuates them in the appropriate time relatlonshlp, so
that the matching address and postage amount are prlnted on the
same mailing label, i.e. the same region of paper web 114.
The meter and prlnter device 111 of this embodiment differs
from conventional mechanlcal postage meters in that select,ing
the amount of postage and trlpplng the prlnt mechanism is accom-
pllshet by a solenold-actuated mechanism 130, instead of manually.
(See Patent No. 2,692,988) The solenoid-actuated mechanism in
t-urn is driven by electrical signals coming over leads 132 and
134 from the computer 116 and additlonal electronlc hardware 136
whlch may be required to lnterfac'e the computer wlth the postage
meter 8ctuating solenoids.
A tlsadvantage of the embodlment illustrated in
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Flgure 2 is that it 18 tlfflcult to de~lgn a mechanlcal po~tage
meter ant printer devlce ~hlch can operate at speeds compatlble
wlth a hlgh Ypeed prlnter and electronlc dlgltal computer,
unle6g the pogtage amount remslns fixed between printing lm-
presslons. Two types of mechanical postage printers, both
motor-driven, are commonly employed ln this type of meter.
One of these, the rotary type, cannot develop a great enough
angular velocity wlthout lntroducing dynamic problems; and
. the other type, the flat bed printer, has so much mas~ for
the motor to accelerate all at once that lt ls unsultable for
high speed operation. In addition, the rotating mechanical
type of register mechanisms which are used for postage account-
lng ln mechanical meters are not capable of high operating
speeds These factors slow down the print cycle of conventional
-postage meters to such an extent that insufficient time i8
left for changing the postage number wheels, if the mailing
labels are to be printed at a rate compatible with electronic
tata processing equipment.
In order to achleve such compatlbility, preferred
embodiments of the invention, illustrated in Figures 3 and 4
respectively, are designed to employ low inertia~ segmented
flat bed postage printing mechanism driven directly by sole-
noid~ for-high speed electrical actuation, and electronic
dlgital techniques for high speed postage accounting.
In the embodiment of Pigure 3 a solenoid-actuated
authorized postage printer 212 and an electronic postage
metering circuit 22Q are both contained within a secured
housing 218. The electronic meter 220 operates ln response
to the po8tage calculations performed by a computer 216, a~
~epre8ented by the arrow 232, and, a~ indicated by t~e arrow
234, drives solenoids 238 which cause the mechanism 212 to
prlnt a postage lmpression. The solenold-actuatet printer 212
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sct~ on the sflme paper web 214 as a computer-reHponslve hlgh
speed prlnter 210l whlch i8 tlrectly re~ponsive to the computer
216 a8 lndlcated by the arrow 228.
An advantage of the embodiment o f Flgure 3 iY that
no secured electrlcalconnectors or ca~1es are required, since
the security-sen~itive electronic circuitry is enclosed within
the same secured housing 218 as the postage prlnter 212. But
a disadvantage of the embodiment of Figure 3 is that putting
the digital circuitry 220 within the same housing as the sole-
noids 238 exposes the digital circuitry to electrical noise.
The approach illustrated in Figure 4 avoids theelectrical noise problem, and is most highly preferred. In
this embodiment a solenoid-actuated postage printer 312 and
its actuating solenoids 338 are enclosed ln a first secured
housing 318, whlle electronic metering circuitry 320 is enclosed
ln a separate secured housing 418 and connected to the sole-
noids 338 by a ~ecured electrical cable 322 and secured conn- -
ector 324. "Secured electrical connectors and cables" are
deflned as those which cannot be disconnected by unauthorized
persons or cannot be disconnected by such persons without leav-
lng traces or requiring counterfeiting. Connectors of this
type are commercially avallable. See for example the XAC
~erles of connectors made by Wlnchester Electronics of Oakville,
Connectlcut; these connectors have housings which are assembled
b~ pairs of threaded fasteners having diametral holes. If a
wire is passed through the diametral holes of both fasteners,
and the ends of the wire a~e secured together by a lead seal
havlng a government authorized impression, the threaded fasteners
c~nnot be turned to disassemble the connector without violating
the seal. Securet electrical cables are also commerclally
- vailable; they are simpl~ conventlonal contuctor cables
electrlcally shlelted by a braldet metal wlre sheath, and the
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lnternal electrlcal conductor~ are connected to termlnal~
lnslde the secured connector 324, which prevents anyone from
dlsconnectlng the cable 322 from the secured connector wlth-
out tlgas8embling the gecured connector. The other end of the
cable 322 i8 8imllarly connected in8ide the 8ecured housing 318.
The metering circuitry 320 is effectively isolated
by the metal hougings 318 and 418 from electrical nolse gener-
ated by the golenoids 338, yet a secured electrical relation-
ship between the meter and the printer 312 is maintained. In
this embodiment, a computer 316 provides calculated postage
amount data to the electronic meter 320 as indicated by the
arrow 332. The meter 320 has exclusive control over the
print solenoids 338 by virtue of the second connection, and
will not permit any amount of postage to be printed without
simultaneously effecting a corre~ponding change in the electro-
nically stored postage balance. Here again, the postage printer
312 and a high speed printer 310 act upon the same web of paper
314 in a known time relationship. The high speed printer 310
regponds to instructions from the computer 316, as indicated ,
by arrow 328.
An atvantageous feature shared by the embodiments
of Plgures 1, 3 and 4 is that through the use of electronic
tlgital techniques, useful feedback information is available
~rom the postage printers 10, 212 and 312 to the electronic
meter,ing circuits 20, 220 'and 320, and to the computers'l6, '~
216 ant 316, as inticatet by the output arrows 40, 42 and 240, ,-
242 and 340, 342 respectively. As a result, the computer
can be advlsed of any error contitions existing in the postage
printer aefore prtnting occurs. The computer then can take ~ ;
appropriate remetial steps as has been programmed. Such error
conditlons ~ill be tigcus~et more fully below, in- connection
qith the specific electronic meter circuitry illustrated ln
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Figure~ 12 ant 13.
Because the embodlment ln Figure 4 ~eparates the
printing components 312 and 338 from the electronics 320,
lt facilitates mounting the printer 312 and actuating sole-
noids 338 in piggy-back fashion atop the high speed printer
310, as symbolized schematically in Figure 4 by the placement
of the housing 318 directly oyer the printer 310. Such plggy-
back placement of the postage prlnter as an auxiliary mechanism
mounted on the high speed printer has the advantage of closer
correlation of the two printing mechanism in time and in space.
The closer correlation in time eases theproblem of printing
the address and postage impression at different times. Thus
in the embodiment of Figure 4 the printing stations are separ-
ated by a relatively small number of print lines. The correla-
tion in space makes for a more compact and convenient install-
ation, since a postage printer mountet directly on the high
speed printer does notoccupy any additional floor space, and
does not lntroduce the problem of a vulnerable paper web
passing across the intervening space between the two printing
devices.
Figures 5 and 6 illustrate a hlgh speed computer
output printer 310 with the auxiliary postage printing mechan-
ism 312 mounted in piggy-back fashion thereon. The computer
output printer 310 may be any standard form of high speed
printer o f the kind which i8 normally driven by an electronic
tigital computer in conventional data processing lnstallatlons.
The particular high speed printer 310 illustrated in Flgure 5
i~ basically a standard IBM Model 1403 chain printer, which
has been modified only to the extent ~ecessary to mount the
postage printer 312 thereon. The high speed printer 310 and
the postage printer 312 receive their data inputs. from the same
tlgital computer (not ohown), but they arrive over separate
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data lnput c~bles 328 and 322 respectlvelg.
The ch~ln prlnter 310 lmpresses printet data upon
paper web 314 in response to computer-generatet slgnals receivet
over tata cable 328. The paper i9 atvanced through the printer
llne-by-line by means of conventional paper tractors (not shown)
scting upon sprocket holes 426 along either edge of the paper
web. For mailing label applications, the paper web 314 com-
prises a backing sheet 428 which has the sprocket holes 426
punchet therein and is wide enough to engage the paper tractors
on either side of the postage prlnter 312, plus a centrally
located front strip 430 which i8 narrower and consists of a
series of individual mailing labels 430.1, 430.2, etc.
Printing by the chain printer 310 takes place some-
what below the level of the postage printer 312, and after
each segment of the mailing label strip 430 i8. completed the
paper web 314 is pulled upwardly by the tractors. At a some-
what higher location within the printing station of the high
speet printer 310, the postage printer 312 makçs its printing
impression upon the same mailing label strip 430, in response -
to a computer-generated data inputs which arr~ves over the
dsta cable 322 and advises the postage printer of the computer~
calculated amounts of postage required for each package.
Because of their different print locations along the path of
the paper web 314, there io a time difference between the
relatet printing operations of printers 310 and 312, of
~hich the computer must be programmet to take account. After -
both printing mechanigms 310 and 312 have finished printing
thelr respective impressions thereon, the label strip 430
1~ ~eparatet from the backing sheet 428 and dlvided lnto
indlvitual malling labels 430.1, 430.2, etc. which are then
~fflxed to respective pac~ages for mailing.
The conventlon frame structure of an IB~ motel
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1403 chaln prlnter 310 lncludes a pslr of upper and lower
frame member~ 422 and 423 re~pectlvely whlch extend horlzon-
tally across the printlng ~tatlon, and are uged as the basic
~upport for the piggy-back postage printer 312. A palr of
side bars 432 are each bolted at thelr upper ents to the upper
frame member 422 and at thelr lower ends to the lower frame
member 423 of the maln printer 310. At thelr lower ends, these
side brackets 432 are formed with rearwardly pro~ectlng bar-
supporting lugs 434 which receive the opposite ends of a
threaded bar 436, and forwardly pro~ecting hinge lugs 438 which
lnterengage with hlnge lugs 440 fiormed on a pair of end
brackets 442. Hinge plns 444 and 446 pass downwardly through
vertical holes which are drilled through all the hlnge lugs
438 and 440 to secure the end brackets 442 to,the slde brackets
432 at either slde of the prlnting station (see also Figures
7 and Y). The postage printer 312 is supported on a pair of
slide rails 448 which extend horizontally between the two
end brackets 442, and permit the postage printer 312 to slide
horizontally to a position of printing relationship wlth the
label strip 430. Set screws 450 hold the prlnter 312 in place
after initial. ad~ustment.
As seen in Figures 6 and 9, a speclal platen assembly
452 for cooperatlng wlth the postage printer 312 ls located
tlrectly behint the paper web 314, and is supported, with
provlslon for lateral position ad~ustment, by threadet engage-
ment with the bar 436 ant clamping engsgement with the lower `~
frame member 423, The threated engagement with the bar 436 is
accompllshet by a palr of upwardly ant rearwardly extentlng -~
tappet lugs 454. The clamping engagement with the lower frame
member 423 is accomplished by front ant rear plates 456 ant
458 respectively which surround the lower frame member 423.
Bolts 460 passing through the front plate 456 are threaded
cb/ - 18 -
~ , .
~osz9~o
to the resr plate 458 to ~ecure the~ in clamplng relationship
about the lower frame ~ember 423, The actual platen ~urface
is a hard rubber in~ert 462 which is receivet withln an appro-
priate rece~s on the front surface of the front clamping plate
456.
An inked rlbbon 464 passes entirely arount the out-
side of the postage printer housing 318 and townwartly between
the postage printer mechanism 312 and the paper print-out
sheet 314, in order to provide ink for postage impre~sions.
As seen in Figures 6, 9 and 10, the ribbon 464 isadvancet
continuously by a roller 466 ~ournalled between plates 468
and 469 and triven by a ribbon advance motor 470 secured to
the plate 468. Both plates 468 and 469 are mounted on the
exteriQr of thç housing 318. Idler rollers 472 are rotatably
mounted upon links 474 by a shaft-476, and the links in turn
., ,
:~ are pivotally mounted upon a shaft 478 ~ournalled between ~ --
the mounting plates 468 and 469. Torsion springs 480 are
.,, . :: .
. wrapped around shaft 478 and react against pins 481 ant shaft
476 for biasing the ldler rollers 472 against the ink ribbon -
2a 464 to maintain driving engagement with the motor-driven roller : -
466. ~ ;
With reference to Figures 7, 8 and 8, the postage
- . ~
printer 312 comprises a plurality of individual type segments 500
for printing the postage ~mpression, including several which
incorporate variable numerical information 501 to form the
~- amount of po~tage. In the particular example illustrated,
`:~ there are eight type segments 500, four of which (500.1 through
:~ 500.4~ are of the variab~e numerical kind, allowing for a max-
i~um postage a~ount of $99.99. The remainter of the type seg-
ments C500.5 through 500.8~ are teticsted exclusively to non-
~arlable information including an authorized government po-t-
age valitation symbol 502 ant an identification 506 of the city
cb/ - 19 -
, ,,, , , , .... . ' '
-
- :: ~ - ' -. . :'
.: :..: : .
105'~910
and country ln which the maller ls located. l'he type ~egments
500 prlnt through a wlndow 508 formet on the under~lde of the
~ecure houslng 318. The wlndow 508 16 ~ust large enough to
permlt the type segments 500 to protrude therethrough for
prlntlng purposes, and does not admit the lntroduction of any
tools which might be used to tamper wlth the mechanlsm lnside
the housing 318. The electrical signals for setting the
variable numerical information on type segments 500.1 through
500.4, and for firing the print ~olenoids 338, arrive over
the armored cable 322 entering one side of the secured ~ousing
318.
For a more complete understanding of the modifications
necessary to mount the postage printer 312 upon a co~ventional
high speed, computer-driven chain printer, see applicant's
Canatian patent ~o. 1,005,274 issued February 15, 1977. - -~
Pigures 8 and 9 illustrate the type of solenold-
actuated segmented printing mechanism which is preferred for
rapid, computer-controlled printing of postage impressions
ln accordance with this invention. The paper web 314 compris-
lng separablelabels 314.1, 314.2 and the inked ribbon 464 are
fed between the platen 462 and the printing ~egments 500. Each
~egment is irst driven through a printing stroke by its
respectlve solenoid 338, and subsequently is retracted by its
respective return spring 522. For a more detailed d~scription
of the solenold-actuated printing mechanism, refer to Canadian
Patent No. 1,005,274 cited above.
Thls type of printing mechanism is much faster than
those used in mechanical postage meters, ant has a much longer
life w~en operatet at speets which are compatible with a
computer-triven chsin printer. It is not as fast as the chaln
prlnter 310, but compatabil~ty~ in this appllcation does not
require equality of ~peets. Inprlnting attress lsbels for
cb/ - 20 -
~05Z910
hlgh volume malllng, a typlcal applicatlon requlre~ the ch~ln
~' prlnter 310 to print se~eral llne6 of adtress informatlon on
each label. If the output of the chaln printer ln such an
appllcatlon 19 consldered ln labels (rather than llne~) per
second, slnce the po~tage printing mechanism 312 neet only
make one prlntlng lmpresslon per label, lt 18 compatlble in
terms of gpeed if it can run at about two or three postage
lntpressions per second. In contrast to conventional motor-
driven 'postage printers, the solenoid-driven mechanism 312 i9
lO capable of achleving such speets even lf the postage amount
ls changed for every print impression.
- Figure 8 illustrates the difference between the
non-variable type segments 500.5 through 500.8 and the variable
1' segments 500.1 through 500.4. Non-variable type segments
500.5 - 500.8 are solid slugs whi-ch contain only the type faces
523 for the fixèd information in the postage impression. The '-
other printing segments 500.1 - 500.4 are formed with hollow
lnteriors 524 which open through windows 525. Surrounding
,the wintows 525 are type faces for a continuation of the
20 fixed information, ~ut in addltlon type wheels 526 protrude
through the wlndows 525 for printing purposes. These wheels
contain respective ~ets of numerical type faces and are rotat-
able to select the number prlntet. The wheels 526 are part
of respectlve number selection modules 528 received within
the hollow interiors 524 of slugs 500.1 - 5~00.8. These
modules lnclude solenoid means ~not shown) for number wheel
rotation and electrical leads 53~ for the input of number
~election commants and the output of signals for verifying
the angular positlon8 of the number wheels. Tl~e variable
30 i,nf,ormation motules 528 are of a type aYailable commercially
~f,roDI the Practical Automation Company of Shelton, Connecticut.
The output leads 530 provlde a data feedback
cb/ - 21 -
lOSZ910
clrcuit whlch can be used to ~ent lnformatlon bgck to the com-
puter verlfying that the number wheels 526 have been rotatet
to the deslred posltion, ~o that the computer can determlne
whether its postage selectlon instructions have been carried
out before it prlnts the postsge. This ~9 one type of informa-
tion which is carried back to the electronic metering circuitry
220 or 320 and to the computer 216 or 316 by the feedback
lines 240, 242 or 340, 342 of Figures 3 or 4.
Figure 11 shows the control and display panel 598
of the electronlc meter 220 or 320. The meter inclutes a
special type of self-scrambling combination lock switch which
ls used for recharging the postage credit balance under secure
conditions. (See patent Nos. 3,664,231 and 3,034,329). The
~witch is manually operated by a knob 599 when the correct lock
combination is entered on a keyboard 602. There is also an on-
off switch 600, three indicator lights 604, 606 and 608 for
power on, meter ready and insufficient postage respectively,
a ~umerical display 610 wh~ch preferaBly has a ten digit
capacity, and a set of display selector buttons 612, 614 and
616 which determine respectively whether the numerical display
610 shallishow the amount in the ascending postage register,
the descending postage register or the number of mailings
recorded by a piece counter. Two additional buttons 618
and 620 are intended respectively to light up all the display
elements for test purposes, or to turn the display off entirely.
With reference to Figure 12, in general terms the
meterlng circuitry 220 or 320 of Flgures 3 or 4 comprises post-
age prlntlng circuitry 700 for drivlng prlnt solenoids 238 or 338,
ant for providing the computer 216 or 316 with feetback lnforma-
tlon as to the condltlon of the varlable number wheels 526~Flgure 8). It also comprises accountlng circultry 702 whlch
keep~ track of the postal balance ant alters that b31ance in
cb/ - 22 -
lOS;~910
re~pon~e to the prlntlng of postage. Th,e elect-ronlc meter
also comprlses sequence control clrcuitry 706 whlch provldes
a hard-wired (i.e, flxed) program for stepping the electronic
postage meter through a required series of operations. The
sequence control circuitry 706 and the postal accounting
circuitry 702 (non-volatile memory and arithmetric unit)
both operate in response to timing circuitry 708 in order to -
achieve synchronous operation. Display circuitry 710 intlcate~ '
the contents of the various postal accounting balances at a
gi~en time. A print confirmation circuit 711 advises the com- ~ '
puter as to whether postage printlng has been accomplished. ,-
All of the circuits in Tigure 8 are energized by power supply
circuitry 712; and circuits 700, 702, 706 and 711 communicate
with the computer through an appropriate interface 714.
As used hereinafter in this descriptlon, the follow-
lng definltions shall apply:
Machine cycle - eight gray code counter states or
one address duratlion,
Neter cycle - duration of generation of en,tire
sequence of 32 atdresses.
~ ode,- any of three control states which generates
a meter cycle. They are Cl~ ENTER POSTAGE, C2) ADD FUNDS and
~3) CYCLE.
ENTER POSTAGE - mode in which postage amount to be
printed i8 attet to the ascending register and subtracted
from the descending register. The piece counter i8 lncrementet
by one.
ADD FUNDS - mode ln which a, fixet postage amount is
atded to the teocending register - other registers remain
unchanget.
CYCLE - mode in which all registers remain unchanged --
this mote is used prlnclpally in accessing memory contents for
- 23
lOSZ910
resdout. It 18 also enteret through the lnitlalizstlon pro-
ceture,
In~ufflcient Postage - an lntlcator whlch ~ignals
that the contents of the tescenting register are below the
maxlmum amount the meter is capable of prlntlng ln one postage
fleld. -,~
Polllng - process by whlch priority of the control
eeateæ (modes) i9 implemented. A sequential check of modes
ls made until one i8 selected. . .
In normal operatlon the following sequence takes
place: ;
One meter cycle in CYCLE mote takes place tue to -- -
lnltlallzation. At least one free machine cycle follows
before the nex~t mote may be initiatet. The mode may be any
one of the three unless inhibited due to postage depletion or
similar condition. Every meter cycle ha~ at least one free
machine cycle following it to allow polling. ~ -
Use of this free machine cycle i9 also utllized
in asynchronously reading meter memory contents, one 4 bit ~-
word at a time. The minimum access rate i8 one word per
meter cycle although in practlce reglster contents would ~e
read out in sequence without intervening meter cycles.
To fetch master memory - ontents, the computer
feeds into the met-r the addre~s of the word it want~ to
~;~ read and a read co~mand. At the end of the then current
~eter cycle, the meter will read the memory locatlon and put
. ~ ~
~ the contents in the interface. To read the complete register,
,: .
the computer has to 8enerate the address se~uence of the
regi8ter, reading the contents one BCD dig~t at a time. ~ ;
~8 een in 8reater detail ln Figure 13, the computer
intarface clrcuitry 714 comprl-ei conventlonal hardware 798
¢16 bit output port with trobe~ whlch 18 deslgned to translate
;
cb/ - 24 -
: .. - . ' ,: , :
.: : . , - , , :
, . ,
lOSZ910
the tlmlng and/o~ data cote for~st of the computer lnto any
other timlng and/or tsta code format that msy beomployet by
the electronlc po~tage meter 220 or 320 (l.e. ! match the
transm~sslon llnes to and from the computer). It also includes
~ computer status register 800 which accepts commands and post-
age amount data from the computer for use by the ~eter, and a ;-
meter status register 802 whlch accepts status indications
and stored data from the meter circuitry and generates interr-
upts for use by the computer. The printing circuitry 700 in-
cludes the print solenoids 238 or 338 whi~h drive the fixed
and variable type segments 500.1-500.8; a solenoid 801 for -
operating a mechanism which loc~s the segments except during
postage printing; switches 803 which sense the condition of
the locking mechanism and the print segments 500.1-500.8 to pro- -~
~lde lnformation needed by the print confirmation circuit 711;
a circuit 805 which fires the solenoids 801 and 238 or 338 in
a predetermined sequence; the varlable number wheel modules ~-
528, one for each varia~le tiglt of the postage amount, which
rotate the number prlnting wheels 526 to select the postage
dlgits in response to computer-generated electrical comm-nds;
and a buffer 8~4 which stores the calculated postage amount ~ -
both for use by the variable modules 528 in setting the number
wheels 526 and also far use by the postal àccounting circuitry
~02 in altering the postage balances, -~
The postal accounting circuitry 702 comprises a
memory 806 which includes an ascending postage register 808,
a te-cending postage register 810, and a piece counter 812
which keeps track of the numbe~r of postage impressions ~ade,
In a preferred embodiment o the invention, thememory 806
`-~ 30 is of the complementary metal oxide semiconductor ~C/MOS~ '
lntegrated circuit type, and requires a back-up battery 813
- to pre~erve storage during A.C. power failures. The current
cb/ - - 25 -
105Z910
drsln of guch me~orle6 18 extremely ~mall ant storage would ~s
remaln lntact even lf a power fallure lasted for very long
intervals. Memory addresslng ls done by a decoder clrcult
814 whenever lnformatlon ls loaded into or fetched from the
ascendlng or descendlng reglgters or the piece counter sectlon
of the memory 806. An arithmetic unit 816 is used to perform
postal accountlng calculatlons, l.e., subtracting the amount
of postage from the descendlng register 810 and addlng to
to the ascending reglster 808 when prlntlng occurs, and
adding postage to the descending register 810 when the meter
is recharged. The arlthmetic unit 816 includes buffers 818
into whlch the ascending and descending register contents --
(from memory 806) and the postage amount (from print buffer
804) are ioadet prior to arithmetic operations.
There is also an insufficient postage decoder cir-
cuit 820 which tests the content of the descending register 810
and determines when the postal credit balance falls below a pre-
determined threshol,d. This could be~done, for example, by
comparing the proposed amount of postage in the prlnt buffer
804 wlth the remaining postage balance in the descending
register 810. In a preferred embodiment of the invention,
however, the circuit is simplified by using the same insuffi-
cient postage criterion that has long been employed in
mechanical postage meters; i,e. whenever the descending postage
c~edit balance equals or falls below the maximum smount of
postage that the meter is capable of printing, in thls instance
$99,99, the balance is insufficient.
For recharging the meter, there is the combination
lock swltch 860 which 18 operated by the knob 599 and keyboard
- 602 seen in Figure 11. When the meter user pays a required
~um, postal authorities glve out the comb~natlon of the lock,
permitting the meter user to operate the switch 860 once,
cb/ - 26 -
,:
,
.
~05Z910
whlch recharge~ the descendlng postage regl~ter 810 by a
fixet lncrement equal to the gum palt. Thereafter the lock
automatlcally re~crambles the comblnation ~o that another ~ -
payment must be made to obtain the next combinatlon from the
postal authorities.
The ~equence control circultry 706 lncludes a clock
822 whlch compriseg a tlme base oscillator 824 (Digltal Equip-
ment Corp., Model No. 401)~ protuoing a pulse stream for driving
a Gray code counter 826. The Gray code approach is employet
to take atvantage of its single bit transition characteristic,
which provides a clean output for drlving followlng circuitry.
The output of the Gray counter 826 is used to drive a memory
addressing counter 828, the count cycle of which i9 numerically
~; equal to the total number of addresses in the memory 806. In
ap~rticular embotiment of the inv~ntion, for example, the capacity -~
of the memory 806 is 32 addresses, each of which stores a
slngle binary-coded decimal dlglt. Slxteen of those addresses
are required for the ascendlng register 808~ eight for the `
descending reglster 810, and eight for the piece counter 812. ~-
The memory addresslng counter 828 steps through a sequence of
all 32 memory.addresses when drlven by the Gray code counter
826.
In order to make sure that each memory address ~ -
count sequence of the circuit 828 is synchronized with the
~tart of a Gray code count se~uence o the clrcuit 826j an AND
gate 830 ordinarily blocks the Gray count from reaching the
memory addresslng counter. However, when the Gray count
- reaches 0, a decoder circuit 832 sets a count starting flip-
flop 834 whlch then enables the AND gate 830, permittlng the
Gray counter 826 to drlve the memory adtresslng counter 828
ia leat 831, At the ent of a complete memory atdre~slng
equence of clrcuit 828, the last memory attress 19 decoted
.
cb/ _ 27 - !
.........
'': ~ ~ . ' ' ' -
lOSZ910
by a clrcult 836 whlch then energlzes a lead 837 to re~et t~e
count startlng fllp-flop 834.
The ~equence control clrcuitry 706 also includes a
polllng clrcuit 838 whlch is driven by the Gray cote counter
826 and continually tests for three commands in the following
priority sequence: 1) postage printing, 2) addition of funds
to recharge the descending postage balance, and 3) display read-
out, When one of these three operating modes is selected by
the polling circuit 838,'it sends the relevant mode command over
a lead 840 to control logic circuitry 842 which then carries
out the indicated activities in a hard-wired program sequence.
The sequence control circuitry 706 also includes an initialization
circuit 844 which includes circuitry 846 and 848 wired for
fixed-program start-up and shut-down routines respectively.
The display.circuitry 710 includes the display selector
panel switches 612-620 of Figure 11, y , means of w-hich the
user can request ascending or tescendini register or piece-
counter lnformation to be fetched from the memory 806 and
dlsplayed on the read-out 610, and can also test or blank the- . .
read-out 610. The latter circuit includes a buffer 852 to .
hold the display data fetched from the memory 806, and a
decoder 854 for translating the data into a form sui,table
for uge by the read-out 610.
'
The power supply circuitry 712 includes main power
~upplies 856. These provide operating voltages re~uire.d by
all the circuits in Pigure 12; and are controlled b~ the on/
off ~witch 600. There is also a Yoltage sensing circuit 858 ~ -
which determines when there is a power failure or low yoltage
condition whlch might produce an error in the computatlons
carried out b~ the arlthmetic unl~ 816. When an out-of~
tolerance ~oltage contition occurs, appropriate algnals are
8e~t to the lnitislization clrcuit 844 ant meter status
cb/ - 28 -
', ' '~- ';; ' :'
105~910
reglster 802,
Panel lnticator light 604 responds to the maln power
0 fiupplieg 856 by indicating whether power i~ on. Panel light
606 responds to the yoltage sensor clrcuit 858 by indicating
whether the meter is reaty for operation. Pinally, panel light
608 responds to tecoder 820 by indicating that an insufficient
postage condition has occurred,
The operation of the circuit of Flgure 13 will now
- be described. When the computer 216 or 316 calculates 8 post-
age amount to be printed on a mailing label, it transmits that
lnformation to the interface hardware 798. The interface hard-
ware then translates the postage data into the data code format ~ -
employed by the electronic postage meter circuit 220 or 320,
and sends $t to a data storage portion 862 of the computer
-status register 800. From there the postage amount is trans~
mlttet to the postage buffer 804 over a cable 864.
The computer also storès a postage setting request
ln a commant section 866 of the computer status register 800.
That register in turn sends a set printer signal to the control
logic 842 over a lead 866. The control logic then issues an
enter postage command over a lead 868 which causes the variable
print modules 528 to be set to number positions representing
the postage amount then containet in the print buffer 804.
A data feedback line 870 carries back a signal from the var-
~able modules 528 to co~yey~ print module status information
to an interrupt and status indlcations section 872 of the meter
status register 802, so that the computer wlll know when the
prlnt wheels 526 are properl~ set. If they are not properly
set, that fact ls reported bac~ to the computer by; the meter
~tatus register 802 and ~nterface hardware 798, As a result,
the computer does not is~ue a prlnt commant until the problem
18 reoolvet. But lf the computer receives an intication that
cb/ - 29 -
105~9~0
the varlable prlnt module~ 528 are ~et to the proper numerical
values, then lt l~sues a prlnt command whlch 1~ t~angmittet
through the lnterface hardware 798 and the command sectlon 807
of the computer status reglster 800, and then over lead 874 to
the flr~t priority ~ection of the polling circuit 838.
The polling circuit enters the first priority print-
ing mode, and sends a print mode commant over the lead 840 to
the control loglc 842, which then issues print instructions
over a lead 876. If a NAND gate 878 ls not disabled, the
print commant passes through the gate and traverses leads 879
and 881 to the solenoid sequencing circuit 805. The latter
then fireg the solenoid 801 to unlock the print segments 500,
and also fires the print solenoids 238 or 338 in sequential
relationship ~for a disclosure of the sequencing circuit 805,
refer to the Lupkas, et al application cited above). The
8ignal on lead 879 is also conveyed over a lead 880 to the
arithmetic unit 816 and causes it to perform a subtraction
operation deducting the amount of postage from the descending
register balance. ^
In order to perform this operation, the arithmetic : ~
unit buffers 818 recei~e the postage amount information over ~ :
a cable 882 from the print buffer, and they also receive the -~
Contents of the descending register 810 over a memory fetch
cable 884. The nece8sary memory addressing operation to acce8s :~
the descending register is carried out by the memory address
decoder 814 ln respon8e to address information received over
a cable 886 Yia a data gate 905 and counter 828. The control
logic circuit enableg the gate 905 a~d arlthmetIc unit 816 by
mean8 of leats 904 and 894, Fespectively.
io The arithmetic unit 816 carries ~ut ~ts calculation
and reloads the decremented postage balance back into the
descendlng register 8ectlon 810 of the memory 806 ~ver a
cb/ - jO -
. . ~ '- ' .:
, . ' ' " ' " . ~ . '' ' ' . ,,~
1~5'~910
cable 895, Once agaln, the memory Addreg~ tecoter 814 per~orm~
the addresslng function turing loadlng, responding to the
address lnformation on the cable,886 whlle control 61gnals
arrlve over leat~ 904 and 894 from control logic 842.
. In similar fashion, the amount of pogtage ig adted
to the ascending register 808, The piece counter 812 i8 incre-
mented each time the "enter postage" mode is initiated.
~ Summarizing the printing operation, the computer
command for setting the variable number wheels goes directly
over lead 866 to the control logic 842, 80 that the setting
unction is carried out off-line with respect to the polling
circuit 838, Then there is a feedback output over leat 870
to the computer to verify correct number wheel setting. Sub-
sequently a print commant goes over lead 874.to the polling
circuit 838. When there is no higher priority operating mode
requested, the print mote is enteret ant the c.ontrol logic
842 issues a commant whic~ simultaneously fires the print
solenolts 238 or 338, initiates the postage subtraction opera-
tlon of arithmetic unit 816, increments the piece counter 812.
ant atds the postage amount to the ascending.register,
These operations cannot be carried out, howeYer,
unless the insufficient postage decoder 820 tetects an ate-
quate pogtage balance remaining in the tescending register
810, and therefore enables the NAND gate 878. If,the postal
: cretit balance i8 insuffictent, the output-from the decoter 820
~nhibits the NAND gate 8J8, As a result, the print solenoits
are not firet, the postage balance is not tecremented, the
ascendlng register i~ not incremented and the piece counter
~s not incrementet. In attitlon, the tecoter output goes
over a leat 896 to turn on the insufficient postage panel
indlcator light, ant goes over a leat 898 to convey an insuffi- -.
clent postage indication back to the lnterrupt and status
cb/ - 31 -
lOSZ910
lntlcation section 872 of the meter ~tatus regigter 802
The computer programmer can then use thlg indlcation to lni-
tlate any teslred program routlne.
In a preferred embodlment o-f the postage prlnter,
theprlnt segments 500.1-500.8 are normally locked, for addl-
tlonal postage securlty, by the locklng mechanism controlled
by solenoid 801. The latter ig unlocked only at the tlme that
- postage printlng is initlated, and then locked agaln after
prlnting. The switches 803 serve to sense the locked and un-
locked condition of the lock mechanism, and also sense when
prlnt segments 500.1-500,8 respectlvely advance to print impact
position upon energizationof the print solenoids 238 or 338.
For a complete disclosure of the locking mechanism, the solenoid
801 and the switches 803, refer to the Lupkas, et al application ~ ;
clted hereinbefore.
When the prine mechanism is unlocked by solenoit 801,
switches 803 issue a signal on a lead 940 to set a lock mechan~
i~m flip-flop 942. The set output of that flip-flop then `
resets each one of a group of.print segment flip-flops 944.1-
944.8, assoclated with the print segments 500.1-500.8 res-
pectively, Then the print segment flip-flops 944 wait to
detect the movement of the print segments 500 to their print -
impact positions. As each print segment 500 advances to print
impact position, a respective lead 946.1-946.8 ls energized
by t~e associated print confirmation switch 803 to set the
associated print segment flip-flop 944. All the set outputs
of these flip-flops 944 lead to an elght-lnput NAND gate 948.
The output of the NAND gate passes through a dela~ circuit 950
and is controlled by~ a coincltence gate 952, -After printlng
the solenoit 801 18 de-energized, ant thus the locking ~echan-
is~ i~ relocked~causing one of the sensing switches 803 to~
issue snother slgnal on a lead 952 which resets the flip-flop
c~/ 32
1052910
942 The reset output of that flip-flop then enable~ coln-
cldence gate 952
Upon the enabllng o~ gate 952, the print confirmation
clrcuit 711 can determine whether all the print ~egments 500.1-
500.8 were guccessfully drlven to prlnt impact position during
the preceding print operatlon. If all the print segments 500
haye been driven to print impact position, the print confirma-
tion switches 803 will have set all the flip-flops 944, and
there will be no output from the NAND gate 948. Accordingly
there will be no output from the print confirmation circuit
711 on its print segment status output lead 954. On the
other hand, if any one or more of the print segments 500 fail
to advance to print impact position, the corresponding flip-
flops 944 will not be set. Consequently there will be an out-
put from the NAND gate 948. This output, delayed by circuit
950, will pass through coincidence gate 952 when the latter .
i~ enabled at the end of the print operation, resultlng in
an output on lead 954 by which the print confirmation circuit
711 advises the interrupt and status indication section 872
of the meter status register 802 that postage printing has
not been successfully carried out as ordered by the computer.
The computer can then carry out any appropriate alarm sub-
routlne dictatet by the programmer.
The next higher priority operating mode of the
polllng circuit 838 i8 the addition of funds to recharge the
tegcending register 810 when an insufficient postage condition
occur~. In order to avold the need for carrying the postage
printing mechanism and the accounting circultry to a Post Office
for recharging, this ln~entlon contemplates the use of the
~elf~scrambling cpmbination lock switch 860. Such locks were
preyiougly developed for remote recharglng of conventional
postage meters. A mechanical combination lock of thi8 type,
cb/ - 33 -
- , '. ~ '. .
:' .
:
105'~9~0
whlch employ~ mutilated gesrs for scra~bling, iH dl~closed
ln U. S. Patent No. 3,034,329 of R. C. Pltney, and ls ~ultable
for use ln the ~witch 860 of this circuit. As 8 preferable
alternative, however, one ~ight employ a keyboard-operated
~elf-scrambling combination lock device as describet in U. S.
Patent Number 3,664,231 iasued May 23, 1972 by Walte~ J. Hanson,
and assigned to the same assignee as the present appllcation.
Briefly, the Hanson device matches a hole pattern punched in
a movable tape with a keyboard-entered combination. If the
combination is correct, the lock is released once, permitting
the switch 860 to operate one time. Thereafter the tape is
advanced to a new position, and consequently the switch cannot
be operatet without obtaining the next lock combination from
postal officials.
The result of each lock-opening operation is to
close the combihation switch 860, sending a signal over a lead
900 to the second priority section of the polling circuit 838.
This causes an add funds mote signal to be transmittet to the
control logic 842 over the leat 840. An att ~unds 9ignal i8
then transmittet from the control logic 842 over a leat 902 to
the arithmeti$ unit 816. The effect of that signal is to
cause a preteterminet increment of postage, equal ln amount
to the payment mate to the postal authorities in order to
Qbtain the loc?~ combination, to be atted to the tescenting
register balance. The tescenting register portion 8I0 of the
memory 806 is accesset ant then reloaded with the new postage
balance by the memory address decoder 814 in response to an ?
addre8sing control ~ignal arriYing over a leat 904 from the
c~ntrol logic 842. The attressing control signal enables
gate 905 turing the memory attresslng count sequence o~ clr-
cu~t 828.
The thlrd priority operating mote of the polling
.
cb/ - 34 -
- lQ5'~910
clrcult 838 18 the readlng out of lnformatlon into the panel
dlsplay 610. This operatlng mote 19 entered in re~ponse to
one of the manually operated panel swltches 612-618, whlch
determlne whether the dlsplay is to show the contents of the
ascendlng register, descending register or plece counter sectlons
of the memory 806, or to llght up a test d~splay which energizes
all read-out elements. Any of these swltcheR generates a
slgnal (representet by arrow 619) which causes the polllng
clrcuit 838 to enter mode No. 1, The switch 620 cancels the
read-out operating mode entirely.
In response to a read-out mode signal on the lead 840
coming from the polling circuit 838, the control logic 842
send~ a signal over address control lead 904 which enables
gate 905 during the memory addressing co~nt sequence. Memory
contents are sequentially read out on cable 884. The signal on
lead 906 from the control logic 842 strobes the selected informa~ -
tion into the read~out 610.
The preferred form of dlsplay for this circuit is -
a light-emitting diode array with built-ln integrated clrcult
decoding logic 854,
The computer can also access the memory contents
at will, and fetch data t~erefrom to use for any purpose that
the programmer teslres. In order to accomplish this, the com-
puter lnserts the deslred memory atdress lnto the tata section
862, and also ~ends a memory readlng instructlon to command
section 807 of the computer ~tatus register 800, which ln turn
sends a read memory signal over a lead 912 directly to the
control loglc 842, bypassing the polllng clrcult 838, The
cont~ol logic 842 in turn ~ents a signal over the lead 892
30 ~o enable the data gate 888, admitting the computer-generated
memory addres-s arriy~ng o~er cable 889 to the memor~ address
decoder 814. This results ln fetchlng the requested ascendlng
reglster~ deJcending reglster, or piece counter d.ata from
cb/ - 35 -
. .
:- :
~05'~910
the memory 806 over csble 884, and ln~erting lt lnto a tsta
portlon 914 of the meter status reglster 802, Then the com-
puter can obtain the teslred lnformatlon from the meter status
register.
There iQ a possibility of arithmetic error lf postage
computationg are performed wh.en the logic voltage levels supplied
by the ma~n power supply circuits 856 are not within tolerance. ~,~
In order to make sure that all arithmetic computations take
place under proper voltage conditions, and thus avoid postal .. ~,
accounting errors, the start-up program section 846 of the , ~ ,
lnitialization circuit 844 does not turn on until it gets a
signal over a lead 915 from the voltage sensor circuit 858
indicating that all logic levels are within tolerance. The -
initialization circuit 844:produces a start signal on a lead ~ :
916 which turns on the memory address decoder 814 and also
makes sure that the gate controlling flip-flop 834 is initially . !;
reset.
, In the event of a power failure, low yoltage condi-
ti~on orshut-down of the meter, the voltage sensor 858 indicates
a power-off situation to the shut-down program sectlon 848
of the initialization circuit 844. At that time, the initial-
~sation circuit sends a stop signal on a lead 918 to a NAND
8ate 920, The NAND gate inhibits the stop signal if the
polling circuit 838 signal~ over a lead 922 that an arithmetic
calculation is currently in progress; i.e. the meter is in'
,mode No. 1 or 2, Under those circumstances, calculation i8
allowed to proceed to completion. The power supplies 856 ,~
are de~lgned with enough~capacitance to allow operation at ~,
pro~er yoltage levels for sufficient time to compIete any
arlthmetic operation that may b.e in progress, eyen a~ter total
pPwer ~a~lure. But a~ter the present calculati,on is concluded, - '
the polllng c~rcult 838 and lead 922 ceuse NAND gat,e 920 to
cb~ - 36 -
~05'~9~
pass the 8top slgnal out over llne 921 in order to turn off
the memory address decoder 814 and thereby preserYe the memory
contents unchanged for the duration of the po~er fallure or
other abnormal condition.
An addltional lead 924 coming from the voltage sensor
858 lights up the meter-read~ panel indicator light 606 when
the logic voltages come up to required levelg, and another lead
926 conveys the same meter-ready indication to the interrupt
and status indication section 872 of the ~eter status register
802, thus advising the computer that the electronic postage
meter i8 in condition for operation. When the voltage sensor
circuit 858 senses a low voltage condition, the meter-ready-
panel light 606 goes out and the meter-ready status indication
in register 802 turns off, advising both the human operator
- and the computer of the problem.
The operation of this postage system will be further
tescribed with reference to Figures 14 through 34. Figure 14
6hows the sequence of operation of the sy~tem incluting a plot
of the clock 824, the gray code counter 826, and the polling
signals with respect to time. The clock 824 as used in this
inventive system is a standard module (~odel M401-0-1, Digital
Equipment Corporation, Maynard, Mass.) set to operate at a 4
~z rate as shown in Figure 14a. The electrical logic elements
illu~tr-ted in the drawings are 7400 series TTL- (transistor-
tran~igtor logic~ components, such as are available from Texas
In$truments, Inc., unles8 otherwise indicated herein. The
lnternal control of the metering system is governed by the
clock frequency, whlch 18 divided into elght tlming periods
~F~gure 14g) for each machine cycle, by the 3~blt blnary Gray
Cote Counter 826 of Figure 17. This free-running gray code
counter 826 comprises 3 ~'J~K" fllp-flops 1000, 1001 and 1002,
re~pectlvely, provldlng outputs A', A'; B~, and ~; ant C C'
cb/ ~ 37 ~
'
~. ~` 105~9~
through buffers 1004, 1005; 1006, 1007; ant 1008, 1009 re~-
pectlvely. The gray code counter outputs A', B~, snd C', res-
pectively (Flgure 14d, 14e snd 14f, re~pectlvely) are repetitlve
every elght perlod~ 80 as to establlsh a machine cycle ~Figure
14g). The flip-flops 1000, 1001 and 1002, change state one
at a time. Th.ls has th.e atvantage that the output is certaln,
and there is no timing (race condition) problem between the
outputs. In other words, quest~onable outputs cannot occur
because one output may be generated sligh.tly out of phase
with another output. These "clean pulses" are used for controll-
lng the system, for gating purposes and polling.
The gray code counter is used to drive a memory
adtressing counter 828 as shown in Figure 17. The memory
addressing counter is a 5-bit synchronous counter comprising
5 "J-~" flip-flops 1010, 1011, 1012, 1013 and 1014 wired as
shown, and proyiding outputs A, A; B, B; C, C; D, D; and E, E;
respectively. Outputs A, B, C, D and E are plotted in Figure -.
15 with respect to time. The outputs A, B, C, D and E are
used to form 32 addresses as shown in Figure 16. The syn-
chronous counter counts in a straight blnary sequence generat-
ing these addresses, but these addresses could also be.supplied
directly by the computer controlling the meter. :~
The memory addressing lines are enabled through perlot
2 through 7. The memory addressing counter changes between ;--
periods 8 through 1, ~o that the addresslng llnes.are enablet
only when no addresslng changes are taking place. As indlcated
on Figure 15, there must be at least one machine cycle before
the address enabie signal becomes high again. This allows a
polllng sequence to take place which then provides the highest
priority mote awaiting 8ervice to be entered.
The meter cycle is generated by any of three controls
(1) Enter postage, (2) Add funds, and (3) Cycle. These modes :
.
cb/ - 38 - ! ~
.. . . .
- - . . . , -., :
~05'~9~0
are sequentlally checked by the polling clrcuitry 83B ~hown
ln Flgure 18. The polllng clrcult 838 i8 tepentent upon the
clock pul~es for tetermlnlng the polllng sequence. The "enter
postage" mode clrcultry h.a~ the ~ighest priority ant is fed
clock pulge 2 over llne 1040; the "Enter $undg" mote ls pulse
4 over line 1041; snt the "cycle" mode has the lowest priority,
because this mode is generally only for the purposes of readout
(accessing the contents of the memory for display purposes).
. The cycle mode circuitry i9 fet clock pulse 6 oyer llne 1042.
(See Figure 14h).
The three flip~flops 1015, 1016 and ~017, respectively
provite a signal to the control logic 842 over lines 1018, 1019
and 1020, respectively. These lines, for the sake of conven- -
ience, are represented by line 840 in Figure 13. Flip-flops 1015,
-1016 and 10.17 are mutually exclusive. When one of these flip-
flops goes "high" it tisables the other two flip-flops by feed-
ing a complementary signal back through the AND-gates 1021,
1022 or 1023 respectively, as the case may be. The A~D-gates
1201, 1022 and 1023 feed their respective flip-flops 1015,1016 .
and 1017. These A~D-gates receive the sIgnal from NOR-gate
1025, which feeds line 1024. The NOR-gate 1025 is tapped into
lines 1018, 1019 and 1020, at points 1026, 1027 and 1028,
respective, as shown.
Flip-flops lQ34, 1035, 1036, respectiyely, store
externally added information, such as enter postage, operate
tisplay, enter funds, over lines 619, 874 and 900, respectively..
This externally applled stored information influences the
operation of 1ip-flops 1015, 1016 and 1017, respectlvely,
. nd may be present while any of the fllp-flops 1015, 1016 or
- lQ17 are inoperative or in a ~ode feeding capacity,
Figures 14b and 14c show the relationshlp of the
addre~s enable signal (Flgure 14c) to that of the polling run
cb!. - 39 -
~05'~9~0
slgnal (Figure 14b). When the polllng run ~gnal goes "high",
~shaded portion shown ln Flgure 14b) the zero count decoder
832 ~Figure 17) cauges the address enable signal to go "hlgh"
at end of period 8.
As can be seen from Figure 14h, the three polling
modes are activated during periods 2, 4 and 6 respectively.
The cycle mode is entered through initialization (when the
system is turned on), and upon activating display select
switches.
Figure 19 depicts cont~ol logic gates 1029, 1030,
1031, 1032, and 1033 of the control logi,c circuit 842 (Figure
13). These gates generate an output at given periods, depend-
ing upon t~e states of the gray code flip-flops lOOQ, 1001 and
1002, i.e., A', or A'; Bl or B'; and C' or C' ¢see Figures 14d,
14e or 14f~
Logic gate 1029 generates output pulse 2; logic gate ~ -
1030 generates output pulse 4; logic gate 1031 generates out~
put pulse 6; logic gate lQ32 generates output pulse 8~ and
logic gate 1033 generates output pulse 7. Output pul8es for
periods 1, 3 and 5 are not generated because they are not used.
The'last address decoder circuit 836 is shown in
Figure 18. This circuit is fed from the memory addressing
counter 828 (Figure 1~). When the last address,pulse is
received by this circuit, it clears flip-flop lOlS over line
1029. Flip-flops 1016 ant 1017 are cleared over line 1030
rom circult 836, ~hich feeds gate 1031. Gate 1031 clears
flip-flops 1016 and 1017 over lines 1032 and 1033, respectively.
The combinatlon lock switch circuit 860 is shown in
Flgure 18, and the add funds circuit oves line 900. The com-
bination lock awitch cirCuit 860 i~ a well-known debouncing
circuit.
Figure 20 depicts the memory clrcuit 806 of Figure
cb/ - 40 -
~os~9~o
13b. The me~ory consl~t~ of RCA'g 16 ~lt ¢OS/MOS memory cSlps
arr~nged to provlde 32 word~ 4 bits wlde. The 32 memory loca-
tlons are dlvlded up lnto three regl~ters; ascentlng reglster
808; te8centlng regigter 810; and a piece counter 812. Each
location (4 blt wort~ holts a blnary cotet declmal ~see ~igure
16). The memory comprises two ldentical card~, each having
4 chips 1037, 1038, 1039 and 1040, respectlvely. In selecting
an address, one bit ls acce~set ln each of the four chlps 1037,
1038, 1039 and 1040. Thls allows you to store a 4 blt binary
coded declmal diglt.
COS/~OS WaS chosen for its low quiescent po~er,
which allows for battery operation over extended periods of
time. This is important because contlnuous power is necessary
to retain the memory contents.
Other features of this memory circuit include high
noise immunity and simplified interfacing, as well as the - -~
aforementioned non-critical power requirements.
F16ure 16 shows that the first ~0-15) sixteen loca-
tlon~ are assigned to the ascending register 808; the next
20 ~ (16-23) eight locations are reserved for the-descending register
810; ant the last ~24-31~ eight locations belong to the piece
counter 812.
Figure 21 illustrates the circuitry for the memory
address tecoder 814 and memory buf~er circuitry ~or the memory
806, The AND~gates 888 and 9Q5 in Figure 21 are represented
aa a slngle AND-gate in Figure 13b for schematic purposes.
The llnes 885 and 887, respecti~vely feeding these AND-gates
a~ shown ln Figure 13b, are shown in Figure 21 as respectlvely
l~nked to the multiple gates 888 and 905,
The outputs of t~e gating network 1041 contalning
AND-gates 888 and q05 are given as AA, AA; BB, BB; CC, CC; DD,
PD; and EE, EE; as shown, These outputs are fed to network
cb/ - 41 -
, , .
1~529~0
1042. The outputs of net~ork 1042 connect to the memory chlps
1037, 1038, 1039 and 1040 ghown ln Flgure 20, The outputs of
o k 042 (Xl; X2; X3; X4; Yl; Y2; Y3; and Y4) connect to
the corresponding chlp location.
The output gates 1043 and 1044 of network 1042,
which provide outputs EE and EE, choose either the irst
deck of chips or the second deck of chips ln memory. In other
words, these outputs correspond to the column bit "E" in Figure
16.
Network 1045 refers to buffer circuitry which is
assoclated with the memory 806. The outputs of the memory -
as Rhown in Figure 2Q ~M120; M121; ~122; and ~123) are fed
to circuit 1045. The second deck of chips (not shown) in the
memory provide outputs ~M220; M221; M222; and M223) which
supply circuit 1045 as shown. The designations 2 and 23
refer to the leàst and most sign~ficant bits, respectively.
The outputs of network 1045 are upplied to the arithmetic
unit 816.
Figure 22 shows the circuitry for the arithmetic
2a unit 816, the buffer circuitry 818 feeding back to the memory
806 from the arlthmetic unit, part of the insufficient funds
cirCu~t 820, and the add postage lock-out circuit (statug
inticator circuit 872),
Circuit 816 of F~gure 22 is fed by the outputs of
circuit 1045 of Flgure 21 through llnes 1046, 1047, I048 and
1~49, respectlvely. The memory outputs fed o~er these llnes
i~ added to the applied ~ignals to enter addltlonal poStage~
whlch is fed over llnes 1051, 1052, 1053 and 1054, respectlvely,
from the postage buffer circuit 804 (Figure 24). The postage
buffer and memor~ output~ are fed to the binary adder 1050,
where correspondlng 1nputs (A and B) are summed. The outputg
. o the adder 1050 are fed to a decoder 1055 whlch converts
cb/ - 42 -
,,;
. . , " '~' ~ ' .. ' ' ' . '
1~5'~0
the blnary ~um~ from binary to BCD.
Fllp-flop 1056 ~nd 1057 recelye clocklng pulse~ CP6
and CP8, respectlvely to control the proper propogation of
the carry bit.
Output buffer circultry 818 comprises four flip-
flops 1058, 1059, 1060 ant 1061 respectively~ which ~eceives
the BCD output from the decoder 1055, store the data, and
pass it on to memory 806 over lines 895 (see Figure 13b).
Lines 895 are tapped into the insufficient funds circuit 820
over lines 1062. The "Descending Register Full" circu~t.
of status circuitry 872 is tapped ~nto lines 895, and is fed
y~a line 1063, The latter circuit receives a signal which
locks out the combination lock ~hen the descending register
~9 full. Pigure 23 illustrates the aforementioned insufficient
postage decoder circuit 820 and the "Descending Register Full"
circuit of circu~try 872.
Figure 23 also s~o~s the arithmetic control circuit
1066, which supplie~ t~e clear carry and preset carry signals
to the arithmetic circu*t 816. The clear carry signal is
carried over line 1064, and the .preset carry signai i9 carried
over line 1065, to the carry control flip-flop 1057 ¢Figure
222 .
Figure 24 depicts the.postage buffer circu~t 804.
The outputs from the print.buffers of Figure 25 are stored
~in a plurality of latches of postage buffer circuit 804.
There are four sets of four latches as shown by arrows 1067,
1068, 1069. and 1070. Eaca set of four latches store~ the
~ostage amounts from $ ,01 to $10.00 as ~hown. Each get of
14tches respectlvelr feeds to a multlplexer ¢multiplexers
1071, 1072, 1073 ant 1074, respectively). These multiplexers
~elect one BCD dlgit at a time from its corresponding ~et of
latches, ~hese multlplexers feet to another row o~ 4ultiplexers
cb/
~05'~910
1075, 1076, 1077 and 10.78, respectively. The ~unctlon of multl-
plexers 1075, 1076, 1077 and 1078 18 to select the postage
a~ount, the nine'g complement of the pogtage a~ount, or zero.
The nine's complement of the postage amount is uset to effect
the subtraction of the postage amount from the descending
regi.ster dur~ng the enter postage mode through an addition
process, The selection of the zero is, for example, to propa-
gate carry through higher order decimal plaees, and to leave
register contents unchanged during cycle (see Figure 16). The
outputs from the multi.plexers 1075, 1076, 1077 and 1078, are
~espectively fed to the arithmetic circuit 816 over lines 1051,
1052, 1053 and 1054. ?.
Multiplexers 1075, 1076, 1077 and 1078 are controlled
by t~e inputs fed over lines 1079 and 1080 from the multiplexer
control circuit 1081 of Figure 23. ~ultiplexers 1075, 1076,
1077 and 1078 gelect the proper postage amount, nine's comple-
ment thereof, or zero for each of the three registers ~ascend-
ini? descending, and piece counter~ during the enter postage,
add funtg, and cycle modes as sh~own in Figure 16. Multiplexers
1071, 1072, 1073 and 1074 are controllet by outputs A ant B
of the memory adtressing counter 828 (Pigure 17) to select
the $ .01, $ ~10, $1~00 and $10.00 tigitS from the postage
buffer circuit 804 ~t the æame time the corresponting tigits `
are being accessed from the ascending register 808 and des- -
ce.nding register 810 ~Figure 13B~. The inputs fed over lines
1082 and 1083 derived from the outputs of th~ first two flip-
flops 1010 and 1011 of the~ synchronous 5-bit counter 828.
The multiplexers 1075~ 1076, lQ77 and 1078 are fed
wIth added funds over l~ne~ 1084, 108~, 1086 and 1087, In
t~ case~ the dIglt 5 is tranamltted over lines 1084, 1085, 1086
and 1087 and atded to the tescendlng register ln the $100~a
- pos~tIon selected by the multiplexer control logic 1081 (see
-
cb/ - 44 - ! -~ .
. .
105'~9~0
Flgure 23) to glve an atded fund increment of $500,
Plgure 25 show~ the prlnt buf~er circultry feedlng
the pogtage buffer circuit 804, The print bu~fer circult comr
prises four banks ~only one shown here) of four D-type ~llp-
flops 1088, 1089, 1090 and 1091 each, Each bank of four fllp-
flops 1088, 1089, 1090 and 1091 inputs one set of four latches
~n postage buffer circuit 804, oyer llnes 1092, 1093, 1094
and 1095 as shown. The signals fed over these lines are also
fed to a comparator 1096 to check for BCD errors. The compara-
tor 1~ also fet from the 4-bit counter of Figure 27 oyer lines,
- 1097, 1098, 1099 ant 1100, Flip-flops 1088, 1089, 1090 ant
1091 receive BCD digit data 862 from the co~puter; strobe -
pulses for enterlng the data into the prlnt buffer are gener-
ated by gates 1125, 1126, 1127 and 1128 ant are outputted over
llnes 1101, 1102, 1103 and 1104 (Figure 27~ to print buffer ,
~consisting of 1088, 1089, 1090 and 10~1) enabling lines 1105
Figure 25) to enter $ .01, $ .10, $1,00, $10.00 digits
respectivel~, As s,hown ln Flgure 28 the BCD tata is on blts
12 through 15 of t~e digital word, ,
' The outputs of each bank of fllp-flops 1088, 1089?
1090 and 1091 are fed to a 4-to-lQ llne tecoder 1106, whose
outputs feed a serles of electrical contacts correspondlng
to various posltions on the yari:able number modules- 528 of
~lgure 8, The decoder proyidea low signal on the contact
corresponding to the posltion to be selected. These electrlcal
contact~ are sensed by a wiper arm on each module.
Figure 26 ~llustrates circuits 1109 and 1110. Cir-
CUit 1ll0 i9 lnputtet on lines 1111~ 1112, 1113 and 1114,
' ~hich connect to each wiper arm (commutatlve bruah) on t~e
- 30 rotative elements of the varlable number modules 528, When a
~'high~' sign~l i8 sensed by a wiper arm, indlcating a wrong
wheel po~ltlon. the ~ignal 18 carried over the appropriate
cb/ - 45 -
.
- - .; . .
:
lOSZ910
input llne (1111, 1112, 1113 ant llI4) to a respective 8ate
1115, thus enabllng the gate and turning on a respecti~e SCR
1116, Each respective SCR 1116 i8 connectet to a triylng coll
of one of the variable number modules for rotating the number
wheels to the proper position. When the appropriate posltion
ls reached, a "low" slgnal i8 detected by the wiper arm, which
ls subsequently fed back through one of the lines 1111, 1112,
1113 and 1114 to dlsable the respective gate 1115 and turn off
the respectlve SCR ~16.
Circuit 1109 is fed from line 1166 of each comparator
1096 of Figure 25, (only one of four circuits shown) over lines
1117, 1118, 1119 and 1120, respecti~ely. The lines feed to a -
gate 1121, which checks for the Binary Coded Decimal and pro-
vides an output on line 1107. Line 110~ feets to gate 1122 in
Figure 27 as shown. Gate 1122 and J-K flip-flop 1123 are part
of the lnterrupt and status indicator circuitry 872.
The gate 1124 o circuit 1110 is connected to each of
lines 1111, 1112, 1113 and 1114, and is used for checking
whether the print wheels of the variable number modules are
in the set posltion. The output of gate 1124 is fed over line - -
1108 to gate 1125 of the interrupt and status circuitry 872
as shown in Figure 27. The outputs of flip-flops 1144 and 1123
form part of the feed back to the computer through the meter
station register ~igure 29).
Pigure 27 depicts the print wheel logic circuitry.
The print buffe~r to be loated i8 selected by bits 10 and 11
of the digital output (Figure 28). AND gate~ 1214~Figure 28)
decode bits 10 and 11 as spec~fying $ ~01, $ '.10, S1.00,
$10.00 dlgits and feeds the appropriate enabl~ng signal to
8ates 1125-?1128 (Figure 27), A sampling pul~e to gate 1125-
1128 8enerates a strobe ~i8nal on one of the outputs 1101-
1104 which goes to the appropriate print buffer enabling line
cb/ - 46 - '
o5~z91~
1105 ~Figure 25) which causes dat~ present on the ti~ltal
output 862 (Flgure 28) t~ be enteret lnto the prlnt buffer
(fllp-flop 1088-1091 in Figure 25~, ' ,
The print wheel loglc clrcuit has pulse generatlng
means (arrow 1129) to generate a 6Q Hz s~uare wave signal
which operates a counter 1130 yia an énabling gate 1131.
~he counter 1130 provides twelye pulses for operating the
print wheels. The prlnt wheels only require a maximum of
10 pulses, so that there are several superfluous pulses,
ThiS over abuntance of pulse$ iS planned, so that all the
wheels will be set wlth assurity. If a wheel does not obtain
the proper position after the t~elfth puls,e thls wlll be sensed
and lndicated on the dlsplay as an error conditlon as afore-
mentioned. ,~
The counter 1130 feeds the puls,es through a decodlnggate 1133 to flip-flop 1134. Flip-flop 1134 passes an enabl-
i~ng slgnal to the gates 1115 of Flgure 26 oyer line 1132 to
; . turn on t~e SCRs.
The meter status register (Figure 29) ls the means
~y ~hlch the meter communlcates wlt~the computer controlling lt.
It performs three functions~ transfer of data 2) indication
of status 3) lndlcation of error conditlons. Bits 12-15 (not
8hown in Plgure 29 ~ are used to transfer data from meter
~emory~ to the computer. Status indicators include:
Print w~eel~ not movi~g ~bit 0) llne 1143
pri~t head not m,oy~ng ~bit 1) line 1221 ~'
Prlnt cspacitor changet (bit 8) line 1220
No funds ~bit 9) line 1217
Regi~ste~ reats co~plete ~bit 10) llne 1219
' Meter ready (bit 11~ line 1215
~Print heat not moYing" ant "print ~heels 8et~' set
fl~p-flops 1140 ant 1139 ~espectlvely which generates interrupts
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through gate 1141. Thl~ relieve~ the co~puter of the neces61ty
of waltlng in a loop Sor the duratlon of the slow mechanlcal
operations lnvolved.
Normally in operating the meter, 4 BCP digits would
be outputted to the print buffers, the meter printer would
set to the number, the computer would check the meter to see
that sufficient postage was available, then issue a print
command The computer would not issue another "set" or "print"
command until after the meter has had time to complete the
previous operation. The meter is logically locked out from
attempting any operation not "~ell defined". Any such operation
sets flip-flop 1135 which outputs a signal on linell36 to
bit 4 (line 1135) of the digital input which indicates a ~ ;
programming error. Examples of such errors are: issuing a ~- -
print command a) before the print.wheels have finished setting
b~ while the print head is moving c~ ~hen there i8 a setting
error d) when BCD is not in the print buffers e~ when there
is insufficient postage in the meter f~ when the printer
power supply iS not ready and g) when the meter is not ready. ?~'
Such an error also generates an interrupt which signal~ the
computer to read the status register and go into a routine to
~andle this - so~e error conditions could be handled by computer
programmlng~ others woult require human intervention. 3it 5
is another error message - non BCD characters in a print buffer.
Bit 6 comes up if'the print wheels should change ~osition due
to th~e impact of printing.
One~shot 1148 pFovides a clock signal to the polling
cirCuit of Flgure 18. This 1 sec signal is carried by line 8~4
to flip-flop io35 ~Pigure 18) to initiat'e the enter postage mode.
One-shot 1150 provide~ a dummy signal of 50 ~ dura-
tion to ind~cate the prlnt heat return. However, the prlnt
heat can actually be monltored by means of a switch, thus
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eliminat~ng the need for one ghot 1150 if ~o defilred.
Pigure 30 sho~s the circuitry Sor the memory power
supply 856, and the yoltage gensing circuit 858. The voltsge
sen8ing circuit 858 compri~es two zener dlodes 1151 and 1152,
Fe5pectively~ The zener dlode 1151 is used to monitor the
yoltage level before the regulator to the logic circuitry,
and the zener diode 1152 ~s used to monitor the voltage level
before the regulator means 1161 to the memory. When the vol-
tage leyel drops below a desired level in either lines 1153
or 1154, one of the transistors Ql or Q2' as the case may be, .-
will turn off. When either Ql or Q2 turns off~ Q8 will be
caused to become non-conducting, which in turn causes Q7 to
turn off. This results in a lo~ signal appearing on line 1155.
This low signal is fed over line 1155 to the control power
supply and initialization circuit 844 of Figure 31. If there
is no operation being performed in the meter, ~for example,
add funds) when thls low signal is receiyed, then a cgmmand to
turn po~er off i9 giYen on line 1156 ~Figure 31). Thig command
is~ then conyeyed over line 1156 to the power circuit of Figure
30 where it turns on transistor Q4. When transistor Q4 becomes
conducting, current i:s drawn in line 1157, thus turning off
transistor Q3. This causes transistor Qg to become non-contuct-
ing, if transistors Ql and Q2 are also non-conducting. Transis-
tora Ql and Q2 are aesumed to be turned off because they initiat-
ed the start of the power-off condition, Transistor Q9 will
now influence transistor Qll to turn off, thus depriving the
memory of power.
On the other ~and, lf an operation is belng perform-
et in the meter when the lo~ signal is receiyed on line 1155,
then gate 1158 CFlgure 31) will remain dlsena~led until the
operation 1~ completed. Thls will prevent the com~ant to turn
off power on line 1156 until the operation la completed.
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~05'~9~0
Zener dlode 1159 (Figure 30) actg to regulate the
voltage going to the memory, ~bove the 12 volt leYel, the
zener diode 1159 conductg, clamping the output of translstor
.. . ,
Qll at about 12 volts,
Translstor Qlo and Q5 are used ln a current limiting
clrcuit to protect the memory power supply. If too much
current i8 drawn in line 1162, transistor Qlo becomes conduct-
ing which in turn causes transistor Q5 to turn on. Current
is reduced in line 1163 which starts turning off transistor
Qll thus ~imiting the current in line 1162 to a safe value.
Transistor ~6 is used to provide a "power-on" signal
on line 1160 which;is fed to the control power supply and
initialization circuit 844 of Pigure 31.
Figure 31 illu~trates the control power supply and
initialization circuit 844 as aforementioned, ~lements 1164
and 1165 are "one-shots". The "one-shot" 1164 supplies the
"turn-power-off" command carried on line 1156 as pre~iously
tiscussed, The "one-shot" 1165 supplies the initialization
~lgnal used to preset lo~ic elements on start-up including the
flip-flop that initiates the "cycle" mode on start-up.
Figure 32 depicts the circuitry for the display
8elector switches 612, 614, 616, 618 and 620. Each switch
cirCuit acts as a buffer register which stores the information.
~ach switch circuit comprises a single pole double throw
~witch 1167, a well known debouncing circuit 1168, and a "J-K"
rflip~flop 1169. Only one switch can be thrown at one time;
the switches are mechanically exclusive.
Information iB tr8nsferred to the fllp~flops 1169
~hen the system is not ~peratlng in any of the three ~odes.
The outputs from these circuits are, there~ore, well deflned
(~,e, conytant) dur~ng the c~cle mode.
~he gate 1171 8enerate~ a ~ignal every time a
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switch iB depressed. The slgn i8 carried-on llne 619 to
the Cycle mode circuit ~f Figure 18.
A swltch clock signal i8 introduced on llne 1170
which synchronizes reading the manually operated switches into
the "J-K" fllp-flops with the clock controllet meter operatlon.
The switch clock signal is generated by the switch clock cir-
cuit 1172 of Figure 33. This signal will only be generated
when there is no run signal, and the addressing counter i9
at zero.
The display used ~n this postage meter system is a
standard Hewlett-Packard display, ~No, 5082-7300) which has
latches and decoder built-in.
The multiplexer circuitry 1173 of Figure 33 gates
data from the memory to the display, and also blanks and tests
the display. The multiplexer elements 1178, 1179, 1180 and
1181 receive memory data from the arithmetic unit output buffer
818 (Figure 22) o~er lines 1174j 1175, 1176 and 117~ respectively.
In the display ~ode the memory tata is outputted to
the tlsplay inputs over lines 1182-1185 one BCD digit at a time.
Circuit 1186 of Figure 33 generates clock signals to enter
data into the appropriate display latch. The "0" output of
1186 clocks data into the least significant number display
and "9" output into the most significant number display.
Because the memory only stores numbers, there is
neet for a circuit to $elect the tecimal point in the ti play.
Circuit 1188 is ~uch a circuit, ant is shown in Figure 33.
- The panel inticator circuits 604, 606 ant 608 (lamp
dr~yerg) are also illustrated in Figure 33.
Figure 34 shows the direct memor~ read control
log~c clrcuitry, which transfer~s attress data to the memory
control logic circultry of Figure 21~ ~
31ts 7 through 11 on the tigital output from the
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co~puter (see Flgure 28) 1B placed on llnes 1189, 1190, 1191,
1192 and 1193 of bufferg 1194, 1195, 1196, 1197 ant 1198, res-
pectively. When the "read memory" command i8 given on line 912,
fllp-flop 1199 i6 set, provlded that *he system is not ln the
mittle of a mode. The buffers 1194, 1195, 1196, 1197 and 1198
transfer the atdress data on line 887 to gates 888 of circult
1041 of Figure 21.
On clock pulse 2, flip flop 1200 provides a "direct"
signal on line 892 of circuit 1041 which enables these gates,
ant the address data i9 transferred to the buffers 1201, 1202,
1203 and 1204 of circuit 1045 via the memory of Figure 20.
Clock pulse 2 also clears flip-flop 1199 via line 1205 from
flip-fl~p 1200.
On clock pulse 6, gate i206 is enabled, and buffers
1201, 1202, 1203, and 1204 ~ransfer to latches 1207, 1208,
1209 and 1210 which feeds into interface circuit 914 (Figure
282 . .
Flip-flop 1211 ~Figure 34) is set on clock pulse 6
indicating that "read" has been completed. Flip-flop 1211
is left "highi' after the meter iB read. An interrupt signal ~ ~
is also provited in circuit 872 as a result. This notifies ~ -
the computer that the read operation has been carried out and
the information requested is present on the digltal input to
the computer. ~ ~ s
On clock pulse 8, flip-flop 1200 is cleared, resett-
~ng th~ circuitry for a new "read" operation.
It will now be appreciated that this invention provides
a secure postage meterin8 tevice which uses a computer-compatible
piggy~back-mounted postage prlnter and electronic digltal
postal accounting techni~ues, and 18 therefore suitable for use
in computer-controlled, hlgh-speed-printer-implemented, high
yolume mailing operations.
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Slnce the foregolng descrlption and drawlngs are .
merely illustrative, the scope of protectlon oS the lnventlon
has been more broadly stated in the following claims; and
these ghould be liberally interpreted 80 as to obtaln the
beneflt of all equlvalents to wh~ch the invention i~ fairly
6 entitled.
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