Note: Descriptions are shown in the official language in which they were submitted.
FIELD_OF THE INVENTION
This invention relates to the field of matrix printers and dis-
play devices wherein symbols such as alpha numeric characters are generated
by controlling a spot forming device that traverses an entire area into
which all possible characters can be fitted. More particularly, this
20 invention relates to mechanism for controlling the spot forming device as
it traverses a scanning path of a raster pattern that covers the area of an
entire page of text. A preferred application of the control of this inven-
tion is in an electrophotographic page printing system wherein pages are
generated by a modulated light spot that traverses a fixed
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1 axial path on the surface of an electrophotographic copy drum with a modu-
lated spot of light to selectively discharge the background or "white area"
of the page being generated leaving on the photoconductive surface an
electrostatic latent image of text symbols that are developed and trans-
ferred to form final copy by techniques substantially identical to those
currently employed in known xerographic copy machines.
BACKGROUND OF THE INVENTION
The generation of symbols for printing or display by selecting
predetermined groups of dots from a set matrix of potential dots is a
highly developed art. This technique has been used in various forms for
telegraph printers, cathode ray tube type computer output terminals, computer
line printers and graphics quality photo-composers, to mention a few diverse
examples.
The technigues and apparatus employed in xerographic copy devices
have been proposed for some time for use in generating original text or
pictures directly from electronic signals, rather than from the usual
optically projected pre-formed image. An example of one such arrangement
is found in U. S. Patent 2,829,025.
A preferred configuration of an original text xerographic printer
exposes a page image by progressive columnar page segments that extend
parallel to the axis of the xerographic copy drum. This arrangement maxi-
mizes the page production speed of the printer by processing pages in the
direction of their shorter dimension or width. Certain types of text are
normally printed with lines of text that read along the long dimension of
the page. An example of this type of text is familiar computer printout
sheets.
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1 It is desirable for an optical printer to be able to generate
ol~tput having lines of text that extend selectively along either the long
or short dimension of the page principally by the selection of type font
control data that presents character matrix information that is prede-
termined according to the desired character orientation. If, for example,
printing is normally to occur with lines of text extending along the short
dimension of the page, such printing can be controlled by a first type font
data bank defining patterns for generating characters in terms of columnar
or vertical raster strokes. To produce writing lines extending horizo-
ntally along the long dimension of the page, a "rotated font" data bank is
provided which defines patterns for generating characters by raster strokes
extending horizontally or along the writing line of the page. In printing
either type of page the paper is fed to the printing machine in an identi-
cal manner, the only difference being the electronic control that places
the image on the xerographic drum.
Printed material can be classified as having fixed or propor-
tional spacing depending upon whether all characters regardless of their
size are alloted the same horizontal spacing or are alloted an amount of
horizontal spacing proportional to their size. Proportional spacing pro-
vides printing with a prestige appearance and also provides a more compact
writing form that is generally found easier to read.
DISCLOSURE OF THE INVENTION
My invention provides improved mechanism for controlling the
conversion of coded symbol identifying data into the light/dark contrast
pattern required for generating printed pages in the preferred configu-
ration of a xerographic page
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1 printer. My invention provides a page memory access control register
having a register stage associated with each widthwise extending row on a
page. Each stage of the page memory access control register stores an
address of data within a preassembled page memory wherein is contained a
code ;dentifying a symbol being printed in the row associated with the
register stage. Each register stage further stores information as to the
number of remaining raster strokes required to complete printing of the
particular symbol identified in the page memory address.
The page memory access control register progressively presents
its stored information in synchronism with the scanning motion of the expo-
sure light spot. The individual codes thus accessed from the page memory
are translated by a table lookup memory that identifies both a reference
address in a type font memory and the total number of raster strokes re-
quired for complete generation of the symbol identified. The reference
address is modified by the number of remaining raster strokes stored by the
associated stage from the page memory access control register to derive a
final contrast pattern that is employed to directly control the exposure of
the light spot onto the xerographic copy drum.
As printing progresses the data stored in the various stages of
the page memory access control register is updated in accordance with a
predetermined regular progression. The "remaining stroke" information is
simply counted down as raster strokes are completed. Upon display of the
last stroke of a given symbol, the page memory address stored in the associ-
ated stage of the page memory access control register is incremented by a
fixed number to thereby identify the page
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1 memory address of the succeeding character to be printed in the associated
row.
By use of my page memory access control register, as thus de-
scribed, it is possible to enable printing of characters having propor-
t~onal spacing in the preferred configuration of the xerographic printer.
Furthermore, it is possible to display data that is pre-arranged in a page
memory to produce either normal or rotated output through the use of a
normal or rotated type font with much simplification through the relatively
simple expedient of controlling the initialization and progression constant
of the page memory access control register.
In the preferred embodiment of my invention, page memory effi-
ciency is enhanced by the use of "white space" indicating control codes
such as "End of Scan" and "End of Row" codes that eliminate the need to
individually code character size white spaces in large areas such as
margins.
These and other objects, features and advantages of my invention
will be fully understood by those skilled in the art from the following de-
scription of a specific illustrative preferred embodiment thereof, wherein
reference is made to the accompanying drawing of which:
Figure 1 is a diagramatic view showing the organization of an
optical printer having a character generator constructed in accordance with
my invention.
Figure 2 is a plan view of a typical page having text printed
thereon by a printer like that of Figure 1.
Figure 3 is a schematic view showing the organization of a control
register employed in the character generator of my invention.
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1 Figure 4 is a schematic view showing the organization of a translating
memory table employed in the character generator of my invention.
Figure 5 is a component and data flow diagram showing the major
fea~ures of the character generator employed in my invention.
Figure 6 is a schematic view showing the organization of a type font
memory employed in the character generator of my invention. (See Sheet 2).
Figure 7 is a diagramatic view showing a cycle control clock used in
the character generator of my invention. (See Sheet 1).
F;gure 8 ;s a diagramatic view illustrating an improved feature of my
invention.
Figure 9 is an illustration of a sample page printed utiliz;ng the
modification of Figure 8 and -
Figure 10 is a diagramatic view illustrating a preferred implementation
of a portion of the character generator more generally illustrated in Figure
5.
In F;gure 1 there is shown a xerographic page printer 10 of preferred
configuration together with a block diagram showing the primary image genera-
tion control components employed in conjunction therewith. Figure 2 illu-
strates a page 20 of the type created by the printer 10. In typical fashion
the page 20 bears symbols 21 arranged in lines of text 22 that read along the
short diminsion 23 of the page. Returning to Figure 1, the page printer 10
includes a xerographic type copy drum 11 providing an image receiving photo-
conductive surface membér 12. Surface 12 is rotated successively past a
charging station 13, an exposure station 14, a development station 15, a
transfer station 16 and a cleaning station
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17. At exposure station 14, a uniform charge applied to surface 12 at
charging station 13 is selectively dissipated by a binarily controlled
light spot 30 that traverses a path 31 extending parallel to the axis of
rotation lla of the drum 11. Selective exposure by the spot 30 generates
binary elements of an electrostatic latent image 32 consisting of dis-
charged white or background area 33 and charged image areas 34. The latent
image 32 is presented to development station 15 where colored thermoplastic
resin powder or toner ;s selectively deposited on the image areas 34. The
thus developed image is transferred by electrostatic force at station 16 to
a support sheet 35. The thus printed sheet 35 is passed through a fixing
station 18 where heat or other suitable means temporarily liquifies the
resin toner to cause it to adhere to the sheet and form a permanent image.
The sheet 35 is then delivered to an exit pocket or tray 19 where it can be
removed from the machine. Any toner powder remaining on surface 12 as it
leaves transfer station 16 is cleaned at station 17 prior to recharging of
the surface 12 for further operation. The details of the xerographic
printer are well known to those skilled in the art and form no part of this
invention, therefore are not further described herein. It is to be under-
stood that a variety of techniques exist for performing the various funct-
ions identified.
Controlled light spot 30 is preferably generated from a source of
high energy coherent light such as a continuous mode laser 36 that projects
a laser beam 37 along an optical path through spot control light modulator
38, redirecting mirror 40, lens 41, scan mirror 42, lens 43, beam splitting
partial mirror 44, and modulation knife edge 45 to the surface
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1 12. Modulator 38 is an accousto-optic Bragg effect device known to those
skilled in the art. Modulator 38 responds to binary electrical information
on its input line 46 to effectively emit the beam 37 in either of two
closely adjacent but slightly different output paths 39a or 39b. If the
beam 37 is emitted along output path 39a, it will ultimately be directed
past the modulation knife edge 45 and strike the photoconductive surface 12
as spot 30 to discharge the surface and thereby ultimately cause white or
background area to be produced on the sheet 35. Light emitted along path
39b is intercepted by the modulation knife edge 45 and thus does not strike
the surface 12. The undischarged surface 12 that remains will develop a
toned image at station 15 to form part of the image area on the final copy
sheet 35.
Scan mirror 42 receives laser beam 37 along both paths 39a and
39b and directs it along the scanning path 31 whereby it generates a colum-
nar segment 24 (see Figure 2) of the image of page 20. Mirror 42 is
configured as a regular polygon and is driven by a motor 47 at a sub-
stantially constant speed that is chosen with regard to the rotational
speed of drum 11 and the size of spot 30 such that individual scanning
strokes of spot 30 traverse immediately adjacent areas on the surface 12 to
provide a full page exposure raster.
Beam splitting mirror 44 intercepts a fraction of laser beam 37
along both paths 39a and 39b as it is moved through its scanning motion by
mirror 42 and diverts this fraction through an optical grating 50 to an
.-. ~
elliptical mirror 51 by which the light is reflected to a photodetector 52
positioned at one foci of the mirror 51. Scan mirror 42 is located at the
;! other foci of elliptical mirror 51 and the optical geometry of
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1 thle system is selected such that grating 50 is positioned to be equiva-
lently located relative to the exposure station 14. Photodetector 52 thus
creates a train of clocking pulses 53 that is a direct measure of the
scanning movement of laser beam 37 relative to the photoconductor surface
12. Conveniently, the pulses produced at photodetector 52 occur at the
same rate that image elements or dots are to be defined by modulator 38
thereby enabling photodetector 52 to directly generate a gating clock
signal for control of the modulator 38. A continuous transparent portion
54 of the grating 50 is provided to enable detection of scan completion.
For specific control of modulator 38, there is provided a source
of raw text data such as a magnetic card or tape reading device 55 which
delivers the data to be printed to data processing apparatus 56 by which
the raw text data is assembled in a desired format into a page memory 57.
In the page memory 57 each character or symbol to be printed as well as
spaces to be inserted between symbols are recorded at individual memory
addresses which are, in turn, associated with the writing lines of a normal
page and with the order position of the symbol within the writing line. For
example, referring to Figure 2, a code defining symbol "b" on page 20 would
be stored in page memory 57 at an address that is identified with the
eighth writing line (seven blank lines provide a top margin) and the
seventeenth order position (the left margin is composed of five blank
symbols in this example).
Once the text has been assembled in page memory 57, character
generation circuitry 58 operates to provide the final dot pattern control
to modulator 38. In addition to page memory 57, both data processor 56 and
the character generation
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1 circuity 58 have access to additional memory S9 which includes the page
memory address control register 60 that is unique to my invention as
well as reference address and escapement value table or translator 70.
PAGE MEMORY ADDRESS CONTROL REGISTER 60 (SEE FIGURE 3)
Page memory address control register 60 ;s shown d;agram-
atically in Figure 3. This register is preferably implemented as simply
a dedicated portion of read-write memory 59 (Figure 1) and includes a
plurality of individually addressable multi-bit stages or memory cells
61. Each stage 61 is capable of storing a data word 62 which is divided
into a page memory address portion 63 and an escapement control portion
64. The addresses of the stages 61 are sequentially ordered to facili-
tate their access in synchronism with row scanning by light spot 30 by a
page memory address control row counting register 65 (Figure 5). When
addressed, register 60 delivers a data word 62 along a divided data path
placing portion 63 in page memory address register 67 and portion 64 in
running escapement register 68.
REFERENCE ADDRESS AND ESCAPEMENT TRANSLATING TABLE MEMORY 70 (SEE FIGURE 4)
Translator 70 is a read only storage memory containing a
series of individually addressable multi-bit data words 71 each of which
is uniquely addressable by a symbol identifying code from page memory
57. Each data word 71 contains a first portion 72 which is a reference
address to font memory 92 and a second portion 73 which indicates the
total number of columnar segments 24 (Figure 2) that are required to
completely generate the symbol.
The data words 71 are individually addressable by the
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symbol representing output codes from page memory 57 as presented in address
register 75 in combination with one or more status bits 76 therein which
are preset to select a particular type font or printing mode. The status
bits 76 enable the selection of basically different data from font memory
92. If font memory 92 is provided with three different proportionally
spaced type styles, the selection of which type style will be employed is
made by the data output from font address and escapement table memory
device 70 as determined by status bits 76. All of the type fonts need not
be of the proportional spacing type, however. If it is desired to have a
fixed space type font, memory 70 is simply coded to identify the same
number of strokes for each character in the type font. Furthermore, if it
is desired to print writing lines extending the long dimension of a page, a
rotated font may be stored in font memory 92 and selected by status bits
76. The rotated font specif;es the contrast control pattern required to
produce symbols by segments that horizontally traverse the symbols.
CHARACTER GENER TING CIRCUITRY 58
A more detailed functional component breakdown of the character genera-
ting circuitry 58 is shown in Figure 5. Page memory 57 has an output data
path 74 to the address register 75 by which a symbol identification code is
input to the translator 70 as an address. The output path 80 of translator
70 is divided into two components, namely, a reference address path 81 that
is connected to write data word portion 72 in register 82, and a total
escapement value path 83 that is connected to write data word portion 73 in
total escapement register 84. When the value in running escapement register
68 is "zero", detection circuit 85 gates selective data path 86
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1 to pass the data word portion 73 from register 84 to remaining escapement
register 87 where it is applied along with the reference address portion 72
from register 82 delivered to font memory addressing subtraction logic 90
to produce a specific font memory address in address register 91 of a font
memory 92. If the data in running escapement register 68 is not detected
by circuit 85 to be "zero", then selective data path 86 passes it and not
the data from register 84 to register 87.
Figure 6 illustrates the organization of font memory 92 which stores a
plurality multibit data words or bit series 93 the bits 94 of which
identify either a light or dark spot. Each data word 93 is accessed by an
address applied to address register 91 (Figure 5) and defines the light/dark
contrast pattern necessary to generate a single columnar segment 24 of a
symbol such as 21 in Figure 2. As complete generation of each symbol re-
quires a plurality of column segments, a like plurality of data words 93 is
provided in font memory 92 thus forming an entire group 95 of data bits
which define the contrast pattern for the related symbol as correlated with
an appropriate raster pattern. Conveniently the addresses of adjacent data
words 93 correspond to adjacent columnar segments of the symbol and thus
differ by the constant "one". It will be recognized by those skilled in
the art that various compression coding techniques could be employed
instead of bit for bit light/dark coding of the word 93 as herein shown.
The scan contrast pattern from font memory 92 addressed by register 91
is delivered on output lines 96 to output control serializing buffer 97.
The individual bits of the contrast pattern loaded into output buffer 97
are gated to
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l modulator 38 by the clock pulses 53.
The running escapement count applied to subtraction logic 95 is also
applied to an input or record-in buffer 69 of the page memory address
control register 60 via data lines 88. A different portion of input buffer
69 receives a page memory address from register 67 updated if necessary by
update summing logic 100. Whenever a detection circuit 101 determines the
value in register 68 to be "one" indicating production of the final scan
required for an individual symbol, update logic 100 is thereby enabled to
add a constant to the address in register 67 thereby deriving the address
in page memory 57 of the succeeding higher order symbol in that particular
writing line. Ordinarily, the constant added will be "one", however, for
reasons hereinafter developed in greater detail, printing of a rotated font
wherein writing lines extend along the long dimension of a page, is facili-
tated by making the number added by update logic 100 to be egual to the
number of characters positions in a writing line. This selective increment
is accomplished by control by data processor 56 of an increment to be added
as stored in an addend register 102. The information in buffer 69 is re-
corded into the stage 61 of register 60 addressed by the page memory address
control row counting register 65 as that stage corresponding to the row
associated with the page memory address recorded therein.
Row counting register 65 is incremented by counting logic 103 once for
each number of clock pulses 53 which represent the traversal by light spot
30 of the entire columnar segment allotted to a symbol 21. It is reset by
a signal generated when photodetector 52 receives light through continuous
clear space 54 at the end of grating 50. Thus, each stage of
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1 register 60 is successively addressed for read-out and write-in by row
counting register 65 operating in synchronism with the scanning travel of
light spot 30 (Figure 1).
_TA FLOW OPERATION
As each stage 61 of page memory address control register 60 is acce-
ssed by counting register 65, its contained data word 62 is divided and
presented to registers 67 and 68. Portion 63 in register 67 is read as an
address by page memory 57 and is also returned through update logic 100 to
the input buffer 69 as described above. If "zero" is detected by circuitry
85, the escapement information contained in register 84 is simply trans-
ferred to register 87. Otherwise, the escapement information contained in
register 68 is passed through columnar segment decrementing logic 104 to
register 87. The same information is passed to the input buffer 69
of the page memory address control register 60. Each address stored in a
stage 61 of register 60 will thus be presented at address register 67 for
the number of times required to generate the raster strokes for display of
its identified symbol as determined from information retained in trans-
lating memory 70. When a given symbol in a given writing line has been
completely displayed, as detected by the "one" in register 68 by circuitry
101, the page memory address is incremented by update logic 100 so that
during the succeeding scan a new symbol code will be derived on output data
path 74 from page memory 57. During the succeeding scan, a "zero" will be
presented to register 68 which will be detected by circuit 85 to enable the
new total escapement derived from tanslating memory 70 to be presented to
subtraction logic 90 and to be stored in register 60 along with the associated
page memory address.
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1 PAGE MEMORY 57
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Page memory 57 can be implemented by any of several well known high
speed memory techniques. The memory stores a plurality of data words that
are individually accessible by specifying one of a series of sequential
addresses. The data word at a specific address will be a coded represent-
ation of a alphabetic or numeric character identified as being either upper
or lower case and indicating whether or not the character is to be under-
scored. In addition, the character encoded may be a "space" character (SP)
of either of two or more widths (number of columnar segments 24) when pro-
portional spacing is desired. The page memory 57 is loaded by the data
processor 56 in accordance with a formatting program such that successive
addresses are allotted to successive characters in the text. For example,
for addresses beginning with "address 20", the following text would be
stored thusly:
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 3~3 39
T h e SP q u i c k SP b r o w n SP f o x SP
In order to format the text into rows for presentation on a page, "end
of row" codes ER are inserted by the data processor 56 and the next succeed-
ing address is recorded as the initial address in the stage 61 of page
memory access control register 60 corresponding to the next succeeding row.
For example: assume that the "line 6" of a page began at "address 20", and
that the line was to end after the word "brown", the page memory 57 would
be loaded by the data processor 56 as follows:
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1 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
T h e SP q u i c k SP b r o w n ER f o x SP
In this example, the stage 61 of page memory access control register
60 corresponding to "line 7" would be initialized to show "address 36". As
hereinafter explained, a special "End of Scan" code ES makes it unneces-
sary to insert separate space codes for the left margin. One example of
similar techniques employed in loading a page memory like 57 is found in
U. S. Patent 3,654,611. In addition, those skilled in the art will rec-
ognize that assembling of texts into the format thus illustrated is well
within the current skill of the data processing arts.
The End of Row code detector 105 (Figure 5) is connected to inhibit
address incrementing by update logic 100. The page memory address con-
taining the ER code is simply repeatedly accessed during successive scans.
Translating memory 70 selects a "blank" data word from font memory 92 in
response to the ER code.
If desired, End of Page logic 106 can monitor the codes delivered to
register 75. If an entire scan by light spot 30 of a columnar segment 24
is accomplished with no symbol identifying codes being delivered to
register 75, End of Page logic 106 overrides control of modulator 38 to
print "white" for the remaining scans of the page. During this time page
memory 57 and page memory access control register 60 are free to be loaded
by processor 56 with text of the next page to be printed. Alternately, the
End of Page function can be implemented by an End of Page symbol code
stored in Page Memory 57.
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1 END OF SCAN CONTROL
In addition to the special control character referred to above as ER
(End of Row), I provide an End of Scan control code ES that also is loaded
by the data processor 56 into page memory 57. The ES code designates that
for the remainder of the immediate scan of light spot 30 only blank space
is to be printed. The special ES code is normally recorded in the page
memory 57 in the first several addresses of the page memory 57 to define
the left margin and following the last line of text. For example, if a
page was to have a 9 space wide left margin and a last line of text beg-
inning at page memory "address 250", the page memory 57 would be recorded
thusly:
1 2 3 4 5 6 7 8 9
ES ES ES ES ES ES ES ES ES
250 251 252 253 254 255 256 257 258 259 260 261 262 263
t o SP t h e SP a i d SP o f SP
264 265 266 267 268 269 270 271 272 273 274 275 276
t h e i r SP p a r t y . ER
; 277 278 279 280 281 282 283 284 285 286 287 288 289
ES ES ES ES ES ES ES ES ES ES ES ES ES
Control register 60 is initialized in its stage 61 corresponding to "line
1" to "address 1"; in its stage 61 corresponding to the last line of text
to "address 250" and in its stage 61 corresponding to the line following
- the line of text to "address 277". The ES code is decoded as a blank
character of a given escapement, for example, four units width, and is
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1 recorded by the data processor 56 a sufficient number of times at the end
of the text to cover the entire unit width of the typing page at the end of
text. In addition to the decode thus mentioned by translating memory 70,
the ES code is detected by logic circuit 107 which sets latch 108 to inhibit
further operation of counting logic 103. Repeated cycles of page memory
access control register 60 thus repeatedly produce the page memory address
at register 67 that contains the ES code until counting address register 65
and latch 108 are reset by the scan completion signal from photodetector 52.
CYCLE CLOCK
In accordance with well known data processing techniques, the various
operations of my character generator are controlled in sequence by clock
circuitry 110, see Figure 7, that defines an 8 step operating cycle that is
produced during the time required for light spot 30 to traverse one symbol
segment. Clock circuitry 110 counts pulses 111 from a regulated oscillator,
not shown, so long as AN~ gate 122 is enabled by synchronizing latch 113.
Dot counter circuit 114 recelves scan indicating clock pulse train 53 and
emits an output to set latch 113 after counting a predetermined number of
pulses of train 53 equal to the length of scan for generating an individual
character segment. Clock circuitry 110 creates times T-l through T-8
sequentially in less time than occurs between outputs of counter 114. At
time T-8, latch 113 is reset to disable gate 112 until a new output is
received from dot counter 114.
Signals T-l through T-8 representing individual cycle times are
employed as gate signals to the data flow paths shown in Figure 5 to
; produce a cycle having the following
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1 operating sequence:
T-l Using the address in register 65, read from register 60 into
registers 67 and 68.
T-2 Using the address in register 67, read from page memory 57 into
register 75.
T-3 Using the address in register 75, read from translating memory 70
into registers 82 and 84.
T-4 Test register 68 for "zero", if register 68 is "zero" transfer
register 84 to register 87; if register 68 is not "zero", subtract
"one" and transfer it to register 87.
T-5 Test register 68 for "one" and test register 75 for ER, if register
68 is "one" and if register 75 does not contain ER, add a constant
to register 67 and transfer it to register 69, if register 87 is
not "one" or if register 75 contains ER, transfer register 67 to
register 69. Test register 75 for ES, if register 75 contains ES
set latch 108.
.; T-6 Subtract register 87 from register 82 and transfer difference to
register 91. Transfer register 87 to register 69.
T-7 Using register 91 as an address, read from font memory 92 to out-
put serializer buffer 97; using register 65 as address, write
register 69 into page memory address control register 60.
T-8 Test if latch 108 is set, if latch 108 is not set, add "one" to
register 65.
Preferably pipelining techniques are employed to allow overlap process-
ing of the data for several successive scans and thereby obtain faster
operation. The foregoing description
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1 adequately shows the operating principles of my invention without the added
complication of such state-of-the-art enhancement techniques.
HE,4DING MODIFICATION FOR ROTATED TYPE FONT
As shown in Figure 8, additional circuitry has been provided to update
summing circuitry 100 which updates the page memory address from register
67, see Figure 4. This circuitry enables the rotated font status, as
preset by an operator, to control the progression of addresses in page
memory 57. As described above, in normal printing the rotated font status
is not selected and the number "one" is delivered through AND circuit 120
for addition to register 67 upon the detection of a "one" in register 68
by circuitry 101. Where the rotated font status is selected, AND circuit
121 will be enabled to gate the number "81" to update summing circuitry 100
to be added to the address from register 67. The number 81 provides storage
of an 80 character line of text and an ES code. As shown in Figure 8, I
have elected to inhibit output of AND circuit 121 upon detection by logic
122 of the first row designated by counting address register 65, and instead
cause OR circuit 123 to enable AND circuit 120 to add "one" in all progress-
ions within the first line. As shown by the following example, this technique
enables me to dedicate the first rsw of rotated font printing, which normally
is a margin area anyway, to definition of completely blank columns thereby
effecting a considerable savings of storage area in page memory 57.
The example is illustrated in Figure 9 which shows a sample of a page
to be printed. Recall that the dot scan 24 occurs along a path 31 in the
direction of the long dimension of the page. It can be seen that a number
of scans providing
.
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the top margin of the page above the words "name", "address", "phone number"
are completely blank as are two lines between the words "name", and "John".
To avoid having to record character or size space or blank codes in the page
memory 57 corresponding to these completely blank lines, first 28 page memory
addresses corresponding to the 28 possible lines of text on the page are
recorded with ES if the line is to be blank and SP if the line ;s to contain
text. Having thus established a certain vertical format by the recording of
ES and SP codes, the text to be printed is then recorded in right reading
fashion in successive page memory addresses exactly as was done in "the quick
brown fox" example set forth above with the one exception that the initial
addresses recorded in page memory access control register 60 are those add-
resses in which the characters and spaces making up the first line of text
"name", "address", "phone number" are recorded. For example, in the stage 61
of page memory access control register 60, corresponding to row 81 page
memory "address 30" will be recorded as containing the initial character to
be accessed when scanning row 81. The page memory 57 for this example would
be recorded as follows:
1 2 3 4 5 6 7 8 etc 28 29 30 31 32 33 - - - -
ES ES ES ES SP ES ES SP ... ES ES N A M E
- - - - 110 111 112 113 114
ES J o h n
'~
Note that page memory "address 111" containing the J of John which falls
directly beneath the N of NAME differs from the
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l address containing the N by the number 81, which is the nu~ber of character
positions along the long dimension of the page - plus one to allow recording
of an ES code.
Considering now the sequence of events involved in printing the page
shown in Figure 9, with initial scanning, page memory address control count-
ing register 65 will specify that the address contained in the stage 61
corresponding to row l be presented to register 67 thereby addressing page
memory address l which contains an ES code. As stated above, the ES code
inhibits further counting by logic 103 until reset by a scan complete sig-
nal. Thus, the ES code will be repeatedly presented to cause blank printing
for a plurality of strokes as encoded therewith in translating memory 70.
Upon completion of the number of scans associated with the ES code, detection
circuit lOl will detect a "one" in register 68 and through the logic shown
in Figure 8 the first row detection from counting register 65 will cause
AND circuit 120 to add "one" to the page memory "address l" thus bringing
the address associated with the first row to "address 2". Again, the ES
code has been recorded in address 2 and the same sequence of events will be
repeated. When the address in register 60 associated with the first row has
been advanced to contain page memory "address 5," a space code SP will be
derived from page memory 57. While the space code will itself produce no
printed output, it does not function to inhibit counting logic 103 as did
the ES code. Thus counting register 65 is allowed to successively bring out
each of the data words contained in its stages 61 which, it will be recalled,
were initialized to specify in sequence those page memory addresses associated
with the first line of text to be printed.
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The initial sequence of this example will begin at "address 5", proceed
to "address 109" which was initially recorded in the stage 61 corresponding
to row 2, and continue down to "address 29" which was initially recorded in
the stage 61 corresponding to row 82. As the final stroke of the printing
of the first line of text is occurring, circuit 101 will detect "one" at
each of the stages 61 of register 60. When the stage 61 associated with the
first row is detected, update summing circuitry 100 will be governed by AND
circuit 120 to simply add "one" to the previous address which was 5 and
thereby derive "address 6" as the updated address. When, however, any other
stage 61 is being processed such as that associated with row 78, AND circuit
121 will be satisfied, thereby gating the number 81 to update summ;ng cir-
cuitry 100 to change "address 33" to "address 114" thereby specifying the
address in page memory 57 containing the letter N which is to appear below
the letter E. During the next succeeding scan, the first row stage of reg-
ister 60 will call out address 6 of the page memory 57 which again contains
an ES code. Counting logic 103 will be inhibited and a row of white will be
printed. The same sequence will occur when the first row stage of register
60 has advanced one to specify page memory address 7. Only when the first
row stage 61 of register 60 has advanced to page memory "address 8" will the
advanced or updated text containing addresses in the remaining stages of
20 register 60 be presented to the page memory 57.
PREFERRED MODIFICATION
While the total number of scans required for a given character can be
stored in memory 70 and processed repeatedly through page memory access
control register 60, I prefer to
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1 employ a two bit or four state counter 124 as shown in Figure 10, to supple-
ment the number provided by registers 84 and 68 such that these registers
nee~ only store a number equal to 1/4 of the total number of required scans.
Character widths thus are specified in terms of a number of space units,
each space unit being equal in width to four raster scans or columnar seg-
ments 24. The principles of my invention as described above in connection
with Figure 5 remain the same with the only difference being that four state
counter 124 is interpreted along with the contents of register 68 by "zero"
detection logic circuit 85 and "one" detection logic circuit 101 and decre-
menting circuit 104 only decrements the contents of register 68 once for
each full four-step cycle of counter 124. Counter 124 is incremented upon
the occurrence of a stroke completion signal generated by photodetector 52
when it receives continuous light through grating portion 54. The stroke
completion signal also operates to reset counting address register 65 to
again specify the initial stage 61 of page memory access control register 60.
Having thus described both the principles employed in the character
generator of my invention and some preferred illustrative implementations
thereof, it will be understood that various modifications, additions, and
deletions can be made to the specific materials disclosed without departing
from the inventive concept as limited only by the appended claims.
20
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,
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