Note: Descriptions are shown in the official language in which they were submitted.
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, The invention relates to electrical circuit logic elements, in
particular a bipolar gate for LSI embodiment, in which there are at least
two Schottky diodes which fulfill different functions in a semiconductor
body.
A known, high-speed bipolar gate logic element for LSI circuits
employs various Schottky-diodes, each connected to a base electrode of a
common pnp-transistor serving as a current source, and a Schottky trans-
istor being provided, as described in Electronics, December 1974 pages 36
and 38. The production of this so-called C3L,gate (C3L = Complementary
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Constant Current Logic) is difficult, inasmuch as two mutually different
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Schottky diode types must be formed by technological steps, together with
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';; a pnp-transistor. The need for different types of Schottky dlode leads to
the use of complex production processes in order to ensure a reasonable
yield and fair compatibility. On the other hand the pnp-transistor which
serves as a current source makes still higher demands on all the process
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steps leading to this component, which results in a smaller yield being
, obtainable. In addition the pnp-transistor necessitates an additional
~- capacitance, and in the case of poor amplification high base currents may
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; flow which do not participate in any switch-over operation. Thus the
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;i 20 presence of a pnp-transistor leads to a loss of switching time, and of power
when operating.
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One object of the present invention is to provide a high-speed
; bipolar gate with a simple production process, high packing density, and
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good amplification.
~ According to the invention there is provided a semiconductor logic
- element, comprising a bipolar transistor and at least two Schottky diodes,
~ the two Schottky diodes being produced side by side in regions of one type
A,"' "~'' Of conductivity on the surface of a semiconductor crystal in such a fashion
~ that the two Schottky diodes show different threshold voltages, characterized
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in that the Schottky diodes show different dopings of the semiconductor -
crystal beneath the Schottky contacts and in that the different dopings are
produced by means of ion implantation and by forming a thin, highly doped
layer which is thinner than the space-charge region at zero volts between a
metal Schottky contact and the semiconductor crystal.
A logic element constructed in accordance with the invention is
relatively simple to produce, and yet provides a good amplification, with
high packing density and a short switching time.
Preferably said diodes have mutually different doping levels pro-
duced by ion implantation. This causes a change in the threshold voltage -
of the various Schottky diodes, as described for example in "Applied Phys.
Letters,~ Vol. 24, No. 8, 1974, pages 369 to 371. The ion implantation
should produce a thin, highly doped layer having a thickness which is smaller
than the space charge zone existing between the metal electrode and the semi-
conductor body at a potential difference of zero volts. Doping with a
greater penetration depth than the space charge zone would lead to high
conduotion currents.
Advantageously, the Schottky diode metal electrodes consist of
coatings of titanium on the semiconductor body. `
The invention facilitates the production of a logic element, in
particular a bipolar gate for LSI circuits, which is simple to produce and
exhibits a high-speed switching behaviour with a high packing density. The
~ ~ technologically differing Schottky diodes may be formed by Schottky diodes
¦~ which differ in area and have a low threshold voltage, using identical
metallization technology. However, a change in the threshold voltage is
preferably obtained by using differing doping levels of the semiconductor
~ body, preferably with the aid of ion implantation. In addition the pnp-
¦~1 transistor required in the C3L_gate is replaced by a resistor, as a result
of which the switching
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behaviour is further improved.
The invention will now be described with reference to the draw-
ings, in which:-
Figure 1 is a circuit diagram illustrating a bipolar NAND-gate
with two inputs;
Figure 2 is a circuit dia6ram of a bipolar gate with multiple
outputs;
Figure 3 is a plan view of an exemplary construction of the part
surrounded by a broken line in Figure 2; and
Figure 4 is a cross-section on the line IV-IV shown in Figure 3.
In the embodiment shown in Figure 1, a first terminal of a first
Schottky diode 2 is connected in one direction to a first input 1, to block
when operating. A second input 3 is connected to a first input of a second
Schottky diode 4 which is likewise poled in the blocking direction with
respect to the input 3. The second terminal of the terminal of the first
Schottky d$ode 2 is connected to one terminal of a resistor 5, to a first
terminal of a third Schottky diode 6 that is poled in the opposite direction
to the diodes 2 and 4, and to the base a transistor 7, and to the second ter-
minal of the second Schottky diode 4. The other terminal of the resistor 5
carries a reference potential Ucc, which may be at earth. The second ter-
minal of the third Schottky diode 6 is connected to the collector of the
transistor 7 and to an output 8.
When operating, the inputs 1 and 3 carry an input voltage UE~ and
there is a voltage drop UDL across each of the Schottky diodes 2 and
4, whereas there is a voltage drop UDc across the different Schottky
diode 6. The emitter of the transistor 7 is maintained at a reference
potential UEE which may be earth. An output voltage UA is presented
to the output 8. The ga~e illustrated in Figure 1 fulfills two logic
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functions:
The resistor 5 together with the two Schottky diodes 2 and 4,
form an AND-diode link. The transistor 7 and the Schottky diode 6
together form an inverter, with means for prevention of saturation.
In order to ensure a satisfactory function of a plurality of
gates of this type (see Figure 2) in the case of large combinations of
such logic circuits, the relationship between the diode voltages should
satisfy the expression UDL<UDc. This can be achieved by means
of different threshold value voltages, and/or different internal
resistances for the Schottky diodes 2 and 4, compared with 6. This
can be achieved by altering the diode surface area or the diode thresh-
old value by means of differing doping levels. Preferably we have:-
UBC>UDC>UDL
where UBc = base-collector threshold value of the transistor 7. -
A voltage ~U = UDc = UDL, corresponds to the logic voltage
range whereas Us = UB ~ UDc determines the degree of the saturation.
As the switching time is considerably impaired in the case of
saturation of the transistor 7, it is preferable to adhere to a voltage
difference Us. In addition it is necessary to adhere to a corresponding
voltage range ~U to ensure that the gate is free from interference.
As will be shown in the following, Schottky diodes with a
low threshold value are particularly advantageous.
For the values UBc = 0.7 V; Us = 0-3 Vj and ~U = 0.1 V, we
DC UBc ~ Us = 4 V, and UDL = UD - ~U = 0 3 V
Thus the threshold value voltages of the Schottky diodes 2, 4
and 6 should if possible lie below 0.4 V. This can be achieved if
the Schottky contacts consist of coatings of mutually differing area,
formed on the semiconductor body, by titanium, and allowing for the
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current density in the components.
A bipolar gate with a transistor 7, possessing an emitter of
length 8 ~m, two titanium-Schottky diodes 2 and 4 each having an area of
8 x 8 ~m, and a titanium-Schottky-diode 6 having an area of 16 x 16 ~m pro-
duces a voltage range ~U = 140 mV, with a speed-power-product A = 0.27 pJ.
~ere the transit time of the gate amounts to approximately 0. 7 ns.
In the case of oxide insulation (see Figure 4), and an emitter
size of approximately 4 x 8 ~m, a packing density of approximately 200
gates/mm can be achieved for gates each with three inputs.
Figure 2 illustrates the electric circuit of the bipolar gate
construction represented in Figure 3. A Schottky diode 24 is connected
in the blocking direction to an input 13. Three Schottky diodes 25,
26 and 27 are connected in parallel to respective outputs 35, 36 and
37 each diode being connected in the blocking direction to the preced-
ing output 8, to form input Schottky diodes (corresponding to the
Schottky diode 24) of separate succeeding gates. Schottky diodes
24, 25 and 26 are of mutually identical construction, whilst the
Schottky diode 6 possesses a Schottky contact of different area.
Figure 3 is a plan view of the fundamental components of
20 that part of the circuit shown in Figure 2 that is surrounded by a
broken line 38 and Figure 4 shows a cross-section on the line IV-IV
through Figure 3. A n conducting zone (buried layer) 41 is provided
in a p-conducting semiconductor body 40. Zones 42 and 43, which are n
conducting, lie on the zone 41. Also provided are p conducting
zones 44 and 45 and a n conducting zone 46. Oxide layers 50 serve
to insulate ad~acent components. The Schottky diode 27 consists of
a titanium-Schottky contact 51 and the zone 43. The Schottky diode
6 consists of a Schottky contact 52 and the zone 42. The transistor
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7 has an emitter contact 53. The Schottky contact s 51 and 52 possess '
mutually different surfaces areasO
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