Note: Descriptions are shown in the official language in which they were submitted.
¦ B-3017
1 10 62 35~3
¦ This invention relates to a data recording system, and
¦ more particularly to a recording system having flexibility to
¦ respond to the electrical state of devices connected to any one
¦ of a plurality of terminals either singularly or in groups of
¦ various combinations.
With the increase in size and complexity of modern
large industrial establishments it is becoming evermore essential
to provide administrative, engineering, maintenance and
statistical information regarding the electrical state of
various devices functioning in the system. Typically, the
electrical devices may be detectors responsive to the opened
'and closed position of valves in a complex piping system of a
chemical processing plant. Such electrical devLces may also
respond to the amount of telephone service used by a customer
or group of customers, that is, the precise time of each
telephone usage, whether the call was incoming or outgoing, as
~;¦ well as various other statistical information regarding telephon
service. In yet another example showing the complete flexibilit
of the present invention is the monitoring of electrical devices
' ~20 ¦ associated with parking spaces in a group of parking lots to
¦ monitor when such space is filled, how long each space was
filled and the time when each space is vacated. Changes in the
electrical state of the devices in each of the above examples
~may be translated into a recording of events, measurement of
'i`~!~`' ~ 25 real or elapsed time, preprocessing and formating the data and
j then providing a tape or a hard copy of the results.
1 .
-2-
- . . -..... - -,, ... -,.-
... .. . . .
- .~ .
. ' ' , ~ ' - . ' ~ ' ~ ' . : :
~062350
For purposes of explanation, consider the use of the
invention in the telecommunications industry where it has been
quite common to provide at a telephone central office traffic
monitoring equipment. This equipment usually consists of
traffic registers and counters (peg count meters, etc.) pro-
viding facilities for obtaining information about all call busy
attempts, group busy, partial digits, traffic usage, position --
disconnect and answering time registration as well as other
miscellaneous data on the various circuits in the office. This
equipment is usually mounted in relay racks because of its
bulk and size and provides individual line indications relative
~ to an associated circuit. Usually no recordings of the figures
-~ on the various meters and counters are included, however,
occasionally facilities for photographing the information are
provided. More contemporary telecommunications systems are
equipped with devices known as traffic usage recorders to pro-
¦ vide traffic data by means of a switch count. Circuit terminals
are scanned at predetermined intervals and those found busy are
recorded on registers for the various circuit groups with
busy conditions accumulated at the end of an hour or other pre-
determined period to indicate traffic load that was carried.
;j Telephone customers are served by a variety of types
of central offices, that is, step-by-step, cross bar, electronic,
;,, etc., and it is impractical to provide a dedicated path for ~-
~ .
every originating equipment line, through the switching machine,
to every possible termination (or telephone number) served by
a particular central o.ffice. Realizing the impracticality of
. ~.?i
,~ ' ' ` ~"~,
-; - 3 -
~ ' . " : .
.~ .
f " . . . . , . .; . ~, . .. . . .
0 6235~D B-3017
a dedicated path for every originating line, most central offices
are designed to bring customers into the office in line groups,
whereby a group of approximately two hundred customers are
served by twenty or less originating switches operating on
S l "paths" or "links" to switch calls to the office. The number
o~ customers that can be served by this form of concentration is
¦ a function of the number of calls placed by the two hundred
¦ customers and the "holding time", or length of a call. In the
¦ telephone industry, "calling rate and holding time per call" is
1 translated into "hundred call seconds (CCS~ usage" or the usage
stated in hundreds of call seconds. Since calling habits vary
widely between customers, and the times of their calling varies
by the hours in each day, it is very desirable to effect a
"balance" within each group and between line groups to obtain an
,i 15 even flow of calls throughout the office throughout the day.
The utopian situation would be to have the same number of calls
2 handled by each line group for every twenty-four hour period.
This would permit serving the maximum number of customers with
the minimum capital expenditure for switching equipment.
~? 20 In actual practice, telephone service customers are
assigned to line groups by types of services, that is, coin
telephone, individual lines, two party lines, four party lines,
business, and other types of telephone service. Traffic
engineers in the telephone industry have established tables
based on theories that are used to state the maximum number of
CCS usage that can be assigned to a group of lines. These
theories assume a CCS usage value for each of the types of teleP
'.~
-4-
,. . .
.. . . .
. : - - ,. ,
~ B-3017
I 10623S0
I . . .
¦service provided, Lines are then assigned so that a line group
¦ is filled up to the CCS usage capacity for a particular central
¦ office. Theoretically, these maximums are based on the busy
hour of the busy day of a busy season~ This theoretical approach
to office loading and balancing works well when labor and equip-
ment are relatively inexpensive, office loads are not exceptionall
heavy and the calling rates are low. With new communications
services now being offered such as ~IATS, data transmission,
computer access lines, teletype services, in addition to others,
the old "average" calling rate and holting times are fast
becoming obsolete. The telephone industry spends many man hours,
dollars and material attempting to "balance" calling loads
through the various switching machines.
. With the present state of the art of recording systems
; 15 as previously outlined, there is no practical economical way to
; determine the actual calling rate and holding time of each
lndividual line in a line group Assuming this is possible,
there is still no way to correlate the number of calls and the
elapsed time per call with the actual time of day the calls are
~;~ 20 made. A feature of the present invention is to provide a data
recording system that translates the elec~rical state of a
device into a recording of a measurement of real or elapsed time.
Further, a feature of the present invention is to provide a data
recording system wherein the electrical state of a device
,! 25 connected to an individual terminal is translated into a recordin~
of events. Still another feature of the present invention is to
providc a data recordinu system for preprocessing ~nd formating
'i
r
B 3017
1 106Z350
data related to the electrical state of a device connected to a
l terminal and provide a tape or a hard copy of the results.
¦ Again specifically referring to the telecommunications
l industry, the data recording system of the present invention
¦ provides data identifying the line number of an individual
¦ customer connected to the system and shows the total number of
I calls on the individual line. This is the total number of calls
¦ both incoming and outgoing. In addition, the system provides
data for the total number of incoming calls received by an
¦ individual customer and also the total number of outgoing calls
.~ made by the customer. Additional data provided by the system of
i the present invention details the number of times a customer
waited more than three seconds to receive a dial tone when
attempting to place an outgoing call. Also Drovided is data
indicating the total time consumed on incomi~g calls for each
individual line and the total time consumed on originating, or
outgoing calls by each line number. These two total time
measurements are given in tenths of a second to conform to
- standard CCS usage studies. In addition, the data recording
system of the present invention provides a record of the total
number of seconds that an individual customer waited for a
` dial tone during a particular period under study. The above
information is of ~reat value in load balancing and line
administration.
Another important feature of the present invention
is the flexibility of the data recording system. For example,
in the telecommunications industry the present invention can
.,
~ -6-
.. . . ~,.
' ' - ~
~' ' - : . . ,
~-3017
I 10 62 350
¦ be adapted to provide data on calls to service code trunks, such
¦ as information calls, repair service calls, and other type
¦ service calls. This information is most beneficial for making a
l charge for placing a call for directory assistance. Data
¦ provided by the system of the present invention permits billing
¦ customers on a per call or CCS usage basis. Further, alarms
¦ can be implemented or printouts made of customers who tie up
I equipment by leaving an open receiver. In the area of equipment
- maintenance, the system can be programmed to alarm when a
particular switch in a line group fails to operate in sequence.
It should be understood, however, that the data
recording system of the present invention is equally useful in
other industries requiring counting and timing of events, that is
valve openings and closings, electrical switching operation,
night watchmen check-in stations and reports from specific
~ ~ stations in an industrial complex.
,:,, ~ O_~;c~0~ ~0~ e.~ 0~
In accordance with~the present invention, a system for
scanning a plurality of wiring terminals, each having an
~dentifying address, to detect changes in the electrical state
at each of the terminals includes a central controller for
sequentially generating, at intervals, the identifying address
data of the wiring terminals to establish a scanning order. The
identifying address data is decoded into gate control voltages
~ that are individually applied to one of a plurality of scanner
?~ 25 gates. The number of scanner gates is equal in number to the
plurality of wiring terminals, with the gates connected to the
wiring terminals on a one-to-one basis and responsive into a
-,
. -7-
,
. . .
.
.
-
~ 06Z350
con~ ct il~ n~o~lc l~y .1 l~rc~lctcr~ c~l gatc control voltagc.
dctector responds to t11e electrical state on a wiring terminal
connected to a scanner gate in a conducting mode to generate
the terminal status signal.
In accordance with one aspect of the present invention
there is provi~ed a condition monitoring system for scanning
termlnal voltage levels on a plurality of terminals each
llaving an identifying address to detect changes in the
voltage lcvel at each of the terminals, comprising in
: 10 combination:
a central controller for repetitively generating group
identifying address codes in a prearranged order of the
terminals to establish a group scanning vrder and including
means for generating a control pulse,
a plurality of means for decoding the group identifying
address codes, each of said means for decoding responsive to
^ one group identifying address code and generating a gate
~ .
Il control voltage,
a plurality of scanner gates at least equal in number
f4 20 to the plurality of terminals, said gates connected to the
.~d1 terminals and enabled by a gate control voltage, said gates
driven into a conductive state by a terminal voltage level
- above a reference voltage,
. .
. ~ means responsive to the control pulse to apply a gate :~
~ control voltage to selected scanner gates to enable said
- :~ gates to respond to a terminal voltage above a reference
. ~ voltage, and
detector means responsive to the voltage level on the
. .~
terminals connected to the scanner gates in the conduction
~; 30 mode to generate a terminal status signal for each such
terminal.
~ ' '
.. ~j .
~062350
In .l~co~ o~o witll anothcr ;Isl~cct of thc l-rcscllt invcntion
thcrc is l)rovi~lcd ;l col~dition n~onitoring systcm for scanning
a voltage level on a plurality of terminals each having an
identifying address to detect changes in the voltage level
`~ of each of the terminals, comprising in combination:
a central controller for repetitively generating at
intervals the identifying address of the terminals to
establish a scanner order,
- means for decoding the generated ideDtifying address of
the terminals into gate control voltages,
a plurality of scanner switches at least equal in
number to the plurality of terminals, said switches connected
3 to the terminals on a one-to-one basis,
means connecting a reference voltage to each of said
~`~ switches for biasing the conducting mode of each switch
above the reference voltage applied thereto,
means responsive to the gate control voltages for
enabling at least one of said scanner switches to be switched
into the conducting mode,
means connected to each of said switches for applying a
;
j~ terminal voltage thereto as a switching voltage to cause an
enablet switch to change into the conducting mode in response
to a switching voltage above an applied reference voltage,
and
~`; detector means responsive to a voltage level at each of
. . . ~
the closed switches, and including means for generating a
terminal status code from each voltage level.
A more complete understanding o~ the invention ant its
atvantages will be apparent from the specification and claims
: 30 and from the accompanying drawings illustrative of the invention.-
;` ..~' ::
~ A ~ - 8a _
.~ :
,
,' . '- - ' . :
.. : . :
Rcfcrrillg to thc drawillgs
l'IGURI. 1 is a block ~iagram of a data recording system
of the prescnt invention for scanning the electrical state
on 512 terminals;
FIGURE 2 is a functional schematic of the system of
FIGURE 1 detailing the decoding logic for sequentially
scanning the 512 terminals in groups of eight;
FIGURE 3 is a logic diagram of a decoder/selector for
generating gate control voltages from address information;
FIGURE 4 is a schematic of the detector/controller of
FIGURE 1 for responding to the electrical states of up to
eight terminals and generating logic level signals to a central
controller for further processing; and
~ FIGURE 5 (appearing on the same sheet of drawings as
: FIGURE 1) is a schematic of one of thirty-two terminal gate
: circuit cards for sequentially scanning the 512 terminals in
groups of e~ght.
,
., :
!','
.i.,
::;. ' ' " '.
h
~,
. i ~
i A - 8b
.
.
.... . . . .. . . . ..
.. . . . . . .
Il 106Z350
¦ B-3017
Referring to the dra~7ings, FIGURE 1 is a block diagram
of a data recording system in accordance with the present
invention for monitoring the electrical state of 512 terminals
I connected by means of cables 10 to terminal gates. The entire
1 scanning system is under control of a central controller 12 havin~
a data recorder 14 coupled thereto. The data recorder 14 may be
a conventional teletypewriter with the capability of inputing
instructions to the controller 12 and printing out data when
performing as an ordinary typewriter by receiving character data
from the controller 12. Typically, the controller 12 may be a
minicomputer of the type marketed under the trade designation
Microdata 400/10 Computer.
Coupled to the controller 12 by means of a cable 16 is
a driver/receiver 18 that provides the proper electrical and
`~ 15 mechanical interface from the controller 12 to the terminals
` connected to the cable 10. Terminal address information
transferred from the controller 12 through the driver/receiver 18
is transmitted over an address bus 20 to decoder/selectors 22
and 24. The purpose of these circuits is to take the basic
address information on the bus 20 and actuate terminal gates
associated with a specific terminal or terminal group.
The decoder/selectors 22 and 24 are enabled by a
control signal on a line 26 from the output of a detector/
controller 28. The detector/controller 28 receives instructions
from the controller 12 through the driver/receiver 18 over a line
30 and transfers terminal status information from an answer bus
32 to the controller 12 through the receiver 18 over a line 34.
~` . .
_g_
. ; , .
. ' ' . ' '
,~'............... .
' ',
; B-3017
1 10 62350
¦ Address information rece~ved by the decoder/selectors
22 and 24 is decoded t`o generate an energizing voltage to one
or more terminal gates contained on the circuit cards 36.
I As illustrated in FIGURE l, each of the blocks identified with
¦ a reference numeral 36 contains sixteen terminal gates that when
¦ closed transmit the electrical state of the terminals connected
to the cable 10 to the detector/controller 28 over the answer
bus 32. By appropriate bias voltages and design of the terminal
gates 36, the electrical state of each terminal connected to the
cable 10 above or below a specified reference voltage will be
- indicated on the answer bus 32 by a lo~ic voltage level. The
terminal gates may be designed to detect voltages on the
terminals above or below a specific threshold, as desired. Thus,
the system is not limited to responding to only an on/off
condition at the terminals, but will respond to detect various
electrical states.
When monitoring the electrical state of 512 terminals
the system requires 512 terminal gates, typically arranged in
circuits of sixteen thereby requiring thirty-two circuit cards 36
The gates are unidirectional and function as the input circuit
to the system from the terminals bein8 scanned.
By means of the terminal gates changes in the levels
of voltage or current on the scanned terminals are translated
into useful data (represented by lo~ic voltage levels) by
coupling the data on the answer bus 32 to the controller 12 which
activates the data recorder 14 to provide hard copy readouts in
any desired format.
'~,i, .
? -lo-
,
.. .. ..
- - - :. ~ -
... . . . . . . . ~ .
¦ B-3017
` I 106Z350
. . . .
When applied to the telecommunications industry, the
voltage levels across a customer's line are detected to monitor
the line usage. Depending on the type of usage, that is,
incoming or outgoing, and also the progress of the call, the
Yarious terminals associated with a particular line have different
voltages~ These voltage differences are used to detect the vari-
ous events that occur for each part of each type of call thereby
making it possible by periodically scanning the terminals of a
customer's line to record eyents taking place on the line.
Referring to FIGURE 2, there is shown a functional
schematic of the block diagram o FIGURE 1 where address infor-
mation from the controller 12 is received on a cable 16. To
address one or more of the terminals connected to the cable 10,
~' the controller 12 outputs an address of six data bits, with each
~ 15 data bit individually connected to one of the inverters 38-43
`~ through resLstor networks. An inverter 44 provides a common
address channel from the controller 12. Each of the resistor
~ networks is identical and comprises a resistor 46 connected to a
-~ ~oltage source in series with a resistor 48 connected to ground.
The inverters 38-43 with the associated resistor network are
collectively part of a driver/receiver 18.
Assume that the terminals connected to the cable 10
;~ are to be interrogated in groups of eight, of the six data bit
address provided by the controller 12, the first four bits are
decoded to identify one terminal gate group of sixteen, that is,
one of the circuit cards 36. m e fifth bit identiies a
,~ 1 selector g associ~ted wich either the decoder/selector 22
,., -11-
~,, , , . , , , . . : . . . . .:
- , , . , , .. ~ .
, . . . . . . . . .
.: - : . . .: . ; : .
¦ B-3017
1 ~062350 .
or the decoder/selector 24. The last bit enables eight of the
texminal gates of each group of sixteen terminal gates on one
.¦ of the circuit cards 36, that is, the "A" or "B" half,
¦ The first four address data bits appear at the output
¦ terminals of the inverters 38-41, respectively, and are applied
directly to terminals of group selector registers 50 and 52. The
group selector registers 50 and 52 comprise, respectively, parts
. of the decoder/selectors 22 and 24. The address bit input to the
inverter 42 is also directly coupled to the group selector
register 50. This bit also is input to an in~erter 54 having an
output connected to the group selector register 52,
. The sixth address bit applied to the inverter 43 is .
~ coupled to the input of an inverter 56 and a NAND gate 58. m e .
. output of the inverter 56 is connected to a NAND gate 60. The .
15 NAND gates 58 and 60 enable either the terminal gates of group A .
3: or the terminal gates of group B on one of the circuit cards 36..ii. The output of the NAND gate 58 is connected to control
.~ gates 64 as representative of gates for controlling the terminalgates of group B for each circuit card 36. The NAND gate 60
hss an output connected to one input of control gates 66 as
y ~ representative of gates for controlling the terminal gates of
. group A for each of the circuit cards 36. That is, there is one
~:: control gate 64 and one control gate 66 for each of the circuit
A,~; ' ~ cards 36 for a total of thirty-two control gates 64 and thirty- twO
control gates 66. Only the control gates 64 and 66 for two of
~: the circuit cards 36 have been illustrated in FIGURE 2 to
8 implify the drawings.
-12-
. ~ . - . .
B-3017
I 106Z350
¦ Each of the control gates 64 and 66 for one of the
¦ circuit cards 36 connects to one output terminal of either the
¦ group selector register 50 or the group selector register 52.
¦ For a system utilizing thirty-two circuit cards 36 the first
¦ sixteen of such circuit cards are connected to output terminals
¦ of the selector register 50 and the circuit cards 16-31 are
: ¦ identified with the selector register 52.
¦ To decode address information generated by the
¦ controller 12, the first five bits are applied to the group
I selector registers 50 and 52 to set one of these registers to
:: ¦ provide a terminal gate voltage on one of the thirty-two output
terminals. As an example, assume that the group selector
~ ¦ register 52 provides a terminal gate voltage on the line 68
¦ connected to one input terminal of control gates 64 and 66 for a
¦ selected circuit card 36. The next code bit, as inverted by the
inverter 43, provides a control pulse at the output of either the .
. NAND gate 58 or the NAND gate 60. For the example previously
.$ considered, if the NAND gate 58 provides the control pulse, the
~: control gate 64 connected to the l~ne 68 is enabled to supply
; ~ 2 on a control line 70 the terminal gate voltage to the terminalgates of group B of the circuit card. This control pulse enables
the terminal gates in the selected group to respond to the :
electrical state of the group of eight terminals connected to
the cable 10. The group B tenminal gates associated with the
twenty-fourth terminal of the group selector re~ister 52 are
~;~ connected to the terminals No. 392-399 which are interro~ated
~, by providing a control voltage on the line 70.
. . '
. -13-
' 1 . . . - .
: . . , . . : .
. .
¦ B-3017
I ~062350
I
¦ Referring to FIGURE 3, the group selector register 50
¦ is sho-~n coupled to a complete array of control gates for scannin
¦ terminals identified with sixteen of the thirty-two circuit
¦ cards 36. Terminals A, B, C, D, Gl and G2 are connected as shown
¦ in FIGURE 2 to set the register to provide a tenminal gate
voltage on one of the sixteen output ter~inals. Each of the
sixteen output terminals is connected to one control gate 64
and one control gate 66. The first terminal of the register 50
connects to one input of gate 64-1 and one input of gate 66-1.
The second terminal of the selector re~ister 50 connects to the
; ¦ gates 64-2 and 66-2 and the remaining terminals of the register
; ¦ are similarly connected. The second input terminal of each of
; ¦ the control gates 64 is interconnected to a line 72 from the
¦ output of the NAND gate 58. For the control~gates 66, the second
., 15 ¦ input terminal is interconnected to a line 74 tied to the output
. ¦ terminal of the NAND gate 60. The output tenminal of each of
l the control gates 66 and the interconnected control gate 64
; ¦ connects to one of the circuit-cards 36 for controlling the
sixteen terminal gates on each card in groups of eight.
A circuit identical to that shown in FIGURE 3 is
pro~ided for the second selector group wherein the group selector
register 52 has sixteen output terminals each connected to one
terminal of a control gate 56 and one terminal of a control
gate 64. Again, each of the interconnected control gates 66
2S and control gates 64 has an output terminal connected to one -
of the circuit cards 36 to control the sixteen terminal gates in
~,~ I groupe of e t. ¦
s .,
~ -14-
'J.,,...... , ......... , , . .
',- - ' ': ' ' ' :. ' ' ' ' ~ .- . '
. ~
-:
~ B-3017
I 1062350
Referring again to FIGUP~ 2, closing a group of
terminal gates within one of the circuit cards 36 connects
selected terminals at the end of the cable 10 to the detector/
I controller 28. The electrical state on the selected terminals
¦ is converted to a logic level signal appearing on the cable 76.
~ Only three of the eight lines of the cable 76 are shown in
-~ FIGURE 2. It will be understood that when the terminals are
selected in groups of eight, there will be eight lines from
each A and B section of the circuit card 36.
The logic level signals on each line of the answer bus
32 are connected to the noninverting input terminal of one of the
gate comparator amplifiers 78 of the detector/controller 28.
The inverting input terminal to all the comparator amplifiers 78
is connected to a positive reference voltage through a resistance
,~ 15 divider including resistors 80 and 82. Each noninverting
, input terminal of the comparator amplifiers 78 is also connected
? to a positive supply through a resistor 84 and coupled to ground
through a diode 86.
Referring to FIGURE 4, there is shown a schematic
,~ 20 of the complete array of gate comparator amplifiers 78 for
-~ processing electrical state signals for eight terminals
simultaneously, Each of the amplifiers 78 of the array has a
s~ noninverting input terminal connected to one of the lines
of the answer bus 32. The output terminal of each of the
amplifiers 78 is interconnected throu~h a resistor 88 to
the positive reference supply connected to the res~stor 88 and
is individually connected to the-inputs of one of ei~ht Suffer
~, .
; -lS-
~' - .
,~ . . . . .
, .. . . . . .
~; B-3017
1 106Z350
l drivers 90 as part of the driver/receiver 18. These drivers do
¦ not invert the output of the amplifier 78, but provide proper
¦ impedance termination to couple to the controller 12.
¦ Whene~er one of the detector comparator amplifiers 78
¦ does not receive a true response from one of the terminal gates,
its output remains high and the interconnected driver 90 provides
a logic high voltage on the cable 16 to the controller 12. A
true response signal from the terminal gate causes a negatiYe
voltage to overcome the positive supply on the noninverting input
~ 10 term~nal of the amplifier 78 and the amplifier switches to its
.3 second logic state. This results in a logic low voltage, or
true signal, coupled through the identified driver 90 to the
f controller 12.
f Referring to FIGU~E 5, there is shown a schematic of
,~ 15 one of the circuit cards 36 for simultaneously scanning eight
of the tenminals connected to the cable 10. ~wo identical
circuits are~ provided in each of the circuit cards 36 and in
FIGURE 5 the circuits are identified as group A and group B.
Each circuit consists of eight high impedance level detectors and
one enable gate controlling all eight detectors. Each of the
level detectors comprises a transistor 92 coupled to the negative
terminal of a power supply through a divider network of resistors
94 and 96. The terminal to be scanned by each of the transistors
92 is interconnected by means of the cable 10 to points 110.
An integrating capacitor 98 is coupled across the collector-base
electrode 3unction for each of the transistors. The gated output
for each detector is applied to one of the lines 76 ~FIGURE 2)
through a resistor 100 and an isolating diode 102.
~!
-~ " -16- .
~!
~.. ... .. . . " . . . . . . .. .. . .... . .. ... . ....... ... . .. ........ ... . .. . .. . ... . .. .
10623S0
Although only three transistor detectors are shown
for each of the terminal groups in FIGURE 5, it will be under-
stood that a circuit for a terminal group comprising eight
terminals to be scanned includes eight transistors 92 with the
associated circuitry including resistors 94 and 96, capacitor
98, resistor 100 and isolating diode 102.
To simu~taneously enable each of the detector tran-
sistors 92, a signal from the control gate 66 is applied to the
emitter electrode of a transistor 104 (group A) having a base
electrode connected to ground through a resistor 106. The
collector electrode of the transistor 104 is interconnected to
each of the collector electrodes of the transistors 92 through
a diode 108. For the circuit of group B, a signal from the
control gate 64 is applied to the emitter electrode of the tran-
' sistor 104 for that circuit group.
Each of the detector transistors 92 provides a two
' state output varying with the electrical state of the terminal
connected to the point 110. If the electrical state of this
terminal is above a reference voltage connected to the emitter
electrode of the transistor 92, the transistor is held in an
. ;
~, off condition because of a bit reverse bias on the base
electrode through the resistor 96. With the transistor 92 in
an off condition, no current flows through the resistor 100 and
` the scanned terminal is considered to be inactive.
If the electrical state of the terminal has a voltagelevel less than the reference applied to the emitter electrode
of the transistor 92, then the transistor begins to turn on.
,~,
.~ .
~ - 17 -
, i .
~ .
.: : - . . ~ . .
.. :, - , . .
.... : :
¦ B-3017
I . 1062350
I .
¦ As the transistor 92 begins to conduct a part of the voltage at
¦ the collector electrode is fed back to the base electrode
¦ through the integrating capacitor 98 for the purpose of slowing
¦ down the turn on time thereby inproving noise rejection. As
¦ the transistor 92 turns fully on, the junction of the capacitor 9
: ¦ and the resistor 98 is approximately at the reference voltage
¦ and current flows through the resistor 100 and the isolating
¦ diode 102 and the scanned terminal are considered to be in an
: ¦ active state. ~ach of the detector transistors 92 operates as
¦ described to check t~e electrical state of the terminal connected
¦ to the point 110.
. To activate each of the detector transistors 92 for
:'' transmitting the electrical state of the scanned terminal to the
controller 12, the transistor 104 in conJunction with the diode
108 gates the transistor output to the detector/controller 28
~ over the answer bus 32 by means of the lines of the cable 76. -
::1 In operation of the transistor 104, in a quiescence .
state this transistor is forward biased by a voltage from the .
` gate 66 for group A or gate 64 for group B through the resistor
106. The output of a voltage divider, composed of resistors 112
~ and 114 and the diodes 108, is clamped to the voltage at the
3;~ emitter electrode of the transistor 104. Any of the detector
transistors 92 that are conducting produces a current through the
,~ resistor 100; however, no current will flow through the diode 102
~?~ 25 since the junction of the resistor 100 and the diode 102 is
clamped to the voltage at the emitter electrode of the transistor
104 through the diode 108. .
,~' . .
:~ . .
~ . -18-
~''
~: .~ . . . . ...
.
~ B-3017
1 1062350
To gate the detector transistors 92 to their respective
¦ lines of the cable 76, the transistor 104 is turned off and all
¦ the diodes 108 are reverse biased by a negative voltage from the
¦ divider of resistors 112 and 114. A current flowing through any
S ¦ of the resistors 100 will forward bias the diode 102 and the
~: ¦ electrical state of the terminal at the point 110 will be coupled
to the detector controller 28. Thus, the detector transistors
92 are in an "on" or "off" condition as determined by the
electri~al state of the terminal connected to the point 110. .
, 10 Interrogating a detector transistor by turning off the
.t' transistor 104 does not affect its "on" or "off" condition and
":! ' hence does not affect any terminal connected to the points 110.
~, This provides effective isolation between external circuitry
and the data recorder system of the present invention.
In operation bf the system of the present invention,
:~ the controller 12 sequentially generates address information for
each of the terminals connected to the cable 10. This address
information is routed over the address bus 20 to the decoder/ .
selectors 22 and 24 and also to the detector/controller 28.
One of the decoder/selectors 22 or 24 is enabled by a particular
; : address to change the logic state of the output at the control
. ~ ~ gates 64 and 66 for a particular terminal of the group selector
registers 50 or 52. Either the control gate 64 or 66 is then
enabled by the data bit from the in~erter 43.
. `: 25 Depending on the gate 64 or 66 that is enabled, the
transistor 104 for either group A or group B of one of the
¦¦ clrcuit ca 36 turns off and any of the detector transistors 92
~, , . -19-
.
`1 . .` . - -
; A-3017
I ` ~062350
¦ that are conducting provides a current through the respective
I diode 102 to the associated line of the cable 76. This current
¦ is ~ated from the detector transistor 92 to the comparator
¦ amplifiers 78 of the detectorlcontroller 28 to provide an "active'
or "inactive" logic output signal to one of the driver gates 90
as part of the driver/receiver 18 The "active" or "inactive"
states of each of the terminals connected to the detector
transistors 92 when a transistor 104 is turned off will be
processed to the controller 12 wherein character data is
l generated to activate the data recorder 14 to provide a hard copy
of the status of each of the terminals connected to the cable lO.
- The sequential generation of address information by
the controller 12 continues such that each terminal is scanned
periodically, typically one scan for each one-tenth of a second.
~; 15 By periodically scanning the terminals the "active" or "inactive"
status information provided to the controller 12 also enables
the generation of time related data. That is, the length of
time a particular terminal was either in the "active" or
"inactive" state may be calculated by monitoring the length of
time the circuit was in one of its respective states.
Although the data recording system of the present
invention was described with emphasis on a telecommunications
application, it will be understood that the system is also
applicable to other industries.
While only one embodiment of the invention, together
¦¦ with modifi ions thereo~, hs6 been degcribed in detall herein
.
~ -20-
,,,1
`~, . . . , .,, ... . . , . .
, . ., ~ . . , ;
,
. . . ~ . .. ...
B-3017
1062350
and shown in the accompanying drawings, it will be evident that
various further modifications are possible without departing
from the scope of the invention.
What is claimed is:
. . .
