Note: Descriptions are shown in the official language in which they were submitted.
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Field of the Invention
This invention relates to control signalling of mini-
computer memories and more particularly to control signalling
to indicate the status of asynchronous memories in a mini-
computer.
Background of the Invention
In minicomputers, it is most desirable to have the
least amount of control lines possible between physically
separate circuit modules. In particular, there should be the
fewest signalling lines between asynchronous memory modules
and the devices they serve. Asynchronous memories are
memories which operate by their own timing signals and
independently of the remainder of the computer. Such
asynchronous memories provide greater flexibility in computer
design and operation since they do not have to have their
timing precoordinated with the time of the remainder of the
computer, such as is necessary with synchronous memories,
and allow the addition of (or subtraction of) memory modules
of different timings.
One of the significant problems with asynchronous memories
is that their operation must be coordinated at all time with
the operation of teh CPU and any I/O devices. This coordination
is most important since it is undesirable to have signals
being input into a ~emory or signals requesting data from a -
memory when the memory is operating on other data. For this
coordination function it is customary to provide a plurality
of different signal lines from each memory so that the status
of the memory can be determined. However, this requires a
separate signal line and separate singal for each state of
each memory module. The result leads to a large plurality of
signal lines between the CPU, data channel, and each memory.
This problem is made more acute when dual port memories are
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used. (Dual port memories can communicate equally via either
port. With such memories, two different memory modules may
be accessed through their ports simultaneously to save data
processing time). When such dual port memories are used, it is
desirable to have a single set of signals common to the same
corresponding port for each group of memory modules, rather
than separate signals for each separate module. Thus, there
is a desire for an efficient means of coordinating a memory
having a plurality of asynchronous memory modules with a data
channel and a CPU and using a single bidirectional bus for
both data and address so that the least amount of signals
and signal lines are used.
Summary of the Invention
An object of this invention is to provide a signal
control system for asynchronous memories having a plurality of
- memory modules and a single bidirectional bus for both address
and data from the CPU so that the least amount of signalling
lines are needed for the most efficient transfer of information.
Another object of this invention is to provide an
efficient system for a memory whereby the status of any memory
module is indicated by a signal being generated under different
mode conditions (e.g., read, write, increment and decrement)
along the same signal line.
Another object of this invention is the provision of a
control system whereby the status of the memory modules of
memory availability, acknowledgement of requests, the avail-
ability of data, and the acknowledgement of receipt of data is
all indicated over the same signal line.
Another object of this invention is to provide a control
system whereby all of the modules of the memory can be signaled
by the CPU and data channel through the same control system.
In one particular aspect the present invention provides
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an asynchronous memory system comprising a memory unit, a
memory control associated with said memory unit, receiving
means in said memory control for accepting mode control signals
from a unit external of the memory, indicative of read, write
and increment and decrement modes, means for producing a memory
signal responsive to each of the mode control signals, a single
path for transmitting all said memory control signals to said
unit external of the memory.
Brief_Description of the Drawings
Figure 1 is a block diagram illustrating the memories -
semiconductor and core, the CPU, the data channel processor,
and the I/O devices.
Figure lA is a block diagram showing part of the micro-
processor 12 in more detail.
Figures 2A and B are a detailed circuit diagram of the
invention.
Figs. 3-6 are flow charts illustrating the handshaking
signals.
Figs. 7-10 are timing diagrams illustrating the hand-
shaking signals. The arrows in the diagrams indicate that anedge of one signal triggers the edge of another signal.
Preferred Embodiment of the Invention
This invention relates to a controller for a memory in
a minicomputer. The memory, which will be described in some
detail hereinafter, may be any well-known memory, such as a core
memory, a semiconductor memory such as an MOS memory, or any
combination thereof. It is an asynchronous memory (i.e., a
memory, which has its own timing control independent of the
remaining parts of a minicomputer, such as the CP~ and datas
channel, and is comprised of a plurality of modules). Signals
generated by this control in the memory are referred to as
"handshaking" signals. The term "handshaking" indicates that
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there is a constant interchange of signals between the memory
modules and the CPU or the data channel. This back and forth
signalling determines the status of each memory module and
specifically its availability to access data, the availability
of data, and the receipt of data.
The module indicates when it is available to receive data
and when the data it holds is requested is available. The
first step in the operation of this system is that a chosen
module is checked to make sure that it is the particular memory
module that is to be accessed. The system, as shown in the
drawing, operates with a plurality of memory modules. Thus, it
is important that that module that is accessed by the data or
address be the desired memory module. A signal is then sent
from one of the I/Os or the CPU to start the selected module.
` If the memory is accessed and it is busy, the memory of this
system will indicate that it is busy and lock out the incoming
signals. If the module is not busy, it will respond by acknow--
ledging the request and thus indicate that it is available.
The CPU or data channel will then indicate that the data is on
a signal bus and is being sent to the module or the module will
indicate that it has data available for the CPU or I/0 or will
perform some other functions depending on the computer's
functional mode. This mode will also determine the meaning of
the signals. The modes may be, for example, read, write, in-
crement, decrement, read or write left byte, and read or write
right byte.
Fig. 1 illuitrates in block diagram the various data and
, control signal paths between the CPU, memory and data channel
including the I/0 devices.
As aforementioned, the menory is preferably asynchronous
consisting of a plurality of separate memory modules, each of
which are separately addressable. The memory may consist of any
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well-known type such as all semi-conductor modules or all core
modules or any combination thereof.
In the embodiment described herein, one of the memories ls
a semi-conductor memory 2 and the other, a core memory 6. The
semi-conductor memory 2, which may consist of a plurality of MOS
chips, is connected to a memory control 4. The memory control
4 generates the internal timing for the data flow into, within
and out of the memory 2, and also controls control signals into
and out of and within the memory 2. The operation of these
control signals will be more fully described hereinafter with
respect to a single memory module in the memory 2. A core
memory 6 and its memory control 8 are also shown in Fig. 1.
A central processing unit (CPU) 10, a data channel (I/O
microcontroller) 14, and I/O devices 16 and 18 are disclosed in
Fig. 1. CPU 10 may comprise a micro-processor 12, an accumulator
20, arithmetic logic unit (ALU) 22, multiplexer 24 and 36 an
instruction register 26, a memory data register 28, an address
register 30, a memory data gate 32, an I.O path gate 34.
Turning first to the CPU 10, the accumulator 20 is connected
via data paths 40 and 41 to the ALU 22. The ALU 22 performs
arithmetic functions in a manner well-known in the art while
the accumulator 20 stores the data to be processed by the ALU
22. The ~ultiplexer 24 receives the data from the ALU 22 via
data path 42. It may pass the data directly through, shift it
to the left (multiply by 2). shift it to the right (divide by
2), or interchange eight bits with the other eight bits in a
sixteen bit word. These are well-known functions whose purpose `
is to facilitate the processing of data.
The instruction register 26 receives instructions serially
along paths 43, 44 (memory bus), 45, 46 from one memory 2 and
along paths 48, 49, 45 and 46 from the other memory 6. The
instructions received by the instruction register 26 are input
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to the microcontroller 12 via data path 47. Information from
the memories 2 and 6 on paths 43, 44 (memory bus), 45, 46, and
48 is received via line 49 by the memory data register 28. The
memory data register 28 conveys this information via path 50
to the multiplexer 36. The multiplexer 36 passes this information
along paths 60 and 40 into the ALU 22. The address register
30 receives data from the multiplexer 24 along data path 52, 53,
54. The address regi~ter 30 inputs this data into the memories
2 and 6 along paths 55, 56, (I/0 bus) 51, 57, 44, and 43
(memory 2) and 55, 56, (I/0 bus), 51, 58, 49 and 48 (memory 6).
The memory data gate 32 receives data from the multiplexer 24
along path 52, 53, and 59. In a like manner the I/0 path gate
34 receives data from the multiplexer 24 along path 52 and 53.
The memory data gate 32 gates the received information via
paths 56. (I/0 bus) 51, 57, 44 and 43 (into one 1 memory 2)
and paths 56, (I/0 bus) 51, 58, 49 and 48 (into the other
memory 6). The output of the I/0 path gate 34 is conveyed in
a smaller manner along I/0 bus 51 and thence, in the same
manner a~ data from the memory gate 32 into the memories 2 and 6.
The tata paths between the memorie~ 2 and 6, the data
channel (I/0 microcontroller) 14, the I/Os 16 and 18, and the
CPU 10 and the control signal paths between the memories 2 and
6, the data channel I/Os 16 and 18 and the CPU 10 are shown in
Fig. 1. Thus, the memories 2 and 6 may receive their data from
a front panel 9 such as along path 46, (memory bus) 45, 44 and
43 (into memory 2). The memories 2 and 6 can receive such data
from the data register 28 through the multiplexer 36. ALU 22,
and memory data gate 32. Data may also be received from the
'. I/Os 16 and 18 along paths 61 and 62 respectively and into I/0
; 30 bus 51. The memories 2 and 6 can also have data when they are
, originally connected to the computer.
Now describing the signalling from and to the memories
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2 and 6: memory 2 receives a signal from memory control 4
along signal path 63 (this signal as well as the other control
signals are as many bits wide as may be needed, they usually
are between 2 and 24 bits wide). The control 4 also sends
signals along lines 64, 65 and 66 to an address register 67
in adder 68, and a data register 69, respectively. Basically
the function of these three units are as follows: The I/0
devices 16 and 18 provide data along paths 61 and 62,
respectively and then paths 51 and 70 into a multiplexer 71.
The multiplexer 71 conveys this information via path 72, data
register 69, path 73, adder 68, path 43 into memory 2.
Information from memory 2 follows the same path in reverse,
to the I/0 devices 16 and 18. Information is also received
and transmitted to the CPU 10 from the memory 2 via line 43,
adder 68, line 73, register 69, line 72, multiplexer 71 and
memory bus 45. The address register 67 designates a particular
address in the memory 2, the data register 69 transfers data
from and to the memory 2. The adder 68 can increment or
; decrement the data being output from the data register 69.
Incrementing or decrementing in the usual manner, refers to
the addition or subtraction of one unit from the data being
transferred.
The signal from the memory control 4 to the address
register 67 along path 65, causes the data register 67 to trans-
fer the address data along a path 74' to the memory 2. A signal
along path 66 from the memory control 4 to the data register
69 causes the data in the data register 69 to be input to the
adder 68 (in the write mode) or the data in the adder 68 to be
input to the data register 69 (in the read mode) along the
same path 73. The signal from the memory control 4 to adder 68
causes the adder 68 to increment or decrement the data from
the data register 69. The data from adder 68 can be input to
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either the memory bus 45 along paths 43, 44 (in the write mode)
or to the I/O bus 51 along path 43, 44, and 57 (in the write
mode) or to both buses 51 and 45 (incrementing and decrementing).
Data is received by the data register 69 from I/O bus 51 or
memory bus 45 through multiplexer 71. Data from the memory
2 is transferred to the data register 69 via adder 68 in the
read mode. Memory control 4 receives its signals from either
microprocessor 12 along signal paths 74, 76, and 78 or from
data channel (I/O microcontroller 14) along prth 78', 80, and
82 and sends a signal along paths 84 and 85 to the microprocessor
12 and along paths 86 and 88 to the data channel, (I/O micro-
controller 14). The data lines to the address register 90 are
101 and 103 from the I/O bus 51 and the memory bus 45,
respectively.
The core memory 6 and its memory control 8, along with
its address register 90, its adder 92, its multiplexer 93,
and its data register 94, are interrelated in the same manner
as similar devices 67, 68, 69, 71 to the semiconductor memory 2
previously described. The control signals from the core memory
control 8 are conveyed along signal paths 100, 98 and 96 to the
data register 90, adder 92, and address register 94, respectively.
The data lines from the data register 94 to the adder 92 is 106,
input and output. The input from the adder 92 to the core
memory 6 is along path 48. Data from the adder 92 is input into
the I/O bus 51 and the memory bus 45 along lines 112 and 49,
respectively. As in the MOS memory 2, the multiplexer 93 is
positioned between the address register 94 and the inputs from
the CPU 10 and I/O bus 51 and memory bus 45, respectively. The
signals to the memory control 8 are along lines 74 and 108, 76
and 109, and 78 and 110 from the microprocessor 12 and along
lines 84, and 87, 85 and 89 from the memory control 8 to the
- microprocessor 12 and along line 86 and 83, and 88 and 81 to the
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data channel (microcontroller) 14.
The colltrol signal from the front panel 9 to the ~icro-
controller 14 is along path 114 and the signals from the micro-
processor 12 and data channel processor 14 to the I/0 devices
are along lines 340.
~ANDSHAKING SIGNALS
These signals are illustrated in Figs. 7-10 with arrows
indicating when an edge of one signal ( a transition from low
to high or vice-versa) causes generation of an edge on another
signal.
Signals from Memory to CPU
CPBP (Central Processor Busy Pulse)
CPBP (shown in Figs. 7 and 8) is the signal from the
memory to the CPU 10 in both the read, write, and increment and
decrement modes. This signal is generated by the memories 2 and
6 and is input along line 84 to the same terminal of the micro-
,
proc2ssor 12 regardless of which memory, 2 or 6, generates the
signal. This signal is a pulsed signal having a leading edge
(hlgh to low voltage transition) and a trailing edge. In the
read mode (Fig. 8) the leading edge 510 acknowledges the signal
from the CPU 10 and requests the CPU 10 to clear the memory bus
45 so that data can be transferred along that memory bus 45 to
the CPU 10. In this mode the trailing edge 512 (low to high
transition of the voltage) acknowledges that the data from the
memory 2 or 6 is on te memorg bus 45 and can be accessed from
the memory bus 45 by the CPU 10. In the write mode, the leading
edge 514 of the signal acknowledges the write request from the
CPU 10 and tells the CPU 10 to remove the address information for
the write instructlon from the memory bus 45 and place the write
data on the memory bus 45. The trailing edge 516 of this ~ignal
in the write mode acknowletges the write data from the CPU 10
ha~ been received by the memory 2 or 6. In the increment and
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decrement modes the leading edge of the signal acknowledges the
request from the CPU 10 and the trailing edge indicates that
data is available as in the read mode. This signal is a
single signal over a single line which indicates each of the
memories 2 and 6 total response to the CPU's 10 requests in all
the modes. The same single signal is used by each of the
memories 2 and 6. Other than this signal there is only one other
minor signal (CPACK) from the memory 2 or 6 to the CPU 10, and
that is only to indicate that the memory addressed exists. This
signal, and the other signals are also shown in Figs. 7 and 8,
in the case where the memory is busy.
CPACK (Central Processor Acknowledge)
CPACK (Figs. 7 and 8) is a signal from the memory 2 or 6
that was addressed to the CPU 10 in the read, write, and
increment and decrement modes. It i8 input along line 85. A
low signal 518 (low is true) indicates in all modes that the
memory 2 or 6 that has been addressed exists. There may be a
plurality of memories. However, only the one memory that is
addressed will generate this signal. A high signal, which is no
slgnal, indicates in all modes that the memory 2 or 6 that was
addressed does not exist (it might not be plugged in).
Signals from CPU 10 to Memory 2 or 6
SMCPU (Start Memory from CPU)
SMCPU (Figs. 7 and 8) is the signal from the CPU 10 to
the memory 2 or 6 in the read, write, and increment and decrement
modes. This signal is generated by the CPU 10 and is input to ~:
the memory 2 or 6 along line 74. The signal is a pulsed signal
and its leading edge 520 in the read, write, and increment and
decrement modes indicates that the CPU 10 requests service of
the memory 2 or 6.
DRMB (Drive Nemory Bus)
DRMB (Figs. 7 and 8) is the signal from the CPU 10 to the
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memory 2 or 6 in the read, and increment and decrement modes.
It is input along line 76. It is not generated in the write
mode. When the signal is high 522 (it is a high true signal)
it instructs the memory 2 or 6 in the read mode and the
increment and decrement mode to hold the data that it has
accessed for the CPU 10 on bus 45. A low signal 524 (which
in this case is no signal at all) instructs the memory 2 or 6
not to put any data on the bus 45 since the CPU 10 wants to use
the bus 45. The trailing edge of this signal 526 in both the
read, and increment and decrement modes indicates to the memory
2 or 6 to release the data that the memory was holding on bus
45. The timing of the leading edge of this signal has no
significance in either the read, and increment or decrement modes.
CPDTE (Central Processor Data Edge)
CPDTE is a signal from the CPU 10 to the memory which is
only used in the write mode. It is input to the memory along
line 78. It has no significance in the read, or increment and
.
decrement modes. The leading edge of the signal 528 signified
to the memory 2 or 6 that the data being sent by the CPU 10 to
the memory 2 or 6 is on bus 45. The timing of the trailing edge
has no significance.
MODE SIGNALS
Mode Control Signals are three signals from CPU 10 to
the memories 2 and 6 to indicate the mode desired as shown by
the table below, with 0 indicating high and 1 inticating low
(true). They are used when the CPU 10 is requested service of
either memories 2 or 6.
MODE CONTROL SIGNAL MO Ml M2
READ 0 0 0
WRITE 1 0 0
30 INCREMENT 0 1 0
DECREMENT 1 1 0
RL (Read left) 0 0
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RR (Read right) O
WL (Write left) O
WR (Write right)
Signals from Memor~ to Data Channel
DCBP (Data Channel Busy PulseO
DCBP (Figs. 9 and 10) is the identical signal to CPBP and
is between the data channel processor 14 and the memory 2 and
6 instead of the CPU 10 and the memory 2 and 6. It is input to
the Data Channel (I/O microcontroller) 14 along line 80.
SMDCH (Start Memory Data Channel)
SMDCH (Figs. 9 and 10) is the identical signal to SMCPU
- and is between the data channel (I/O microcontroller) 14 and
the memory 2 and 6. It is input along line 75 to the memory
control 4 and along lines 75 and 77 to memory control 8.
DCHDRIO (Data Channel Drive I/O)
DCHDRIO (Figs. 9 and 10) is identical to DRMB and is
between the I/O microcontroller 14 and the memory control 4
along path 82 and paths 82 and 83 to memory control 8.
DCDTE (Data Channel Data Edge)
DCDTE (Figs. 9 ant 10) is identical to CPDTE and i8 between
the data channel (I/O microcontroller) 14 and the memory control
4 ant 8 along paths 101 and 103, respectively.
DCACK (Data Channel Acknowledge)
DCACK (Figs. 9 and 10) is identical to CPACK and is between
memory control 4 and 8 and the data channel (I/O microcontroller
14) along path 89.
The mode control signals are identical to the mode control
signals for the CPU 10 except that instead of being generated
by the I/O microcontroller 14 as are all the other data
channel "handshaking" signals, they are generated by the I/Os
16 and 18 themselves and are input along line 88.
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Ma~or Logic Blocks of the Memory
For convenience, the ma~or logic blocks in the memory
have been broken up (as shown in FIG. 2A) so their function
can be readily understood.
The arbitration unit AU decides whether the proper
memory unit is being addressed. It does this by testing
an internal memory busy signal, (the signal indicates
whether or not the memory is busy), and by the use of the
signals SMCPU and SMDCH as are subsequently described.
When dual port memories are being used it can decide which
memory port to use, depending on a memory flag. It also
issues DCACK and CPACK in response to either SMCPU or SMDCH
to indicate that the address in the memory bus is in this
memory.
CG
This generates the CPBP and DCPB signals and sends
them to the CPU 10 in response to a signal from the
- arbitration unit A~ and the other internal memory signals
to start the memory.
TG (Timing Generator)
The tlming generator TG which controls the internal
timing of the memory in response to a start memory signal
from the arbitration unit AU and mode signals from the mode
control and other signals.
MU (Memory Unit)
This is the memory unit which is a plurality of
' conventional dual port memories, each of the right ports
of the memory 2 are connected together and connected to the
remainder of the memory ports as indicated hereinafter.
The left ports are also similarly interconnected and
connected to an identical system to that of the right ports
However, for convenience only one of the two port systems
is shown.
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106Z376
DC (Data Circuit)
This unit controls the placing and removing of data
on the memory bus 45.
MC (Mode Control)
MC is the mode control signal which inputs the mode
signals from the CPU 10 and data channel 14 into the
memory 2.
Ma~or Logic Blocks in the CPU 10 (FIG. 2B)
MR
The microprocessor 12 generates the control signals
to control the CPU 10. This generates PM REQ which is the
signal to the memory 2 to start the memory and causes the
generation of the mode signals to the mode generator. It
also causes the reset of DRMB as will be described
subsequently.
CM
` The CPU memory control, controls the enabling or
disabling of the CPU address and data on the MB0 bus during
a memory cycle by sending signals to the address generator
and the data gates. It also controls the request to a
- memory by sending a signal to the synchronizer as
subsequently described. It generates DPDTE and DRMB, and
controls these signals based on information from the CPU,
microprocessor, DPBP and CPACK.
AG
The address generator sends an address via the MB0
bus to the memory for each memory cycle. This is based
on a control signal from CM.
MG
The mode generator sends mode signals to the memory.
SC
The synchronizing circuit sends SMCPU and SMDCH and
ensures that they are not sent simultaneously.
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Detailed Description of the Handshaking Signals
This description will be with respect to the semi-
conductor memory 2 and its control 4 and related equipment.
However, it will be appreciated that it would apply equally
as well to core memory 6 and its control 8 and related
equipment. The following description describes the
interconnections between a single port of a memory module
and the remaining ports of the memory 2 and the CPU 10.
It will be appreciated, however, that the same discussion
applies equally as well to the other port of the memory 2
and to other multiple memories. Basically, if dual port
memories are used, all of the right ports will be connected
to the remaining part of the memory 2 and all of the left
ports will be connected to a duplicate set of controls
for those ports. It will further be appreciated that the
data channel is identical in operation to the CPU 10 as
- far as the memories are concerned and thus, for simplicity,
it is only briefly mentioned and not described in detail.
Signals between the Memory and the CPU
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CPBP
SMCPU
Instruction register 26 receives an instruction from
memory control 4 or 8. The instruction register 26 which
is a single word memory (a group of IC's) generates a
signal along path 47 to instruction decode control 120
which i~ located in the microprocessor 12 (see FIG, lA). ~-
The instruction decode unit 120 consists of a group of IC's
which decode the signal from the instruction register 26
into an initial starting address for the microprogram ~ .
that will control operation. This signal is gated to a
micro ROM 124 which contains the microprogram. This
microprogram is burned into the micro ROM initially.
Combined with the decode instruction from the decode unit
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120 are the remaining instructions. These instructions
are input from the microprogram counter (PC) 126 along
line 127 to an OR gate 128. The data (addresses) to the
PC 126 are from the micro ROM 124 by way of data path 130.
The OR gate 128 firstly permits the address from
instruction decode 120 to be input to the ROM 124 and
then the remaining addresses from the PC 126. The PC 126
stores the addresses from the ROM 124 during the time the
addresses are being input from the instruction decode unit
120 into the ROM 124. The ROM 124 is a bi-polar high-speed
ROM, (i.e., its matrix is 256 words by 4 bits). After
these addresses are input to the ROM 124, addresses are
input from the PC 120 so that a full set of addresses
exist in the, ROM 124. The ROM 124 now generates signal
PM REQ. This signal is a high true signal as shown in
FIG. 7. (As previously mentioned, the arrows in FIGS. 7-10
indicate that an edge of one signal triggers another signal.).
Leading edge 500 is effective when the memory is not busy
and leadlnp edge 501 is effective when the memory is busy.
The signal is the same in the Read Cycle as shown in FIG. 8.
The PM REQ signal may be input to the J terminal of a
standard JR type flip-flop 132 (FIG. 2B), (the K terminal
being at ground and the clock input terminal being a
clock pulse). This flip-flop 132 generates M REQ at its
Q output. The leading edge 502 of this signal as shown
in FIGS. 7 and 8 in both the CPU Write and Read cycles
respectively, is generated as a result of the PM REQ signal.
The M REQ signal is input to the D input of D type
flip-flop 134. This flip-flop 134 acts in conjunction
with flip-flop 366 (described subsequently) to act as a
synchronizer to prevent both a CPU signal and a data channel
signal being simultaneously input to the memory 2.
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One output signal of flip-flop 134 is a high (true)
signal along line 136 to an AND gate 138. The other
output signal of this flip-flop 134 (0) is described
subsequently. The AND gate 138 also receives a signal
from a control circuit which will only act to block an
output signal to the memory if a front panel signal
exists. This does not form part of the present invention,
The output of gate 138 is SMCPU. The leading edge of
this signal as shown in FIGS 7 and 8 is generated as a
result of the M REQ signal.
SMCPU, which is a high (true) signal, is input to
the memory, specifically into NAND gate 258 (FIG 2A).
This NAND gate 258 is in the AU. The other inputs to
this NAND gate 258 come from the module decode 256 which
output is true only if the CPU 10 has addressed the
module AU. These inputs are the memory addresses. The
timing is-such that the mode signals and address signals
have reached the memory 2 prior to the receipt of the
SMCPU. This is shown in FIGS. 7 and 8 where it is shown
that the memory address signal and the mode signal go high
at the same time as M REQ and before SMCPU. The output
of NAND gate 258 is true if the CPU 10 has addressed this
module and SMCPU is true. This signal passes through ~ -
inverter 260 and ls the CPACK signal which is described
subsequently, and is the signal output from the memory 2
to the CPU 10 to indicate that the memory is available.
As shown in FIGS. 7 and 8, the leading edge of this
signal is generated as a result of SMCPU. The CPACK
signal is also input to NAND gate 142. Other signals are
also input to this NAND gate 1~2, one of which is a flag
signal which is normally high - when low, it indicates that
certain conditions exist whereby the Data channel is
given priority. Under those conditions, the SMCPU signal
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will not pass through the NAND gate 142. Another input
to NAND gate 142 is along line 143. A low signal on this
line 143 will indicate that signal SMDCH is being sent
from the data channel (FIG. 2B) and has passed through
AND gate 258 (FIG. 2A). This will block the SMCPU signal
from passing through the AND gate 142 so that SMCPU are
not simultaneously input to gate 150. The other inputs
to gate 142 are to lock out SMCPU if it is desired to
externally prevent the memory module from operating.
The low output signal from gate 142 is input along
line 144 to inverter 148. This gate 142 will pass SMCPU
if the memory module that was addressed is the correct
memory module. There are a plurality of memory modules
in memory 2. The output signal is thereby inverted
(made high) and input to negative NOR gate 150 along line
149. This low signal is combined with a high signal along
line 134' from the data channel as will be discussed
subsequently. A Refresh signal is also input to this
gate 150 to refresh the memories. In other words, if
either a signal from the CPU 10 or I/O microcontroller 114
(data channel) is present, a signal will be generated. An
output signal from this gate 150 will be input into a
positive NAND gate 152 along line 151. A disable signal
is also input to the NAND gate 152 to prevent the output
of a signal if the memory is already busy. A low signal
would indicate that a signal from the data channel 14
is to be input to the gate 150. This is accomplished by a
high signal from the inverter 148. This occurs because
the output signal along line 143' blocks a signal from
being passed by gate 142. A low (true) output signal SM
is then input to a D type flip-flop 154 (~IGC) alon~ with
a REFRESH signal and a busy signal. The busy signal
indicates by a low signal that the designated memory is
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busy. The SM signal causes the memory to begin processing.
It causes M busy to go high (become true) in the CPU 10
write and read cycles when the memory is not busy (FIGS.
7 and 8). When the memory is busy the Disable signal,
input to gate 152 by the busy signal will prevent the SM
signal from being generated by gate 152. If a signal is
on line 151, but because of a Disable signal the SM is
not generated, the signal will be generated when M busy
goes low (in the busy cases shown in FIGS. 7 and 8).
The Refresh signal is for refreshing the information
in the memory in the conventional manner. The Q output
of the flip-flop 154 does not form part of this irvention.
The Q output of the flip-flop 154 generates the leading
edge of the CPBP signal (low to high transition as shown
in FIGS. 7 and 8), or in other words, the SMCPU signal
from the CPU 10 to the memory is now causing the memory
to respond with the CPBP signal. The CPBP (in both the
read and write modes) is the "not busy" case, is generated
in response to CPACK (which is in response to SMCPU). In
the busy mode it is generated in response to the busy
'~ signal as shown in FIGS. 7 and 8. The busy signal is
input to flip-flop 154. The Q output signal of flip-flop
154 is now input to NAND gates 156 and 156' along with a
signal from another flip-flop 176.
` Flip-flop 176 generates a signal as a result of the
Mode Control Signals. When there is a low signal output
d from 176 along with a signal along path 155 from the
flip-flop 154, both a CPBP and a DCBP output signal will
be produced. The DCBP signal will be described later.
AND gate 156 now forms the trailing edge of the CPBP
I (high to low transition) as shown in FIGS. 7 and 8. The
CPBP signal is input to the CPU 10 from the memory,
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specifically to JK Flip-flop 132 (CM-FIG. 2B) in the CPU
10 to reset flip-flop 132. This is done because CPBP
has already been generated and there is no longer any
need for the M REQ signal to be generated, ( as shown
in FIGS. 7 and 8, CPBP causes the trailing edge of M REQ).
The CPBP signal i8 also input to flip-flop 134 (unit SC)
to also reset that flip-flop 134 so SMCPU is no longer
generated (this causes the trailing edge of SMCPU as
shown in FIGS. 7 and 8). Thus, generation of SMCPU by
the CPU 10 caused the generation of CPBP by the memory 2
and thereby the memory's acknowledgement of the CPU's
reque~t to complete the cycle of request and response.
The leading edge of CPBP also causes the trailing
edge of the memory address signal along the MBO bus.
The leading edge also causes the CPU 10 to place data on
the MBO bus via data gate 32 in the write mode. This is
shown in.FIG. 7 by the leading edge of the signal mar~ed
CPU MBO bus.
The SM signal from positive NAND gate 152 (FIG. 2A-AU)
is also input to negative NOR gate 158 (FIG. 2A-TG) along
with Load I/O and Load CPU signals. These signals are
for placing data on the CPU and I/O buses 45 and 57.
Gate 158 acts as an inverter to convert the SM signal to
a high (true) signal. This high (true) signal is output
along line 160 to a timing generator comprising mono stable
multivibrators (one short multivibrators) 166, 168, 162
and 169 (each of which includes an AND gate as one input).
Another signal is input to the flip-flop 176 from NOR
gate 188. The Q output signal of the gate 154 is input to
NAND gate 156 and 156' which generates the trailing edge
of signals CPBP and DCBP, a6 aforementioned.
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CPBP is also input to a negative NAND gate 178 which
passes the signal if the gate 178 also receives a write
mode control signal along line 180. The output signal
from gate 178 is input through a delay circuit 181. The
output signal CPDTE goes high at this point as shown in
FIG. 7. This tells the memory 12 that the CPU 10 has
the data on the MBO bus. FIG. 7 also shows that the data
is on the MBO bus at about this time (CPU DATA MBO BUS)
goes high at this point. Also FIG, 7 illustrates that
the address has been removed from the CPU MBO bus, i.e,,
the signal "MEMORY ADDRESS MBO BUS" goes low at this time. --
CPDTE i8 then input to an inverter 185 and from there into
positive NAND gate 184. The output of NAND gate 184 is
the LOAD CPU signal and is input along line 186 to negative
NOR gate 188 along with a similar signal from NAND gate
184 on the I/O Microcontroller side of the circuit. These
..
signals are input to flip-flop 176 along with a signal
along path 175 from NAND gate 174, The latter receives
~ignals from multivibrators168 and 162 through NOR gate
;20 172 and multivibrator 166. The output of flip-flop 176
then, in con~unction with NAND gate 156 form the trailing
edge of CPBP. This trailing edge of CPBP is generated in
response to the leading edge of CPDTE as shown in FIG. 7
in the write mode. In the increment and decrement mode
signals from multivibrators 162 and 166 pass through NOR
gates 170 and 172 and into flip-flop 176 to generate the
~- trailing edge of CPBP as in the read mode aforementioned.
DRMB
Now discussing the generation of DRMB: A signal is
generated by ROM 124 in the MR (FIG, 2B) in the manner as
discussed previously. This inputs a group of signals
along lines 190 to register 192 that stores the signals,
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ROM 124 as well as register 192 consists of a plurality
of individual modules. There are a plurality of outputs
one of which is input along line 194 (CTDR) through
inverter 196 and into the clock input of flip-flop 198
(D type). (This resets the flip-flop). The CPBP signal
is also input along line 202 through positive NAND gate
204 and into the preset of flip-flop 198. A signal along
line 203 is also input to the NAND gate 204. This signal
only allows flip-flop 198 to generate DRMB in the read
and increment and decrement modes. Another signal is input
along line 199 to block the generation of DRMB in certain
other conditions, which do not form part of this invention.
The output of flip-flop 198 (along line 200) is the DRMB
signal. The leading edge is generated in response to
the leading edge of the CPBP signal, as shown in FIG. 8.
Similarly, the trailing edge of DRMB is generated by
flip-flop 198 in response to the trailing edge of CPBP
and CTDR (as shown in FIG. 8). The DRMB signal is then
input along line 200 through an inverter 206 and at this
point ia input to the memory board. Specifically this
signal is input to a D type flip-flop 212 (FIG. 2A - DC)
which passes a low signal on its Q output to an enable
NAND gate 214. The other input to this gate is from NOR
gate 215 - whole input in read and increment and decrement
modes is control signals RL and RR. These signals are
; normally low in read and increment and decrement modes
and when a signal is input from flip-flop 212 it will
enable gate 214. (In the read and increment and decrement-
ing modes a signal will be generated as well by RL and RR).
Gate 214 actuates a buffer 216 whose O-ltpUt is the
generation of the signals to the bus 45 to control the
placement of data on bus 45 by the memory. DR~IB is a low
~ignal. If it is high, no signal will be passed by the
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flip-flop 212 to NAND gate 214 and therefore no data will
be placed on the bus. The trailing edge of DRMB also
generates the trailing edge of ' MEMORY DATA MBO BUS"
(as shown in FIG. 8). This clears the bus.
Thus, the DRMB signal is only used in the read and
incrementing and decrementing modes and not in the write
mode.
CPACK
The CPACK signal is generated as follows: The M REQ
signal travels over path 250 (FIG. 2B - CM) through an OR
gate 252 (the other signals into the gate are front panel
logic control and microprocessor control signals). This
inputs a signal into address register 30 (FIG. 1) (which
includes memory register 254). This register 254 is in
AG and its output signals are address signals MBOl, MB02
and MB03, which travel along memory bus 45 into the
memory board, specifically into decoder 256 (FIG. 2A - AU).
Decoder 256 determines whether the input address signals
are the correct ones for lts memory module. If they are
the correct signals, then they actuate the memory module.
Signals are emitted by the decoder 256 and are input along
with SMCPU to an AND gate 258. The output signal of the
AND gate 258 is input along path 259 into gate 142.
This gate has been described previously. The output of ~-
gate 258 is also input to buffer 260 and CPACK is output
therefrom. CPACK is then input to buffer 262. The
output of 262 and inverter 261 forms a "WIR~D-AND" function
(phantom AND gate). The function performed at this
polnt is that after SMCPU becomes true, if CPACK is not
true also, this high signal generates a pseudo CPBP signal
to act as the CPBP signal and reset flip-flop 132 and 13
This is to prevent the system from stopping since it is
waiting for a CPBP signal and none exists. If, on the
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other hand, the CPBP signal does exist CPACK will be low
and no signal will be emitted from buffer 262. This will
block the generation of a pseudo CPBP signal.
MODE CONTROL
The mode signals are generated by the CPU 10 and
lnstruct the memory to operate in the reat, wr-ite, increment
and decrement modes. They can also instruct the memory
to operate in the read mode or write mode with only elght
of the sixteen bits - the high order or low order bits.
10 These latter signals are read right byte (RR), read left
byte (RL), write right byte (WR) and write left byte (WL).
These mode control signals are incorporated with the
"handshaking" signals as follows:
Micro ROM 124 receives instruction signals from
instruction regi~ter 26 as aforerentioned. These signals
are input to storage unit 283 (FIG. 2B - MG), The output
of this-unit is the leading edge of signals "MODE MODR
BUSI' (FIGS. 7 and 8) which are input from the CPU 10
to the memory 2 and specifically to an inverter 306
20 (FIG. 2A - MC) and into a multiplexer 208 which temporarily
stores the information. The data is on the bus before
SMCPU is sent to the memory as shown in FIGS. 7 and 8.
The output of the multiplexer 308 is input along lines
310, 311 and 312 to decoding PROM 314. The output of the
PROM 314 is the actual mode signal - READ, WRITE, and
EXTEND (increment ant decrement) WL (write left byte)
WR (write right byte) RL (read left byte) RR (read right
byte) and RM (read, write and increment or decrement).
The READ, WRITE, and EXTEND signals are input to the timlng
30 generator 164 previously discussed. The signals WL and RL
are input to memory storage units. The WL and RL signals
r cause only the least significant bits of information to
~ be transmitted. The mode must remain on the bus until
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the leading ed8e of CPBP is input to the CPU. The leading
edge of CPBP signal indicates to the CPU that the memory
has loaded the mode signals. The WL and RL signals are
input to multiplexers to shift the high order byte into
low order position (RL) and vice versa (WL).
FLOW CHARTS
CPU WRITE
FIG. 4 illustrates a CPU write mode, a CPU write
right byte and a CPU write left byte. The CPU 10 enables
the write mode code on the mode bus, places the memory
address to be accessed onto the mode bus, and sets the
SMCPU signal to make the signal true. This is to attempt
to start a particular memory module. If that memory module
exists, the memory will enable the CPACK signals upon
receipt of the address and SMCPU from the CPU. This
signal tells the CPU that the memQry that it wishes to
access actually exists. If it does not receive a signal
then it follows the following sequence: The CPU creates a
pseudo CPBP signal by first setting this signal and then
later resettlng it. Also it resets the SMCPU signal and
puts a high impedance on the memory bus. This remove~
any data that it placed onto this bus. Then the CPU 10
continues onto the next cycle. If the memory did exist
then the following sequence takes place: The memory waits
for its own internal cycle to end if there was a previous
cycle in process. The CPU waits for the leading edge of
CPBP from the memory which indicates to it that memory
has acknowledged itsattempt to start. If the previous
cycle has ended then the memory will accept the address
from the memory bus and place it in an address register
and generate CPBP. The CPU responds to CPBP by resetting
SMCPU andthen placing the data to be written into the
memory on the memory bus. The CPU then enables the CPDTE
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pulse which tells the memory that the data is available
on the bus. The memory then responds by accepting the
data from the memory bus into the data register and
resetting CPBP. The CPU responds to the resetting of
CPBP by removing the data from the memory bus. The CPU
then continues into the next cycle.
CPU READ
FIG. 5 illustrates a CPU read left byte, read right
byte and increment and decrement. The CPU 10 enables
the mode code on the mode bus, places the memory address
to be accessed onto the mode bus, and sets the SMCPU
signal to make the ~ignal true. This is to attempt to
start a particular memory module. If that memory module
exists, the memory will enable the CPACK signals upon
receipt of the address and SMCPU from the CPU. Thls
signal tells the CPU that the memory that it wishes to
i access actually exists. If it does not receive a signal
then it follows the following sequence: The CPU creates
a pseudo CPBP signal by first setting thls signal and
then later resetting it. Also, it resets the SMCPU signal
and puts a high impedance on the memory bus. This removes
any data that it placed onto this bus. Then the CPU
continues onto the next cycle. If the memory did exist
then the following sequence takes place: The memory
waits for its own internal cycle to end if there was a
', previous cycle in process. The CPU waits for the leading
edge of CPBP from the memory which indicates to it that
memory has acknowledged its attempt to start. If the
previous cycle has ended then the memory will accept the
address from the memory bus and place it in an address
register and generate CPBP. The CPU responds to CPBP by
setting DRMB and then placing a high impedance on the
MB0 bus. The memory then waits for data access time t~ be
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complete. The CPU waits for the trailing edge of CPBP
which indicates that the memory has accessed the data.
If the memory has accessed the data and DRMB is set, the
memory places the data on the memory bus. The memory
then resets CPBP, the data is on the bus of if time has
- expired and the data has not been placed on the bus, the
CPU then accepts the data from the memory bus and resets
DRMB. When DRMB is reset the memory places a high
impedance signal on the memory bus and the CPU then
continues into the next cycle.
SIGNALS BETWEEN THE MEMORY AND DATA CHANNEL
The signals between the memory and data channel and
data channel and memory function are generated in the same
manner as the aforementioned signals between the memory
and CPU and CPU and memory. The DCBP, DCHDRIO, DPACK and
other data channel signals operate in the same manner as
the corr~esponding CPU signals. The DCHM inputs also operate
in the same manner as CPUM inputs. Some of the componentæ
in the memory which are used for the data channel have
been shown however, it will be appreciated that they
; operate in the same manner as the components in the memory,
however, they have been identlfied with primes after the
numbers. In other words, components 258', 142', 148'
184', 185', 212', 214' and 216' operate in the same manner
as the counterparts without the primes.
Thus, it will be appreciated that a control has
been described whereby handshaking signals are generated
between a memory and CPU and data channel 14 and a memory
where there is a single signal and a single signal line
j 30 from the memory to the data channel and the memory and
4 the CPU, in all modes; read, write and increment and
~ decrement.
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DATA CHANNEL WRITE
FIG. 6 illustrates a data channel write right byte
and a write left byte. The data channel14 enables the
mode code, places the memory address to be accessed onto
the data bus, the data channel microcontroller and sets
the SMDCH signal to make the signal true. This is to
attempt to start the particular memory module. If that
memory module exists, the memory will enable the DCACK
signal upon receipt of the address and SMDCH. This
signal tells the data channel 14 that the memory that it
wishes to access actually exists. If it does not receive
a signal then it follows the following sequence: The
data channel 14 creates a pseudo DCBP signal by first
setting this signal and then later resetting it. Also it
resets the SMDCH signal and the DCH puts a high impedance
on the data bus. This removes any data that it placed
- onto this bus. Then the data channel continues onto the - -
next cycle. If the memory did exist then the following
sequence takes place: The memory waits for its own internal
cycle to end if there was a previous cycle in process.
The data channel waitæ for the leading edge of DCBP from
the memory whlch indicates to it that memory has
acknowledged its attempt to start. If the previous
cycle has ended then the memory will accept the address
from the I/O bus and place it ln an address register and
set DCBP. The data channel (I/0 microprocessor 14)
responds to DCBP by resetting SMDCP and then the data
channel places the data to be written into the memory on
the I/0 bus. The data channel microcontroller then
enables the DCETE pulse which tells the memory that the
data is available on the bus. The memory then responds
by accepting the data from the I/O bus into the data
register and then resetting DCBP. The data channel
- ~ mb/~ 28~
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1062376
microcontroller responds to the resetting of DCBP by
removing data from the I/O bus, that is, putting a high
impedance on the I/O bus. The data channel 14 then
continues onto the next cycle.
DATA CNANNEL READ
FIG. 6 illustrates data channel read modes; read
left byte, read right byte, increment and decrement.
The data channel enables the write mode code onto the
mode bus and the data channel microcontroller sets the
SMDCH æignal to make the signal true. This is to attempt
to start a particular memory module. If that memory
module exists, the memory will enable the DCPACK signal
upon receipt of the address and SMDCH. This signal tells
the data channel thst the memory that it wishes to access
actually exists. If it does not receive a signal then it
follows the following sequence: The data channel creates
a pseudo DCBP signal by first setting this signal and
then later resetting it. Also it resets the SMDCH signal
and the data channel puts a high impedance on the data bus.
This removes any data that it placed onto this bus. Then
the data channel continues into the next cycle. If the
memory did exist then the following sequence takes place:
The memory waits for its own internal cycle to end if
there was a previous cycle in process. The data channel
(I/O microprocessor) waits for the leading edge of DCBP
from the memory which indicates to it that memory has
acknowledged its attempt to start. If the previous cycle
has ended then the memory will accept the address from
the I/O bus and place it in an address register and set
DCBP. The data channel responds to DCBP by setting
DCHDRIO and then placing a high impedance on the ItO bus.
The memory then waits for data access time to be completed.
The data channel waits for the trailing edge of DCBP which
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indicates that the memory had accessed the data. Now
the memory has accessed the data and DCHDRIO is set,
the memory places the data on the I/O bus. The data
channel then accepts the data from the memory bus and
resets DCHDRIO. When DCHDRIO is reset the memory places
a high impedance signal on the I/O bus and the data
channel then continues into the next cycle.
While specific embodiments of the invention have
been disclosed it will be appreciated that many
1~ modifications thereof may be made by one skilled in the
art which falls within the true spirit and scope of
the invention.
mb/l'~ 30-
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