CODED RECORD AND METHODS OF AND APPARATUS FOR ENCODING AND DECODING RECORDS

DISQUE CODE ET APPAREIL ET METHODE DE CODAGE ET DE DECODAGE DE DISQUES

English Abstract

A CODED RECORD AND METHODS OF AND APPARATUS
FOR ENCODING AND DECODING RECORDS

Abstract of the Disclosure
A novel record with alternate width modulated bars
and spaces is decoded by comparing the width of each bar or
space with a pair of reference values based on the product and
quotient of a constant and the width of another bar or space
to establish bit value. When the width value is greater or
less than the reference value, the bit value is established.
When the width values lie between the reference values, a
state of equality is established which is resolved into a bit
value by reference to the results of a prior or subsequent
comparison. A system embodying the method includes storage
means for storing width values, reference registers for
establishing successive different sets of product and
quotient reference values, and comparators controlled by the
stored width and reference values for establishing the
greater and less than and equality status conditions. In one
embodiment, a shift register and logic circuits controlled by
the status conditions provide dynamic interpretation of the
status conditions into code bits as the character is read.
In another embodiment, the status conditions are stored and
then translated into code bits after a complete character has
been read. In one code set, each character code of seven bits
formed by four bars and three spaces uses five bits to define
the character and the remaining two bits to provide separate
bar and space parity bits. This and the fact that only one


space "1" and one bar "1" are included in a proper code
results in a code with an extremely low expected rate of
undetected error. The system also includes separate parity
check circuits for the decoded bar and space bits.

Claims

The embodiments of the invention in which an exclusive
property or privilege is claimed are defined as follows:
1. A method of decoding a data entry of N bits encoded
with X bits of a first characteristic and Y bits of a second
characteristic wherein X + Y = N and separate X and Y parity
bits are provided, which method comprises the steps of
decoding and storing the X bits and the X parity bit,
decoding and storing the Y bits and the Y parity bit,
separately parity checking the X and Y bits with the
X and Y parity hits for an X or Y parity error,
and producing an error indication whenever an X or a
Y parity error is found.

Description

`~
~0~
This invention relates to coded records and methods
of and apparatus for encoding and decoding these records, anA,
more particularly, to improvements in such records, methods,
and appaxatus using width modulated code areas.
The need for acquiring data at~ for example, a
point of sale is well recognized, and many attempts have been
made in th~ past to provide records, tags, or labels and
reading and interpreting systems that are capable of being
used in retail stores at the point of sale and for inventory.
In this application, the records must be easi}y and econom-
ically made and must be such that, for example, handling by
customers does not deface the coding or render the code
incapable of accurate reading. The record should ~e such
that it can be read either by a portable manually manipulated
reader or~a stationary machine reader of low cost, and the
code used should be easily checked or errors with low error
pxobability. Further, when the record or label is to be
; read by a manual reader, it should be such that the record
interpretation is as independen~ of speed of reading as is
possible.
Prior~approaches to this problem have used sequen-
~ , :
tial areas or bars~ o diferent light reflecting characteris- ;
tics in which bit value is determined by color. These records
are expensive to px~duce and~require somewhat more elaborate
2S reading systems than desirable. Other techniques provide
cod~s in bar or stylized character form with magnetic or light
reflecting recor~ings in which absolu~e values in a dimension
such as width are assigned to the different binary~ weights or


~668~LO

~a~ues. Thes~ codes can be r~ad seri.ally or in parall~l.
~he parallsl codes require plural transducer~ which cannot
be easily a~commodated in a por~ble reader~ and the magnetic
recording~ are also not ea~ily read with manual or portable
reader~. The sequa~tial bars o~ varying width~ are eas.Lly
read using a sing~e transducer in a portable unit but g~ner
ally use level detection equipment or individual width timers
in the interpre~ing system which are not easily compensate~
fo.r variation~ in the manually controlled ~pe~d of r~lati~e
1.0 movemenk ~e~w~en the reader and the recoxd. Thesa bar codes
are ~asily printed on p~per or card stock ~y inexpens:ive
e~uipment, and a ~ystem shown in-Canadian Patent
Number 1,004,767 issued February 1, 1977 compares widthQ ~:
~, . .. . . . . .
pairs of bars or paixs o spac~ to reduce error~ arising
~S xom printing ink changes.
Accoxdinglyg one object o~ the present invention
is to provide a new and improved method of and apparatus for
in~erpreting a ~ode~ record.
A~other object i~ to provide a coded xecord and
code cap ~ le of interpretatioll w3.~h a low r.ate o~ undete~ted
rror.
An~thex object is ~o pro~ide a n~ and improved
metho~ of interpretin~ a coded record in which the ~ize o
e~ch code ~rea is a~igned a~bi~a~y valale all~ in which each
given ~rc~ d~coded ~y compari.n~ its ~ wi~h ~o
erence value~ ba~ed orl mult~plying and divid:ing an~ler
ode ar~a ~ a by ~ con.~tant~ !
~n~ther c~e~t i~ to provide ~ method ~ and



.:..... . ~ . . . ., "

i6~
apparatus for interpreting or translating records binary
coded in areas of different widths by comparing the widths
of individual areas with two reference values established
during translating by multiplying and dividing dif~erent
area widths by a constant. Decoding is accomplished by
establishing a greater than, ~ess than, or equality relation
between each set of reference values and different code
area size values.
A further object is to provide an apparatus for
reading records wherein each chara ter is enc~dEd by a
combination of areas in two ranges of wide and narrow widths
and which includes registers for storing scanned width
values, a paix of regis~ers in which are sequentially stored
the product and quotient of a constant and the width of each
area~ and a means for decoding code values by determining
the relation between each stored width and the two reference
~alues based on anothar area.
Another object is to provide a method of and
system for decoding area size coded records in which a
determination that a code area is greater or less than a
reference value results in immediate ccde value establish-
ment while an equality determination defers code value
establishment and makes it dependent on a subssquent or
prior greater or less than determination.
A further o~ject is~to provide a width modulated
bar and space coded record and parity check means for
separately checking bar and space parityO
In accordance with these and many other objects,





~ 6681~
an embodiment of the present invention comprises a record,
tag, or label made, or example, of a membar having a light
reflective surface on which are recorded a plurality o non-
reflecting bars. The widths of the nonreflecting bars and
the reflecting spaces disposed between and defined by the
nonreflecting bars are modulated in width so ~hat a binary
"1" is represented by one width, i.e., a value in a range of
wide widths, and a binary "0" is represented by another
different width, i.e., a value in a range of narrow widths.
In one embodiment, each character is represented by a seven
bit binary code formed by four blac~ or nonreflective bars
and the three white bars or spaces separating the four
black ~ars. Five bits define the character, and the
remaining two bits are separate parity bits for space and
bar encoded data. ~ low error code of this type uses only
one space enco~ed "l" and one bar encoded "l".
These records can be easily produced using nothing
more than conventional papex or card stock and simple coding -
elements either individual or in sequence for applying ink
or other nonreflective material to the record. The record
mak~ing apparatus can be such as to sequentially or concur-
rently record~a plural character message, each character
; comprising a plurality of bits. The message can be preceded
and ollowed by start or control codes coded in the same
manner as the charac~ers of the message.
This record is interpreted by a manually held light
pen or reader including, for example, a liyht source for
directing light onto the record and a light responsive




... ..... . . . .. . .

~68~
element providing a varying output in dependence on the
quantity of reflected light received from t:he record, although
this reading assembly could as well be incorporated into a
stationary record reading mechanism. The record is read by
producing relative movement between the reader and the record
requiring only that the reader pass across the entire coded
message along a line intersecting all o~ the bars and spaces.
The analog signal developed by the photoresponsive unit in
the reader is digitized and used to sequentially gate clock
signals into a series of counting registers to sequentially
store the values o~ the sizes of different bars and spac~s.
Through the use of clock signal dividers gated by the
digitized signal, the products and quotients of a constant
and each of the bar and space widths are stored in sequence
in a pair of reference value registers. The reference
values stored for any given bar (space) are compared with
the value of the size of a preceding bar (space) to deter-
mine whether the preceding bar (space) is greater than,
less than, or approximately equal to ~he given bar (space).
.... . .
The results of the comparison control logic
circuits to store binary "O"s and ~'l"s in a storage unit
when a greater than or less than relation or status is
found. A determination of a condition of equality for an
area defers the establishment of a binary value and makes
it dependent on a pxior or a subse~uent greater than or less
than relation~ In one embodiment, the storage means is a
plural stage shift register having an input stage and inter-
mediate stages in which immediately and delayed d~termined


~0668~
bits are entered. In another embodiment, a pair of shift
registers store the comparison results~ which shift
registers control a read-only-memory (ROM) that decodes the
comparison results into a character.
To increase the probability that only correctly
decoded characters are provided, the systern includes a
parity checking circuit that independently checks for parity
the decoded space and bar binary bits. In the seven bit
character codes used in the present system and with the
permissable character codes selected to include only those
containing two binary "1" bits (a 2-7 character code), the
probability of error can be reduced to.000~1%. Comparable
results can be obtained using a seven bit code with three
binary "l"s (a 3-7 charac~er code).
By using as reference values for comparison with
the stored bit widths values based on arit~metic operations
on a code area measured during khe reading of the stored
widths, variations in reading speed, for instance, cause like
and proportionate changes in the re~erence values and the
code area wid~hs, and velocity errors are reduced or
eliminated .
Many other objects and advantages of the present
invention will become apparent from considering the following
detailed description in conjunction with the drawings in
which:
~ FIG~ 1 illustrates a record in conjunction with a
reader and interpreting circuit which embodies the present
invention and which is shown in simplified block diagram form;


J16~

FIG. 2 is a schematic illustration of one three bar
character code in a set of codes capable of interpretation
according to the present invention shown i.n conjunction with
certain signal waveforms used in decoding the character code;
FIG. 3 illustrates one 2-7 character code of a set
using four bars which can be translated using the system
shown in FIG. 1, the code being illustrated in con~unction
with a digitized scanning signal, decoding control signa1s,
and a shift register used in decoding; :
FIG. 4 is a circuit diagram in logic form illus-
trating certain control components of the system of FIG. l;
FIG. 5 is another Iogic circuit diagram illustrating -:
code area size registers, reference value registers, and
comparators forming a part o~ the system shown in FIGo 1
FIG. 6 is a logic circuit diagram illustrating
certain control and decoding 1ogic components of the system
of FIG. 1,
FIG. 7 illustrates in block diagram form another :
form of decoding circuit useful with the system o FIG. 1, and ~:
FTGS. 8 and 9 illustrate certain timing and control ~ :
signals used in the record reading circuit of the present
invention.
Reerring now more specifically to FI~. 1 of the
dxawings, therein is illustrated a system indicated generally
as 10 for interpreting a bar coded record 12. In the coding
used on the record 12, the widths of the bars and spaces
:~ var~7 in accordance with the bit value to be encoded so that
when relative movement is produced between the record 12 and
~ - .
:~ 7

~L~6~
an optical reader 14, the apparent width varies in dependence
on ~he speed of relative movement. In accordanc~ with the
present invention, the system 10 includes rneans for establish-
ing reference values during the actual scanning of the
record 12 by the reader 14 against which the widths of the
bars and spaces can be compared so that the true binary
significance of the encoded data can be accurately determined
substantially independent of reading speed ~nd without
requiring additional indicia over and above the usual bar
code on the record 12. ~odes used in the present invention
are such that undetectable errors are almost impossible.
The code used in preparing the record 12 can be
one of a general type known in the art, and FIG. 2 o he
drawings illustrates one character ~ode "00111`' that can ~e
used in carrying out the present invention. The illustrated
code is a Eive bit code whose bits are deEined by three
bars or areas 16A, 16B, and 16C of onP charackeristic and
two intervening bars or spaces 18A and 18B of a di~ferent
characteristic. In a preferred embodiment~ the bars 16A-16C
are formed by printing a suhstantially nonxeflective
; materialg such as black ink, on the reflective surface of
the record 12 so that the areas, bars, or spaces 18A and 18B
comprise the light reflective surface of the record. The
different characteristics of the bars 16A 16C and 18A and 18B
~5 could a~so be defLned by ~he use of different materials, such
as the presence or absence of magnetic material or materials
of suEficiently diEferent light reflecting characteristics.
The encoding technique used in the code illustrated

~ L~668~0
in FIG. 2 is to assign a wide width to the bars or areas 16,
18 to represent a binary "1" and to assi~n a narrow width to
the bar or area 16, 18 to reprPsent a binary "0".~ The
relative sizes of the wide and narrow width should ~a
optimized to insure adequate differentiation on interpreta-
tion, and in general this is accomplished by maximizing th~
difference between the wide and narrow wid~hs within the
constraints that the narrow bar must be large enough ~)
insure a proper width value entry on interpretation, and the
wide width must not be so large as to provide an overflow
condition on entering a width value. The wide and narrow
widths can extend over ~ range of values limited by the
~actor noted above? printing toleranc~s, and factors noted
below. Another factor to be considered is that an increase -~ -
in the differentiation between widths generally results in
an accompanying loss of bit density or packing on the record,
while a reduction in width difference can be used to incr~ase
bit density. In one embodiment of the present invention,

:
the narrow width representing a binary "0" was selected to
. .
be in the range of six to fifteen mils, nominal, while the
wide width was set ~o fall within the range of seventeen
to thirty-four mils? nominal.
A fu~ther factor to be considered with regard to
~ :.
the selec~ion of widths for the bars is the printing toler-
ances which must be maintained to insure accurate record
interpretation. Using the values set forth above, accurate
differentiation with single bit parity error detectlon can
be obtained with width tolerances of minus bw~to plus five

~ .
g

~ 668~
mils. A change in bar size of from minus Eourteen to plus
fourteen mils can result in an undetected error uslng a
single bit parity check.
To illustrate one possible width coding techni~ue
using true binary, one code in a code set assigned, for
example, to the numerical character three with an odd parity
check on binary "l"s (FIG. 2) is "00111". Considered from
left to right, these binary bits represent the binary weights
"8", "4", "2", "1", and parity, respectively. The binary
values "1" in the third and fourth bit positions are denoted
by the wide widths assigned to the bar 16B and the space 18B. ~-~
Tne binary values -01l in the first and second bit positions
are represented by the narrow widths assigned to the black
bar 16A and the white bar 18A. The bar 16C is assigned a
wide width to provide a parity bit for the odd parity check.
Other codes in this set including the remaining character
codes and possihle control codes are shown in the following
table together with the bar and space width assignments
expressed in mils.




: . :
,;~ : ,

~6~

_ aracter 16A 18A 16B 18B 16C
000~ .4 14.0 11.4 14.0 29.
0~010 1~.2 15.3 12.~ 34.~ 5
00100 1}.4 ~4.~ 2902 14.0 11.4
~0111 6 11.2 2~.5 ~.1 16.8
0100~ 6 34.5 12.2 15.3 12.2
,. 01011 6 25.5 6 25.5 I7.9
01~0~ 6 22.8 2~.6 ~ ~0.6
~1}~0 6 ~5.5 17.9 25.5 ~ ~-
~0 7.0000 29.2 14.Q 11.4 ~4.0 11.4
~0011 23.9 10.9 6 22.7 16.
1~101 20.~ 9 2006 9 20.6
1.
1~110 20.6 9 2~.6 22.~ 6 :
11001 ~ 1~.5 22.7 6 10~9 23.9 `,
11010 17.g ~5,5 - 6 ~5.5 6
11100 16.8 ~2.1 24~5 11.~ 6



~ When ~hese code~ are read in forwàrd or rev~rse
direction~ ~he binaxy aignifican~e of the bars and spaces is
unchang~d, bu~ the nrdex o~pres~ntation of the character - ~ .;
c~ode is raYersed. C~rt~i.n additional codes used or start
c,r~top codes can be provided which are dis~inct when read
in~o~ward or reYersa direcSion.~ ~hiæ permit~ reverse read ~,
c~s to ~e~changed ir. order ~o correct codes. Such an
ar~anyement o staxt and ~top c~des i~ ~hown a~d described
X5 ~n C~nadian Patent Number ~lrO00,859r issued Movember 30
~:~ ; 1976,; a~nd a~si~,ad to ~he sdme as~ignee~ ~9 ~e pre~ent ;
applicat~an.
s~


~6Ç;~
FIG. 2 of the drawings also illustxates, in addition
to the fragmentary showins of one three bar character code, a
digitized representative waveform resulting rom the reading
of this code by the reader 14 in which a high level signal
represents a black bar 16 and a low level si.gnal represents a
white bar or space 18. In this digitized signal~ the widths
of the bars 16,- 18 axe represented by the time intervals
tl - t5. In accordance with the present invention, the
binary significance or value to be attributed to the various
widths signified by the times tl - t5 is established in depen-

dence on the relationship between the width o~ a given area or
bar and the quotient and product o a constant K and another
area or bar, either adjacent or spaced therefrom where the
constant K is a nu~ber greater than one.
To illustrate the novel method of decoding the
record 12 wherein the relationship of adjacent bars or areas
is used~ the algorit~n for decoding can ~e stated as fol~ows:
(1~ Relation A implies tn~ tn(l/K)
~2) Relation B implies tn l~tn(K)

(3) Relation C implies t (Kj~t ~ t (l/K)
n n 1 n
In statement ~l) the est~blishment of relation A indic~tes
that the binary significance of the width tn 1 is a binary "0"
because the width of the area t l is less than the quotient
of the width of the following area and the constant K. In
statement (2) the esta~lishment of relation B implies thatthe binary signiicance to be attributed to the w.idth t
is a ~inary "l" because the width t -l is greater than ~e
product of the constant and the width of the adjacent area tn.




12

68~
The establishment of relation C in stateme.nt(3)implies that
binary signi~icance cannot be attributed. This is true
because the width o~ the area or bar under examination tn 1
is less than the product of the constant a.nd the wid~h tn f
the adjacent area and greater than the ~uotient o the
constant K and the width tn of the adjacent area.
In a system for carrying out the method of decoding
using the algorithm embodied in statements (1)-(3) above, the
system includes a register for storing a value proportional
to the time tl representing the width of the bar 16A as the
record 12 is read. As the reader 14 khen enters the first
white bar or space 18A, a value corresponding to the width
of this area t2 is stored, and a pair o~ reference registers
are provided with values representing the product and
quotient o~ the constant K and the width t2 of the bar 18A.
When all of these values are in storage, the system develops
a first sampling strobe signal (#l~ which enables logic
circuits such as comparators to compare the value tl with a
product and quotient reference values based on the width t2.
By re~erence to the statements (1~-(3), it will be seen that
only statement (3) is satisfied because the value tl is less
than the value of the product o~ t~ and ~ and greater than ..
: the value of the quotient of t2 and X. This establishment
of condition C implies that binary significance cannot be
: 25 attributed to the width tl at khis time. A representation
o~ the established condition or relation C is stored.
~he system then discards the width t~ and s-tores
both the width t3 and ~he product and quotienk of the ~.




13

~ C~66~
constant K and ~he width t3. When the next sampling s~robe
(~2)is developed by the system, the value t2 is compared with
the values based on the product and quotient o~ the constant
K and the width t3. By re~erence to statements (1~-(3~,
condition A is established because the width t2 is less than
the quotient of the constant K and the width t3. At this
time~ two options exist with regard to the translation or
interpretation of the coded record. The logic circuit can
be such as to assign binary significance to all three of
the areas 16A, 18A, and 16B at this time, or the condition A
can be stored until the completion of the scanning o~ the
characters shown in FIG. 2, at which time binary significance
can be assigned to each of the width modulated areas. Assuming
that binary significance is to be established upon establish-

ing the condition A, the establishment of this conditionstates that the width t2 is less than the width t3 so that
the width t2 is probably a binary "0" and the width t3 is
probably a binary "1". In view of the previously established
condition C arising from the first comparison and since the
width t2 is a binary "0", the width tl is also probably a
binary "0".
The system then establishes ~he product and
: quotient reference values for the width t4 which are compared
with:the stored width t3 on the third sampling pulse ~#3)
resulting in the establishment of condition C. Using
se~uential decoding, theestablishment of condition C does not
; establish binary significance and requires reference back to
the next adjacent determinative condition, i.e., a relation A



14

~ lal66~
or B. Since khe closest adjacent established condition is
relation A, the relation C established on the third sampling
stro~e signal indicates that a binary "1" is to be assigned
to width t4. On the next or fourth sampling stro~e signal
(~4), the product and quotient referPnce values based on the
wid~h t5 are compared with the stored widt:h t4 to again
result in the establishment of relation or condition C. In
the sequential decoding arrangement, the establishment of
this e~uality condition or relation C again reguires
reference back to the most recently established determinative
condition, i.e., the relation A established on the second
sampling strobe,with the result that a binary "1" significance
is attributed to the width t5. In this connection, it is
noted that the width t5 is never ac~ually measured by the
system and that the binary significance to be attributed to
the bar 16C is established on the basis of the relation
between the product and quotient reference values based on
the width t5 and the measured width of the preceding area t4.
In the alternative method of interpreting a
character code such as the illustrative code shot~n in F~G. 2,
storage means are provided for skoring reprasentations o the
sequentially established relation, i.e.a CACC~ and a trans-
lating means such as a read-only-memory (ROM) translates the
pattern of sequentially established relation into binary
code corresponding to the width modulated bars~
To facilitate an understanding of and the app~ica-
tion of the interpreting method of the present invention
based on prior statemen s (1)-(3~, there is set forth below

: : :


~6~
a set of correlative statements de~ining the binary implica-
tions o various sequences of the three relations defined in
statements (1)-(3):
(4~ A followed by C implies 0~1.
(5) C ollo~ed by A implies 001.
(6) B followed by C implies 100.
~7~ C followed by B implies 110.
(8) A followed by B implies 010.
(9) B ~ollowed by A implies 101.

(10) C followed by C followed by A implies 0001.
(11) C followed by C ollowed by B implies 1110.
(12) A followed by C followed by C implies 0111.
(131 B followed by C followed by C implies 1000.
By reference to the statements above and FIG. 2 of the
drawings, statement (5) defines the first ~hree bits "001"
formed by the bars 16A, 18A, and 16B of the representative
code. Considered alternatively, the bits de~ined by the bars
18A, 16B, and 18B are established by statement (4). Considered
from another viewpoint, the last Eour bits represented by bars
18A, 16B~ 18B~ and 16Cg respecti~elyg are defined by statement
(12). By reference ~o statements (4~-~13), the relations
established during the xeading of a character can be examined
: in saquence or concurrently to determine the binary significance
to:be attributed to the various areas or bars of a character
,
: 25 code set.

: ~ Under certain conditions involving printing
tolerances and selection o extreme limiting values for
widths, either broad or narrow, in the establishment of the
.


~ 16 ::

6~
character code set, it is possible that two other sequences
o tha relations A and B may be established which axe set
forth below in statements (14) and (15):
(14) A followed by A implies 001.
(15) B followed by B implies 100.
As an exampleg using the character cod~ set in which~ or
example, a first "0" representing bar has a nominal printiny
width of six mils, a following first space has a nominal
width of eleven mils also representing a binary "0", and the
second bar representing a binary "1" has a nominal width of
twanty-four mils, all in the ranges set forth above, it is
possible that the comparator logic would interpret the
successive widths of six mils, eleven mils~ and twenty-four : .
mils as a pair o successive A rel~tions, rather than a C
relation followed by an A relation. This condition is
covered by statement (14) which implies that the binary
significance is "001"7 the same as if the code had been
interpreted as in statement (5) above. An opposite condition
with respect to the relative widths of the successive areas
would result in the sequential establishment of condition B's
which would ba interpreted as "100" by statement (15) and
would reach the same result as if interpreted in accordance
with statement (6~ above.
The decoding technique set ~orth a~ove can be used
25: wi~h codes using a grea~er or lesser number of bars wich the
consequent change in the number of intervening white bars or
spaces, and can also be used in interpreting codes in which
the spaces are without signiicance and intelligence i.s width




17

61~

modulated in only the prinked bars, and vice versa. By width
modulating only printed bars and having bars eithPr narrow or
wide printed on uniform centers, ~he code is adaptable for use
with high speed serial printers of the type used as computer
output units. As an example~ a BCD character with a parity
bit can be encoded in five bars, and an error that cannot be
detected by usual parity checking circuitry requires the
inversion of both a narrow bar and a wide bar with a conseque~t
rever~al in binary significance of the encoded bit. As an
10 example, using nine mil centers between bars and assigning ~-
narrow bars a nominal width of six mils and large bars a
nominal width of twelve mils, each o~ the fifteen character
odd parity character set can be recorded in an eighty mil
character width or ten characters per inch. This t~pe of
code ~ont can be recorded with a ~odel 104 printing unit
manufactured by Monarch Marking Systems, Inc. of Dayton,
Ohio.
Based on experience with three bar systems and
conventional parity checking techniques, ~ast operating
experience has demonstrated tnat a one percent error rate
can be anticipated.
;~ As noted above, the prLmary source of undetected
errors results ~rom an inversion in the binary significance
to ~e attributed to a width modulated area. In a record in
whLch black or nonreflective bars are printed on reflective
record material wlth either or both of the black and white
bars being modulated in width, the inversion in binary
significance of a bar or area arises rom printing smears




18

~ 66~
which extend a black bar or width with a corresponding
reduction in the adjacent white bar width or rom printing
voids in which the apparent width o the bl.ack bar is reduced
with a corresponding incraase in the width of the adjacent
white bar. Printing smears normally result: from heavy or
intense application of ink to the record, whereas voids result
from a light application o~ ink. In accordance with the
prasent invention, there is provided an encoded record, a
method of encoding the xecord~ and a method of error checking
the record decoding by which the experienced error rate of
around one percent is reduced to an error rate approaching
.OOOOl percent.
More specifically, one character code from a
character set embodying the invention is illustrated in FIG. 3
of the dr~wings and is de~ined by four black bars Bl B4 and
three intervening white spaces Sl-S3. The character is
deined by width modulating the first five bits formed by
th bars Bl-B3 and the s?aces Sl and S2. The space S3
provides a parity check bit for ~he bits defined by the
spaces Sl and S2~ and the bar B4 provides a parity check bit
:~ for the black bars Bl-B3. The bars Bl-B3 and the spaces
Sl-S2 can be checkad ~or either odd or even parity, but in
the illustrated code are checked for odd parity. In
addition~ the entire seven bit code is checked for the
~ 25 presence of only a single space Sl-S3 pro~iding a binary "l"
:~ and a single bar Bl-B4 defining a binary "l'i. With such a
code the orlly possible character inver~ion resulting in an
undetected error requires two print aults, and these l?rint




: 19

66~

~aults must be a large ~oid in a bar and a large smear on a
bar. Since these ~aults normally arise ~rom contradictory
printing error conditions, i.e., light printing and dark
- printing, the errox probabilities reach the low level
referred to above. This character set ~s :referred to as a
2-7 code set. I~ h~s also been determined that the expected

improvement in error ra~e can be achieved usin~ two 3-7
code sets in which bars and spaces are separately checked for
parity, and a correct code includes three binary "l"s, e.ither
two "l"s defined by bars in one set or t~o "l"s defined by
s~aces in the vther set, with the remaining binary "1" being
defined by a space or a bar, respectively.

There is listed below a table setting forth a 2-7
code set adapted for use in accordance with the present
invention and illustra~ing typical wid~h assignments for the
various bars Bl-B4 a~d spaces Sl-S3. This 2-7 character set
includes twel~ discrete character codes, and in the fol}ow-
ing table the wid~hs are expressed in mlls:
Characters ~ Bl Sl B2 S2 B3 S3 B4
200 0 0 0 0 1 I 7 9 7 9 7 23 17~9
0 0 0 0 1 1 0 7 9 7 9 17.9 23 7
0 0 0 1 0 0 1 ~ 9 7 23 7 9 17.
: 0 ~ ~ 1 1 0 0 7 9 ~ 23 17.9 9 7
0 0 1 0 0 1 0 7 9 17.~ 9 7 23 7

:~ 250:0 1 1 0 0 o 7 9 ~7.9 23 '~7 9 7 ~ -
1 0 0 0 ~ 1 7 23 7 9 7 9 l~u9
~0 1 0 0 1 0 ~ 7 23~ 7 9 17.9 9 7
0 1 1 0 0 0 0 7 23 17.9 g 7
.1 ~ 0 1 0 ~ 0 17.~ 9 7 23 7 9 7
301 1 ~ 0 ~ 0 0 17.9 23 7 ~ 7 9 7
o n 0 0 1 0 17.9 9 7 g '7 23 7
2n
~ . . ; l :

~ii68 3L0

~his chaxacter set is designed ~or recording~ or exa~ple, by
using the Model 104 printer provided by ~onarch ~arXing Systems,
Inc. of Dayton, Ohio. Wi~h the nominal widths shown in khe
table ahove, ten character codes per inch can be recorded on
the record 12.
Another possible source o~ error in interpreting
printed codes wherein bo~h the bars and spaces are modulated
arises from more or less uniform increase~ or decreases i~ the
apparent widths of the b~rs and an opposit2 effect on the
intervening spaces due to light and heavy printing. Errors in
in~erpretation of a coded record arising from this effect can
be obviated by separating comparing bar~ with bars and spaces ~ ~.
wi~h spaccs becau e of the correlated chang~s in areas of l~k~
: ~haracteristics~ Such a system .is.shown and descr~bed in
. . . . . . . . . =.
Canadia~ Patent Number 1,004,767, issued February 1,
: . 1977, ~nd as~igned to the same assignee as the present
in~ention~
FIG. 3 of the drawings illu~trates in addition to a
representati~e charac~er code ~rom ~he character set ~hown in
- ~20 ~he table ab~ve cert~in waveform~ ~nd circuits ~or interpret~
in~ the chaxacter ~ode using t~e technique or algori~m and
~tatements set :Eorth above in conjunction wikh ~he description

o~ t~e code shown in FIG~ 2 of the drawings. ~he method illus-

:; ~ tra~d in ~IG. 3 is de3ign~d to compare pairs of ~ars Bl~B4
:~ 25 and to compare pa.ixs o~ ~paces 51-S3O ~ccordi~gly, ~tatement~ i
~- (1) (3) mu~t be r~stated a~ statement~ (163-(18) below. ~
16) ~elation ~ impli~5 tn 2 < tn(lJK) ~ ~:
~17~ ~lation B impli.~s t~ ~ ~ tn(~
'I

~.~6~
(18~ Relation C implies tn(K)~ t ~ ~ t (l/K).
A comparison o~ state~ents (1~-(3) with statements (16)-(18
indicates their identity except that conditions A, B, and C
arise in dependence on the relationship between a given area
and not the adjacent area~ but an area spaced by two in the
sequance. Thus, bars are compared with bars and spaces are
compared with spaces.
In FIG. 3 of the drawings, there is illustrated a
shit register indicated generally as 20 formed of seven stages
Ql-Q7 for serially interpreting a 2-7 character set o the
present invention. The shift pulse inputs are connected in
common to an advance or shift pulse line 22 which receives an
advance or shift signal on each bar-space or space-bar
transition, as illustrated in FIG. 3. The inputs to the
stages Ql-Q7 are connected in series with the input to the
input stage Ql '~eing strapped to ground or a re~erence poten-
tial to enter a binary 10ll into the stage Ql on each advance
signal. Priming or preset inputs are provided for the stages
Ql, Q3, and Q5 as shown in FIG. 3. The application of a more
positive signal to one of these preset inputs enters a
binary "l" into the stage.
The logic equatlonsfor decoding a character code in
the 2-7 charact~r set using the relations A, B~ and C deter-
mined in accordance with sta~ements (16~-(18) are set forth
belov in statements (19~-(213. Since a binary "0" is
~; continuously entered into the input stage Ql of the shit
register 20 on each advance signal, the logic equations (l9)
(21) s~t orth the condition -for presetting "l"s into th~
,

22

~1~66~
stages Ql, Q3, and Q5 in dependence on the relation A, B, or C
established in accordance with statements (16)-~18) and the
data standing in the shift register 20 at any given time. In
the following equations~ SS represents any sampling strobe, and
~3, #4, and ~5 represent the third, fourth, and fifth sampling
strobes:
(19) Preset Ql - (SS) A ~ (SS) . C Q3.
(203 Preset Q3 - (SS) B.
(21) Preset Q5 = (#3 ~ ~4 ~ ~5) B Q3 Q4.
The necessary logic implementation required for dynamic
decoding in the shift register 20 as expressed in statements
(19)-(21) is relatively simple and arises from the fact that
the 2-7 code set includes no more than ~wo binary "l"s in the
seven bits and that these binary "I"s can only occup~y a small
finite number of different positions within the seven bit code.
In general, the first term of statement (19) supplies
a binary "1" to the input stage Ql whenever relation A is
established. Relation A states that the bit whose width is
being compared is smaller than the last bit scanned, and by
~0 implication states that the last bit scanned is larger and
thus represents a binary "1". Since the shift register 20 is
always three steps in advance of the first comparison or sam-
pliny strobe due to the three advance signals preceding the
flrst sample strobe (see FIG. 3), the stage Ql is the proper
stage in which to preset the binary "1". With respect to the
second term in statement (19), if stage Q3 is set indicating
a binary "1" and a condikion C arises implying equality, Ql
must also be "1", and Ql is preset to a binary "1" setting.


:
23

iQ6G81V
With regard to the presetting o~ Q3 under the
conditions e~pressed in statement (20), the establishment of
relationship B indicates that the stored width being compared,
i.e., tn 2' is greater in width than the l:Lke area just
scanned~ i.e , tn. Since, again, the sett:ing of the shift
register 20 is three steps ahead of the cuxrent comparison,
the established binary "l" for thP area tn 2 should be pximed
into stage Q3, the shift register stage in the sequence in
which this code bit belongs.
Statement (21) takes care of a special condition in
one of the character codes in the set shown above in which the
binary "l"s appear in the first two spaces. This will
initially result in the establishmant of a condition o
e~uality on the first sample. Accordingly, the decision on
the value to be entered must be delayed. As set forth in
statement (21), when the greater than relationship B is
esta~lished and binary "l"s are not stored in stages Q3 and
Q4, Q5 can ~e preset to a "1" condition during the third,
fourth~ and fifth sampling strobes.
~The se~uence of decoding the character shown in
FIG. 3 is illustrated in the following table with "X"
denoting bits of unknown or arbitrary value:



~ .
~::


:.' ~

~ 24

~066~
Ql Q2 Q3 Q4 Q5 Q6 Q7
Advance ~1 0 X X X X X X
~o Strobe
Advance #2 0 0 X X X X X
~o Strobe
Advance ~3 0 0 0 X X X X
Sample ~1 - C 0 0 0 X X X X
Advance ~4 0 0 0 0 X X X
Sample #2 - A 1 0 0 0 X X X
10 Advance #5 0 1 0 0 0 X X
Sample #3 - C 0 1 0 0 0 X X
Advance #6 0 0 1 0 0 0 X
Sample #4 - B ~ 0 1 0 0 0 X
Advance ~7 0 0 0 1 0 0 0
15 Sample #5 - A 1 0 0 1 0 0 0 ~:
With reference to FIG. 3 and the above table, the
first advance pulse results in the entry of a binary "0" in
the iApUt stage Ql. Since sampling strobe signals are not ~
generated by the control system prior to the next two advance :~:
signals, these ~wo advance signals shift ~inary "O"s into the
;~ first three stages Ql-Q3 as the reader 14 passes over the
first bar Bl, the ~irst space Sl, and enters the second black
~, :
bar B2o When the reader 14 reaches the end of the second
black:bar~B2, the:system has stored in three discrete
counters the wid~hs of the first two bIack ~ars Bl and B2
and the width of the first space Sl. In addition, the
: system has stored the product and quo~ient of the constant K
: and the width of the second black bar B2 in two reference



~5

~ L06~
counters.
At this time, the system generates sampling strobe
~1 which controls the decoding logic to compare the width o~
the first black bar Bl with the product ancl quotient reference
values based on the second black bar B2. Since only statement
(18) is satisfied at this time, a relation C is established.
Further and by reference to statements (19)-(21), none of the
logic equations for presetting any of the stages in the shift
register 20 are satis~ied, the ourth advance pulse enters a
binary "0" into the input stage Q~ and the previously entered
binary "O"s are shifted to the stages Q2-Q4.
As the reader 14 advances across the record 12 and
through the second space S2~ this value is stored in one of
the storage registers, and the product and quotient reference
values based on the width of the space S2 are stored in the
reference registers. When the s~cond sampling strobe ~2 is
generated, the value of ~he width of the first space Sl is
compared with the quotient and product reference values based
on the width o~ the space S2, and the condition A defined by
statement (161 is established. Since the s~mpling strobe SS
lS present, the first term of logic equation (19~ is satisfied,
and Ql is preset to a binary "1" condition, as shown in the
` ~abo~e table. On the following or fifth advance pulse, this
binary "1" is shifted into stage Q2, a binary "0" is shifted
,
into input st~ge Ql~ and the preceding three binary "O"s are
shifted into the stages Q3-Q5.
As the reader 14 advancas over the record 12 through
the third black bar B3, a relation C i5 established on
. .

26

~)6168~
sampling strobe #3 in accordance with statement (16), and none
of the stages of the shift register is preset since none of
statements (19)-(21~ is satisfied. Accordingly, on the
following advance signal, a binary "0" is entered into the
input stage Ql, and the remaining bits are shifted one step
to the right as shown in the above table.
Further movement of the reader 14 results in the
storage of product and quotient xeerence values based on
the width of the third space S3, and the fourth sampling
strobe #4 compares the previously stored width of the second
space S2 with these reference values. This comparison results
in the establishment of relation B by satisfying statement
(17). This in turn satisfies statement (20~ so that Q3 is
preset. However, Q3 is in a set condition, and presetting of
Q3 does not change the status of the data stored in the shift
register 20 (see table above3.
On the seventh and last advance pulse, the data is
shifted one step or stage to the right so that the stayes Ql-
Q7 of the shift register 20 are filled. At this time, all of
the stages of the register store binary "0"s except for stage
Q4 which stores a binary "l".
The reader 14 now passes over the last black bar B4
so that product and quotient reference values based on the
width of this bar are stored. At the end of the bar B4, the
fifth sampling strobe #5 is generated, and the reference
~alues based on the width of the bar B4 are compared with the
stored width of the smaller black bar B3. This comparison
establishes relation A which in tuxn satisfies the first term



.
27

~C3 668~L~
o~ statement (19) so that a "l" is preset into the first stage
Ql of the shift register 20 (see last line of table above). At
this time, the decoded character is stored in the shi~t register
20 in reverse order with a binary "0" of the first black bar Bl
stored in the stage Q7 and with the binary "1" of the last
black bar B4 stored in the first stage Ql. The decoded
character is now checked or a correct code and, if correct,
transferred to a utilization or output means.
As set forth above, the character set from which the
character code shown in FIG. 3 is caken is one in which the
first five bits defined by Bl, Sl, B2, S2~ and B3 define the
character, in which the space S3 provides a parity check bit
~or the data bits encoded by the spaces Sl and S2, and in
which the black bar B4 provides a parity bit for the data bits
encoded by the bars Bl-B3. Furtherg the character set is such
: that there is only one wide space and one wide bar in the code .
so ~hat only one binary "l" is encoded in the spaces Sl-S3 and
only one binary "l" is encoded by the black bars Bl-B4. Stated ~:
alternatively, the character code has ~ (five) data bits encoded
in areas or signals o diferent characteriistics in which X
(three) bits are encoded by the bars Bl-B3 and Y (two~ bits
. . ,:
ara encoded at a di~ferent level with a diferent characteris- :
: tic by:the spaces Sl and S2. The character code i5 completed
by ~he two additional parity bitis in which the parity bit
: 25 provided by the ~ar B4 provides a check for the X bits encoded
by the bars Bl-B3 and the space S3 provides a parity bit or
the Y bitis encoded by the bars Sl and S2. Accordingly, the

.
complete character code includes M + 2 bits. It should be




28

~668~0

noted that although the coding is described with reference to
the black and white bars or spaces, the coding and checking
technique descri~ed above is useful with and is, in fact,
applied to the multilevel digital signal resulting from these
5 bars and spaces, as illustrated in FIG. 3.
With this character set, a correct or proper charac-
ter code can be established by determining whether one binary
"1" is encoded in the spaces S1-S3 and one binary "1" is
encoded in the bars Bl-B4 and by insuring that odd parity
exists for the spaces Sl-S3 and for the bars Bl-B4. The bar
encoded data is stored in the odd numbered stages Ql, Q3, Q5,
and Q7 of the shift register 20, and the space encoded infor- -
mation is stored in the even numbered stages Q2, Q4, and Q6 of
this shift register. Accordingly, the logic equation defining ~ -
15 a good character can be e~pressed as follows: .
(22) Good Character - [Ql Q3 Q5 Q7 ~ Ql Q3 Q5 Q7 ~ Ql Q3 Q5 Q7
_ _ _ _ _ _ _ _
Ql Q3 Q5 Q7] [Q~ Q4 Q~ ~ Q2 Q4 Q6 + Q2 Q4 Q6]
Accordingly, by coupling the true and false outputs or Q and Q
outputs of ~he stages Ql-Q7 of the shift register 20 to a logic
; 20 gating network~ the correctness of each code stored i.n the shift
register 20 can easily be determined beora transferring this
character to the utilization means.
Reerring now more specifically to FIG. 1 of the
drawings, therein is illustrated in block form a system
~ 25 embodying the present invention and capable o~ translating or
;~ : decoding a character set including the character code shown
: ~ in FXG. 3. In general~ the system 10 is controlled by the
reader 1~ during relative movement ~etween this reacler and
:::

~ : 2~

,, , ., . , ~ .. . ., ,, . : . .. . .. . ....

68~

the record 12 to search for and detect a proper start code,
reading the record 12 in either a forward or a reverse
direction. When a proper start condition is detected, the
system 10 translates successive character codes forming a
message and transfers these characters to an output or util~
ization means. The system is res~ored to its search mode from
the read mode in which characters are decoded in response to
the detection of a stop condition. In the e~ent that an error
in the character code is detected, the system is reset, and
the reading of the message on the record 12 must be started
once again. -
The reader 14 is coupled to a timing and control
circuit 24 which includes means for digitizing the analog
signal received from the reader 14 and for performing various -
clearing and resetting operations. As each bar or space is
read by the reader 14, the control circuit 24 controls a gate
asse~bly 26 so that values corresponding to the widths of
three areas, either two bars and a single space or two spaces
and a single bar, are stored in sequence in three counters 28,

,., . - .
30, and 32. Assuming tha~ the code properly begins with a
black bar, the first black bar width is stored in the counter
28, the first space width i5 stored in the counter 30, and

:: :
~ the second black bar width is stored in the counter 32. Con-

;~ cuxrently with storing the second bar width in the counter 32,

the control circuit 24 controls a pair of reference counters


~4 and 36 to store the product of a constant and the width of

the s~cond black bar in a xeference value counter 34 and to
,;
store the quotient of the width of the second black bar and
. '
. ~:




66~
the constant in a reerence value counter 36.
To initiate the first comparison operation so as to
dete.rmine the existing relation defined by one of the state-
ments (16)-(18), the control circuit 24 controls a steering
circuit 38 to supply the width value of the first black bar
stored in the counter 28 through the steering circuit 38 to a
pair of adders 40 and 42. These adders are also coupled to
the outputs of the reference value counters 34 and 36 in which
are standing the product and quotient reference values based
on the second black bar. By selectively coupling true and
complement outputs to the adders 40 and 42, the width of the
first black bar stored in the counter 28 is compared with the
reference values stored in the counters 34 and 36 by the
adders 40 and 42, and the outputs of these two adders repre-

15 senting the presence or absence of the relations A and B is ~ .
supplied to a decoding logic circuit 44. The absence of
either relation A or relation B implies the existence of
relation C. The decoding logic circuit 44 is coupled to the
shift register 20.
The decoding logic circuit 44 in dependence on the
; existence of the condikions specified in statements ~19)-(21)
selectively enters binary "l"s in the shift register 20, the
shift register being advanced and supplied with shift pulses
under the control of the circuit 24.
After the value ~ased on the comparison of the
firsk and second black bars is completed and as the reader 14
enters the second spa~e, the counter 28 is cleaxed and ~ ~ :
supplied with ~he width of the second space, ~nd corresponding
: :

~ : 31

~ L~6~ V
reference values based on the width of the second space are
stored in the reference value counters 34 and 36. The control
circuit 24 then controls the steering circuit 38 to transer
the width value of the first space stored in the counter 30
through the steering circuit 38 to the input of the adders 40,
42 in which it is compared with the reference values stored
in the counters 34 and 36 based on the width of the second
space. The outputs of the adders 40, 42 control the decoding
logic 44 to supply an input to the shift register 20 based
on the established relation. These values are shifted along
the register 20 by the control circuit ~4.
As ~he reader 14 moves into the third black bar, the
counter 30 i5 cleared, and the width of the third black bar is -
stored in this counter while the product and ~uotient reference
values based on the width of this third black bax are stored in
the counters 34 and 36. The control circuit 24 controls the
steering circuit 38 to supply the width of the second black bar
now stored in the counter 32 to the inputs of the adders 40~ 42
in which it is compared with the reference values based on the
width of the third black bar stored in the counters 34 and 35.
The results of this comparison operation are supplied to the
decoding logic 44 which then effects the entry of the proper
blnary bit into the shi~t register 20, and this register is
ad~anced or shifted a single stage.
This operation continues during the remaining of the
first scanned code. If the shi~t register 20 is ~ound to ~ -
contain a proper start code read either in a forward or a
reverse direction, the system 10 is shifted from a search mode




32

~06~;81~
to a read mode, and the system 10 translates or decodes the
first charactar code on thP record 12 and stores the results
thereof in the shift register 20. If this coda is correct, as
dekermined by the parity checking means, the contents of the
S shift register 20 are supplied in serial or in parallel to an
output means 46, and the syst~m 10 starts the translation of
the next character code in the message.
These operatlons continue until such time as the
complete message has been checked~as determined by the receipt
10 of a proper stop code~ When the stop code is detected, the
system 10 is returned from its read mode o operation to its
search mode of operation in which it continuously monitors
data supplied by the reader 14 for a set of codes comprising
a proper start condition.
The circuitry of the system 10 is illustrated in
FIGS. 4-6 of the drawings in simplified logic form using ~A~D
and NOR logic. In one embodiment constructed in accordance
with the present invention, the logic components from which
the system 10 was constructed used complementary symmetry MOS
devices ( OS/MOS) manufactured and sold by the 5Olid State
Division of RCA in Summerville, New Jersey. The family of
devices used is identified as the CD4000A series of logic
co~onents. Obviously, however, the system 10 could be con- ~-
structed using different families of logic elements, i.e.,
TTL logic devices, or could be implemented using other types
of logic functions, such as A~D and OR devices.
In the following description, the signa~ generated
by the various logic compone~ts and used for control functions


'
33

~66~
are designated by alphabetical or alpha-numeric designations.
Throughout the description, the corresponcling signal in an
inverted form is indicated by the same designation followed
by "/". As an example, a signa~ BLACK generated by a ~lip-

flop 402 (FIG. 4) is thus identi~ied~ and its inverted signalis identi~ied as BLACK/.
As indicated above, the message on the record 12 can
be disposed be~ween a beginning start code and a terminating
stop codP, and this message is capable of heing read in forward
or reverse direction. In the embodiment o-f the system 10
shown in FIGS. 4-6, the message is preceded and followed by a
single code which, read in its forward direction, implies
reading in a forward direction, and when read in its reverse
direction advises the system 10 that the record 12 is being
read in a reverse direction. Although a number of start codes
or a number of dif~erent start and stop codes can be used,
the illustrated system 10 is designed for use with a single
start code ~rom the 3-7 character set. Thus, this code
includes three binary "l"s rather than two binary "l"s. The
20 selected start code used in the system shown in FlGSo 4-6 is ; -
"1001100" when read in a forward direction and "0011001" when
read in a reverse or backward direction. This start code is
such that on decodingg only relations or conditions A and B
in ac~ordance with statements (16) and (17) will be established,
:
and a relation C implying equality in accordance with s~a~ement

(18~ will not be established. This s~lection of the start

~ code assists in discarding spurious start codes resulting from

; optical "hash" that may be generated incident to initi.ating




34

- `
~06~3L()
relative movement between the record 12 and the reader 14.
As noted above~ the system 10 is normally in a
search condition in which the contents of the shift register
are continuously monitored for the presence o~ a valid
start code read in either a forward or a backward direction.
During this interval, the control circuit 24 continuously
provides sampling strobesso that the coding logic 44 can
search for a valid start condition as each bar-space or
space-bar transition occurs. After a valid start code is
found, the system switches to a read condition in which
sampling strobes are provided as set forth above in the
description of the decoding logic with respect to FIG. 3 o
the drawings. The search or read status of the system 10 is
established by the condition of a pair o flip-flops 466 and
468. The flip-flop 466 is set when a valid ~tart code read
in the forward direction has been detectedg and the flip-flop
468 is set when a valid start code read in a backward direc-
tion has bèen detec~ed. Accordingly, when both o the flip-
flops 466 and 468 are reset, the output of a ~OR gate 470 is
at a more positive potential and is effective through an
inverter 472 to provide a moxe negative start signal START or
a more positive signal START/. The level of the signal START
co~trols the search~or read status of the system 10.

;~:
Assuming ;that the system lO is in a search condi~ion
as repxesented by a more positive signal START/ and tha~ the
record 12 is to be;read in a reverse direction by the reader
]4 so that the terminating start code as well as the ~essage
initiating start code will be read in a reverse direction, the


: ,
: ,
: ' '


~366~

reader 14 is placed adjacent the record 12, and relative
movement is produced therebetween. The output of the reader
14 is coupled through an analog-to-digital converter 400 to
the D terminal o~ a ~lip-flop 402. As the reader 14 enters
the first black bar of the raverse-read st:art code, the poten-
tial applied to the D terminal of the 1ip-flop 402 rises to
a more positive level. On the following positive-going
transition of a master clock signal CLK ox the s~stem lO,
the ~lip-flop 402 is set to provide a more positive signal
B~ACK (FIG. 8). This positive-going signal sets a flip-flop
406 to provide a more positive signal WCH which is effective
through a ~OR gate 410 to provide a low level signal RAD/.
The generation of the low level signal RAD/ initiates the
generation of a common group of t~ming signals used to
control the operation of the system lO.
More specifically, the signal RAD/ is applied to the
reset ~erminal of a Johnson counter 412 which is advanced by
the clock signal CLK whenever;an enabling input terminal E is
held at a reference or low level~potential. The Johnson
counter 412 is a counter providing discrete decoded outputs
01-05 in response to successive input signals CLK. Accord~

:
ingly, when the signal BLACK rises to a high level and the
signal RAD/ drops to a low level, the clock signal CLK
advances the counter 412 to provide a more positive signal
25 01~(FIG. 8). On successive clock si~nals CLK, the signals ;
; 02-05 are generated. If desired, the en~bling terminal E of
:-
the counter 412 can be coupled to one or more flip-flops ~ ;

connected in series and supplied with clock signals CLK to
:: :
~:

36

6~
provide one or more clock period delays between the setting
of the flip-flop 402 and the initiation of the counting
operation of the counter 412, if it becomes desirable to
delay this operation to prevent propagatio.n delays from
S interfering with the logic o~ the circuit 10.
On the next clock signal CLK following the signal
~5, the counter 412 is advanced to a setting to proviae a
more positive res~t signal to the reset terminals R of the
flip-flop 406 and a similar flip-flop 40~. When both o-E the
flip-flops 404 and 406 are reset, the signal WC~ and a similar
signal BCH are both at a low level, and the signal RAD/,or~vided at
the output of the ~OR gate 410 rises to a high level to hold
the counter 412 in a reset condition to prevent further opera- : :
~ion under the control of the clock signal CLK.
Each time that the reader 14 enters a white bar or
space, the unit 400 holds the D input terminal of the flip-
flop 402 at a low level, and the clock signal CLK resets this
1ip-flop so that a signal BLACK/ becomes more positive. The
leading edge o~ this signal sets the flip-flop 404 to provide
a more positive signal BCH. This signal is effective through
the gate 410 to remo~e the inhibit applied to the reset
termina~ R of ~he counter 412, and this counter operates ;~
through a cycle of operation to generate the timing signals
05 to thereafter reset the flip-flops 404, 40~ and elevate .
the signal RAD/ to a more positive level. Thus, on each bar-

;: space or space-bar transition, the counter 412 is operated
:~ through one ~ycle to develop t~e phase or timing signals01-05.
:~ In addition, the transitions in the state of the




37

1~6681C)
signal RAD/ control the operation of two additional Johnson
counters 426 and 428. The counter 426 is a steerlng circuit
providing in sequence three more positive steering siynals
RA, RB, and RC on successive positive-going transitions in
the siynal RAD/. The more positive output from the counter
426 following the signal RC is applied to the res~t terminal
R of this counter so that the signal RA immediately follows
the signal RC. Since the counter 426 is ad~anced on the
positive going edge of the signal RAD/ (compare FIGS. 8 and 9~,
the counter 426 advances through a cycle on each three trans-
itions in the si~nal level applied to the input of the flip-
~lop 402.
The Johnson counter 428 is provided for counting
bit positions within each seven bit character. The enable
terminal E of the counter 428 is pxovided with a continuous
low level enabling signal. However, the reset terminal R of
tha counter 428 is provided with the siynal START/ so that
the counter 428 is disabled until such time as the system 10
is placed in a read condition. In the reset state of the
counter 428, a signal J0 is more positive. The counter 428
provides successive signals Jl-J7 on successive positive-

: going transitions of the signal R~D/. Further, the timing
- ~ of the development of the signal RAD/ on detectiny a start
condition to remove the inhibit from the reset terminal R of
the counter 428 is such that the signal Jl defines the white
space separating characters, the signals J2-J7 define the
first throuyh sixth bit positions, and the siynal J0 defines

the seventh or last bit position o~ each character code.
'

38

~6~
These signals are, however, not generated wien the system lO
is in the search mode, and the slgnal ~O remains at a high
level during the s~arch mode (see FIG . 9) ~
Referring back to the above-described assumption
that the start code is being read in a reverse direction on
the record 12 by the reader 14, the reader 14 enters the ~L~st
black bar of the s~art code and sets the flip-flops 402 and
406 so that the Johnson counter 41~ operat:es through a cycle
in which the signals 01-05 are produced in sequence followed
by the resetting o~ the flip-flop 404. The ~irst three
signals 01 produced by the counter 412 at the initiation of
the reading of the record 12 are counted and used to control
the enabling of the shift register 20. More speciically, the
shift register 20 comprising seven stages 621-627 (FIG. 6) are
normally held in a reset state by a more positive signal D RES
provided at the output of a flip-~lop 620. This signal is ~ -
directly applied to all of~ the stages 621-627 with the~excep- -
tion of the stage 623~ The signal D RES is forwarded through
' .
a ~OR gate 640 and an inverter 642 to hold the stage 623 reset.
The flip-flop 620 is the output of a counter including two
additional flip-flops 616 and 618. This counter basically
absorbs~he first three signals ~1 produced by the counter 412
to prevent spurious signals ~rom entering the shift register 20
at the beginning of the reading operation and thereby reduce
the possibi1ity or false start codes being introduced into
the register 20.

.
Accordingly, the firs~ 01 signal produced when the

reader 14 enters ~he irst black bar of the start code sets


~ ':

8~L~

the flip-1Op 616 to remove a continuous high level reset
signal from the reset terminals R of the flip-flops 618 and
~20. The second signal ~1 sets the flip-flop 618 so that a
low level signal is applied to the clock terminal CLK of the
following flip~flop 520. On the following or third signal 01,
the flip-flop 618 is reset, and the more positive signal
derived from its Q/ output sets the flip-flop 620. When this
1ip-1Op 620 is set,thesignal D RES drops to a low level, and
the stages 621-627 o the shift register 620 are enabled to
10 receive input information. ~:
Reerring back to the first cycle o operation of ;.
the counter 41~ a~d assuming that a counter 426 is in a
condition providing a more positive signal RC when the
reader 14 enters the ~irst bar (see FIG. 9~, the more positive
15 signal RC partially enables a gate 434 forming one of a set : .
of three gates 430, 432, and 434 for supplying signals for .
selectively resetting the value storing c.ounters 28, 30, 32,
34, and 36. When the counter 412 generates the s~nal 03
incident to the reader 14 entering the first black bar in
the reverse read start code, the gate 434 is fully enabled
:; to provide a low level output whlch is forwarded through an
:~ inverter 442 to provide a more positive signal RRAC ~FIG. 9).
~ This signal is applied to the reset or clear terminal CLR Qf
: the counter 28 to reset this counter to its normal state. The
25 low level signal from the g~ 434 also controls a ~AND gate
436 to provide a more positive signal RRCR for the duration
of ~h2 signal 03. The signal RRCR is applied to the reset
: tenminals of the produ~t and quotient reference value registers





~ 0668~L~
34 and 36 to reset these registers.
When the signal RAD/ rises to a more positive level
(FIG. 8~ after the resetting of the flip-f]op 406, ~urther
operation of the counter 412 is inhihited. The positive-going
signal RAD/ advances the countex 426 a st:ep so that a more
positive signal is applied to the reset terminal of this
counter~ When the counter 426 is reset, the signal RA becomes
more positive. This signal and the related signals RB and RC
control the gate assembly 26 including three ~A~D gates 416
418~ and 420 to store the widths of bars and spaces in the
counters 28, 30, and 32. More specifically, the system 1~
includes a divide by five counter 414 which can comprise a
Johnson counter, the fifth output of which supplies a signal
CLKF which is applied to one input of each o~ the gates 416,
418, and 420. The counter 414 is nonmally disabled by the
more positive signal RAD during the interval in which the
signals 0I-~5 are generated. HowevPr, the signal RAD drops
to a lvw level when the counter 426 is advanced and supplies
the output signal C~KF at one-fi~th the rate of the clock
signal CLK. Since the gate 416 is partially enabled by the
more positive signal RA, the gate 416 provides a series of
signals GRA at one-fifth the clock pulse rate. The signals
GRA are applied to the clock input of the counter 28. This
counter is a ripple counter with true binary outpu~s A~l-AC12.
As described above, this counter was reset by the gate 434
~just preceding the de~elopment of the mure pcsitive signal
RA by the counter 426. Thus, the value of t~e width of the

~: :
~ first black bar in the start code read in a reverse direction
: . ~ .
.~.. :' '
; 41

~ 0~Çi81~
can now be stored in the ripple counter 28.
The signal RAD also controls the storaye o a
product reference value in the counter 34 and a quotient
reference value in the counter 36 based on -the value of the
first black bar whose width is now being stored in the
counter 28. ~lore specifically, the system lO includes a
divide by three counter 500 and a divide by eight counter
502, both of which are Johnson counters. During the period
in which ~he signals ~1-05 are generated by the counter 412,
the signal RAD is at a high level, and operation of the
counters 500 and 502 is inhibited. However, at the end of
the transition period in which the signals 01-05 are gener-
atedg the signal RAD drops to a low level and enables these
two counters. The output of the counter 500 is a signal
CLKT which is a series o clock pulses at one-third the rate
of the clock signal CLK. The output of the counter 502 is a
series of signals CLKE appearing at one eighth the rate of
the clock signal CLK. Ih3signals CLKT are applied to the
clock or count input CLK of the product counter 34, and the
signals CLKE are applied to the count or clock input CLK of
the quotient counter 36. Thus, the counters 414, 500, and
502 are simultaneously rendered effective by the low level
. .
signal RAD to provide the si~nals CLKF, CLKT, and ChKE to
accumulate the code area width value in one of the registers
28y 30, or 32a~d the corresponding product and quotlent
referenc~ values in the registers 34 and 36, respectively.
; ~ Since the widkh value is accumulated at one--fifth
the clock pulse rate while the product and quotient reerence



~2

,, . ~ , , , - , . . - . ~ . .

68~
values are accumulated at one-third and one-eighth clock pulse
rates, respectively, the constant by which the width value is
multiplied and divided, respectively, is 1.6. This constant K
was selacted to provida optimum printing tolerance with regard
to large and small bars and large and small spaces in a 2-7
and 3-7 code o the type referred to aboveO Obviously, however,
this constant can vary in dependence on such actors as
permissible printing tolerance and bit packing density
required.
Accordingly, as the reader 14 enters the first black
bar in the reverse read start code, the signal GRA accumulates
the width of this first black bar in the previously cleared
register 28, and the product and quotient reference values
based on the width of this first black bar are stored in the
: 15 counters 34 ana 36.
When the reader 14 leaves the ~irst black bar and
: enters the first white space, the flip-1Op 402 is reset to
provide a more positive signal BLACK/ which sets the flip-~lop
404. When the flip-flop 404 is set, the ~OR ate 410 provides :;
a more negative signal RAD/. This releases the counter 412
to generate ~he signals 01-05. Further, when the signal RAD/
drops to a low level, the ignal R~D becomes more positive to
inhibit further counting in the counting circuits 414, SOO,
and 502. Thus, the accumulation o~ values in the registers
., .
28, 34, and 36 is terminated~ When the signal ~3 is
developed, the gate 430 is ~ully enabled to provide a more
positive signal RRBC through an inverter 438. The signal ~:~
RRBC i5 applied to the clear terminal C~R o~ the counter 30



~- 43

~6~
to clear this counter to receive the next width value to be
stored. Furthex, the low level output from the gate 430 is
effective through the gate 436 to provide the signal RRCR to
clear the refexence value registers 34 and 36. These values
are not used inasmuch as the data necessaxy fQr the first
comparison is not accumulated until the third code area has
been read.
After the development of the signal 05, the flip-
flop 404 is reset, and the signal RAD/ rises to a more
positive level. This advances the counter 426 50 that the
more positive signal RA is terminated, and a more positive
signal RB is provided (FIG. 9). The more positive signal ~B
partially enables the gate 418. Further, when the signal
RAD/ rises to a more positive level, the signal ~AD drops to
a low level to remove the inhibit from the counters 414, 500,
and 502. Thus, the signal CLKF is forwarded through the
partially enabled gate 418 to provide a pulse stream GRB
which is appIied to the clock or count input ChK o the
previously cleared counter 30. Thus, the system 10 now
stores the width of the fixst space in the reverse read start
code in the counter 30 and accumulates the product and
quotient refexence values related thereto in the counters 34
; and 36~ When th~ end of the first space or whlte bar is
r~a~hed and the reader 14 enters the second blac~ bar, the
flip-flops 402 and 406 are set, and the signal RAD/ drops to
a low level so that the counter 412 runs through its third
-~ cycle of operation. When the signal 03 is developed, the
gate 432 is fully enabled and is e~fective through an




44

~, - ,, , , , :

3L0668 3Lq:~
inverter 440 to provide a reset signal RRCC (FIG. 9). This
signal is applied to the clear terminal CLR of the counter 32
and clears this counter to receive the width of the second
black bar. In addition, the low level signal from the gate
432 is efective through the gate 436 to again generate the
siynal RRCR (FIG. 9) which clears the product registers 34
and 36 because the comparison operation is not yet to be
performed.
When the flip-flop 406 is reset by the counter 412,
the signal RAD/ rises to a high level and advances the
counter 426 so that the signal RB drops to a low level, and
the signal RC rises to a high level. The signal RC partially
enables the gate 420 in the gate assembly 26. Further, the
signal RAD drops to a low level, and the counters 414, 5009
and 502 are again frsed for operation under the control of
the clock signal CLK to accumulake the width of the second
black bar in the counter 32 through the signal ~RC provided ~ -
by the gate 420 and to accumulate in the ripple counters 34
and 36 the product and quotient reference valuesg respectively.
These values are completely stored when the reader 14 reaches
the end of the black bar to reset the flip-flop 402 and to
set the flip-flop 404 so that the si~nal RAD/ drops to a low
level once again.
At thi~ time, the irst comparison operation i5
performed inasmuch~as three code areas in the reverse read
start code hav~ been traversed by the reader 14.
Referring to the previously described operation of -
the counting circuit including the flip-flops 616, 618~ and




.....
. . .~ . . . :

~IL06G810
620, which control the reset signal D RES, the flip-flop 620
was set to remove the signal D RES leaving all of the stages
621-627 of the shift register 20 in a reset state when the
reader 14 provided the third transition on entering the
5 second black bar. Data stored in the shi:Et register 20 is
advanced or shifted to the right (FIG. 6~ by the signal 05/,
and the input terminal D of the input stage 621 (Ql) is
strapped to ground to enter a binary "0" in the input stage
on each shi~t siynal 05/. As described above in conjunction
10 with FIG. 3 of the drawings, the first three shift signals
05/ should have shi~ted binary "O"s into the first three
stages 621-623. In view of the persistence of the signal
D RES through the first three signals 05, binary "O"s cannot
be shifted into the shift register 20. Eowever, since the
15 signal D RES holds all of the flip-flops in a reset condition,
binary "Ol's are now stored in the first three stages 621 623
just as if the shift signals 05/ had been rendered effective.
Referring back to the reader 14 leaving the second
black bar and entering the second white bar to provide the
20 low signal RAD/, corresponding high level signals RAD inhibit
the counters 414, 500, and 502 so that the ol:Lowing values
.:
are now stored in the registers 28, 30, 32, 34, and 36: -
1. The~counter 2a stores the width of the ~irst
black bar.
2. The counter 30 stores the width of the first
space.
3. The counter 32 stores the width of the second
black bar.
' '
.

3.0~ii8~
4. The product countex 34 stores the product of
the width of the second black bar a~d the
constant K (1.6).
5. The ~uotient re~erence value counter 36 stores
the quotient of the width of the second black
bar and the constant K tl.6)-
With the count~r 412 now released by the low level ~ignal RAD/,
the signal 01 is generated. This signal provides the sampling
strobe used by the decoding logic 44 and is provided through
the decoding logic on each transition when the system 10 is in
its search mode.
The logic e~uationspreviously set forth in statements
(19), ~20), and (21~ for presetting the first, third, and fifth
stages of the shift regi~ter 20 can be restated ln the
following statements (23), (24)~ and (25) modified to include
the logic requirements for interpreting the start code from
the 3-7 character set. In the following statements, the shit
register stages Ql-Q7 correspond to the shift register stages
621-627, respectively. The remaining notations represent the
signals previously referred to above:
- , . .
(23) Preset Ql = (A-01-START/) ~ (A ~

(J4 ~ J5 + J6 + J7 ~ J0) + (C-~l-Q3)-

(J~ ~ J5 ~ J6 ~ J7 ~ J0)

24) Preset Q3 = (B-.~l-START/) ~ (B-~l)-(J4 ~ J5

~ + J6 ~ J7 + J0~

(25) Preset Q5 = (B-~l-START)-~J6 + J7 + J0~ Q3-Q5


From consldering the ab~ve, statement (23) specifie~ that ~1 or

the input stage 621 will be preset to a binary "1" condition




47

66~1~
whe.n relation A is established, the system 10 i6 in a search
condition, and the timing signal 01 appears. The first term
in statement (24) specifies that Q3 or the third shi~t register
stage 623 will be primed to a binary "1" condition when
5 relation B is established, the system 10 i.5 in a search
condition, and the timing signal 01 appea:rs.
To provide means ~or selectively establishing the
conditions A and B and by implication the condition or relation
C, the true outputs of the ripple counters 34 and 36 are :
10 individually connected to corresponding ordered inputs to the
~ull adders 40 and 42. The other sets of inputs to the full
adders 40 and 42 comprise the complements of the outputs rom
a selected one o the width value storage registers or counters
28 or 30 or 32 and are designated as Ml/-M12/. These signals
15 are provided by the multiplexer or steering circuit 38.
More specifically, the steering circuit 38 comprises
twelva sets of gates such as a set 510 for the lowest ordered
output from the registers 28, 30, and 32 and a set 520 for the
highest ordered output from the registers 28, 30, and 32. Each
20 oE these sets S10, 520 includes an output ~Ai~D gate 514, 524
and three input A~D gates 511-513 or 521-523. The gates 511-
513 and 521 523 are coupled to the corresponding output
signals from the counters 28, 30, and 32 as shown in FIG. 5
~ and are selec ively enabled under the control o~ the steering
25 signals RA-RC developed by the counter 4~6.
With the system 10 in the situation describad above,
the signal RC is at a more positive level at the end o:~ the
reading of the second black bar (see FIG. 9~ so that ol1e



48


- f , - ~ ~ ,
., ~ . . , . ~ : . . .

8~0

input to each of the gates 511 and 521 and the corresponding
gates in the other sets of gates is enab:Led. The other inputs
to these gates are supplied with the signals ACl-AC12 repre-
senting the output from the register 28 in which is stored the
width of the first black bar in the reverse read start code.
~he outputs ACl-AC12 represent true binary output from the
ripple counter 28, and the presence of a binary "1" in the
first or lowest ordered stage places the signal ACl at a hiyh
level so that the ~MD gate 511 is fully enabled. This applies
a more positive signal to one input of the NAND gate 514 and
provides a more negative output Ml/o This output signal as
well as the remaining ~ignals M2/-M12/ when applied in
negative form to the corresponding binary ordered inputs to
the full adders 40 and 42 provides a "2"s complement o~ the
value standing in the width counter 28.
With the "2"s complement of the width values from
the selected counter 28, 30~ or 32 added to the true values
supplied from the counters 34 and 36, the width value is
effectively subtracted from the reference values~and the
carry outputs from the adders 40 and 42 provide signals repre-
senting the presence or absence o relations B and A,
respectiv~ly~ in accordance with statements '16) and (17)
above~ For example3 if ~he stored width value is greater
than the product reference value stored in the counter 34,
thus establishing the axistence o relation B as deflned in
statement (17)~ the carry is consumed in the full adde~ 40~ -
and a low level signal CB/ is providedO The signai CB w~ll
be at a more positive level indicating the presence of




~9

66~3~LQ
relation B.
With regard to relation A, when the width value
supplied by the steering circuit 38 is less than the ~uotient
reference value stored in ~he counter 36, thus satisfying
statement (16), the full adder 42 provides a more positive
carry signal as a signal CA. The signal CA indicates the
establishment o relation A as defined by statement (16).
Wi~h regard to the specific example in which the
start code is read in reverse direction, the narrow width of
the first black bar is stored in the counter 28 and is
supp~ied by the steering circuit 38 as the signals Ml/-Ml2/
to the inputs of the adders 40 and ~2. This value is
compared with the reference values based on the wide width
of the second black bar now skored in the reference value
counters 34 and 36. Thus, the stored value from the counter
28 representing the width of the first black bar is less than
the quotient reference value stored in the counter 36, and . ~-.
the adder 42 provides a more positive signal CA representing
: the establishment of relation A as defined by statement (16~.
Further, since the width value stored in the counter ~8 lS
: much less than the product reerence value based on the
second wide black bar stored in the reference counter 34,
;the signal CB/ is at a more positive level, and ~he krue
slgnal~CB is at a low level indicaking the absence of
rela ion B.
A signal CC is provided which represents the
presence of condition C as defined in sta~ement (18) when-
ever~the signal CC is at a high level. This signal iB

~ ~ -
~ ' ;' ~ '~ ': ' ,"'

~668~V

generated by a ~OR ~ate 632~ the two inputs to which compr.ise
the signals CA and CB. Thus, if condition A is not present,
as represented by a low level CA, and if relation B is not . .
present as represented by a low level CB, the signal CC rises
to a high level. The signals CA, CB~ and CC representing
conditions or relations A, B, and C~ respectively, as defined
by statements (16)-(18~ provide the necessary data for
decoding the width modulated code areas and storing the
results thereof in the shift register 20.
This decoding takes place during the signal ~1 on
each transition following the first three transitions when
the system 10 is in a search condition and takes place during
the last five transitions during the read mode of the system
10. To provide a sampling strobe signal SS, thare is
15 provided a NOR gate 448, one input of which is supplied with .
the signal 01~. The other input to the NOR gate 448 is
provided by the output of a ~OR gate 446, one input of which
is supplied with the signal START/. Accordingly, wh~never
the system is in a search mode and the signal START/ is at a
high level, one input to the ~OR gate ~48 is held at a low
level potential, and the signal ~1/ provides a more positive
: :: stro~ing signal SS during each timing signal ~1. This signal
SS is applied to one input of each of three N~ND gates 606,
610, and 612 connected to th~ prime inputs of the stages 623
~:~ 25 :and 621 in ~he shift register 20. The gate 610 coupled with
a following NAND gate 614 implements the first term of sta~e-
~ment ~23). The ~AND g~te 606 coupled with the following
inverter 608 implements the first term of statement (24)o
~ ~ .
51

~ . . , . ., , . .. . . , . . ". - :

lOG~ii8~!1LO
Stage 625 (Q5)cannot be primed to a binary "1" condition
when the system 10 is in a search mode because of the
continuous inhibit applied by the signal ST~RT/ through a
~OR gate 600~
The shift register stages 621-627 are all in a
reset condi ion at this time because o~ the recent removal
of the reset signal D RES. When the signal SS is generated
in the manner descxibed above as the reader 14 enters the
second white space in the reverse read start code and with
the signal CA at a more positive level at the output o~ the
adder 42 for the reasons set forth above, the gate 610 is
ully enabled to provide a more negative output which
controls the gate 614 to preset a binary "1" into the input
stage 621. Wh~n the counter 412 develops the signal 03, the
gate 434 and the inverter 442 again develop the signa~ RRAC
to clear the counter 28 from which the width value was just
: read by the steering circuit 38. The signal 03 also contro~s
the gates ~34 and 436 to provide the signal RRCR (see FIG. 9)
to clear the product registers 34 and 36.
When the counter 412 advances to provide the more
positive signal 05 and on the~trailing edge of this signal as
: defined by the inverted signal 05/, the contents of the shift
register 20 are shifted one stage to the right. The binary
"1" from ~h~ input stage 621 is transferred to the stage 622,
a binary "0" is stored in the input stage 621 by virtue of
the grounded input to this stage, and binary "0"5 are stored
in the stages ~23-627~
:~ At the end of the cycle o operation of the counter


: 5~

~ ~6~
412~ the flip-flop 404 is reset and the signal RAD/ rises to
a more positive level to advance the counter 426 a single
step so that the signal RA becomes more positive (see FIG. 9~.
The sign~l RA enables the gate 416 so that the pulse train
S consisting of the signa~sGRA starts to acc:umulate the width
o~ the second space in the reverse read start code in the
cleared counter 283 the counter 414 being enabled by the low
level signal RAD. This low level signal ~ ~ also enables
the counters 500 and 502 so that product and quotient
reference values are stored in the counters 34 and 35 based
on the width of the second space in the reverse read star~
code. The more positive signal RA also controls the steering
circuit 38 to enable the gates 512 and 522 and the correspond- -
ing gates in the other sets so that the "2"s complement of
the ~alue standing in the counter 30 in which is stored the
width of the first space is applied to the inputs of the ~ull
adders 40 and 42.
As the reader 14 travels over the width of ~he
second space and enters the third black bar, the flip-flop
406 is set to drop the signal RAD/ to a low level. The
signal RAD rises to a high level to terminate the accumulation
of the width of the second space in he counter 28 and to
tenminate the storage of the product and quotient reference
~alues in the registers 34 and 36 based on the width of the
5~ second space. The low level slgnal RAD/ also releases the
counter 412 to operate through a cycle o operation.
,
` During the signal 01, the signal SS examines the
output signals CA and CB from the ~ull adders 42 and 40,



53


~668~L~
respectively. Since the width or the second space is greater
than the width oE the first space now stored in the counter
30~ the signal CA is more positive and the gates 610 and 614
again preset a binary "1" in the input sta~e 621. During the
siynal ~3, the signals RRCR and RRBC are genexated (see FIG. 9)
to clear the registers 30, 34, and 36 now that the results o~
the comparison operation have been used to store values in the
shift register 20. At the end of the signal ~5~ the contents
of the shift register 20 are shifted one step to the right so
10 t~at binary "l"s are ~tored in the stages 622 and 623, and
binary "O"s are stored in the stages 621 and 624-627.
At the end of the cycle of the counter 412, the flip-
flop 406 is reset, and the signal RAD/ rises to a more
positive level to advance the counter 426 a single step so
that the signal RB becomes more positive. The signal RB
enables the gate 418 to provide the siynal GRB ~o~ storing
the width of the third black bar in the previously cleared
: ~ counter 30, the signal RAD being at a low level to enable not
only ~he counter 41~ bu~ also the counters 500 and 502, and -- :
20 thus the product and quotient values are stored in the just ~:
cleared counters 34 and 36 based on the width of the third
black bar. The more positive signal RB also controls the
gating aircuit 3~ to partially enable the gates 513 and 523
and the corresponding gates in the remaining sets so that
: :
~ : 25 the "2"s complement of the value of the width of the second
:
black bar stored ~n the counter 32 ~s now supplied to the
puts o~ the fu11 adders 40 and 42.
: During continuing movement of the reader 14
~ ' " ,
:: , .
5~

~61~
relative to the record 12, the remaining bar and space widths
of the reverse read start code and the corresponding product
and quotient reference values are stored in the counters 28~
30, 32, 34~ and 36, and the output signals from the adders 40,
42 are sampled by the sampliny strobe signal SS in the manner
described above. At the end of the comparison of the width of
the second space to the reference values hased on the third
space, and after the 05 signal has shiftecl the contents of
the register 20 one step to the right, the stages 621-627 con-

tain "0001100" when considered from left to right in FIG. 6.As the reader 14 leaves the fourth black bar of the reverse
read start code and enters the space separating the start code
from the first character (FIG. 9), the same operations
described above are performed including the operation of the
counter 412 through a cycle of operation. When the signal 01
is generated to provide the sampling stro~e signal SS, the
relation A is established beca~se the third black ~ar is
smaller than the fourth black bar, and the gate 610 is again
fully enabled to prime a binary "l" into the input stage 621.
~hus, the contents of the register 20 are now, considered
from lef~ to right, "lO01100". This is a correct start code
when read in reverse or backward direction.
During the initial sear~h for a proper start
condition, a logic circuit indicated generally as 630 is used
to reduce the possibility of detecting an erroneous start
condition arising out of the initial movement of the reader : .
::
: ~ l4 and resultant spurious optical signals. As noted above,

: a proper start code does not result in a relation C.
::: :
: : :

r~
~J

lOG16t31V
Accordingly, the establishment o~ this condition represented
by the more positive signal CC partially enables a NAND gate
634 which is fully enabled during the sampling period deined
by the signal ~1 only when the system 10 i5 in the search
mode defined by the positive signal START/. The low level
output from the enabled gate 634 controls a NAND gate 634 to
apply a more positive input to the ~OR gate 640. This gate
and the inverter 642 reset the third shi~t register stage 623
to clear any binary "l"s stored therein. The same binary "1"
clearing function with respect to the third stage 623 is
performed by a ~A~D gate 636 when the relation A is established
as represented by the more positive si~Jnal CA~ This resetting
o~ ~he third s~age 623 does not change the decoding of proper
start signals but reduces the chances o improper start code
detection.
Detection for a valid start code occurs on timiny
signal 04 and will thus occur prior to generation of the
signal 05 which would shi~t the valid start code one step to
the right in the shift register 20 and thus provide an
incorrect start code. More specifically, detection of a valid
start code is performed by a gating network or control circuit
650. This network includes three ~OR gates 652, 65~, and 656
the outputs of which are coupled to two NAND gates 658 and
660. The gates 652 and 654 control the gate 658 when a
correct start code read in a forward direction is ~ound~ The
gates 654 and ~56 control a gate 660 when a correct start
code read in a backward or reverse direction is detected.
The inputs to the gates 652~ 654, and 656 are supplied by the


: .
56

. . ~ -.- . --

~66~
true and alse outputs of the shift register stages 621-627.
More specifically, when the reverse read start code is stored
in the stages 621-627, as described above, all of the inputs
to the gates 654 and 656 are at a low level, and at least
5 one input to the gate 652 is at a more positive level. Thus,
the output of the ~OR gate 652 applies an inhibit to the upper
input of the gate 658. However, the outputs of both of the
gates 654 and 656 are at a high level to fully enable the
gate 660, thereby providing a more negative backward start
10 signal STBD/.
The true signal STBD which is now at a positive
level is applied to one input of a l~A~ gate 464, the other
input to this gate being supplied b~ an inverter 460, the
input of which is coupled to the output of a NA~D gate 458. ~ -
15 When the system 10 is in a search condition, the signal
START/ is more positive to ena~le one input to the gate 458
to provide a further control over the rejection of spurious
start signals, and since a proper start condition can be
established only on leaving a black bar and entering a white
20 space, the high level signal BLAC~/ enables a second input
to the gate 45a. A third input to this gate is supplied by
the signal ~4. When the signal 04 rises to a more positive
` ~ level, the gate 458 is fully enabled, and its low level
~output is effective through the inverter 460 to fully enable
25: the gata 464 so that its output drops to a low level~ At
the: end of the signal 0~, the gate 4G4 is no longer enabled,
and its output ri.ses to a high level. This positive--going

::: ,
~ signal sets the ~lip-flop 468 to provide a more positive
: ::
:~
57

~L~66~1~
backward signal B~ indicating that a proper start condition
read in a reverse dl.rection has been detected~ The more
positive signal B~D is ef~ective through the NOR gate 470
and the inverter 472 to provide a more positive start signal
S START (FIG. 9). The presence of the more positive signal
STA~T conditions the system 10 for operation in its read
mode.
More specifically, the signal START/ is now at a
low level and controls the gates 446 and 448 to prevent the
continuous generation of the strobing signal SS on each
phase one signal ~1. The generation or the strobing signal
SS is now dependent on the setting of the counter 428. The
low level signal START/ also removes the inhibit applied to
the gate 600 so that the circuitry for effecting the
controlled priming o-f the fifth stage 625 of the shift
register 20 can be efected during the read operation. In
addition, the low level signal S~ART/ disables the gates634
and 636 which form a part of the decoding logic peculiar to
detection o start codes as described above. .:
The low level signal START/ also removes the
inhibit or continuous reset rom the counter 4~8 so that
.
this counter is hereaf~er advanced on each positive-going
transition in the~signal RAD/.~ More specifically, since
the proper s~art;code was detected on signal 04 generated
:; :
: ~ : :
25~ when~the reader 14 enters the space separating characters~

when the counter 412 completes a cycle of operation and
.
resets the flip flop 404, the~signal RAD/ rises to a more

~ positive level and advances both of the counters ~26 and



: , ' ':
5~ .
:, ~

'
~o~
428 a single step. The advance of the counter 426 provides
a more positive signal RB so that the signal GRB is supplied
during the inter-character space for storage in the reyister
30, this register previously having been cleared on a
preceding signal 05. The storage of this value is of no
consequence inasmuch as sampling stro~es SS are inhibited
during comparison operations involving this value stored in
the counter 30. The same is true with re-lard to the reEerence
values stored in the counters 34 and 36.
More speciically~ when the counter 428 is advanced
a single step, the more positive signal JO is terminated, and
a more positive signal Jl is generated ~FIG. 9). The signal
Jl persists during the inter-character interval defined by
the white space separating the last black bar of the start
code read in reverse and the first black bar of the first
- ~
character which will also be read in reverse. The more
positive signal Jl is applied to one input of a ~OR gate 444
so ~hat one input to the NOR gate 446 is held at a low level
potential. Since the signal START/ is also at a low level,
the output of the gate 446 rises to a more positive potential
and holds the signal SS at a low level, regardless of
variations in the level G~ the signal 01/~ The re~aining
two inputs to the gate 444 are provided by the signals J2
and J3 which~become~positive in seauence as the reader 14
enters the flrst black bar in the following character code
and the~irst space bar in the following character code.
SinCe the counter 428 i5 advanced a~ter the generation of
the sampling signal 01, the gate 444 prevents the yenexation




59

~ 6~
of sampling strobes until th~ reader 14 leaves the sacond
black bar of the first character and enters the second space.
The sampling strobe signal SS can then be generated during
tha more positive se~uential signals J4-J7 and J0 defining
the last five bit positions in the character read.
FIG. 9 of the drawinys illustrates the code of the
first character of the message to be read following the
receipt o the valid start code read in a backward direction.
Since the first charactar is also read in a backward d:irec-

tion, the character code shown in FIG~ 9 is the tenthcharacter code shown in the table above at page 20. This
particular character has been chosen for illustration because
the sequence of signals or the binary bits is the reverse of
the character illustrated in FIG. 3 of the drawings. The
character shown in FIG. 3 o~ the drawings is the third
character in the table on page20 read in a forward direction.
Thus3 the tran~lation and decoding operations performed by
the logic 44 a~dthe shift register 20 in decoding the first
character shown in FIG. 9 are the same as those described
above with regard to the character shown in FIGo 3 when read
in a forward direction.
More speoiically, the system 10 during the
decoding of the ~irst character of the message illustrated
in FIG. 9 operates in the manner descxibed above to provide
the phase signals ~ 5 on each signal transition to advance
he counter 426;on each signal tran ition, to clear the

~ .
registers 28, 30, 32, 34, and 36, to skeer various width

values and re~erence values into these registers following
: :



~66~
their clearing, and to advance the counter 428 to generate
the signals Jl-J0 in sequence. These signals marking bit
position are used to control tha decoding logic 44 and to
sequence certain operations of the system 10.
As an example, the signals J6, J7, and J0 defining
the last three bit positions in a character are connected to
the input of a ~OR gate 455 so that a signal SS0/ drops to a ;~
low level during the last three bit positions. This signal
is applied to one input of the ~OR gate 600 to partially
enable this gate which forms a part of the logic for priming
the fifth stage 625 during the read operation.
Referring now more speciically to the decoding
logic 44, the strobing signal SS now appears only during the
signal~ J4-J7 and J0 defining the five times at which
comparison operations are to be made. ~hus, the gates 606,
610, and 612 are partially enabled at these times. Accord-
ingly, the gate 610 satisfies the second term of statement
(23j for presetting the input stage 621 with a binary "1".
The gate 612 satisfies the third term of statement (23) in
including as an input the signal FE which is more positive
when the third stage 623 (Q3) o~ the shift register 25 is
set.~ The gate 606 satlsfies~the second term of statement
(24) ~or presettlng the~ third stage 623 (Q3) of the shift
register.
25~ The gates 600 and 60Z satisfy the single term of
statement (25~ ~or presetting Q5. The signal FE and the
signal FE/ applied to the gates 600 ~nd 602~ respectively, ~-

provide the~WOT~onditions or Q~ and Q5 (stages 623 and 625,
: ~ :


~ 61



. : . . . : . .. .. : , . .

~61~8~3

respectively). The signal 01 and CB applied to the gate 602
provide the first two elements in statement (~5). The signal
SS0/ provides the second parenthetical term in statement (25),
and the signal START/ applied to the gate 600 provides the
enabling only during a start condition.
Accordingly, as the reader 14 is moved across the
bars and spaces of the first character with the proportionate
widthsshown by the configuration of the signal BLACK in FIG. 9,
the same bits of information are stored in the shift register
20 in the same sequence as illustrated in the table in FIG. 9.
The storage of width and re~erence values is controlled by the
counters 412, 414, 426, 500, and 502 in the manner described
in detail above. The step-by step operation o the counter
428 marks the bit position currently sensed by the reader 14.
Thus, as the reader 14 enters the last black bar of ~he first
character code read in a reverse direction, the counter 428
advances to a setting in which the signal J0 becomes more
positive, and as the reader 14 leaves the last black bar and
enters the first white spaceS the counter 412 is operated
through its sequance of operation in which the timing signals
01-05 are generated. On the signal ~13 the last sampling
operation takes place to add a binary "1" to the input stage
621 in the manner shown in the above table and described
a~ove. Thus~ a complete correct code for the tenth character

: .
in the character set is stored in the shift register 20 in
reverse direction. During time ~31 a parity check is made
to determine whether the code is correct~
This parity check is performed by a parity




62

3L~)66~
checking network 670 which includes five ~AND gates 671-675
for performing an odd, single binary "1" check on the infor-
mation encoded in bars, and four NA~D gates 676-679 -for
making an odd parity, single binary "1" check on the informa-

tion ancoded in the spaces o~ the character code. ~Iorespecifically, the inputs to the gates 671~674 are inter-
connected with the outputs of the stages 621, 623, 625, and 627
in which are stored the bar encoded information in such a
manner that the gates 671-674 satisfy the first four terms
~0 in the first brac]ceted term in statement (22). Similarly,
the inputs to the gates 676-678 axe interconnected with the
outputs of the stages 622, 624, and 626 in which are stored
the space encoded in~ormation in such a manner as to satisfy
the first three terms, respectively~ in the second bracketed
term of stateme.nt (22). In this connection, stages 621-627
correspond to stages Ql-Q7, respectively.
Accordingly, when the bar encoded information
includes a~single binary "1" and satisfies an odd parity
check, one of the gates 671-674 is enabled to control the
connected gate 675 to provide a more positive signal to one
nput of a ~D gate 680 which co~bines the results of the :~
bar and space parity checks. Similarly, when the space
encoded infor$Qtion is correct, one o~ the gates 676-678 is
fully enabled to control the gate 679 to provide a more
25 positive input to the connected input of the gate 680. Thus~ :
when the parity check is satisfac~orily perfonned on ~oth ~he
bar and space encoded in~ormation, the gate 680 is fully
enabled and provides a more negative signal PARITY/.




:~ 63

~)6~;8~
Assuming that the parity check was satisfactorily
performed and that the signal PARITY/ is at a low level, this
signal is applied to one input o~ a NAND gate 452. The other
inputs to this gate are provided by the signals J0 and ~3 so
that the parity check can be performed only when ~3 is gener-
ated following the time at which J0 rises to a positive level,
i.e.g the end of a character, and following the black bar to
space transition at the end of the fourth black bar in a
character code. Since the signal PARITY/ is at a low level,
the parity error output signal P~/ from the output of the
gate 452 is held at a high level indicating the absence of
parity error or the satisfactory results of the parity
checking operation.
Since the decoded character comprises a proper
code in the selected 2-7 character set, the contents of the
shift reglster 20 can now be transferred to tha output means
46 (FIG. 6). This operation is per~ormed on the signal 04.
More specifically, a ~AND gate 454 (FI&. 4) is provided
having three input signals ~4, START, and J0. Accordingly,
on the signal ~4, ~ollowing the signal 03 on which the parity
error is checked and when the system tO is in a start
condition d~fined by the high level signal START, the gate
454 provides a more negative signal SRS/. This signal is
supplied to the output means 46 (FIG. 6) and eEfects the
~rans~er in parallel of the contents of the register 20 to
the output means 46. The output means 46 also is supplied
with the signal BWD indicating that the code stored in the
shift register 20 is in a reverse condition. The output


~, ~
64

3~366~
means 46 can comprise any number of suitable arrangements
such as a display unit or a computer input such as an input
for a transaction computer system such as the one shown in
United States patent ~o. 3,596,256. The circuitry controlled
by the signal B~3 for inverting the order of the bits
xeceived in the shift register 20 can also be of conventivnal
constxuction such as that shown in the above-identified
copending application~ Alternatively, the output means can
comprise a shift register coupled to the output stage 627 or
supplied with the signal FA. With this arrangement, as the
bits for one character are shifted into the shift register 20
the bits from the preceding character can be shifted out into
the shift register in the output means 46.
Accordingly, at the signal 04 developed by the
counter 412 on the transition from the fourth black bar of
a character code into the white space separating the charac- :
ter from the first black bar in the next character, the :~
; complete character code has been decoded and stored in the ::~
register 20, checked for parity error, and transferred to the
output means 46. When the counter 412 completes its cycle of
operation and resets the flip-flop 406, the signal RAD/ again
rises o a high:level to advance the counter 428 to a position
supplying a more positive signal Jl which is present during
the inter-charàcter interval. The positive-going signal RAD/ --
also advances the counter 426 so that the next width register
28,~30, or 32 is~selected to receive the width of the first
black bar,~ ~hese:registers and the reference value registers .
:: :
~ 34 and 36 having previously been cleared.

: ` : :


~L~6~
The system 10 then translates or decodes the
remaining character codes in sequence and transFers the
decoded contents stored in the shift register 20 into the
output means 46 following the performance o ~e parity
check. ~his continues until such time as the message has
been determined to contain a predetermined minimum number
of chaxacters, and the terminating code is detected. This
terminating code comprises a start code read in a reverse
direction~ in view of the fact that the message is being
read in a reverse direction. If the message is read in a
forward direction, ~he message is terminated by a start
code read in a orward direction.
To provide means for countiny the number of charac- -
ters in the message, the control circuit 24 includes a ~AND
gate 450, one input of which is supplied by the signal 03.
The other input is provided by the signal J7. Thus, the gate `~-
450 is fully enabled once during the decoding of each charac-
ter to provide a more negative signal SOT/. This signal is
supplied to the clock or count input terminal CLK of a
Johnson counter 64~. The counter 64~ is nonmally held in a
reset state by the high level signal START/ until the system
lO;is placed in a read mode. ~At this time the level of the
s~ignal S~ART/ drops to a low leveI to remove the continuous
reset. Assuming that the counter 644 has a counting capacity
of ten, ~he decoded tenth output from the counter $40 is
: ~ : : : : :
returned to the enable input terminal E so that the coun~er

644 i~s ena~led in its reset state.

Successive signals SOT/ each representing a decoded




66

1~668~
character advance the counter 644 on the positive-going edge
of the signal. When ten or the selected number of characters
have been counted, the output ~rom the counter 644 rises to a
more positive level and enables one input to a NAND gate 646.
The other input to this gate is provided with the signal 02.
Ac~ordingly, on each signal 02 following the counting o~ the
minimum required number of dharacters, an output signal 02G/
from ~he gate 646 goes negati~e for the duration of the ~2
signal. The inverted signal 02G is applied as one input to
a pair of ~A~D gates 484 and 486 which are used to detect a
stop condition.
More specifically, in the assumed condition in
which the message on the record 12 is being read in reverse
dlrection, when the terminating start code read in a reverse
direction is stored in the register 20, all of the inputs to
khe gates 65~ and 556 are again placed at a low level, and
the outputs of these gates ully ena~le khe NAXD gate 660 so
that the signal STBD/ drops to a low levelO The inverted
signal STBD which is at a positive level provides another
input to the gate 486. A further input to this gate
provided by the signal BWD is at a more positi~e 10vel
because the record 12 is being read in a reverse diraction.
Further~ the signal J0 is at a more positive level since a
co~plete stop code can b~ detecked only on leaving the
- 25 fourth black bar in a code and entering the white space
follo~ing the message. Thus, the gate 486 is enabled to
provide a more negative output signal which is applied as
one input ~ a NAND gate 488~ ~he ~AND gate 488 and an


:
67

~ OG~i310
additional ~A~D gate 490 provide an end-oE-message latch.
The low level signal supplied by the gate 486 to
one input of the ~AND gate 488 drives the output oE this
gate to a more positive level. Since this signal is gener-

5 ated during the signal 02, the signal RAD is at a morepositive level, and together with the ou~put of the gate 488
completes the enabling of the gate 490 so that its output
drops to a low level. The low level output of the gate ~90
is returned as a further input to the g~te 488 tD hold the
10 output oE this gate at a more positive level. The more
negative output from the gal:e 490 is also applied to one
input of a yate 482. This gate controls the resetting of
the forward and backward flip-flops 466 and ~68.
More speciically, the low level signal from the
15 output of the gate 490 applied ~o one input of the ~A~D gate
482 drives the output of this gate to a more positive level ~-
and resets both of the flip-flops 466 and 468. Since the
re~ord 12 was read in a reverse direction, the flip-flop 468
is reset to remove the more positive signal BWD. This
20 removes the reversing control signal from the output means
46 and also drops the start signal STP~RT to a low level.
The more positive output from the gate 482 also
provides the the reset signal RES. This signal is applied
to the reset terminal of the flip-flop 616 to reset this
25 flip-flop. When the flip-flop 616 is reset, its Q/ output
rises to a more positive level and resets the flip-~lops 618
and 620. When the flip-f lop 620 is reset, the shiEt register
reset signal C) RES rises to a more positive level and is




68


~66~
effective either directly or through the gates 640 and 642
to reset all of tne stages 621-627 in the shift register 20.
The loss of the start signal START places the
signal STA~T/ at a high level, and this signal is effective
to restore the system 10 to its search mode by reversing the
enabling operation previously desc ibed. In addltion, the
high level signal STA~T/ resets the counter 644 to remove the
enabling for the gate 646 to prevent further generation of
the signal 02G/.
At the conclusion of the cycle of operation of the
counter 412 during which the stop code was de'cected on the
signal 02, the 1ip-flop 406 is reset, and the signal RAD/
rises to a more positive level. This drops the inverted
signal RAD to a low level. When the signal RAD drops to a
low level, the output of the gate 490 in the end-of-message
latch rises to a more positive level and terminates the
reset signal ~ES.
; The system 10 is ~ow in condition to interpret the
;next message on the next record 12. This record interpreta-
tion or translation is performed in the manner described
above. If, however, the record 12 is read in a forward
direction, a proper start condition is detected by the gates
652, 654, and 658 which provide a for~ard staxt signal STFD.
~; ~ This signal and the signal provided by the inverter 640
control the gate~462 to set the forward flip-flop 466 to
provide the signal FWD. This signal~ in turn, provides the
start signal START. The gates 652, 654, and 658 also detect
the terminating start condition to control the gate ~84 to




69

~L~66~
set the end-of-mes6age latch includiny the gates 488 and
490. In addition3 the output means 46 is provided with a
low level signal BWD indicating that the message is being
read in a forward direction and the contents of the shift
register 2~ are transerred directly into the output means
46 without inversion in order.
The system 10 also includes means for producing
an error indication when certain abnormalitie~ occur during
the translation of the record 12. One of these error
conditions is the failure o the circuit 670 to detect
proper parity conditions in the translated code stored in
the shi~t register 200 As set forth above, the gate 680
provides a low level signal PARITY/ when a correct code is
stored in the register 20. However~ if either of the NA~D
gates 675 or 679 representing the results of the parity
check on bar encoded information and space encoded informa-
tion respectively is not supplied with a low level signal
from one of the groups of gates 671-674 or 676-678, thus
indicating the ailure of either the bar parity check or the
space parity check, the gate 680 is not fully enabled, and
the signal PARITY/ remains at a hlgh level.
Thus, when the gate 452 is enabled by the signals
JO and 03 on the transition from the fourth black bar into
~the white space following a character, the gate 452 is fully
, ~
enabled, and the parity error signal PE/ drops to a low

;~ ~ level. ~his signal is supplied to one input to a NAND
.
gate 47~ to drive the output of this gate to a high level.
: ::: :
If the system 10 i5 in a r~ad condition, the signal 5TART





~ 6~89L~
is also at a high level so that a NA~D gate 480 is fully
enabled to provide a more negative error signal E~/. This
more negative signal controls the gate 482 to reset the set
one of the flip-flops 466 and 468, thus returning ~he syskem
10 to a search condition,and ~o generate the more positive
reset signal RES. Accordingly, the detect:ion of a parity
error at any point in the translation of the message on the
record 12 immediately resets the system 10 to a search mode.
In addition, the more negative signal ER~ sets an
error register comprising a pair of cross-connected ~AMD
gates 474 and 476. The low level signal ER/ applied to ~ne
input of the NAND gate 476 drives the output of this gate to
a more positive level to provide an error signal ERROR. This
signal can be used to control a visible indicator or an
audi~le annunciator. The more positive output rom the gate
476 is returned to one input of the gate 474. Since the
flip~10ps 466 and 468 have both been reset, the output of
the NOR gate 470 is also at a more positive level, and the
gate 474 is fully enabled to develop a more negative signal
ERROR/ which holds the output of the gate 476 at a more
; positive level when the signal PE/ disappears in the termina-
tlon of the signal 03. ~he error latch including the gates
~ ~; 474 and 476 can be reset only upon the subsequent detection
; o~ a propar start condition read in either a forward or
backward direction so that the output of the gate 470 drops
to a low }evel and thus controls the gate 474 to provide a
~: re positive signal ERROR/.
:~ A fur~her abnormality detected by the system 10 is `~

.,
71

: . ,. . ., . . . - , . .

6t;8~C~
one in which a bar-space or space-bar transition is not
detected by the reader 14 within the limits expected. A
result of this condition is that one or more of the registers
28~ 30, 32, 34, or 36 will count beyond its counting capacity,
thus destroying the validity of the scanned inormation. So
as to detect this condition as quickly as possible~ the
highest rate value accumulating pulse stream is used. As set
forth above, the signal CLKT appears at one-third the clock
pulse rate, as contrasted with the one-fifth rate used to
store values in the registers 28, 30, and 32 and the one-
eighth rate used to store the quotient value in the register
36. Accordingly, the highest ordered stage of the ripple
counter 34 in addition to supplying data to the adder 40
supplies a signal FR0 which becomes more positive when the
counter 34 approaches its counting capacity. This signal is
applied to one input of a NA~D gate 422.

.
To prevent the detection of an overflow condition
in the space separating characters, i.e., the position
defined by the signal Jl, the inverted signal Jl/ is
supplied as ~he other input to the gate 422 to inhibit this
gate during the inter~character interval. However, during
all other intervals when the signal FRO becomes positive, the
;~ gate 422 is fully 0nabled to provide a low level signal to
.
; the clock input ChK of a f}ip-flop 424. I~ the product

counter 34 opera~es through another complete counting cycle
:
after the highest ordered stage has been set to provide the
more positive sig~nal FR0~ thus indicating that the counting
capacity of this register has been exceeded~ the highest




.
72

~68~
ordered stage is reset~ and the signal FRO drops to a low
level. This dri~es the output of the gate 422 to a more
positive level and sets the ~lip~10p 424 to provide a more
negative overflow signal OVF~/. The setting of the flip-

10p 424 indicates that an over10w condition has ~eenesta~lished in the most rapidly advanced counter 34 and that
the data derived from the reader 14 is not valid.
The signal OVFh/ provides one input to the MAND
gate 482 and efects the resetting o the set one o the
flip-10ps 466, 468 as well as the generation of the more
positive raset signal RES. This signal restores the system
10 to its search mode and forces the operator to rescan the
message on the record 12.
In addition, the signal OVFL/ is applied to one
input of the gate 478 and is effective through the gate 480
to develop the error signal ER/. This signal in turn sets
the error ilatch including the gates 474 and 476 to
produce the results set forth above. This error latch
is reset only upon detection of a subsequent valid start
condition.
The overflow flip flop 424 is reset on the next
transition resulting from r~scanning the record when the
~ signai RRCR used to reset the registexs 34 and 36 is
;~ ~ generated.
~ further error detected by the system 10 is a
; ~ condition in~which the reader 14 has, for example~ encoun-
tered a pencil line or some other mark on the recoxd 14
that is not a valid code and which results in the concurrent
:


73

1~6~8~
setting o:E the flip-fls:)ps 404 and 406. In other wor~ls, a
proper record will never .include transitions between bars
and spaces so closely spaced together that both of the flip-
flops 404 and 406 are concurrently set. I~ both Oe the
flip-1Ops 404 and 406 are concurrently set, both of the
pair o~ signal~ BCH and WCH become more po,sitive to fully
enable the gate 40~3.
The fully enabled gate 408 provides a more negative
under~low error signal U:E~/. This signal is applied to one
input to the gate 478, and this controls the gate 478 and
the gates 480 and 482 to both set the error latch including
the gates 474 and 476 and to reset the set one of the flip-
flops 466, 468 and provide the more positive reset signal RES.
The functions performed by these operations are the same as
~hose set forth above. The signal U:E/ is returned to a high
level by resetting the flip-flops 404, 406 under the control
of the counter 412.
FIG. 7 of the drawings illustrates a control
circuit 700 that can ~e used in the system 10 in place of
:, .
the decoding logic 40, the shift register 20, the start
detecting network 650, and the parity checking networl~ 670
to !?er~orm the functions performed in the system 10 by
~: these components. In general, the control circuit 700
includes a pair of five bit shift Fegisters 710 and 720
individually associated with the adders 40 and 42, respec :
tiveIy. The preset terminal P o the inpu~ stage of the
shift register 710 is supplied with the output signal CB
from the adder 40 through a NA~D gate 702 and an inverter


74

~;68:~
704. The preset terminal P of the input stage of -the shit
register 720 is supplied with the output signal CA from the
adder 42 through a ~AMD gate 706 and an inverter 708. Both
o the shift registers 710 and 720 are reset by the reset
signal D RES and are provided with shift pulses by the
signal ~5/.
The outputs o the ive stages in each of the
shift registers 710 and 720 are coupled to select inputs o
a read-only-memory (ROM) 740. This read only memory 740 is
of conventional construction and in essence comprises a
plurality of gates with prewired logic for implementing l~he
start and stop decoding function~, the parity checking
functions, and the character translation function. Accord-
ingly, the unit 740 includes as outputs the start forward
signal STFD, the start backward signal STBD, the parity
error signal PE/, and a group of leads for presenting a
translated character to the output means 46, as in BCD formO
The unit 740 also includes as an input signal the signal
START which advises the unit 740 whether the system 10 is
in a search or read mode. In general, the signal START --
selectively enables and inhibits translating gates for
carrying out decoding functions comparable to those performed
by the circuit 630 which are peculiar to the detection o a
start code.
; ~ 25 When the reader 14 has passed over the record 12
incident to the beginning of tha reading of a message on
the record 12 and with the system 10 in a search mode, the
various bar and space widths are stored in the reg;sters 28,
~: '


.

~ 66~1~
30, and 32 and selectively compared with reerence values
stored in the reyisters 34 and 36 int~ manner described above
so as to provide the signals C~ and CA representing relation-
ships B and A, respectively. These two signals are supplied
to the inputs of the gates 702 and 706 which are also
supplied with the strobiny signal SS. As set forth above,
the signal SS appears on each bar-space or space-bar trans-
ition when ~he system lO is in the search mode. Accordingly,
the results o each comparison operation are forwarded through
the gates 702, 704, 706, and 708 to the preset t~rminals P o
the input stages o the registers 710 and 720. Thus, the
input stage-to the shift register 710 is primed to a binary
"1" condition whenever a relation B exists, and the input
stage of the shift register 720 is primed to a binary "l"
condition whenever a relation A exists. With the D terminals
of these input stages strapped ~o ground, the shift signal
provided by the signal 05/ enters a "0" whenever the input
stages are not primad under the control of the signals CB or
CA. Thus, a binary "0" in corresponding stages of the shift
registers 710 and 720 represents the eauality condition or
relation C.
Accordingly, with the system 10 in the search mode,
the two shift registers 710 and 720 are loaded wi~h a pattern
of binary '10"9 and binary "l"s corr2sponding to the pattern
~5 of relations A, B, and C established under the control of the
output from the adders 40 and 42. Further, the unit 740 is

~ .
supplied with the output of the gate 458 in the system 10 to

; interrogate the unit 740 on each code area transition so that

:
76

~6683L~
the contents of the registers 710 and 720 are continuously
monitored ~or a start condition, either a start code r~ad in
a forward direction or a start code read in a reverse direc~
tion. When a proper start condition is detected, a more
positive signal STFD or STBD representing a start read in a
forward direction or a start read in a backward direction i5
supplied by the unit 740 and returned to the system 10 to
produce the same functions described above.
More specifically, these signals place the system
10 in a read condition, and the signal START applied to the
memory 740 rises to a high level to remove the decodiny logic
peculiar to detection of a proper start condition~ Further,
the gate 458 is inhi~ited as described above to prevent
interrogation o the memory 740 during the time defined by
~he signal 04 on each code area transition. As noted above,
this logic is used only in the detection of the initial start
condition and not the terminating start code so as to avoid
errors resulting from the initial or relative movament between
the record 12 and the reader 14.
As the reader 14 moves relative to the record 12,
the conditions or relations A and B determined by the bars
and spaces of the first character code are again supplied by
the adders 40 and 42 in the manner described above and are
supplied to the preset terminals P of the input stages of the
shift registers 710 and 720 under the control of the strobing
signal SS whlch forms an input to each of the gates 702 and
706. As set forth above, the strobing signal SS appears
only five times during the bit positions defined by the

:; :
77
.. . ., , .. . . . . - . .- , .... . - . - . -

8~)
signals J4-J7 and J0. Thus, only five bits are shi~ted into
the shift registers 710 and 720 during character translation.
At the time de~ined by the signals ~3 and J0, i.e., following
the reading of the ourth black bar in a character code, a
gate 734 is enabled to control the unit 740 to interrogate
the stages of the shift registers 710 and 720 for the purpose
of performing a parity check. The parity check gates which
can implement the logic functions defined in statement (22)
selectively provide a high or low le~el output signal PE/
in dependence on the results of the parity check. I:~ the
parity check is not satisfactorily completed, the system lO
is placed in an alarm condition in the manner described
above.
If, on the other hand, the parity check is satis-
factorily completed, the signal SRS developed by the gate 454
during the timing interval defined by the signal 04 i5 next
applied to the unit 740 so that the contents of the shift
registers 710 and 720 are examined and decoded into, for
example, BCD signals which are supplLed in parallel to the
output means 46.
~; This operation continues in the manner described
above until a minimum number of characters has been received,
as defined by position o the counter 644. I~hen a minimum
number of characters has been received, the signal 02G/ is
generated in the manner described above~ and the inverted
signal 02G is applied to one input of a NA~D gate 732. The
other input to this gate is provided by the signal J0.
Accordingly, at the end of each complete chaxacter following


iOG6810
the receipt of the minimum number oE characters~ '~he gate
732 becomes fully enabled during the time defined by the
si~nal 02 to control the memory unit 740 to interrogate the
contents of the shift registers 710 and 720 or a valid stop
code, i.e.~ the terminating stop code read in either a
forward or a reverse direction. Whenever such a condition
is determined by the memory 740, the proper one of khe
signals STFD or STBD is supplied, and the system 10 is reset
to a search mode in the manner described above.
Although the present invention has been described
with re~erence to a number of illustrative embod~ments
thereo, it should be understood that numerous other modif-
ications and e~bodiments can be devised by those skilled in
the art that will fall within the spirit and scope of the
principles o this invention.
What is claimed and desired to be secured by
~etters Patent of the United States is:



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~ 79 ~