Note: Descriptions are shown in the official language in which they were submitted.
18Back~round of the Invention
19Yield is a measure.of the success of a se~iconductor
device processing sequence in producing quality ~inished
21 chips or wafers which are acceptable for their intended uses.
22 It is known that yield is adversely effected by the occurrences
23 of certain de~ects which can be introduced at various stages
24 of the device processing sl~quence. Clearly, it is advantageous
to detect such occurrences at the earliest possible time so
26 that costly but futile additional processing steps normally
z7 required to complete the devices are not undertaken. More
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1 particularly, it has been found that the defect count
2 is a reliable predictor of yielcl of devices which are later
3 formed in the semiconductor material provided that the count
4 is limited to those defects which are electrically active,
i.e., current carrying defects or leakage paths which can
6 result in shorted junctions or emitter-to-collector shorts,
7 for example. Defects which are not electrically active are
8 inconsequential to the performance of later fo~med devices
9 and, therefore, are not to be included in the defect count.
Summar~ of the Invention
11 Electrically active defects a`re detected in N type
12 silicon substrates and epitaxial layers by the anodic
13 etching of the semiconductor material exposed to a hydro-
14 fluoric acid solution. In order to enhance the visual
15 discrimination between electrically~active defects and non- ;
16 electrically active defects (which do not affect device yield),
17 it is preferable that the concentration of the HF solution
18 employed be less than about 15~ and that the potential
19 difference between the solution and the semiconductor material
be set so that the width of the resulting depletion layer
21 below the surface of the semiconductor material in contact
22 with the solution is commensurate with the depth of the
23 active device area in the semiconductor material. Higher
24 concentrations of HF tend to initiate an unwanted relatively
low level of uniform anodic etching of the entire exposed
26 surface of the semiconductor material with the result that
27 the etch pits denoting the electrically active de~ects are
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1 less clearly distinguishable by visual inspection than in the
2 case where no back~round etching is produced. Higher potential
3 differences cause unwanted etch pits to appear denoting the
4 presence of inconsequential electrically active defects lying
below the active device area. The defect count is a reliable
6 predictor of the yield of satis:Eactory semiconductor devices
7 which are later formed in the semiconductor material.
8 Brief Description of the Drawing
g FIGURE 1 is a diagramatic sketch of the apparatus employed
in the performance of the method of the present
11 invention;
12 FIGURE lA is a plan view of the silicon wafer sho~n in cross-
13 section in Fig. l; and
14 FIGURE 2 is an out-of-scale enlargement of a portion of the
silicon wafer of Fig. 1.
16 Description of the Preferred Embodiment
17 Referring to Figure 1, semiconductor wafer 1 is sealed
18 to the opening 2 of synthetic resin polymer cup 3 by O ring 4.
19 Wafer 1 is supported against O ring 4 by stainless steel
fixture 5. Cup 3 is filled with HF electrolyte 6 in which
21 is immersed platinum foil 7. Power supply 8 provides a
22 potential difference which is applied between foil 7 and
23 fixture 5, making foil 7 negative with respect to fixture S.
24 Only the surface portion of wafer 1 interior to O ring 4
is contacted by electrolyte 6. Different surface portions
26 of wafer 1 may be exposed at different times to electrolyte 6
27 in order to obtain defect data across the Eace of the wafer.
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1 As indicated in Fig. lA, three separated surface regions 9, 10,
2 and 11 are anodically etehed at successive times. Alternatively,
3 the entire wafer may be anodieally etched at one time by
4 increasing the size of the opening 2 of cup 3. The number
of and si~es of the etched surface areas of wafer 1 is not
6 a critical aspect of the present invention.
7 Examining semiconductor wafer 1 in more detail with the
8 aid of Figure 2, wafer 1 comprises a P substrate 12 into
g whieh N+ subcollector 13 is diffused. N epitaxial layer 15
is deposited over the surface of substrate 12 under conditions
11 which permit subcolleetor 13 to ~iffuse partially into it.
12 - Eleetrieally aetive defeet 16 extends from subcolleetor
13 13 to the surfaee of epitaxial layer 15 which is in eontact with
14 eleetrolyte 6. Defeet 16 is typical of those which adversely
L5 effect device yield in that defect 16 will present a conductive
16 pathway from the eolleetor through a P+ base region to the
17 emitter of a transistor (not shown) whieh is later formed
18 in the epitaxial layer above subeolleetor 13 by subsequent
19 processing steps. Eleetrieally aetive defeet 16 aets as a
souree of holes in N type epitaxial layer 15. Said holes
21 migrate toward the overlying surfaee of epitaxial layer 15
22 under the influenee of the eleetric field extending aeross
23 the depletion region generated within epitaxial layer 15
24 by the potential differenee applied between eleetrolyte -
6 and substrate 12. As a rbsult of the migration of the holes
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1 to the surface of epitaxial laye~ 15 and into contact with
2 electrolyte 6, a pit 17 is etched into the surface of epitaxial
3 layer 15 directly over the location of defect 16. There being
4 no significant source of holes elsewhere within N type epi~
taxial layer 15 except at the s.ites of defects such as deect
6 16, there is no other silicon erosion.
7 Anodic processing of silicon wafers in HF solutions has
8 been employed previously to form porous silicon for device
g isolation, for electro polishing, and for wafer thinning.
Such applications, in common with the defect detection method
11 of the present invention, involve the dissoluti.on of silicon
,12 by an electro chemical reaction which requires~the presence .
~13 or introduction:o:f~holes. It is'believed that the initiation
14 ~iof silicon dissolution is hole (e ) dependent, in~.ac¢ordance
,15 with the expression Si.t 2HF + (2-n) e ~ Si F2,,+ 2H ~+-~:
16 ne where n < 2.
17 In N type silicon where holes are minority carriers,~
18 enhanced electr,o.chemical etching will occur wher.e~er holes
l9 -are inj,ected. ~Eleatrically active defect :sites ac-t as:re~
.~20 combi~ation-gqnera..tiion::,centers,in the N.type-.silicon and
,~21 ~provideiithis hol,e~in.jection on a::localized:basi,s tolprQd;uce~ , -
:~22 theietch pit,-~such~:as~pit 17, discussed aboye.i .Such~-etch~p!its
3 a~e7most easi.Ly.s.e.en whe,n.the concentration~oi.the.E~F iniithe~
~a4 ~-ele~c~olyte s~lu~tiQ~ 6;is less than akQut 15~ Concentrations ~ -`- . :
~5 .-.of about S~i;a]~eipreferred. .Evidence has beenl:obtained that . .-,.. ..
6 theleitch~.pits,/deno~tiing,:the presenc~ .Qf elect~ically,acti,ve .,.
~7 ~defe~ts-are llss. clearl~y distinguished:by~,viis~al.examination ::~
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1 when the concentration of the HF is increased abo~e about 15~.
2 It is believed that such increased concentrations of ~P
3 initiate anodic etching of the silicon surface in accordance
4 with the above-described electro chemical reaction in the
presence of randomly distributed hole sources at the surface
6 of wafer 1 due to unwanted impurities, surface states, dan~ling
7 bonds, excessive surface illumination, and the like. The
8 last-named silicon surface conditions, in the presence of
9 increased HF concentrations, cause the appearance of a surface
"haze" due to a low level anodic etching reaction which tends
11 to obscure the presence of the etch pits designat-ing the
12 presence of the electrically active defects which are of
13 interest in accordance with the present invention. However,
14 when the HF concentration of the electrolyte solution 6 is set
below about 15%, the surface "haze" effect is minimized or
16 eliminated.
17 It can be seen that not all electrically active defects
18 are of consequence in terms of device yield. Those electrically
19 active defects which lie below the active device area in the
silicon wafer in most cases will not adversely effect the~
21 performance of the semiconductor devices (bipolar transistors,;~
22 etc.) which are later formed in the active device area of the
23 wafer. In accordance with the method of the present invention,
24 etch pits~are avoided with respect to electrically active
25 defects lying below th~e active device area of the wafer by -~
26 setting the amplitude~of the potential applied between the
27 electrolyte 6 and the wafer 1 so that the width of the ~
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1 depletion region produced within wafer 1 is commensurate with
2 the depth of the active device area, i.e., the depth af the
3 collector-base junction of the vertical bipolar transistors
4 to be formed in wafer 1. Consequently, electrically active
defects lying below the base region in epitaxial layer 15
6 within substrate 12 lie below the depletion region so that
7 any holes injected thereby experience no significant electric
8 field and are not driven to the surface of epitaxial layer lS.
g In the absence of holes at the surface of epitaxial layer 15,
10- no etch pits are developed corresponding to electrically
11 active defects lying below the active device region of the
12 silicon wafer which is the desired result.
13 Upon the completion of the anodic etching method of
14 the present invention, wafer 1 is removed from the apparatus
1`5 of Fig. 1 and visually examined by any convenient technique
16 such as microscope inspection, infrared TV camera and monitor,
17 etc. The presence of one or more etch pits within a known
18 critical surface area of wafer 1 is a reliable predictor
19 that any device later formed within that critical area will
be unacceptable. Alternatively, the number of etch pits per
21- square surface area has been found to correlate closely with
22 device yield. The anodically etched wafer surface areas may
23 be predetermined portions o actual product wafers or the anodic
24 etching may be done on test wafers which had been subjected to ; ~;
the same processing steps as the product wafers. In either
26 event, the appearance of etch pits in critical wafer surface -
27 areas or in excess of an allowable surface area density (count)
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1 reliably establishes that the wafers tested and all those
2 which are untested but fabricated with the same process
3 steps as the tested wafers will not yield good devices.
4 Accordingly, those further costly but futile manu$acturing
steps ordinarily required to complete the desired devices in
6 the tested wafers ara not undertaken thus minimizing the
7 fabrication investment in material that in any event would
8 be scrapped eventually.
9 While the invention has been partic~larly shown and
described with reference to the preferred embodiment thereof,
11 it will be understood by those skilled in the art that various
- 12 changes in form and details may be made therein without
13 departing from the spirit and scope of the invention.
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