Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to digital pulse communication
systems and more particularly to a device for signal conversion
between one and the other of a digital ~it stream and an
amplitude variant analogue signal, such as speech. Such
a aevice may be xeferrea to as an analogue/digital (A/D) or
digital/analogue (D/A) convertorO A more general term which
encompasses ~/D and D/A convertors is the term codec.
In discussing the prior art, reference will be made
to the accompanying drawings which will now be introduced.
Accordingl~, in the drawings:-
Fig. 1 is a block diagram of delta encoder according
to the embodiment for converting an analogue signal to a
digital bit stream,
Fig. 2 is a block diagram of a delta decoder according
to the embodiment for converting a digital bit stream to an
analogue signal,
Fig. 3 is a circuit diagram of an anti-logarithmic
convertor and a current pulse amplitude modulator of the
embodiment of Fig. l and 2,
Fig. 4 is a circuit diagram of a compand current
pulse unit of the embodiment of Figs. 1 and 2,
Fig. 5 is a typical prior art delta encoder,
Fig. 6(a) and 6(b) show graphs of intermodulation
distortion against input signal level for the prior art encoder
of Fig. 5 and Fig. 6~bj includes a curve representing a level
500Hz; lOOOH~ com~onents of delta modulation with average peak
slope companding of the present invention,
Fig. 7 shows a graph of linearity of gain against
input level o a typical prior art encoder as shown in Fig. 5,
Fig. 8 shows a graph comparing syllabic companding
with the average peak slope companding of the present invention,
and
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Fig. 9, which appears on the same sheet of drawings
as Fig. 5, is a further graph showing the reconstruction
step si~e for syllabic companding and the average peak slope
companding of the present invention.
Throughout the drawings like reference numerals
indicate ~ike or similar parts.
Generally speaking analogue to digital conversion
falls into two important classes, namely:
(i) Pulse Code Modulation ~PCM) wherein the analogue
signal is amplitude sampled at a frequency fs, the sample is
encoded in an n-bit binary word and data of rate n.fs is
generated, and
(ii) Delta Modulation (DM) wherein the analogue signal
is approximated b~ a series of positive or negative slopes
which combine to form a reconstruction signal and each data
bit transmitted is the polarity of the reconstruction slope
at any instant.
In telephone networks the standard for PCM is the
CCITT system where the input signal is sampled at 8K~z and an
8 bit word generated according to the A-Law companding. Such
a standard snsures good voice transmission performance but
PCM codecs are generally more complex and therefore more costly
than delta ~odecs.
Published literature shows many delta modulation systems
utilizing companding and such systems are capable of good voice
transmission performance but the performance for objective
transmission parameters, or example, linearity of gain at
different input levels and the level of intermodulation
distortion products is below the standard expected of high
quality analog~e to digital conversion for telephony use as
set forth, for example, in the abovementioned CCITT standard.
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The literature also indicates that for optimum voice
performance the companding rates should be syllabic. Syllabic
companding tends to adjust the reconstruction step size to the
mean slope of the lnput signal averaged over the syllabic decay
time constant. A typical system of this kind is illustrated in
Fig. 5 and is similar to a system developed by Phillips and des- -
cribed in an article by K.T. ~lanser and S.J. Zarda, "The design
of digitally delta modulation codecs" Proc. IREE, July, 1971
P286-295. In Fig. 5 the compand logic 27 detects slope overload,
that is, the occurrence of four 'ones' of four 'zeros' in shift
register 24 and on occurrence ~he current pulse unit 2~ delivers
a current of magnitude +Ia to the compand control capacitor Cc
and thus the reconstruction step size is increased. If four ~-
~ones' or four 'zeros' do not occur, then Vc (the voltage on Cc)
is decayed through resistor Rc. The attack and decay rates of
this system are such that companding is approximately syllabic.
The prior art system shown in Fig. 5 will only give an
acceptable level of intermodulation distortion over a limited
range of input levels and only at the lower input frequencies as
will become apparent below with reference to Figs. 6(a) and 6(b).
The linearity of gain with input level is only acceptable at high
input levels as mentioned below and shown in Fig. 7. The voice
transmission quality on this typical prior art system shown in
Fig. 5 is reasonable with some distortion of transient voice
sounds, that is, sounds such as "ta".
~ s mentioned above syllabic companding tends to adjust
the reconstruction step size to the mean slope of the input sig-
nal averaged over the syllabic decay time constant. Thus the
compand control (reconstruction step size) simply cannot follow
instantaneous high slope regions of the input signal. The opera-
tion of this type of coMpanding is shown by reference 65 in Fig.
8. The fl + f2 slnosoid type of input signal 64 has instantan-
:
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eous high slope regions (a) and instantaneous lo~ slope regions
(b).
Note:
The signal has in fact regions of zero slope at (C), so
the use of "instantaneous" high or low slope is not strictly cor-
rect. Instantaneous refers to the slope at zero crossing.
Syllabic companding will adjust to the average step
size over many cycles, that is, an integration time much greater
than 1 _ and so the reconstruction step size set will beless
fl f2 than optimum to track the high slope regions of
the signal, and severe slope overload occurs as the companding
averages the high and low slope regions of the signal. Thus ~or
a delta modulation system to have a low level of intermodulation
distortion the companding must set the reconstruction slope
according to the average of the peak or high slopes; hereinafter
referred to as "average peak slope". Thus the reconstruction
step size will attack in region (a) and decay in region (b) of
the signal, that is, adapts to follow the peak slope. It has
been determined from experimental results that the important
requirement for low intermodulation distortion is that the recon-
struction tracks in region (a), because slope overload produces
the intermodulation products. Slight over tracking in the region
(b) Fig. 8 (caused by a reconstruction signal above optimum) will
tend to produce granular noise (approximately white in the voice
~requency range) but such noise is acceptable because it does not
adversly a~ect the voice transmission performance or the ob~ec-
tive transmission parameters discussed above. Thus it is not as
important to decay the step size in region (b) as it is to
increase step size in region (a).
There are prior deIta systems having true instantaneous
companding, that is, the companding is set by instantaneous slope
and not average -~
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. :..: -
peak slope as in ~le p.resent invention. Thus the step size of such
a system does decay in region (c) of Fig. 8 which enables ~ore accurate
tracking in the region of high level signals but such systems suffer the
disadvantage of poor tracking capabilities each time an input signal
having an instantaneous high slope occurs after an input signal having
an instantaneous low slope, that is, when a signal such as in regic,n
(a) of ~ig. 8 occurs immediately after a signal such as in region (b).
q~lis poor tracking produces unacceptable interm~dulation distortion
characteristics. Another prablem with such a sysbem is the wide dynamic
range required of step size to follow the instantaneous ccmp mding law
at all times~ that is, requiring t~pically 20dB mKre range th2n a syllabic
or type of this inventian.
The object of this invention is to provide an improved delt~
~odulation codec which is capable of good voice transmussion perform~nce
an~ which provides Improved objective ~ransmission paramebers over the
prior art syllabic and instantaneous co~panded delta ~odulation sysbems
discussed abcve.
In order to realize the above object the present inventian pr~vides
C~rpan~hDg whioh tends to adjust step size bo the average peak slope
2Q ~ver a short time ~say _ 1 where ~1 and f2 are the two different
fl f2
frequencies shown in Fig, 8), and not to the instantænecus slope by any
de~inition. For input sign21s such as speech with peak level to average
level ratios of 12 ~ 15 dB, this type of average peak slope c~nçxrflng
allows mDre accurate encoding d speech sounds with a high transient
factor, that is, sounds like ta, pa, etc. as discussed below with reference
to Fig. 9 and shown by reference 66 in Fig. 8. ~ ;;.
l`hroughout this specification the tern "average peak slope ccnpanding"
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.,.
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. . . . . .
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is used to mean that the companding adjusts to the average of the
high slope reyions of the input signal as opposed to syllabic or
instantaneous companding.
The "average peak slope companding" oE the present
invention cannot beachieved by simply increasing the attac~ and
decay rates of typical syllablically companded delta modulation
systems or reducing the attack ra-tes of typical instantaneously
companded delta modulation systems. For one thing a defined non-
linearity must exist within the encode/decode compand loop to
ensure that the "average peak slope companding" occurs and is
established over a wide range of analogue input levels. The ;;
defined non-linearity establishes a relationship between attack
and decay time and input signal level, thus ensuring "average
peak slope companding" over a wide dynamic range. For special
types of input signal (not necessarily voice frequency) a suit-
able non-linearity may be chosen to given optimum compand control.
A known system employing a non-linearity in the compand
loop is disclosed in U.S. Patent 3,699,566 by Schindler and
assigned to the IBM Corporation. Further reEerence to the
Schindler system may be found in an article entitled "Delta
Modulation'i by H.R. Schindler published in IEEE Spectrurn October
1970 P. 76. However, the compand step size of Schindlers'
system indicates that companding approaches instantaneous com-
panding because of the high attack and decay rates, 2dB and 0.2
d~, respectively, per sampling interval. Therefore this
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system would be expected to suffer the inherent probem of
unacceptable intermodulation distortion discussed above.
Without the non-linearity in the compand control
loop then attack and decay times would increase proportionally
to the input signal level. Thus the companding would be
optimum at onl~ one input level. The syllabic system discussed
previously has this characteristic. For signal levels above
this optimum level the attack/decay times would be too long,
so severe slope overload would occur. For signal levels
below this optimum the attack/decay times are too short and
unstable encoding would occur~ Thus the non-linearity chosen
in the present invention is logarithmic such that the attack
and decay rates are independent of signal level.
Accordingly, the present invention provides an average
peak slope companded delta codec for converting an analog
signal to a diyital signal comprising: comparator means
receiving saia analog signal and a variable raconstruction
signal for converting said analog signal to a digital bit
stream, detecting means for detecting the presence of at least
one preselected sequence of bits in the digital bit stream,
means responsive to said detecting means for generating an
attack/decay signal which increases upon the occurence of said
preselected sequence and decreases upon the non-occurrence of
said preselected se~ence, converter means receivng said attack/
decay signal for providing a compand signal which is substan~
tially an anti~logarithmic function of said attack/decay signal,
means for accumulating said compand signal to form said
variable reconstruction signal, and polarity inverting means
for invertlng the polarity of said compand signal when said
3Q reconstruction signal exceeds said analog signal, thereby
causing said reconstruction signaI to change in value toward
the value of said analog signal during each bit period, said
~ . ' .
compa~ding adjusting to the average of thc high slope regions
of said analog input signal.
Referring now to Fig. 1 it is seen that the encoder
of this embodiment includes a comparator 20 which has two
inputs 21 and 22 respectively. An analogue input signal on
input 21 is compared with a feed~ack on input 22 and the
comparator provides an output in the form of a high or a
digital 'one' when:.the analogue signal exceeds the feedback
signal and a low or digital 'zero' when the feedback signal
exceeds the analogue signal ! The comparator is clocked at
64KHz and its output 23 is a digital bit stream of 'ones' and
'zeros' depending upon the values of the analogue input and ~ . -
the fPedback signal relative to each other.
The output 23 of the comparator 20 is connected to
the input of a four bit shift register 24. The output 25
of the shift register is the digital bit stream which is sent
to line. Since the data on the output :.
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25 is the same as the data on the input 23, except that it is
delayed by four clock periods, it is conceivable that the line
connection could be made at the input 23 of the shift register
24. The 64 K~z clock signal for ~he device is provided on con-
nection 25 to the shift register 24.
The shift register 24 has each stage connected to a
compand logic unit 27. The compand logic unit 27 comprises a
number of gates and detects the occurrence of four 'ones' or
four 'zeros' in the shift register ~4. The output from the com-
pand logic unit 27 is connected to a current pulse unit 28.
During the period when the compand logic unit 27 detects four
'ones' or 'zeros' in the shift register it pulses the current
pulse unit 28 to activate -the curren-t pulse unit to provide, at
its output 29, a constant current of positive polarity durin~
the time it is activated. During the period when the compand
logic unit ~7 does not detect four 'ones' or four 'zeros' in the
shift register 24 the current pulse unit provides, at its output
29, a constant current of negative polarity.
Choice of attack and decay rates determines the type of
companding. By choosing both attack and decay rates long the
companding is said to be syllabic, that is, the companding aver-
ages slope and sets step size according to the average slope of a
syllable of speech. If both the attack and decay times are short
the companding i9 said to be lnstantaneous, that is, the compand-
ing varies companding step size proportional to the actual instan- -
taneous slope of the input signal. It has been discovered that
if the attack times are short and the decay times long then the
companding behaves such that the step size is set to average peak
slope.
Considerable experiment has been conducted during the
development of the invention to find the optimum attack and decay
rates. The experiment considered the subjective voice perform-
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ance and objective performance (such as intermodlllation dis~or
tion). The optimum attack rate was found to be 0.7dB/clock pulse
and attack to decay ratio of 100:1. The optimum is quite broad
and reasonable performance is obtained well outside this choice
of companding parameters. The attack rate may be reduced to say
Q.25dB/clock pulse and increased to 3dB/clock pulse and the
attack/decay ratio varied from 30:1 to about 500:1 with some
degradation of performance. It is interesting to note thai as
the attack rate is reduced, that is, the companding tends towards
syllabic, the performance degrades and as attack/decay ratio is
reduced, that is, the companding is tending toward instantaneous
the performance again degrades thus indicating the improvement in
performance with average peak slope companding as opposed to the
prior art.
:
As mentioned above the range of attack rate and attack
to deca~ ratio where average peak slope companding is defined as:
attack rate in the range .25dB/clock pulse to 3dB/clock pulse and
attack/decay ratio in the range 30:1 to about 500:1. The system
will give good performanae over this range and even slightly out-
side the range but the optimum lies within the range. The actualchoice of optimum depends on the signals for which the system is
intended. If the system is for voice only then the optimum wi~
be different than if the system is for transmission o sinosoidal
signal but will still lie in the abo~e range. The optimum (attack ~ -
rate 0.7dB/clock pulse and 100:1) is the optimum for a system ~
.
designed to pass speech as well as sinosoidal signals when the
clock. rate is 64KHz and the detected sequenae is four bits long.
If other clock rates and sequence lengths in the same order are -
used then the optimum will still lie in the range but for these
other systems there could be some small areas of the range where
the system does not provide acceptable results.
In this embodiment positive aurrent from the current
_ g _
:. - . . .- .
pulse unit 28 provides the attack current to cause the recons-truc-
tion or feeclback signal to increase invalue towards the analogue
signal and the negative current from the unit 28 provides the
deca~ current which reduces the magnitude of the change in the
feedback signal when the feedback signal has exceeded the analogue
signal, as will be described hereinafter. The positive current
from the current pulse unit 28 is in the order of 100 times the
negative current in this embodiment but may be trimmed to alter
the relationship. During the period when the constant current
device is activated the positive output current thereErom charges
a compand integration capacitor 30 to cause a linear build up of
voltage across the capacitor. The value of the capacitor 30 and
the positive polarity current are selected such that during a
clock period (15.6 ~s) the voltage build up across the capacitor
is about 100 mV each time four 'ones' or four'~erS~ occur.
As explained above the value of the current may be trimmed and
thus the rate of voltage build up may be altered. During a clock
period when the constant current device 2~ supplies negative
polarity current to the capacitor 30 the capacitor is discharged
and the voltage decrease across the capacitor 30 is about lmV.
The voltage across the capacitor 30 is supplied to an
anti-logarithmic converter 31. The anti-logarithmic convertor
31 is arranged such that lts output 32 is an anti-logarithmic
current function of the input voltage as is illustrated in equa-
tion (3) below. Therefore, for low voltages across the capacitor
30 a change in voltage will cause the output current -from the
anti-logarithmic convertor 31 to change by a lesser amount
whereas for higher voltages across the capacitor 30 the same
voltage chan~e will produce a much greater current change. It
:`
should be apparent that when the rate of occurrence of four
'ones' or 'zeros' in the shi~t register 24 is high the voltage
on the capacitor 30 is high, that is, the compand voltage is high.
:- .
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34
The action of the anti-logarithmic convertor in the
companding feed~ack loop makes at-tack rate independent of signal
input level. The attack time ~or a signal to attack from -40dB
to -30dB is the same as to attack from -lOdB to OdB; the OdB
pOint is some arbitrary reference. Thus the attack rate is
expressed as dB per time interval. A system which has attack
rate (expressed in dB/time interval) constant with input level
must have some anti-logarithmic element in the compand feedback
circuit. The attack to decay ratio does vary slightly with input
level because of the time constant formed by capacitor 30 and
resistor 3~ plus resistor 40. For a ratio of attack -to decay
current of 100:1 the attack to decay ratio of reconstruction
signal may be say 70:1 for high input levels and 130:1 for low
input levels.
The output 32 from the anti-logarithmic convertor is
connected to a current pulse amplitude modulator 33. The modu-
lator 33 supplies an output current which is proportional to -the
voltaye siynal from the anti-logarithmic convertor 31. The cur- -
rent from the modulator 33 is supplied to an integration network
34 which converts the current signal to a voltag~ signal to be
fed back to the comparator 20 on the connection 22. The voltage
on the connection 22 is the reconstruction or feedback voltage
which follows the analogue input signal. As previously explained
the output of the comparator 20 depends on whether the analogue
signal is greater or less than the feedback signal. In addition
to the signal from the anti-logarithmic convertor 32 the mod~la-
tor 33 receives a digital signal via connection 35 from the first
stage of the shift register 24. The digital signal to the modu-
lator 33 is a polarity connection which establishes the polarity
of the step change in the feedback signal to the comparator. For
example, if a 'zero' appears on connection 35 immediately after
a 'one' has appeared the polarity of the step change in the feed-
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back signal is rev2rsed since the feedback signal has exceeded
the analogue input signal. For a Iflat' analogue input to the
comparator the bit stream to -the shift register 24 would com-
prise alternative 'ones' and 'zeros' and the polarity of the
step change would be reversed for each successive clock period.
The decoder according to this embodiment is shown in
Fig. 2 and is essentially the same as the encoder described
above with the exception that the comparator 20 is eliminated
and a filter 36 is included. The transmitted digital bit stream
enters the shift register 24 on input 25 and each bit is succes-
sively clocked into the shift regis-ter. The remainder of the
device is iden-tical to the encoder down to the integration net-
work 34. The voltage signal out of the in-tegration network 34
of the decoder is the same as the feedback signal on the connec-
tion 22 of the encoder and is therefore a signal which approxi-
mates the original analogue input signal. The filter 36 serves
to smooth ou'c the signal from the integration network 3~ to pro-
vide a signal at its output 37 which closely approximates the
original analogue signal.
Reference should now be made to Fig. 3 which is a com-
bined circuit dia~ram of the anti-logarithmic convertor 31 and
the current pulse amplitude modulator 33. The voltage across
the capacitor 30, hereinafter called Vc, is applied to the anti-
logarithmic convertor 31 on connection 29 and is applied via
resistor 38 to the base of transistor 39. The base of transistor
39 is coupled via resistor 40 to the base of a further transistor -
41. The two resistoxs 38 and 40 form a voltage divider network.
The transistor 39 is supplied with a constant collector current
Ia by means of a feedback network including an opera-tional ampli-
fier 4~ and a resistor 43. The current Ia is derived from a posi-
tive power supply voltage 44 which, in -this case is +5V, and is
dependent on the value o~ a series resis-tor 45 (Ia = 5 ). The
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base of transistor 41 is connected -to a negative power supply
voltaye 46 which, in this case is -5V.
l'he operation of -the anti-logarithmic convertor relies
on the collector current (Ic) - base emitter voltage (VBE) charac-
teristic in the forward biased mode of a transistor illustrated
by the following equation (l):
q BE
Ic = Io exp- (l)
where q = electron charge (Coulombs)
K = Boltzman's constant
T = absolute temperature ( K)
Io = constant of the transistor
The equation illustrates the logarithmic transfer ratio.
The emitter voltage of transistor gl is controlled by the low
impedance, temperature compensated emitter of transistor 39, that
is, the emitter voltages of the two transistors are controlled by
Vc in the ratio;
38 ~ c (2)
where R40 is the ohmic value of resistor 40, R38 is the ohmic
value of resistor 38, and VBB is the base to base differential
between the two transistors. Since Ic of transistor 41 is shown
as IR from the current pulse amplitude modulator 33 then,
IR = Ia exp. ~ q (Vc 40 ~ -
~ KT R38 + R40 J
The current IR is switched in polarity by the current
pulse amplitude modulator 33. If the voltage on the polarity
connection 35 to the modulator 33 is greater than a reference
voltage 47 on the base of a transistor 48 then a further tran-
sistor 49 is switched on and a current IR flows from the integra-
tion network 34 (Fig. l and 2) into the collector of transistor
~ . ' ' '
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49. If the voltage on the polarity connection 35 is less than
the reference vol-tage 47 then transistor 49 is OFF and -transistor
48 is ON. Thus IR flows from matched transistors 50 and 51 con-
nected as a current mirror and a current IR flows from the col-
lector of transistor 51 into the in-tegration network 34 on con-
nection 52.
Reference should now be made to Fig. 4 which shows the
circuit diagram of the compand current pulse unit 28. This uni.t
is similar to the modulator 33 and consists essentially of four
transistors 53, 54, 55 and 56 connected together as shown. Refer-
ence 62 represents a constant current source. The connection 29
is to khe anti-logarithmic convertor 31 and capacitor 30 whilst
the connection 58 is.the connection from the compand logic unit
27 and is applied to the base of transistor 54 via resistor 59~
If the voltage on the connection 58 (hereinafter called compand
control) is greater than the reference voltage 47 then transistor
5~ is ON and a current Ia flows from the capacitor 30 into the
collector of transistor 54. If the voltage on the compand control
is less than the reference voltage 47 transistor 53 is ON and
~20 transistor 54 is OFF. The voltage across resistor 60, call VR
is equal to the product IaR where R is the ohmic value of resis-
tor 60. A further re~istor 61 connected to the emitter of tran-
sistor 56 has a value of dR where d is selected in this case to
be 100. The voltage acro~s dR is approximately equal to IaR and
therefore a current of approximately Ida flows from the collector
: of transistor 56 into the capacitor 30. By adjusting the value
of resistor 61, that is, by altering d, the relationship between
the attack step size and the decay step size may be varied and
any ratio within:the limits defined above will produce acceptable
results although a ratio of 100:1 with an attack rate of 0.7dB/ .
clock pulse provides optimum performance. ;
The operation of the A/D convertor of Fig. 1 may be ;:
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understood by corlsidering a sinusoidal inpu-t to the comparator 20.
Ini-tially, as the sine wave rises there is no feedback signal and
the firs-t bit from the comparator is a digital one. The 'one' is
sent to tne shift register 24 an~ is gated into the first slot.
The digital 'one' in the firs-t slot is -transmitted to the modu-
lator 33 by the ~olarity connection 35. The modulator 33 causes
a signal to be fed back to the comparator 20 and -the s-tep size of
this feedback signal is very low and depends on the value of
background noise entering the system prior -to the sinusoidal
input. During the next clock period -the feedback vol-tage is
still far below the analogue signal and thus a further 'one' is -
' sent to the shift register and the original 'one' is shifted
into the next slot.
~ The polarity connection 35 outputs the modulator 33 in
the same manner as before and a further feedback signal of the
same step size as before is added to the previous signal and fed
back to the comparator. The operation continues in this manner
and the feedback signal increases approximately linearly until
four 'ones' appear in the shift register 24. On de-tection of
four 'ones' the logic unit 27 pulses the current pulse unit to
cause aconstant currentto befed into the capacitor 30 to thus increase
the step size of the signal added to the feedback signal. The
feedback signal is -thus caused to 'attack' the an~logue at a
greater rate than before. However, the signal through the anti-
logarithmic convertor 31 is, as yet, of a low level and therefore
the output of the anti-logarithmic convertor is lower than its
input. The feedback signal is still less than the analogue sig- -
nal and during the next clock period a further 'one' bit is sent
from the comparator 20 to the shift xegister 24. The logic cir-
cuit again detects four 'ones' in the shift register and pulses
the constant current device to further increase the step size of
the signal added to the feedback signal. The process continues
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as each further 'one' ~oes in-to the shift register 2~. However,
the input signal to the anti-logarithmic convertor 31 quickly
reaches a value such that the output therefrom exceeds the input.
Therefore the rate at which the feedback signal 'a~tacks' the
analogue signal increases rapidly and the feedback signal soon
exceeds the analogue signal. On the first clock pulse after the
feedback signal has exceeded the analogue signal the comparator
20 outputs a 'zero' into the shift register 24. The logic unit
27 does not detect four consecutive similar bits and therefore
there is no output to the current pulse unit 28. The current
pulse unit 28 therefore supplies a -ve polarity current which
commences discharging the capacitor 30 and reducing the voltage
Vc to the anti-log converter 31. Also, the polarity connection
35 is now a 'zero' so that the step change of the feedback sig-
nal is subtracted from the previous value. The value of the step
is less than for the previous clock period due to the lesser
charge on the capacitor 30.
The feedback signal will continue to overshoot the
analogue signal in opposite directions, but each time by a re-
duced amount until the minimum step size is reached and over-
shooting is at a minimum.
As stated above E'ig. 5 shows a typical prior art delta
encoder. In the figure the output of pulse amplitude modulator
33 is a current ir and the current ir (' Signal PX Constant Vc) ;
is fed to integrator network 34. The ou-tput from integration
net~ork 3~ provides a signal on connection 22 for comparison
with the analogue input signal by comparator 20. The output of
comparator 20 is a digital bit stream on connection 23. The
remaining parts of the encoder of Fig. 5 have been disc~ssed in
3~ the introduction hereinabove. Most parts of the encoder of
Fig. 5 are similar to parts of the encoder of the present inven-
tion and thus corresponding reference numerals have been used.
.
- 16 - ~
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In -the graphs of Figs. 6(a) and 6(b) the axis 16 repre-
sents the input level (ds) and the axis 15 represents the level
of intermodulation distortion (IMD) measured in (dB). Fig. 6(a)
shows typical levels of ~OOHz products 17 and 1600Hz products 18
for an encoder such as that shown in Fig. 5 for an input signal
combining fre~uencies of 400Hz and 1200Hz. Similarly, Fig. 6(b)
shows typical levels of 500Hz products 67 and lOOOHz products 68
for an encoder of the type shown in Fig. 5 Eor an input signal
combining frequencies of 1500Hz and 2000Hz. Also shown in Fig.
6(b) is a graph 69 of the typical level of 500Hz and lOOOHz com-
ponents of delta modulation using the average peak slope compand-
ing of the present invention.
Fig. 7 shows the typical fall off in linearity of gain
~ at low input levels with the prior art devices such as that shown
; in Fig. 5. The axis 13 represents the output level in dB and the
axis 1~ represents input level in(dB)~
Fig. 8 shows the operation of both the average peak
slope syllabic companding utilised in this invention as well as
the syllabic companding of the prior art for an analogue input
signal whose root mean square voltage (RMS) is constant but which
has larger variations of slope over a single cycle. The syllabic
compandlng shown by reference 65 adjusts step size approximately
proportional to the average slope over the syllabic time constant
and thus the step size is not of suEficient magnitude to track
the high slope regions of the signal with low distortion. A
system with the average peak slope companding of the above
embodiment as shown by reference 66 can change step size within
the signal period and therefore can adjust step size to follow
the instantaneous high regions with rninimum distortion. ;
Fig. 9 shows the reconstruction step size for the
average peak slope companding of the present invention compared
with the prior art syllabic companding. In the graph of Fiy. 9
- 17 -
' ' , ''~.. ' ......... . ,' ~ ,'~
-l.V'~
the line 10 defines the envelope of the input signal, the line
11 defines the reconstruction step size for average peak slope
companding and the line 12 defines the reconstructi~n step size
for syllabic companding.
It should be appreciated from the above that the pre-
sent invention provides a considerable improvement over prior
art devices. By setting the compand parameters such that the
companding controls reconstruction step size to average peak
slope the overall performance exceeds that of delta modulation
systems with syllabic or instantaneous companding.
According to a modification of the above embodiment
the companding may be arranged to detect more or less than four
bits of data by altering the number of bits in the shift register
24 and accordingly the compand logic unit 27. Also the anti
logarithmic convertor could comprise a resistive device which
is capable of producing a number of linear functions of different
slo~es which approximate the continuous anti-logarithmic func-
tion of the above embodiment but such a modification would comp- ;
licate the device unnecessarl1y. Naturally voltage levels and
frequencies may also ~e varied to suit particular applications
of the device. The embodiment described hereinabove has particu-
lar utility in a digital PABX telephone system.
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