Note: Descriptions are shown in the official language in which they were submitted.
RAV-101 1~7~58
INTRODUCTION
This invention relates to data recording and re-
trieval systems for use in connection with musical instruments
whereby data defining a musical performance may be spontane-
ously recorded for later reproduction via the same or anotherinstrument.
BACKGROUND OF THE INVENTION
It is well known that musical instrumentsl such as
pianos and organs, may be controlled for the reproduction of
a musical presentation by way of prerecorded data. The best
known form of prerecorded data is the so-called "piano roll"
which is essentially a punched paper tape having at least 88
channels which are read in parallel to control the actuation
of the piano keys. The preparation of the prior art piano
roll is a painstaking and expensive process and is not sus-
ceptible to spontaneous generation or modification to any
significant extent.
A more recent development in apparatus for recording
a musical performance for subsequent reproduction involves
the use of a tape recorder and a system for recording key
depression data on the tape in a single or double channel
time-multiplexed sequence thereby to permit the tape to be
replayed and demultiplexed to reproduce the musical presenta-
tion. This system has the advantage of eliminating the
2~ tedious preparation of the piano roll and permitting both
carefully and elaborately prerecorded performances as well
as spontaneously prerecorded performances to be reproduced
as often as is desired.
The prior art tape recorder system involves the
production of a relatively fixed frequency sinusoidal waveform
which is broken up into scan frames of predetermined length.
Each scan frame comprises the serial combination of eighty or
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RAV-101
more data units represented by sinusoid cycles, each unit
being assigned a count and each count representing a piano
or organ key or some auxiliary function, such as expression.
The prior art system comprises an elaborate mechanism includ-
ing circuitry for amplitude modulating the sinusoidal waveformwithin each data unit of the scan frame such that a high
amplitude level represents a "sync" pulse, an intermediate
amplitude represents a "key-on" signal, while a low amplitude
signal represents a "clock" quantity. In short, the count
of the sinusoidal excursion identifies the particular key
within a scan frame and the amplitude level of the waveform
excursion represents the particular function to be performed
with respect to that key or, in the absence of a key function
code, the excursion is used to resynchronize during the decode
operation.
The ùse of such precise amplitude modulation as
is described above within a tape recorder system is extremely
difficult and typically calls for high-cost, precision record-
ing equipment so as to minimize output signal amplitude
variations due to such error causing factors as tape speed
changes, tape stretching, circuit drift, and other factors.
In brief, the accurate encoding and decoding of data using no
less than three distinct amplitude levels in extremely short,
serial data units is an extremely difficult task, giving rise
to prohibitive cost factors where a commercial unit for home
entertainment is concerned.
BRIEF DESCRIPTION OF THE INVENTION
The present invention provides a data recording and
retrieval system especially for use in combination with
musical instruments such as pianos whereby musical performances
may be spontaneously recorded and reproduced and, moreover,
wherein the system is well adapted for implementation using
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~74~58
low cost home entertainment type tape recordin~ equipment, such
as cassette tape recorders and tape decks. In general, this is
accomplished by means of a system for recording a stream of
data in a serial recording medium, such as a magnetic tape, using
a binary code wherein the recorded waveform comprises only first
and second relative signal levels and relatively abrupt coded
transitions between said le~els thereby to render the code and
the demodulation system completely independent of absolute
amplitude levels and th.e need for analog amplitude detection,
threshold detection, or other absolute monitoring devices. In
the preferred form the data is recorded in a self-clocking
binary waveform wherein the key depression signals as well as
the clock signal are represented by the positions of transitions
between thè binary leveIs and the levels or amplitudes themselves
have no significance whatever. Accordingly, a single channel
tape may be employed for the recording of self-clocking data `
from which both ke~ depression data and clocking data may be
readily retrieved.
A further feature of the present invention is the
expanded data encoding efficiency which results from the use of
transition encoding and the consequent capability of the
recorded waveform to actuate or control auxiliary devices such
as rhythm accompaniments and video displays in synchronism
with the reproduction of the-musical performance. In general,
this is accomplished by allocating certain data units within a
scan frame to the recording of the auxiliary drive data in the
same transition code between binary signal levels as the musical
data itself and, ~during demodulation, segregating such signals
and using such signals for the direct excitation and control of
the auxiliary dev.ices. :.
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Thus, in accordance with one aspect of the invention,
there is provided, in a keyboard musical instrument having
selectively actuatable key depression devices for producing
music and a plurality of input data signal generating means
operatively associated ~ith the said selectively actuatable key
depression devices for producing input data signals representing
the depression of discrete keys of said keyboard instrument at
discrete times in the production of music; scanning and sampling
means for scanning and sampling said input data signal generating
1~ means during a fixed lengt~ scan frame and at a rate higher
than the rate of occurrence of the key depressions producing
said input data signals and for converting the scanned input
data signals to a serial waveform, logic circuit means for
combining said serial ~aveform with a clock signal to produce
a recording waveform including serially arranged frames of data
units ~hich occur as a junction of the rate of said clock signal
and withi~ which`scan frames said input data signals as sampled
have a predetermined order, magnetic recording means for
recording said serial waveform onto a magnetic recording medium
as a serial sequence of abrupt magnetic flux transitions between
first and second magnetic signal levels so as to be self-clocking
during retrieval, playback ~eans including means for detecting
said abrupt magnetic flux transitions, and ignoring magnetic
flux amplitude variations, means for producing a serial waveform
having abrupt signal t~ansitions corresponding to said abrupt
magnetic transitions, means for decoding said signal transitions :. :
for retrieving sa:id clock signal in the serial waveform from
said magnetic recording-medium, means controlled by said clock
signal for cyclically reconverting the serial waveform of input
data signals into parallel form and means for applying the ;
input data signal~ as reconverted to key depression devices of a ~ -
keyboard musical to reproduce the recorded musical production.
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~6~7~158
In accordance with another aspect of the invention
there is provided a musical data storage and retrieval system
for use in operating an electrically controlled music generat-
ing instrument having selectively actuatable music generating
devices comprising: storage means containing a serial sequence
of timing and musical binary information for operating said
music generating dev~ces, said timing and musical information
being constituted by relatively abrupt transitions between first
and second signal amplitude levels and the clock and music
control data for each said selectively actuatable music generat-
ing device, is represented solely by said abrupt transitions
without regard to said signal amplitude levels, means for
retrieving said data from the storage means in serial form,
means for retrieving clock data from the retrieved data, means
controlled by said retrieved clock data for cyclically reconvert-
ing the serial-musical control data into parallel form, and
counter means controlled by said retrieved clock data for
applying the musical control data as reconverted to said music
generating devlces to reproduce the musical production recorded
thereon.
According to ano~her aspect o the invention there is
provided an electronic data storage and retrieval system for
use in operating a musical instrument having selectively
actuatable keys or the like comprising: a plurality of input
signal generating means operatively associated with the keys for :
producing data representing the actuation of the keys at discrete
times for the production of music, said data comprising
simultaneous as w~ll as time spaced combinations of key
actuation signals, means for sampling said data repeatedly during
scan frames of fi:~ed length and at a rate which is higher than
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1~7~58
the rate of occurrence o~ said key actuation signals, logic
circuit means for combining clock signals with said data
signals and produce a serial waveform comprising only first and
second signal levels and abrupt transitions between said levels,
each scan-frames of said waveform including serially arranged
data units which occur at the rate of said clock signals and
within which said discrete data signals have a predetermined
order, means for recording said serial waveform in a recording
medium, means for retrieving said data in the serial waveform
from said medium and including means for decoding the abrupt
transitions between said signal levels independently of the
absolute value of said le~els and producing clock signals and
data signals, means controlled by said clock signal for
cyelieally reeonvert~ng the diserete serialized data signals as
reconverted to said key actuation devices to reproduce the
recorded musieal produetion.
Aecording to a further aspect of the invention there
is provided a method of producing a musical presentation
comprising the steps: playing a musical production using an
2a instrument having selectively actuatable keys or the like,
generating discrete key depression signals for the depression
of the instrument keys, sampling, at a higher rate of speed than
the aetuation of any of said key depression devices, all of the
key depression signals in a series during a sean time, generating :~
a serial binary eoded ~aveform of fixed length related to the
sean time and containing a fixed serial arrangement of the key
depression signals, encoding said fixed serial arrangement of
key depression signals by logical com~ination with a clock
signal to produce an encoded signal, recording said encoded sig-
nal in a single ehannel of a magnetie tape, thereafter reading
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- : .. : -. . . ~ , . - !
~L~74~5~3
the magnetic tape to rep~oduce the encoded signal as recorded,
decoding the recovered signal to recover the clock signal
therefrom, using the recovered clock signal, reconverting the
serially arranged scan frames into sequentially occurring
groups of parallel key actuation data, and, under control of
said recovered clock slgnals, applying said data to key actuation
devices for the reactuation of the keys and reproduction of
the music.
Further features and advantages of the present
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~7~5~3
RAV-101
invention will become apparent upon reading the following
specification. It is to be noted that while the invention is
described with reference to a system for both recording and
reproducing data defining a musical performance, the invention
contemplates the possibility of recording musical performance
data at one location and facility and replaying or reproducing
the performance at another location and facility. Thus, the
advantages of the present invention may be realized within
a reproduction system having no spontaneous recording capability.
For a thorough understanding of the invention reference should
be taken to the accompanying specification and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
. . _ . _ _
FIGURE 1 is a block diagram of the data recording
and reproduction system;
FIGURE 2 iS a diagram of data recording format
within a scan frame;
FIGURE 3 is a block diagram of an expression control ~-
system;
FIGURE 4 is a circuit diagram of a second automatic
20 expression control system; ~ -
FIGURE 5 is a block diagram of a multiplexing system; ~;~
FIGURE 6 is a bi-phase encoder;
FIGURE 7 is a wave diagram illustrating the operation
of the encoder of FIGURE 6;
FIGURE 8 iS a second encoder;
FIGURE 9 is a wave diagram for the encoder of
FIGURE 8;
FIGURE 10 is a schematic circuit diagram of a
receiver;
FIGURE 11 is a circuit diagram of a bi-phase decoder;
FIGURE 12 is a waveform diagram for the decoder of
FIGURE 11;
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RAV-101 ~1~7~58
FIGURE 13 is a circuit diagram of a phase-locked
loop synchronizer;
FIGURE 14 is a bi-phase decoder using a phase-
locked loop;
FIGURE 15 is a waveform diagram for the decoder of
FIGUÆ 14;
FIGURE 16 is a circuit diagram of a double density
decoder for use in combination with the encoder of FIGURE 8;
FIGURE 17 is a waveform diagram for the decoder of
FIGURE 16;
FIGURE 18 is a circuit diagram for the timing unit
of FIGURE l;
FIGURE 19 is a demultiplexer; and
FIGURE 20 is a perspective drawing of a piano key
data ~enerating and actuating apparatus.
DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT
Looking to FIGU~E 1, a system 10 for recording and
reproducing a spontaneously generated piano presentation is
shown. System 10 is especially adapted for use in combination
with a conventional piano (not shown) modified only to include
key closure contacts forming switches 12 which are closed to
produce data in digital binary form each time any given key
is depressed. This is more fully described with reference to
FIGURE 20. The piano further comprises a pedal switch 14
indicating the use of the"sustain" pedal and a binary source
16 of expression signals created incident to the playing of
a musical present:ation on the piano in the conventional
fashion. Sources 12, 14 and 16 are all useable by a player
in the course of playing a musical presentation to generate
input signals which occur in various combinations according
to a sequence, the timing of which is determined by the player.
The combinations of signals include single key depression
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~7~158
RAV-101
signals as single notes are played in the course o~ a musical
presentation, and simultaneous combinations of key depression
signals as chords or other note combinations are struck during
the musical performance.
The system 10 comprises a multiplexer 20 the
function of which is to establish scan frames of a predeter-
mined serial bit length (in this case 128 bits in length) and
to serialize the parallel input data from the input data
sources 12, 14 and 16 within the scan frames; i.e. the multi-
plexer 20 lines up the parallel input data from all of the
sources in a predetermined numbered sequence of one hundred
twenty-eight data cells or bits as best shown in FIGURE 2.
The data format which is selected includes the allocation of
8 bits for a sync word, 72 bits for piano keyboard switches
12, 1 bit for sustained data, 12 bits for expression data,
12 bits for data to drive a CRT display of words, musical
notes, etc., and 15 bits for auxiliary functions such as
rhythm accompaniments and other miscellaneous operations.
The serialized data from multiplexer 20 is in a code
format known as non-return to zero (NRZ) wherein a positive
transition between binary signal levels represents a "1" and
negative transitions represents binary "0". Those familiar
with data and coding principles will recognize that the NRZ
code is not inherently self-cocking since a long string of
bits of the same binary value is characterized by the absence
of any transitions at all. This can create several problems
including (1) that the frequency responses of the receiver
network must go from D.C. to the bit rate and, (2) a separate
clock signal must be encoded or recorded on a second recorder
track so as to synchronize the readout operation with the actual
location of data cells in the data train or scan frame. On the
1074158
RAV-101
other hand, tne NRZ code does have the advantage o~ high data
density and, therefore, it is desirable to preserve the high
density advantage to the extent possible, The encoder 26
preferably takes such form as hereinafter described with
reference to FIGURE 8 as will combine clock information from
timing unit 22 with the serialized NRZ data from multiplexer
~0 and present to storage medium 24 the data in such code or
format as to produce a guaranteed transition between the binary
signal levels for most or all of tne data cells in each scan
frame. This code format has at least two advantages: (1) the
data stream is self-clocking and, thus, requries no separate
clock signal on a second recording medium channel, and (2) the
data in the scan frame is contained in the transitions rather
; than in the amplitude or level of the signal, The result
of these two advantages is the realization of high data decod-
ing accuracy, high density data storage and the substantial
reduction in performance requirements of the recording equip- i
ment employed. The storage medium 24 preferably takes the
. - . - .
form of a standard single-track magnetic tape recorder-player
of the type using standard reel~to-reel tape cassettes, Other
recording devices may, however~ be employed, Power supply 28
provides electrical excitation to all of the system elements
in FIGURE 1 requiring same as will be apparent to those skilled
` in the art,
FIGURE 1 further discloses the means for retrieving
the stored data from medium 24 and demultiplexing the data for
use in reproducing the musical production represented by the
data from input sources 12, 14, and 16, as previously described.
The reproduction system comprises a conventional read head
30 arrangement for presenting the data defining the musical pro- i
duction and the auxiliary functions along with the inherent
clocking data to a recei~er 30~ a decoder 32, and synchronizeL
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RAV-101 ~7~158
34 which extracts the clock signal from the scan frames~ The
reconstructed clock is applied to the decoder 32 as shown to
restore bi-phase data to N~Z form for application to ~he de-
multiplexer 36, The demultiplexer 36 performs an operation
which is substantially the reverse as the multiplexer 20; i,e,,
it reorganizes the serialized data from each scan frame into
parallel form for presentation via output bus 38 to the key
drive solenoids of a piano or organ or other musical instru-
mentality as may be employed, The expression data is simul-
taneously applied to the power supply 28 by way of bus 40 tomodulate the amplitude of the drive voltage which is supplied
to the key drive solenoids to accomplish the expression func-
tion. As also shown in FIGURE 1~ the reconstructed clock
signal from decoder 32 is applied to the timing unit 22 which
synchronizes the demultiplex function, It will also be
observed that the eight-bit sync signal in the scan frame of
F~GURE 2 is extracted during the demultiplex function and `
applied to the timing unit 22 to restart or synchronize the
strobe clock for each scan frame to ensure that the read strobe
signal does not drift outside of the data cell boundaries with
the result of signal degradation and possibly a loss of data
cell sync.
FIGURE 1 also shows output bus 42 from the demulti-
plexer 37 for transmitting the auxiliary drive signals to an
auxiliary unit such as a CRT display for word pictorialization,
color display or to perform some other auxiliary function such
as controlling house lights to a desired level of brightness,
operating a rhythm unit~ operating other accessories and
appliances~ any of these func~ions either bein~ related or
unrelated to the reproduction of music~
Expression control may be provided in Yario~s ways,
One expression control system is shown in FIGURE 3, In this
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RAV-101 ~4~58
system transducers 50 are mounted to sense the intensity with
which the keys are struck. This information is serialized by
way of N-channel multiplexer 52 and amplified at 5~. The
amplified signal is applied to a power detector 56 which may
be a simple threshold detector having several levels of dis-
crimination. The output of detector 56 is applied to the analog
di~ital converter 58 which generates a digital signal suitable
for recording within the system of FIGURE 1.
The transducers 50 may take any of several forms, for
example, they may be microphones, simple accelerometers, or
magnetic pickups. ~hatever the form, the transducers are volt-
age generating devices which produce signals that are then
multiplexed at 52 to form a single analog voltage stream. The
analog-to-digital converter 58 does, of course, operate under
the control of the clock signal from the timing unit 22 since
each of the transducers 1 through N must be sampled at the
appropriate time.
In Figures 4-19 many of the elements otherwise
identified by reference characters also contain nu~bers which
are indicative of industrially standardized integrated cir-
cuits, such circuits being commercially available and hence no
specific description will be given herein. These circuits are
available as pre-packaged devices from various manufacturers i'
including Texas Instruments, Inc., Signetics, Fairchild, and
Harris. According to catalogs published by or for these com-
panies in 1972 and 1973, the following specifically identified
integrated circuit units are available from the indicated com-
panies. Signetics: NE565 (phase locked loop); Fairchild:
741,710, 37002, 7400, 7404, 74193, 74150, 74151, 7486, 7474,
74121, 7420, 74192, and 74164.
FIGURE 4 illustrates an alternative system for
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RAV-101 ~7~5~
expression control in the piano and comprises four microphone
sensors 60 spaced at uniform intervals behind the keyboard.
The microphone outputs are serially multiplexed together at
62, this unit preferably taking the form of a Fairchild 37022
dc unit, a four-bit analog multiplexer. The serial output from
the multiplexer 62 is amplified at 54 and applied to a low-pass
filter 66. The filtered output is then digitized by means of
the comparator 68, counter 70, and ladder network 72. The
ladder network is a well known device, easily constructed using
discrete components or available as a pre-packaged circuit
device from Angstrohm Precision, Inc. as part of their DIP
series of binary circuits. The frequency response to the low-
pass filter is centered about approximately 30 Hz. The output
of the low-pass filters 66 is converted to digital form and the
least significant bit of the analog digital converter switches
back and forth from a "1" to a "0" and the three most signi-
ficant bits are used as an output to give as much as eight
levels of control over the intensity or volume by varying
voltage to solenoids that strike the keys in the respective
quarter of the piano keyboard. The three bits of data may be
added to the data format, stored or transmitted, arld recon-
verted back into parallel information. After being converted -
from digitai to analog form, the voltage at which the solenoid
is operated is adjusted in response to the analog signal, thus,
to control the force with which the key is struck.
Other forms of expression control including manual
expression control can, of course, be employed.
FIGURE 5 illustrates the details of a typical imple-
mentation for the multiplexer 20 of FIGURE 1. Multiplexer 20
includes a seven-bit counter providing 27 combinations for
the 128 multiplex function. The circuit of FIGURE 5 is a ~
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RAV-101 ~7~158
two-level multiplexing scheme, the first level of which
assembles the data into eight parts of sixteen bits each and
the second level of which further assembles the eight parts
into one scan frame having 128 or more data units. The first
level utilizes four bits from timing unit 22 to accomplish a
sixteen-bit multiplex function. In circuit 80, for example,
the four bits of timing information and the sixteen bits of
input data generate a serial output from the sixteen input
information bits, bit 1 being the first out and bit 16 being
the last out. Running parallel with this multiplexer unit
are seven other multiplexers of substantially identical con-
struction generating output bits at the same rate and con-
trolled by the same four input timing bits. The outputs of
these eight multiplexer units are, however, fed into the
eight-bit multiplexer 82 the timing of which is controlled by
the subsequent three timing bits from unit 22 shown in FIGURE
l; i.e., the least significant bits of the timing sequence.
The output of multiplexer unit 82 samples each of the other
eight multiplexers once for each of their output bit times, thus,
generating the 128 bit serial NRZ data stream with bit 1 of
multiplexer Al out first and bit 16 of multiplexer 80g coming
out last.
The sync word illustrated as the beginning of the
scan frame in FIGURE 2 may comprise, for example, a series of
eight ones tl's), thus, to present a distinct data form which
is not likely to be generated during random musical data pro- -
duction and which can be distributed and reco~nized as a sync
word by the synchronizer 34. The sync word can be hard wired
with the first eight bits wired to zero if all ones (l's) are
required for the sync word. The SN 74150 suggested for units
80 produces an inversion between input and output; therefore~
11 '
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RAV-101 ~7~58
all zero's would be wired for an all one sync word. The
switches 12 from the piano keyboard as well as for the sync
word are wired directly to the inputs of the multiplexer units
80 and, when the key is closed, the switch grounds to common
providing an input signal. The output data is, thus, inverted
to convert the ground or binary zero to a binary one.
In reproduciny music, the sample rate is of substan-
tial significance in order to ensure the complicated composi-
tions as well as the auxiliary functions can be suitably repro-
duced using conventional recording equipment. The sample
period for each data cell is about 250 microseconds for both
multiplexers to ensure that the sample rate is much faster
than the playing speed. Thus, a sample time is negligible
compared to the time a key is actually depressed in normal
operation of a piano or an organ or another instrument. Any
key switches that close in the middle of a bit time or other
erratic operation of the keys would be undetectable because
the sample rate is very high.
Referring now to FIGURE 6, there is shown a bi-phase
encoder for implementation of unit 26 in FIGURE 1. Encoder 26
is responsive to the NRZ data from the multiplexer 20 to
produce a code which has the self-clocking feature and which
exhibits no significant dc component. The basic bi-phase
level code is that zero information is the inverted clock and
the one information is a true clock. This code is a simple
exclusive/OR of the NRZ data and the inverted clock informa-
tion. It is provided by the gates 90 and 92, implemented and -
connected as shown. In the timing diagram of FIGURE 7, the
bi-phase data is the clock for binary ones (l's) and the in-
verted clock for binary zeros (0's). The maximum time between
transitions in the data is the bit time. There is always a
12
RAV-101 ~ 5~
transition in the data in the middle of the bit; it is a
transition from high to low to represent a l'1" and from low to
high to represent "0". In utilizing the exclusive/OR gates
90 and 92 to generate the bi-phase data, spikes or transients
generated in the data which are of high frequency or narrow
pulse width are filtered out by the fairly low frequency
response tape recorder system. Thus, the bi-phase data encoder
of FIGURES 6 and 7 is especially well adapted for tape recorder
use but may call for some alternative approaches for other
transmission medias such as radio or hardwire transmission.
Where correct data phase is a requirement of the -~
storage or transmission system and the system has good signal-
to-noise ratios, a double-density encoding scheme may be
employed using the implementation of FIGURE 8. This results
in a code format as represented in FIGURE 9. The double-density
code of FIGURE 9 has a transition in the middle of a one and
a transition at the end of zero. However, when a single zero
with a one on either side occurs, there is no transition at
all. To generate the double-density code, a bi-phase level
code is generated utilizing a clock and NRZ data as applied
to exclusive/OR gate 96. The output of gate 96 is stored in
a buffer flip-flop 98 to eliminate voltage spikes. The "not"
output of the flip-flop is applied to the clock input of flip-
flop unit 100 which toggles the flip-flop on the negative edges.
The flip-flop, thus, generates a double-density code which does ~`~
not require the phase of the code be maintained by the storage
or transmission medium 24. The bandwidth may be half of the
bandwidth required for the bi-phase data. The dou~le-density
code does exhibit some dc component and requires randomess of
the data or an offset due to the dc component may be generated.
Other code formats including return to zero (RZ) can, of course,
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RAV-101 ~7~8
be employed. This may be of a distinct advantage where the
storage or transmission medium 24 requires the clock as well
as the data; for example, the use of a telephone llne transmis-
sion means required clock and NRZ data but other media may
require RZ data.
Receiver 30 may take any of several forms, one form
being illustrated in FIGURE 10. The input to receiver 10 is
ac coupled from the tape read head to a zero crossing detector
comprising transistor 102. A resistor Rl which loads the input
to the correct load, R2 or R3 bias the transistor 102 to zero
crossing. Capacitor Cl is a coupling capacitor. Capacitor C2
is a low-pass filtered capacitor to filter out noise. Resistor
R4 is purely a load for the transistor 102 and the output is
the restored data in the original format. Most tape recorders
and other transmission systems may employ the receiver of
FIGURE 10.
A bi-phase decoder implementation unit for unit 32
is shown in FIGURES 11 and 12. The bi-phase decoder 32 of
FIGURE 11 utilizes a one-shot which extracts transitions from
the bi-phase data by delaying the bi-phase data through the
transitor Zl with Rl and Cl as the delay network. Circuit 32
then exclusive/"OR's" the output of Ql which is inverted and
delayed bi-phase data with the input bi-phase data. The out- -
put of the exclusive/OR 110 is a positive going spike on the
edges of the incoming data and trigger a one-shot unit 112
with the timing set by R3 and C2. The output of the one-shot
112 is a three-quarter bit period clock; the first time the
one-shot sees a transition from one to zero or a zero to one
..... .. .. .
in the bi-phase data, the one-shot will synchronize with the
30 incoming data train. This clock is then utilized to clock
into the data flip-flop 114 the inverted bi-phase data. The -
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R~V- 1 0 1
output of the data flip-flop 114 is the reconstructive NRZ
data and the output of 112 is the clock that is utilized in
the demultiplexing of the data.
FIGURE 13 shows a phase-lock loop synchronizer suit-
able for the implementation of unit 34 of FIGURE 1. Where the
data storage and transmission unit has a low signal-to-noise ~-
ratio or where tape speed varies or other factors result in a
degradation of the data, the clock information may be regener-
ated by the utilization of a phase-locked loop of the type
shown in FIGURE 13. In either a bi-phase or double density
code, a clock signal related to two times the clock frequency
is obtained from the data by extracting the edges of the tran-
sition of the data utilizing a delay network R C, transitor
116, and exclusive/OR gate 118, a flip-flop 119, and a one-shot
unit 120. The output of the one-shot is approximately one-
quarter the bit time o~ the clock rate use. This pulse is fed
to a phase-locked loop including transistor 121 that generates
an output clock which is at twice the bit rate. The decode
scheme can then divide the clock by two and phase it correctly
with the data. In the circuit of FIGURE 13, the output of the
one-shot is fed to the phase-locked loop utilizing a Signetics
NE 565 or equivalent which is running at a center frequency of
two times the bit rate. The signetics NE565 is a self-contained
adaptable filter and demodulator for the frequency range 0.001HZ
to 500 KHz. The circuit comprises a voltage controlled oscil-
lator of exceptional stability and linearity, a phase comparator,
an amplifier and a low pass filter as is more fully described
in the Signetics Linear Integrated Circuit catalog, pages 6-72
through 6-76. The VCO output is allowed to track over a large
range of variations in input frequency and flutter or track
through noise. The output of the phase-locked loop is
~ . . . : ,
7~58
RAV-101
buffered providing two times the bit rate clock. The phase-
locked loop is a simple circuit utilizing standard, integrated
circuits.
Looking to FIGURE 14, a bi-phase decoder using a
phase-locked loop is illustrated. The 2X clock from the phase-
locked loop is utilized to shift the bi-phase data into data
flip-flops 132 and 134 operating as a shift register to store
two half bits in a shift register. Upon obtaining ones in
both flip-flops or zeros in both flip-flops and decoding this
condition along with a clock, an output flip-flop 136, 138
is cleared to phase the clock with the incoming data. In the
circuit shown in FIGURE 14, a zero-to-one transition in the
data syncs the clock flip-flop 132, 134 to the correct phase
of the data. The bi-phase data is loaded into the data flip-
~lop 136, 138 utilizing the bit rate clock ~lip-flop and is
then decoded with the timing diagram, shown in FIGURE 15, to
provide the NRZ data.
A double-density decoder utilizing the phase-locked
loop as a clock is shown in FIGURE 16. The double-density
input data is shifted into a four-bit shift register utilizing
data flip-flops 150, 152, 154, and 156. The output from these
four data flip-flops is decoded to sync the clock and to set
the output data to zero. From the timing diagram of FIGURE 17,
is is apparent that when all four data flip-flops have ones
or all four data flip-flops have zeros, the clock and the data ~ -
should both be zero at this time. By decoding that state, all
.,ones or all zeros in all four flip-flops clearing the clock
flip-flop and c:learing the data flip-flop are properly phased
together. The output data flip-flop is toggled to reconstruct
the NRZ data.
FIGURE 18 illustrates suitable implementation for
16
,. ,:
. ~ ............. - , ~-- ~ . . - -.... . .
.- .. - : . .
~L~74~8
RAV-101
the timing unit 22 of FIGURE 1. The timing unit in both the
multiplexed modes and the demultiplexed modes utilizes the
same counters. Whether the system is operating in a multi-
plexed mode or a demultiplexed mode can be determined in
several ways. The ideal way is to have a command input from
the tape recorder 24. Commands to operate the clock to be used
in the timing network 22 may be obtained from timing reference
oscillator 160 by command or sensed from incoming data. This
clock whether obtained from oscillator by enabling gates 162
and 164 or from data via gate 166, is then fed via gate 168 to
a synchronous counter 170, 172 implemented with two SN 74 192's
as a one-hundred twenty-eight pulse per count cycle. The sync
that synchronizes the counter during a receive mode comes
from the demultiplexer which senses the sync word. The sync
pulse is then counted and after obtaining two sync pulses in
a row, the inhibit signal is released to allow the output data
from the multiplexer to be utilized. The sync counter 174,
176 is implemented using two since SN 74 74 data flip-flops.
The clock from an internal oscillator which oscillates the
bit rate clock or the clock from the receiver synchronizer is
gated through the gates using an SN 74 00, also marked 178,
with the command to select the required clock (see FIGURE 19 ) .
Looking to FIGURE 19, a demultiplexer 37 is shown.
In FIGURE 19 the seven timing bits from timing unit 22 control
an output demultiplexer consisting of one eight-channel demul-
tiplexer 180 feeding eight sixteen-channel demultiplexers 182 ;
for a two-stage demultiplex operation. The output from the
demultiplexer exists for only two-hundred fifty microseconds
which is not sufficient to drive a solenoid and, accordingly,
a pulse stretcher 184 is required to extend the output to the ~ -
required thirty milliseconds. A suitable pulse stretcher is
17
~ .
.. . . . . ........ . .
.
RAV-101 ~74~8
disclosed in Figure 9B of the patent to Wheelwright 3771406;
see reference character 290 and the description in column 6
of the patent beginning at line 33. Other devices such as
one-shots may also be employed. The stretched pulse is applied
to driver switch 186. The multiplexer of EIGURE 19 employs no
storage uni~. A demultiplexer utilizing storage for time bits
may also be employed.
FIGURE 20 illustrates apparatus which is required in
some form in the piano itself. Key 188 operates through con-
ventional mechanism 190 to move hammer 192 to strike string
194. ~hen key 188 is manually struck and depressed, noncon-
ductive trip 196 pushes spring wire 198 into contact with con-
ductor 202, making an electrical circuit from excitation plate
200 to conductor 202 which is connected to the multiplexer 20. '~
A smilar arrangement is provided for each key. Eor playback,
solenoid 204 may be energized with a voltage pulse to raise
plunger head 206 to pivot key 188 just as if it were struck
manually.
The auxiliary and video signals from demultiplexer '
37 may be employed for a variety of operations including those '~
which are not musical in character. A video word display may ,
be provided by means of a CRT device of the type described in
the Radio-Electronics article published in 1973 by Gerusback
Publications of New York and entitled "TV Typewriter". That
device comprises a CRT (television) set 300 which can be
programmed via a typewriter to display words at a selected rate. -
To employ such a system in combination with the player piano -
system described herein, a first operator types words in syn- ,'
chronism with t'he simultaneous rendition of a musical member by
a second operator and all information is input to the encoder ,
26 via the multiplexer 20. The unit 80g of FIGURE 5 may be
18
s~
RAV-101
allocated to the TV typewriter input. On playback, the
channel 182f of demultiplexer 36 may be allocated exclusively
to the TV set control.
It will be understood that the foregoing description
is merely illustrative of the invention and is not to be
construed in a limiting sense.
:.
, . .
19
