Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to an input structure which provides
complementary signals in two channels of a charge coupled device and more
particularly to one which may be used to implement transversal flltering
; in such a device without the need for an associated operational amplifier.
Background of the Invention
In an article entltled: "Charge-Coupled Devices - A New
Approach to MIS Device Structure", IEEE Spectrum, July 1971, pp 18-27,
W.S. 80yle and G.. Smith describe a new information-handling structure,
the charge-coupled device, (CCD). The device stores a minority-carrier
charge in potential wells created at the surface of a semiconductor and
transports the charge along the surface by the application of bias
potentials to control electrodes so as to move the potential wells.
;~ Numerous applications have been proposed for the CCD. It
can be utilized as a transversal filter, such as described in an article
by A.Ibrahim et al entitled: "Multiple Filter Characteristics Using a
~ Single CCD Structure", International Conference on the Application of
!~ Charge-Coupled Devices, October, pp 245-249; or as a recursive filter,
such as described in an article by D.A. Sealer and M.F. Tompsett entitled:
"A Dual Differential Analog CCD For Time-Shared Recursive Filters", ISSCC
February 1975, pp 152-153. One disadvantage of prior structures of this
type is that in order to provide both positive and negative coefficients
of the sampled signals, it is necessary to subtract two charge signals
at each delay stage. This is generally achieved utilizing a differential
~ amplifier. However, the success of this approach requires the integration
; of a MOST (metal-oxide-silicon-transistor) operational amplifier on the
same chip as the CCD, to reduce the final cost.
Statement of the Invention
The present invention provides a unique input structure for
providing complementary charges in two CCD channels which permits weighting
and direct summing of the detected signals thereby negating the
requirement for a differential amplifier.
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Thus, in accordance with the present invention there is
provided a complementary input structure for a multi-channel charge coupled
device comprising: a charge storage body, a dielectric layer disposed over
the body and a pair of channels each having a plurality of electrodes
disposed over the dielectric layer for controlling the sequential transfer
of mobile charges along the body in response to clock voltages applied
thereto. The input structure comprises a common input electrode disposed
over the dielectric layer adjacent the head of each channel for controlling
a charge of fixed magnitude in the body from an adjacent source. In
addition, the input structure includes a control electrode at the head of
each channel in juxtaposition with the common input electrode and
individually responsive to separate control signals for transferring a
selected portion of the fixed magnitude charge to one channel and the
balance to the other channel, whereby the charge in the other channel
is the complement of that in said one channel.
In a particular embodiment, selected ones of the electrodes
in each of the two channels are divided along the length of the channel
to divide the charges being transferred therebeneath in preselected ratios.
One portion of each of the divided electrodes from both channels are
connected in common, whereby the total charge beneath the common portions
of the divided electrodes is a function of the individual magnitude of the
charges being transferred along the two channels and the relative division
of each of the electrodes in the two channels.
Brief Description of the Drawings
An example embodiment of the invention will now be described
with reference to the accompanying drawings in which:
I Figure 1 is a pictorial plan view of a dual channel charge
coupled device including an input structure in accordance with the
present invention;
Figure 2 is a pictorial diagram of a side elevational view
of the structure illustrated in Figure l; and
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Figure 3 illustrates typical waveforms of the various clock
voltages which are applied to the device illustrated in Figures 1 and 2.
Description of the Preferred Embddiment
The fabrication of the charge coupled device described
herein utilizes technologies well established and known in the
semiconductor field. It is therefore considered unnecessary to describe
in detail the individual steps for forming the device. However, Canadian
Patent No. 941,072 issued January 29, 1974 to James J. White describes
one method of constructing a two-level poly-silicon charge coupled device
which is the basic structure of the device disclosed herein. Also, it is
evident that the figures shown in the drawings are exemplary of the
construction of the invention and not necessarily drawn to scale.
In the following detailed description and accompanying
; drawings basic reference numerals are assigned to individual elements of
the device. Where it is necessary to distinguish between repetitive
elements in a row additional reference characters are added to the base
;~ number. In general, reference is made only to the base number.
Referring to Figures 1 and 2, the two-phase charge coupled
device comprises a charge storage body 10 of p-type silicon having a
variable thickness silicon dioxide (SiO2) insulating layer 11 deposited
~ thereon. A row of alternately upper 12 and lower 13 elongated
; poly-silicon electrodes laterally disposed so as to overlap adjacent
ones thereto, have been deposited on the insulating layer 11. As will
be manifest hereinafter, the lower electrodes 13 function as storage
control electrodes while the upper electrodes 12 function as transfer
gates in a well known manner.
As illustrated in Figure 1, the silicon dioxide insulating
layer 11 includes gate oxide regions 15 beneath which the packets of
charge are transferred in n-channels along the row under control of clock
voltages applied to the field plates 12 and 13. These gate oxide regions 15
consist of alternating thicknesses of insulating layer 11 which is
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approximately 1100 ~ thick under the storage electrodes 13 and 3000 Q thick
under the transfer electrodes 12. The surrounding thicker portions are
designated as field oxide regions 16. These latter regions 16 are
sufficiently thick (approximately 1.2~m) that the portions of the
semiconductor substrate 10 immediately beneath them do not invert in
response to the application of clock voltages to the electrodes 12 and 13.
Consequently, the minority-carrier charges are only carried along the
substrate 10 immediately adjacent the gate oxide regions 15.
At the head of the channels 15 is a diffused n+ source of
mobile charges or carriers 20. This is followed by a transfer gate 12R
and an initial storage electrode 13R which is common to both channels 15.
Immediately adjacent the common storage electrode 13R in each channel 15A
and 15B is a control electrode 12A and 12V respectively. Unlike the
balance of the electrodes in the channels 15, these electrodes 12R, 13R,
12A and 12V are controlled by separate clocks as will be described
hereinafter.
In addition, it can be seen that every second storage
electrode 13 is divided along the length of the channel 15 with the inward
facing portions of the divided electrodes 13J, 13K, 13L and 13M being
connected in common. These divided electrodes provide the weighting
` factor during the nondestructive sensing of the magnitude of the analog
charges being transferred along the channels 15.
In Figures 1 and 2, the clock drives are identified by
reference characters 01' P2- 0s' 0sl and 0s2 having voltage waveforms
identified by corresponding reference characters in Figure 3. Referring
I now to all three figures, at time tl, the clock drives Pl and 0s 9 high
¦ and a mobile charge of electrons is transferred from the source 20 to
beneath the storage electrode 13R which has a fixed reference voltage VRR
applied thereto. This reference voltage VRR is selected to provide a
~; 3Q charge QRR under electrode 13R of a preselected magnitude which acts as
a virtual source of charge for the two channels 15A and 15B. At time t2,
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05 goes low and 0sl goes high. This signal 0sl is the composite of a d-c
bias voltage V8 and an a-c signal VS such as from a transmission line
(not shown). Since electrode 13A has already been driven high by clock 01
at time tl, the signal under control of clock 0sl transfers a preselected
portion of the charge QRS to beneath the storage electrode 13A.
At time t3, PSl goes low and PS2 goes high. This applies
sufficient voltage to transfer gate 12V to transfer the balance of the
, charge beneath the electrode 13R to beneath the storage electrode 13V
` which has also been driven high. Thus, the charge stored beneath the
electrode 13V, QRR-QRS is the complement of the charge stored beneath
the electrode 13A. At time t4, clock 02 goes high, followed by clock Pl
going low which transfers or dumps the charge beneath the electrodes 13A
and 13V to beneath the divided or split electrodes 13B, 13J, 13L and 13W
in a well known manner.
; Since the magnitude of the voltage applied to each half
of the divided electrodes is the same, the charge will split between the
two in accordance with the relative length of each electrode.
The relative magnitude of the total charge beneath the
electrodes 13J, 13L, 13K and 13M can be monitored by a floating gate
sensing network 16 using a nondestructive sensing technique such as
described in the above-mentioned paper by A.Ibrahim et al.
In a typical application of a CCD transversal filter an
a-c signal v5 superimposed on a d-c bias voltage VB is applied via
clock 0S1 to gate electrode 12A, to transfer a preselected portion QRS
of the charge QRR previously stored beneath storage electrode 13R to
beneath electrode 13A. The complement or balance of this charge QRR-QRs
is then transferred beneath storage electrode 13V under control of
clock 0s2 The charges are then concurrently transferred along the
channels 15A and 15B under control of clocks Pl and P2. At each of the
3Q: split electrodes 13 the weighting factors are determined by the relative
lengths. By repeatedly nondestructively sampling the weighted charge
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under the various split storage electrodes 13 and summing their outputs
in the network 16, an output signal from the electrode 17 can be obtained
which is proportional to the magnitude of the charges being transferred
along both channels 15A and 15B and the relative weighting determined by
the divisîon of the split electrodes. Because the complement of the
charge being transferred along channel 15A is transferred along channel 15B,
the sensed signals can be summed directly without the necessity of
providing a differential ampllfier. This technique results in a d-c
offset on the sensed signal on electrode 17 which can be readily removed
in the output network 16.
While the floating gate sensing network utilizes semiconductor
amplifiers, these can be readily constructed utilizing MOS (metal-oxide-
silicon) technology, the same as that used to construct the CCD. Also it
will be understood that the entire structure could be implemented
utilizing p-channel technology on a n-type silicon substrate.
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