Note: Descriptions are shown in the official language in which they were submitted.
~8~ 21-ME-15
BACKGROUND OF THE INVENTION
Field of t~e Invention
This invention relates generally to remote auto-
matic communication systems and more particularly to a remote
meter reading and load control system for reading the measure-
ment of commodities at terminal points along a utility power
transmission network and controlling loacls at the terminal
points.
Description of the Prior Art
Utility companies have long used meter reading
personnel for reading the consumed commodity information
provided by utility meters (i.e., gas, water, electricity,
; and the like). However, in recent years significant strides
have been made in the development of fully automatic meter
reading systems.
- 15 Most remote meter reading systems have similari-
ties in their designs. Generally, they comprise some type
of encoder device attached to a meter to give an indication
of the meter reading, means for storing the meter reading
indicated and a transponder for transmitting meter data over
a communication link to a central station when interrogated
by a signal from the central station. Various types of com-
; munication links have been used in transferring the meter
data from the individual meters to the central station. One
known system utilizes a mobile van which travels over a
specified route in a community and, while traveling, trans-
mits interrogate signals to meter equipment transponders at
the houses located along the traveled route. The transponder
at each house, in response to the interrogating signals,
transmits a message to the van, which includes a meter iden-
tification number and the present reading of the meter.
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Receiver equipment-in the van effects the storage o~ the
meter data for subsequent use in billing the customer.
Various other types of svstems have been devel-
oped which utilize the telephone lines of the subscriber
as the communication link to the central station. Also,
there are arrangements in which the power :Lines of the sub- -
scriber and the utility company are used as the link between
the customer's meter and the central station.
While many communication systems have been devel-
~oped for utility companies, all of which utilize one or moreof the various links and equipment aforementioned, no known
economically feasible system has yet been designed which
affords the capabilities o mass meter data accumulation and
load control at a consumer residence and which meets the
universal neec~s of utility companies.
An electric po~7er network, involving as it does a
vast number of meter locations, logicallv dictates that the
most economical communication system will be that system
which affords a minimum expenditure for the transponder equip-
ment at each meter location, while allowing a greater expend-
iture for more sophisticated equipment for the processing of
large amounts of meter data and the rapid distribution of
command information to the transponder meter locations.
This logical consideration has generally made the approach
of providing radio xeceiver-transmitter units at each meter
location unfeasible. In effect, this approach involves the
use of as many communication systems as there are meter ;
terminal locations. The desired approach, by contrast, would
utilize an existing communication network which links all
meter terminal locations togather and would minimize the
expense o~ the control equipment at each terminal location.
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Further, overall system control would be effected by a
central station and section or group equipment which, being
required in smaller numbers, can be of greater sophistication.
Additionally, the desired system would allow
utility companies to read all meters in a city at desired
intervals, such as during daily peak power periods. This
has the advantage of allowing the utility companies to im-
prove the system load factor b~ encouraging the customer to
; 10 improve his residential load factor. This improvement of
load factor can be accomplished in a number of ways by effect-
ing a shifting of loads on the system from on-peak periods to
off-peak periods. Three modes, but not necessarily all in-
clusive, of accomplishing this load shift have been suggested
15 as follows:
1. Alerting the customer by the automatic
ackivation of an indicator at his residence
when he is using energy during peak periods
so that he can reduce his load during those
periods.
2. Metering and billing the customer at a
premium rate for his on-peak usage.
3. Controlling or limiting the customer's on-
peak usage of energy by automatically turn
ing off various loads in his residence (e.g.,
hot water heater, clothes dryer, etc.) during
those periods.
Thus, it can be seen that a need exists for an automatic
meter reading and control system which affords the pre-
ceding advantages and which has a built-in flexibility to
accommodate future changes in utilit~ company operating
philosophy.
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Summar of the Invention
Y __
The aforementioned advantages are provided by
the present invention which provides a remote automatic
utility meter reading and control system for reading the
measurement of a commoditv and controlling loads at a con-
sumer or customer residence over a network of power lines.
A central station includes a computer with
input/output equipment for the multiplex generation of
.
commands and the rec~ipt of data over a pluralit~ of com-
munication lines. The commands generated by the central
station contain at least an address portion and a function
code portion.
At least one control unit is connected to each of
the central station communication lines and provides signal
transmission and coupling of commands and data between the
central station and a power line. Each control unit includes
means for recognizing two addresses, its own distinct address
and an all control units address. Whe~n a control unit recog-
nizes any one of its allowable addresses in a command, it
transfers that command to its connected power line in the
form of high frequency pulse bursts at a specified frequency
representative of binary l's and O's and at a specified Pulse
repetition frequenc~. Each control unit al50 includes means
to decode the function code in commands received from the
central station. If the command function code specifies that
an addressed control unit is to receive a data message from
its power line and transfer that message to the central sta-
tion, the control unit will go into a wait mode, after it
has transferred the command to the power line. After a data
message has been received by the control unit and trans-
ferred to the central station, the control unit reverts to
a standby mode for the receipt of another command from the
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" ~1336~39
central station.
The function code, in certain commands, merely
specifies that an external operation is to be performed
at a customer residence, in which case no data is expected
from the power line. When a control unit receives a com-
mand of this latter t~pe ~rom the central station, it re-
verts to the standby mode, after transmitt:ing the command
; onto its power line.
Each control unit also includes a plurality of
receiver means for simultaneously receiving data messayes
from a plurality of transponder or meter terminal units
- connected to the power line. There is a meter terminal unit
located at each customer residence. Each receiver means is
tuned to a different frequency to simultaneousl~ receive
~5 data messages from the power line at frequencies which
correspond to the transmission frequencies o~ the messages
transmitted by the meter terminal units. Each meter termi-
nal unit transmits a data message at a different fre~uency
; in the foJ:m of high frequency pulse bursts at a specified
pulse repetition rate. There are the same number of re-
ceiver means in the control unit as there are simultaneousl~
transmitting meter terminal units.
Each terminal unit is capable of selectively
communicating with a plurality of utilitv meter encoders
for reading a plurality o~ meters and for selectivel~
driving a plurality o loads at a customer residence.
The transponders or meter terminal units are re-
~ sponsive to commands transferred to the power lines ~ the
- control units. Each terminal includes means for recognizing
a plurality of command addresses. To be activa~ed, a trans-
ponder must receive ~he address of the control unit to which
it is connected, as well as another one of a plurality of
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33~9
addresses that it is capable of recognizing. Each terminal
unit on a power line can be individually addressed, or
several can be addressed in small groups to simultaneousl~
respond to a command as specified by the function code.
Additionally, all transponder units on a power line can be
simultaneously addressed or the~ can be acldressed in large
sets comprised of several groups.
Each transponder unit responds to specific
commands to either selectively read and store data in one
of several storage m~ans ~rom a plurality of meters a~
specified by the command function code, selectively transmit
the previously stored meter data from the several storage
means to its associated control unit or selectively control
the operation of the residence loads as specified by the
function code,
The present invention manifests itself in the
combination of the central station, the control and meter
terminal units and the means pro~ided thereby to selective-
ly, under command control, read and store meter data into
singular or lar~e groups, or sets of meter terminal units,
and singularly or simultaneously transmit stored meter data
from singular or addressed groups or sets of meter terminal
units to the central station and to singularly or simultane-
; ously control large numbers of loads at consumer residences.~f 25 It is therefore an object of the present inven-
tion to provide a remote automatic meter reading and c~ntrol
system having enhanced operating capabilities.
It is another object to provide an automatic
; utility meter reading -system for reading the measurement of
a consumed commodity over utility power lines.
A still further object i~ to pxovide a computerized
data communication system capable of reading meter data from
a plurality of residence meter terminal units under command
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1(:98368~31
control of a computer.
It is another object to provide an automatic
meter reading system capable of simultaneously reading and
storing meter data from a plurality of meters and simul-
taneously transmitting the stoxed data to a computer undercommand control of the computer.
It is another object to provide an automatic
meter reading and control system capable of transferring
commands from a central station over a power line via a
control unit to a plurality of meter terminal units on the
power line to effect load control operations in the meter
terminal units and the transfer of stored meter data from
the meter terminal units to the central station over the
power line.
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BRIEF DESCRIPTION OF T~E DRAWING
The prescn~ ir,vention may be ~nore readily under-
stood by reference to the accompanying drawing in which:
FigO 1 is a major block diagram of the system of
the present invention.
Figs, 2 - 6 illustrate the various formats of
messages and data trans~erred between units of the system.
Figs. 7 and 8 are flow charts useful in under-
standing the sequence o operations which take place in the
system,
Figs. 9, 10, 11, 13, 14, 15, 19, 21 and 22 are
legendary drawings showing the inter-relationships between
, Figs. 9A and 9B, lOA - lOD, llA - llH, 13A - 13F, 14A - 14D,
¦ 15A - 15D, l9A - l9D, 21A and 21B, and 22h - 22D.
Figs. 9A, 9B, 10A - 10D, llA - llR, and 12 are
lS timing dia~rams useful in understanding the oF.eration of
the section control units of Fig. 1.
Figs. 13A - 13F and 14A - 14D are detailed block
diagrams of a typical one of the section control units of
; Fig. 1.
Figs. l5A - l5D, 17, 19A - l9D and 22A - 22D are
detailed block diagrams of a typical one of the meter
terminal units of Fig. 1, and
Figs. 16, 18, 20, 21A and 21B and 23 are timing
diagrams useful in understanding the operation of the meter
terminal units of ~ig. 1.
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DESC~IPTION OF THE PREFERRED EMBODIMENT
System Description
Reference is now made to Fig. 1 of the drawing,
which presents a block diagram of the overall system. Sys-
tem control is directed by a reading control center 10
thereinafter referred to as the ~CC), which is comprised of
~a data processor or digital computer; The computer is of a
general purpose type having sufficient memory capacity to
store da~a pertaining to the entire system and is pro~rammed
to transmit messages or commands throughout the system and
lQ to collect data from the system as described herein below.
Many such digital computers are commercially available. Fox
a relatively small system, the PDP8/E computer manufactured
by the Digital Equipment Corporation is suitable. For large
system applications, the H4010 data processor manufactured by
the Honeywell Corporation may be employed. It is to be noted
that each of these computers contains its own input/output
equipment for the transfer of commands and the receipt of data
between the RCC and the rest of the system.
The RCC 10 issues commands and receives data pref-
20 erably in a multiplex mode over a pluraiity of digital input/
output serial transmission lines 12. It will be noted that
some of the lines 12 are connected to modems ~modula~or/
demodulator circuits), which in turn provide communication
~ with a plurality of section control units 16 (SCU) over in-
dividual voice grade or trunk lines 14 of the conventional
dedicated telephone type. Each SCU 16 also has a ccnven-
tional modem for interface between its trunk line and the
logic internal to the SCU. Transmission of data between the
modems is preferably of the frequency shift keying ~FSK) type;
however, othcr type~ of transmiss~on may also be ~mployed.
Each of the modcm~ are prcfexably o~ thc voice frequcncy
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type comprised of a con~ercially a~ailable transmitter/
receiver. Typical transmitters and receivers of the type
which may be employed in the present system are models
68T,2F and 68R,2F, respectively, manufactured by RFL Industries,
Inc., Boonton, New Jerse~. These transmitter/receivers are
documented in the RFL Industries, Inc. publication entitled
Voice-Frequency Carrier Equipment, Seri~!s 6850, revised May
1975.
Certain other o~es of the diyital input~output
lines 12 of the RCC are connected directly to the SCV's 16.
In most applications, the SCU's will be located at such a
distance from the RCC that it is desirable to use the ~odem
in order to properly amplify the signals transmitted over
lines 12 and 14. However, there ma~ be situations where one
lS or more SCU's are directJ.y adjacent the RCC, in which case
signal strength will be large enough that it is unnecessar~
to employ the modem.
~ For purposes of simplicit~, the system is illus-
trated with several SCU's connected to onl~ one modem via
their associated voice grade line 14. It is to be understood
that all of the other lines 14 could likewise have SCU's
connected thereto in the same fashion.
Yt will be noted that each of the SCU's is con-
nected to an associated electrical power transmission line 18.
- Each of the power lines also has connected thereto at least
; one meter terminal unit 20 tMTU). In the preferred embodi-
ment, the transfer of commands and data between the RCC and
the SCU's over the voice grade lines 14 is in ASCII code
format. Comrnands or messages issued by the RCC are trans-
ferred from the SCU's to their corresponding power lines as
digital data consisting o~ pulses o~ ~F ~nergy at a pulse
~ - 2
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39
repetition frequency ox preferably 30 Hz. It will be
noted in Fig. 1 that output messages from the SCU's are
designated as being transferred at a fre~uency of fO as
indicated by the arrow going downward on the page adjacent
each power line 18. The designation fO indicates the pulse
frequency of each bit of transmitted data. Also, as shown
in ~;g. l, each SCU, if desired, is capable of transmitting
messages at a different frequenc~ as indicated bv the fO'
and fO" notations.
As will be more fully descrihed, each SCU is
uniquely addressable and is also capable of recognizing an
ALL SCU address in commands received from the RCC. F'urther,
each SCU is capable of recognizing a function code contained
withln the command to determine the action that it is to take.
Message parit~ is also checked by each SCU. If an SCU rec-
ognizes its address, and the command contains proper paxity,the SCU will transfer the command onto its associated power
line 18. Depending on the contents of the function code, the
- SCU will go into one of two modes. If the function code
specifies that no data is to be received over the power line r
from one or more MTU's, the SCU will revert to a standby
mode. However, if the function code specifies that data is
to be received from one or more MTU's, the SCU will go into
a receive data mode and wait for receipt of data from the
MTU~s) for transfer to the RCC.
It is significant to note that when the reading
control center (RCC) issues a command over a voice grade
line 14, the SCU's connected to that line simultaneousl~ re-
ceive that command. Only those SCU's recognizing their
assigned address(s), as specified by the command, willtransfer that com~land over their corresponding power lines 18.
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21ME-15
~83~9
As previously mentioned, messages are transmitted
at a frequency of fO over each SCU's respective power line
to a plurality of meter terminal units (MTU's) connected to
each of those power lines. In response to certain commands,
the MTU's will respond with data representative of a measured
commodity at a specified frequency.
Table 1 illustrates representative power line
transmission or carrier frequencies which may be employed in
the systemO A Set No. column in the table specifies a set
number of a group of frequencies in the row corresponding to
the Set No. The frequency in the fO column specifies the
power line carrier frequency of messages transmitted by the
various SCU's. The frequency in the fl - 8 columns speci-
fies the power line carrier requencies transmitted by a ~ ~'
group of eight MTU's connected to the power line by the SCU
transmitting the f~ carrier in the Set No. corresponding to
those frequencies (fl ~ f8).
It will be noted that the MTU's 20 on each p~werline 18 are organized into groups, such as Group l:through
Group N in Fig..1. Likewise, N number of groups comprise one
set of N MTUgroups Each MTU in a group transmits it3 data at
an assigned frequency. For example, in Group 1 it is shown
that an MTU 20' transfers its data at a frequency fl, where-
as an MTU 20" transfers its data at a frequency f8. All
other MTU's, not shown în Group 1, transmit their data at
corresponding frequencies f2 ~ f7. Preferably, the data
transferred from the MTU's to the SCU's is at 30 bits per
second with data pulse bursts of energy at frequencies f
through f8.
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Reference is now made to the meter terminal units
20 ~MTU's) of Fig. 1. Each o~ the MTU's is located at me~
tering locations ~uch as household residences, business
residences, factories or the like. The primar~ pur~ose of
each MTU is to provide communication interface between the
SCU's 16 via the power line~ 18 and commodity measuring
meters 22 and electrical loads 24 connected to the MTU'~.
Each MTU responds to messages or commands to read and store
meter data representative of a measured commodity such as
the consumption of power, water or gas, and transmit the
previously stored data to the RCC via the MTUIs associated
SCU. Each MTU also responds to commands to control user
loads within a residence such as hot water heaters, air
conditioners, alert lights, etc.
A command function code specifies to the MTU's
whetller meter information is to be read and stored, whether
the previously stored information is to be transmitted o~er
the power lines or whether a load or loads is to be con-
trolled. The function code also specifies a particular meter
to be read or a load(s) to be controlled.
The MTU's are individually addressable, group
addressable or addressable in large sets comprised of several
~roups. A set may encompass all MTU's on a power line. One
MTU is generally addressed when it is desirable to interxo-
gate only one residence, for example, during meter surveyoperations. During normal m~ter reading operations, however,
groups of eight MTU I 5 are generally addressed. The purpose
of this will become more clear in the ensuing description.
There are situations in a large power system of the type
Ahown in Fig. 1 when it is either desirable, or necessary,
to ~uickly remove all loads from the entire system. This
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~83~8g
would occur under conditions o a catastrophic power
failure which necessitates a mass scramble to shutdown an
entire system to prevent damage to the power transmission
equipment. In this latter situation, the MTU's can be
addressed in large sets or, if desired, all MTU's in an
entire system can be simultaneousl~ addressed. Set address-
ing of the MTU's can also be used for the mass reading and
storing of the meter data in the MTU's for subsequent
transmission.
The unique addressing scheme of the system permits
calling on small concentrated groups of MTU's ~or the trans-
mission of meter data or for the performance of various
functions in large geographically dispers~d sets of MTU's
for simultaneous actions such as read and store data or load
control.
There are many su~h meters on the market suitable
for employment in the present system. In the preferred em-
bodiment, however, the meters employed ha~e encoders for
transferring consumed commodities such as power, water or
gas to the MTU's for storage for transmission at a later
time. Several types of encoder type meters are known such
as contact switch closure types, parallel switch contact
types, optical read-out, etc. The present s~stem preferably
employs a mechanical non-destxuctive storage encoder which
provides a meter serial data readout as disclosed in U. S.
patent 3,846,789, issued November 5, 1974, entitled Remote-
Reading Register with Error Detecting Gapability, to
Warren R. Germer et al and assigned to the assignee of the
present invention.
Message and Data Formats
Prior to proceeding with a further description of
the system, it is considered advantageous at this time ko
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1~836~
provide a detailed description of the various message and
data formats of the information transferred between the RCC
and the SCU's and MTU's of the system. Xeference is now
made to Fig. 2, which illustrates the format of the messages
or commands transferred from the RCC to the SCU's. It will
be noted that the message is in ten bit ASCII code ormat
wherein each character is comprised of a start bit at the
beginning of the character and a stop bit at the end of the
character. Eight bits o~ information are included between
the start and stop bits of each character. The first charac-
.
ter received by an SCU from the RCC is an SCU address. The
second character forms a portion of the MTU address. It will
be noted that the third character is comprised of three bits
of MTU address and five bits of information which specify an
SCU/MTU function code. The decode o~ these five bits by the
SCU speci~ies to that unit its mode of op~ration. If the
function code speci~ies that either a control or a meter read
and store function is to be performed by an MTU(s), then a
data response is not expected by the SCU, and it will revert
to the standby mode after transmission of the message to the
MTU(s). If, however, the function code specifie~ that
information is to be received from the MTU, the SCU will go
into a wait or data receive mode. After the MTU(s) data
has been received by the SCU and transferred to the RCC, the
SCU will revert back to the standby state in preparation for
receipt of another message from the RCC.
The last character in the mes~age received by the
SCV from the RCC is a parity character. The present system
employs the well-known Bose-Chauduri check code generated
by the Polynomial 1 + X ~ x6 operating on the 24 meesage ~its
tran~m~tted ~rom the RCC to tha SCU, and on 36 bits of data
transmitted by each MTU. Only ~ix bits of the elght-bit
parity character are used, the la~t two ~t6 ~eing ignored.
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21 ME-15
Even though the use of parity is described in the present
system, it forms no part of the invention and is merely
illustrated for a more simple understanding of the disclosure.
It is to be understood that other types of parity schemes
could be just as effectively used.
Reference is now made to Fig. 3, which illustrates
;the message format of messages transferred from an SCU(s) to
~an MTU(s). It will be noted in this message that the start
::,
and stop bits do not exist. Logic within the SCU removes or
strips off the start/stop bits and appends to the front of
the message a start message code of three bits having the
binary configuration of 001. These start bits are used by
the MTU to detect the start of a message from the SCU. It
will also be noted that the SCU passes the message intact as
received minus the start/stop bits. That is, it transfers
the SCU address in an eight-bit field, the MTU address in an
:3eleven-bit field, the MTU function code in a five-bit field
and the six-bit parity code. For purposes to be later de-
scribed, it should be noted at this time that the SCU regen-
erates the SCU address and does not pass that address on
precisely as received from the RCC. Additionally, the SCU
regenerates parity because a portion of the message address ;
may be altered.
Reference is now made to Fig. 4, which shows the ;
data format of messages transmitted from an MTU(s) to an
SCU(s). As previously mentioned, the MTU responds to
basically three different commands: Read and store, per-i~
form a control action, and transmit a meter reading. As
such, as shown in Fig. 4, the only data transferred from
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the MTU's to the SCU'~ ov9r the poWer lines is a message
carrying information or data repxesentative of the metex dial
readings from the encoder of an addressed MTU meter. When
an MTU receive.s a transmit command from the SCU, the message
format as shown in Fig. 4 is transmitted by the MTU. The
MTU, like the SCU, generates three message start or sync bits
as binary 001 for recognition by the SCU to detect the start
of a message or data word. Further, the meter encoder gen-
erates an identific~tion code (ID~, as the second six-bit
character. The generation of this code is shown and described
in the aforementionedU.S. Pat. 3,846,789, and is for usé by t-he
RCC computer program to identif~ the particular meter being
read.
Following the meter encoder identification code are
five six-bit binary characters generated by the meter encoder
representative of meter dial readings 1 through 5. The last
character in the message transferred by the MTU's to each SCU
is the six-bit parity code. It is to be emphasized that the
message format shown in Fig. 4 is representative of the data
message transmitted by each addressed MTU to an SCU over the
power lines.
As previously mentioned, in the present system
groups of MTU's ~e.g., eight MTU's) can be simultaneousl~
addressed to transer their corresponding meter data to the
SCU. In the present s~stem, when a group of eight MTU's is
addressed, these eight MTU's basically transfer the meter
data symultaneously over the power lines to their corre-
sponding SCU. Also, as previously mentioned, this trans-
mission of data from each MTU is at a different frequenc~
corresponding to each MTU. Each SCU contains eight narrow-
band receiver amplifier circuits capable of discriminating
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between the frequencies of the messages ~rom each of the
eight MTU's. As a result, when eight separate messages are
placed on the power line, the SCU is capable of receiving
each of those eight messages in its corresponding amplifiers.
Reference is now made to Fig. 5, which shows the
message o~ data format of information from an addressed
group of eight MTU's and how that information appears on
the power lines at the SCU's. Not shown in Fig. 5 are the
three message start or sync bits 001 generated by each MTU.
It will be noted that when eight MTU's are simultaneouslv
addressed to transmit information to an SCU, the message bits
of each MTU are transmitted simultaneously in a serial fashion
onto the power line. The first character to be transferred
by each MTU (at their corresponding frequencies fl - 8) is
the first identification code bit of the addressed encoder
or meter of each one of the MTUIs 1 - 8 (See Fig. 1). Not
shown in Fig. 5, but also transmitted immediatel~ thereafter
are the 2nd, 3rd, 4th and 5th identification code bit char-
acters. Next, the sixth identification code bits are trans-
mitted from the MTU's 1 - 8. Following the last character
containing the meter identification code bits are the meter
dial readings (dials 1 through 5) in corresponding bits
characters 7th through ~6th. Following the 36th bits
character are bits characters 37th through 42nd, which
contain the parity bits generated by each of the MTU's.
The information as shown in the message format of FigO 5
i~ received a bit at a time ln each of the eight separate
channel receivers of the SCU and assembled in the SCU into
eight-bit ASCII characters for transfer to the RCC for
processing.
C - 11
~9
..
33~;~9
Reference is now made to Fig. 6. Comparing the ~ ;
message formats of Figs. 5 and 6, it can be seen that a great
deal of similarity e~ists between those formats. The SCU,
in reformating the message for transfer to the RCC, first
s appends a start and stop bit to each chara¢ter developing ~;
the ASCII code. As previously described, each MTU message
; to the SCU is comprised of ~2 bits (i.e., minus the three
message start bits). The SCU detects these three message
start bits; however, they are removed before the message is
transferred to the RCC. ~s can be seen in Fig. 6, the
message is transferxed basically intact as shown in Fig. 4.
That is, the fixst character transferred from the SCU to the
~CC is comprised of eight bits corresponding to frequencies
fl ~ f8 from each of the ~5TU's 1 through 8. Each o~ these
bits corresponds to one bit from the MTU generating the
message bit at that specific fre~uency. The message format
of Fig. 6 is basically the same format of Fig. 5, wherein
bits 1 - 8 of characters 1 - 6 of the message co~prise tha
meter encoder identification code ~or eight MTU's. Bits
1 - 8 of characters 7 - 36 comprise the meter dial readings
of meters 1 - 5 of each of the eight MTU's and bits 1 - 8
of characters 37 - 42 comprise the parity bits for each of
the eight MTU's.
Although not forming a part of the present inven-
tion, it is worth noting that the RCC program receives the
data in the format shown in Fig. 6 and organizes that data
by assembling each of the bits of the characters into com-
plete words corresponding to data from ~ach of the MTU's.
Once this data is formatted into words corresponding to each
of the MTU's, then that data can be appropriatel~ processed
b~ a computer program for billing purposes, load control,
C - 12
~ 2D ~
~33~iit39
~eter surveying, etc.
~ System operatiGn - Flow Charts
:.
Figs. 7 and 8 are flow charts showing the sequence
of operations for the entire system. Referring first to
Fig. 7, there is shown a flow chart which exemplifies the
operation of the system during the generation of a read an~
store or load control sequence by the RCC. The initiation
of a command from the RCC is indicated by a start circle in
Fig. 7. The read and store or load control command is pro-
vided to one of the voice grade trunk-lines 14 (Fig. 1)
activated at that time by the RCC. The message is then re-
ceived by the SCU's on that line, which check to see if
message parity is okay and if ~he address contained within
the message is meant for one or all of the SCU's. If an
SCU does not recognize the address, or if the parity check ;
is bad, that SCU branches through a no exit into an "SCV
resets to standby" block. That SCU will thus remain in a
- standby mode pending receipt of another message. If, however,
a~ SCU determines that the parity check is oka~, and that
the address contained within the message is meant for that
SCU, it exits through a ~es branch into an action block
wherein the SCU proceeds to retransmit the command onto the
power line and reset to standby.
The message now being transEerred onto the power
line goes to each of the MTU's connected to that power line.
Each MTU checks to see if the ~arity of the message is okay.
Each MTU also checks to see if the message address is meant
for that MTU and if the function code is valid. If any one
of these conditions does not properly check, the MTU will
exit a no branch, at which time it resets to a standbY mode
in preparation to receive another message. However, if all
of the tests are valid, the MTU exits through a ~es branch
and the function code is decoded to d~termine which operation
C - 13
21
~. .
1~8~6~ :
.
is to take place by the MTU. If the function code is
detected as a read and store oommand, the program exits
through an R & S branch into an action block wherein the
MTU reads the specified meter encoder of one of a plurality
of meter encoders and stores the meter dial readings of
; that encoder into a designated one of several registers in
the MTU as specified by the function codle. The MTU then
resets to the standby mode. It is in this manner that the
MTU can be commanded to read and store meter information for
subsequent recall by the program in response to an MTU
transmit command to subsequently be described.
Referring now back to the "which function code?"
decisi~n block, if the function code is decoded as a load
and store command, the MTU then exits through an LC branch.
The LC branch enters into an action block wherein the MTU
or MTU's, if more than one is addressed, actuates the speci-
fied load or loads to perform a designated operation or
operations as specified by the function code. Upon termi-
nation of the load control operation(s), the MTU then resets
to standby in preparation to receive another messa~e.
Reference is now made to Fig. 8, which is a flow
chart showing how each MT~ responds to a transmit command
issued by the RCC. Similarly to Fig. 7, the RCC/ in a
start circle, initiates the transmission of a transmit com-
mand to a selected one of the trunk lines 14 to the SCU(s)on $hat line. The SCU(s) connected to that trunk line checks
the message parity and address as described for Fig. 7. If
either of these conditions fail, a no branch is taken out of
the "SCU Parity Address OK?" decision block and the SCU re-
sets to standby. If, however, the parity and address checksare positive, the SCU exits through a yes branch into an
C - 14
~?2
~983~
.
: action block whereln the SCU retransmits the co~mand onto
the power line and then goes into a waik mode for receipt
of the meter data from the addressed MTU(s). The MTU(s~
then checks the parit~, address and function code as pre-
:~ 5 vlously described. If either of th~se checks fail, the
MTU exits through a no branch and resets to standb~. If
all conditions are positive, however, the MTU(s) begins to
transmit the meter data from the register as specified by
the function code in the transmit comman~. After tlle MTU(s)
has transmitted all of the meter data from the designated
register, it resets to the standby state in preparation to
receive another con~and.
: SECTION CONTROL UNIT
(SCU)
OPERATIONAL D~SCRIPTIO~
Reference is now made to Figs. 9, 10, 11, 13 and
14, which are legendary drawings showing the inter-relation-
ships between the various drawings of the SCU~
The timing diagrams showing the operation of the
SCU are shown in Figs. gA and 9B, Figs. 10A - 10D, Figs. llA -
llH,and the detailed logic of the SCU is shown in Figs. 13A -
13F and 14A - 14D. The various shi~t registers, counters,
flip-flops and gatiny circu:Lts utilized in the construction
of the SCU are preferably fabricated from integrated circuit
logic.
The various blocks comprlsing the above-mentioned
circuits may be fabricated from commercially available de-
vices as listed in Table 2. The listing in Table 2 gives
the manufacturers' names, the manufacturers' part number
and the circuit name identification as shown in the drawing.
Footnotes 1 - 5 at the end of Table 2 give the manufacturers'
references where the various circuits can be found.
C -15
.~3
. ;. . . i . ~ ;;
.. . .... ... .
15al8~
`` TABLE 2
SECTION CONTROL UNIT
MANUFACTURERS' CIRCUIT
IDENTIFICATION
CIRCUIT NAME MANUFACTURER MANUFACTURER~S
_ NO. _
MODEM RFL ~NDUSTRIESt1 TRAMSMITTER
INC. (68AT-WF-D)
RECEIVER
(6SR-~F-5)
DATA TRANSMITTER/ GENERAL INSTRUMENT2 AY-5-10131
RECEIVER CORP. AY-5-10134
RECEIVE DATA MEMORY SIGNETICS CORP.3 S54170
REGISTER
CHARACTER COUNTER ll ~I S5~93
WRITE CHARACTER F/F ll ll S547~
SYSTEM CONTROL F/F l~ ll S5474
PARALLEL IN SERIAL ll l~ S54166
OUT REGISTER
RE5PONSE EXPECTED F/F ll ll S5474
FFEF 1~ ~ S5474
FFDF I~ ll S5474
RTSFF ~l ll S5474
PLRFF - ll ll S5474
SAXFF l~ ll S5474
GRFF l~ ll S5474
POWER LINE CONTROL ~ ~l ll S54161
COUNTER
REGISTER READ OUT/ ll ~I S54161
ADDRESS CHECK COUNTER
S/R CONTROL F/F ll n S5474
SCUADD F/F ~ S5474
POWER LINE XUITR F/F n n S5474
ISEC DELAY FOR NEXT ll 1~ S5490
CHAR.
30 Ms DELAY COVNTER ~ ll S5495
3 Ms DELAY CONTROL F/F ll ll S5474
~ 16
.?~
-: . .
- . ,
.. ~. . . . .. . .
~`\ ~
Tab1e 2
Page - ~ -
STATE F/F SIGNETICS CORP. S5474
STORE A F/F ~ 547~ -
STORE B F~F ~ S5474
267 MS DELAY . COUNTER ~ 5492
FF1A ~ S~474
50 M5 F/F ~ S5474
FF2A ~ S5474
EOM F/F ~ S547~
50 MS DELA~ . 12 COUNTER ~ ~ S5493
30 HZ STROBE CI,OCK ~ S5493
COUNTER
MESSAGE LENGTH COUNTER ~ S54161
~A, 0B, 0C, 0D F/F~S ~ S5474
REMOVE START BITS ~ TWO S5473
COUNTER
ONE SHOT ~ S54121
NARROW BAND TEXAS INSTRUMENTS4 THREE
RECEIVER/AMPS INC. SN52709AL
BAN~ P~SS FILTER GENER~L INSTRUMEMTS5 TWO AY-6-4016
CORPORATION INTERCONNECTED
THR~GH AN
SN52709AL
: . lThis modem can be found in RFL Industries, Inc., :
Boonton, N. J. U. S. A., publication entitled,
Voice-Frequency Carrier Equipment,.Series 6850,
revised 5/75.
- 2This circuit can be found in General Instruments
Corp. Microelectronics Technical Bulletin entitled,
UAR/T Universal Asynchronous Receiver/Transmitter,
AY-5-1013/AY-5-1013A, March 1974~
All Signetics circuits, including logic gates not
listed in Table 1, can be found in the manual entitled,
Signetics Digital Linear MOS Data Book, copyright 1974.
4This circuit can be found in the Texas Instruments, IncO
manual entitled, The Linear and ~nterface Circuits Data
Book for Design Engineexs, copyright 1973.
5This circuit can be found in General Instruments Corp.
Advance Bulletin 1970, entitled MTNS 16 ~hannel
Random/Sequential ~ccess Multiplexer AY-6-~016.
C - 17
~ 2 5
The operation of the SCU will be described in
basically two modes of operation. The first mode will be
with the SCU starting in standby and its oyeration when
receiving a message from the RCC and the transmission of
S that message onto the power line for receipt by an MTU(s).
The second mode of operation to be described will be with
the SCU in the wait mode and its operation when receiving
meter data over the power line from an MTUts) and the
transfer of that data to the RCC.
Let it first be assumed that power has just been
applied to the SCU. With the applicatlon oE power, a
power on reset block 26 in Fig. 13A applies a binary 1 re-
j set pulse to an R terminal of a system control flip-flop 28
i via an OR gate 30 and a conductor 32. Flip-flop 28 now re-
sets ~enerating a ~inary 1 SCU reset signal on a conductor 34
connected to an O output terminal of flip-flop 28. The SCU
reset signal is applied to the various registers, counters
and ~lip-flops in the SCU, causing those devices to all re-
set to a binary 0 state and placing the SCU in the standby
mode.
Referring now to Fig. 13E, there i8 shown a master
clock generator 36 now genera~ing a plurality of output
timing signals for use in controlling the SCU timing opera
tions. These various timing signals are shown connected to
the appropriate circuits in the SCU as well as being shown
in the aforementioned SCU timing diagrams.
Reference is now made to Figs. 9A and 13A. In
Fig. 9A at the top of the timing diagram, there is shown a
message from the RCC appearing at a receiver/demodulator 38
of an SCU modem on a trunk line 14. As previously described,
- this message is transmitted in ASCII code using FSK
C - 18
~ .
~6
39
transmission techniques. Transmission is preferably at
300 baud. The receiver 38 passes the message in serial
~orm into a data transmitter receiver circuit 40 via a
conductor 42. The data transmitter receiver 40 is a
universal asynchronous receiver/transmitter LSI subsystem
which accepts binary characters from eithex a terminal
device such as a modem, or a computer such as the RCC. As
will subsequently be described, this subsystem also re-
ceives data characters in parallel, Data output ~rom this
subsystem is also in serial or parallel.
As previously described in connection with Fig. 2
and as shown in Fig, 9A, all incomin~ characters to the SCU
from the RCC contain a start bit, eight data bits and a stop
bit. As shown in Fig. 9~, when the data transmitter/re-
ceiver 40 detects a mark to space transition, it detects
- that transition as the start bit of a character and begins
to take ln the eight data bits plus the stop bit. When the
tenth bit (end of the first character) is received by the `~
data transmit;er/receiver 40, that cixcuit generates a
binary 1 data available signal D~V on a conductor 44. The
DAV signal is applied simultaneously to a set input(s) of
a write character flip-10p 46, as one input to an ~ND gate
48 and to a one-second delay circuit 50 of Fig. 13C via a
conductor 49.
The presence of the DAV signal at AND gate 48
causes that gate to be enabled due to three binary 1 output
signals, CCA, CCB, CCC, applied to gate 48 from a character
counter 52 via a plurality of conductors 54. With AND gate
48 enabled, a binary 1 CC0 (character count 0) signal is
; 30 generated on a conductor 56 and applied to a set(s) input
texminal of the system control flip-flop 28, setting the
latter,
C - 1
27
21ME-15
~8;~8~
' It will be xecalled, at the outset of the present
discussion, flip-flop 28 was reset when power was applied
to the system. With the system control flip-flop 28 now
sët at the time shown in Fig. 9A, the SCU reset signal goes
to a binary 0 removing the reset signal from all counters,
registers and flip-flops in the system, thus freeing the
system to run.
- Reference is now made back to the write character
fl.ip-flop 46, which is set by the DAV signal. As can be
seen in Figs. 9A and 13A, the write character flip-flop
generates a write enable signal WE on a conductor 58, which
:
is applied as an enable signal to a receive data memory
register 60 to effect the parallel transfer of the eight-
bit data character now in the data transmitter/ receiver 40
into the receive data memory register via conductors 62.
The receive data memory register 6~ is basically
an LSI memory capable of storing a complete 32-bit message
(four eight-~it characters) into selectable character
locations of that memory. The locations in the data memory
register are selected hy a plurality of address signals CCA
and CCB (called write select in Fig. 13A) on conductors 64
fr~m the character counter 52, As shown in Fig. 9A, the
WE signal allows the first message character to be loaaed
into the receive data memory register into a location
specified by CCA and CCB It will be noted that the write
character flip-flop 46 receives at its reset (R) input
terminal a 48 kHz clock signal from the master clock gen-
erator 36 of Fig. 13E~ This signal is shown in Fig. 9A
resetting flip-flop 46.
As soon as the write character flip-flop 46 is
reset by the 48 kHz clock, it~ one-output terminal causes
the WE signal to go to a blnAry 0 and it~ O output term~nal
C - 20
`' ,~f~
. .
~Ci8
.
to go to a binary 1 generating a Reset DA~ signal. As
shown in Fig. 13A, ~his latter signal is applied to the
data transmitter/receiver 40 and to the character counter
52 via conductors 66 and 68, respectively. The Reset DAV
; 5 signal causes the DAV signal to now go t:o a binary 0 ~nd
simultaneously causes the character counter 52 to count
up to a count of one as shown in Fig. gA ~CCA set). With
the character counter now setting at a count of one, it
can be seen that the CCA signal is at a binaxy 1 and the
la CCB signal is at a binary 0, thus applying the proper input
address`signals to the receive data memory register fi0 on
conductors 64 for receiving the second message character.
The second, third and fourth characters will con-
tinue to be taken into the data transmitter/receiver 40 and
placed in the proper character positions of the receive data
memory register 60 under control of the CCA, CCB and WE
signals in the manner just described. As shown in Fig. 9A,
when the fourth character has been loaded into the receive
data memory register, the CCC output of the character counter
2Q 52 goes to a binary 1, indicating that the rece~ve data
memory register is full.
A momentary di~ression is now made in the present
description by referring to Fig. 13A to the one-second delay
for next character circuit 50. It will be noted that that
circuit receives the DAV signal and a 4.8 kHz clock signal.
The purpose of the one-second delay is to cause the SCU to
reset if it does not receive a data character within one
second from the generation of the first DAV signal. If a
character is not received within the one-second time inter-
val, a binary 1 time-out signal on conductor 70 is applied
to the system control flip-flop via OR gate 30 causing the
SCU to reset. In this manner, should a falsle start bi~ come
C - 21 .,
~ 9 , ~.
~ 336~
down the telephone line 14 fro~ the RCC, the system will
not be fal~ely triggered into operation. It will also be
noted that the CCC signal from the character counter is
~p~l~ed to an inhibit input of the one-second delay via
conductor 72. The CCC signal is normally a binary O to
enable the one-~second delay through a circle inverter.
However, when the CCC signal goes to a binary 1I that signal
is ~nyerted to a binary O inhibiting the operation of the
one~second dela~ and pre~enting the time~out signal from
bein~ generated a~ter the last character has been fully
l~aded into the receive data memor~ register,
Reference is now made to a register read-out/
address check counter 74 of Fig~ 13C recei~ing the CCC sig-
nal fro~ the character counter 52. The CCC signal is a
binary O until the character counter has counted to its
~aximu~ (count of 4). When the CCC signal is a binary 0,
; it provides an inhibit/reset input signal to an R terminal
of counter 74 preventing the counter from counting and keep-
ing it in the binary O or reset stateO As shown in Figs. 9A
2Q and 9B, when the CCC signal goes to a binary 1, the inhibit/
reset signal is removed, enabling the register 74 to begin
counting at a 48 kH~ rate as shown by a start RR and ACC line
in Fig. 9B. Fig. 9B is actually a continuation of Fig. 9A,
but it is based on a different time frame with all timing
derived at a basic 48 kHz rate.
The purpose of the register xead-out/address check
counter 74 is to generate coded count outpu~ signals to con-
trol the operational timing of the SCU during checking of the
message received from the RCC.
It will be noted that register 74 generates six
output signals designated RCA through RCF on a plurality of
conductors 76. The final stage of register 74, des:ignated
C 22
~L~8361~
RCF, is applied as one input to an AND gate 78 as RCF.
The other input to AND gate 78 is the 48 kHz clock signal
as shown in Fig. 13C. Since register 74 is reset at this
time, the RCF signal is a binary 1, thus enabling AND gate
78 to allow the 48 kHz clock to be applied as a register
count signal RCNT to a trig~er (T) input terminal of xeg-
ister 74. The relationships between the RCA through RCF
signals are shown in Fig. 9B. Since register 74 is a
straight-forward blnary counter, only signals RCA, RCB and
lQ ~CF are shown, it being understood that the operation of
such type counters is well understood by those of ordinary ;~
skill in the art.
A decode network comprised of two sets of AND
gates 80 and 82 in Fig. 13C receives the RCA - RCF output
signals from register 74 to generate the proper control sig-
nals for controlling the operation of the SCU. Reference is
first made to an AND gate 84 of the group of AND gates 80
receiving input signals RCA, RCB and RCC. As shown in the
timing diagram of Fig. 9B, a binary 1 xead enable 1 signal
2Q is generated on conductor 86 from AND gate 84 in response to
the just described input logic conditions. The read enable 1
signal is applied via conductors 86, 88 and an OR gate 90 as
a read enable signal to the receive data memory register 60.
The read enable signal is also applied as a shift/load sig-
nal to a parallel in~serial out-register 92 via a conductor
94 to enable that register to receive a parallel character
from memory register 60.
The read enable signal now enables the receive
data memory register 60 to transfer the first message
character, in parallel, via its output data lines 96 through
a conventional multiplexer circuit 98 into the parallel in-
~erial out-register 92. Addressing of the receive data
C -
~1 :
3. .
memory register is controlled by two input signals RSA and
RSB on conductors 100 from two OR gates 102 and 104. llhe
- OR gates 102 and 104 receive respective input signals RSAl
~nd RSBl via conductors 106 and 108 from the output of
register 74. These two signals are actually the RCD and
RCE outputs o register 7~. As can be ~een in the timing
diagram of Fig. 9B, during the transfer of the first charac-
ter from memory register 60 into registry 92, the RCD(RSAl)
and RCE (RSBl) signals are binary 0's~ These two binary 0
signals effect the generation of binary 0, RSA and RSB sig
nals to cause the read-out o the least significant charac-
ter o~ the message from the receive data memory register.
_ by referring to Fig. 2, it can be seen that this first
character is the SCU address character.
The SCU address character, which i5 now present
in the parallel in-serial out-register 92, is the first
character to be checked. This character is checked as
follows: Reference is now made back to Fig. 13C to the
group of ~ND gates ~2, whcrein one of those ~ND gates 110
is receiving the read enable signal and an output signal on
conductor 112 from another AND gate 114, the latter re-
ceiving the 48 l~h~ clock and the t~o input signals RCD and
RCE from the register read-out address counter 74. Since
these latter two signals are now binary l's, AND gate 114
is enabled to allow the 48 kHz clock to be applied to AND
gate 110 generating a check address (first character) output
signal on a conductor llG. The generation of this latter
signal is shown in Fi~, 9B in coincidence with the read
enable signal applied to the memory register 60 and
register 92.
The check address (first character)~,signal on
conductor 116 is applied to two gate logic structures
C ~ 2~
.
32
~83~
labeled, this SCU address compare gates 118 and all SCU
address compare gates 120 of Fiy. 13E. As previouslv
mentioned, each SCU is capable of recognizing its own dis-
tinct address as well as an address which is common to all
SCU's in the entire system. The comparison of the address
in these two gate structure~ i~ effected by the parallel
input address bits being applied thereto from the receive
data memory register via a data bus 122.
The comparison of the distinct SCU addres~ in `~
gate structure 118 is effected by a comparison of the SCU
address now applied from the receive data memory register
with a plurality of binary signals TSCUA (this ~CU address)
on conductors 124 from a box 126 designated this SCU fixed
address. Box 126 may be hardwired or switch selectable to
apply the appropriate binary input signals (TSCUA) to the
;compare gate structure 118. 'rhe contents of box 126 is
preferably switch settable so that each SCU can easily be
assigned its own address. If the address from the receive
data memory register does not match the TSCUA addressing
signals, a fail 1 signal is generated on conductor 128 and
applied to an AND gate 130 oE Fig. 13D. The purpose of which
will subsequently be described.
The ALL SCU address compare gate structure 120
contains its own hardwired address for comparison with that
address coming from the receive data memory register. The
logic in box 120 is designed to recognize an address common
to all SCU^s in the system. If the ALL SCU address compare
does not check with the message address, compare gates 120
will also generate a fail 2 signal on conductor 134. This
latter fail s.ignal is also applied to AND gate 130. If
both inputs (fail 1 and fail 2) to AND gate 30 are binary 118
an SCU address flip_flop 132 is set.
C - 25
33
, . . .: ,
~83~ J
Setting of the SCU address Elip-flop 132
generates a binary 1 output signal designated address
compare fail on a conductor 136, which is applied to the
system control flip-flop 28 via OR gate 30 to reset the
SCU. Thus, it can be seen, upon examination of the very
first character of a message, if the acldress does not
mat~h the ALL SCU address or the addrec;s of the specific
SCU, the system will revert immediately to the reset or
standby mode. The timing for setting and r~setting the
SCU address 1ip-flop 132 is shown in Fig. 9B.
Let it now be assumed that the address check is
valid. Under this condition, as can be seen in Fig. 9B,
the read enable 1 signal is again generated (the second
read enable 1 signal) to again enable the receive data
memory register to gate the data in parallel through multi
plexer 9~ into the parallel in-serial out-register 92. The
second data character is the MTU address (see Fig. 2), which
is gated from the second character position of the receive
data memory register under control of the RSA and RSB siy-
nals as previously described. At this time the RCD signalis a binary 1 and the RCE signal is binary 0. Thus, the
RSAl signal is in binary 1 and the RSBl signal is a binaxy 0.
It is the decode of these two signal~6tates which selects
the second character position out of the receive data memory
register 60. This data character is loaded into the parallel
in-serial out-register. However, as shown in Fig. 9B, the
MTU address is not checked.
After the MTU address is loaded into the parallel
in-serial out-register, the next character to be read into
that register from the receive data memory register is the
third message character, the SCU/MTU function code ~see
Fig. 2) As shown in Fig. 9B, the third read enable 1 signal
C - 26
3~
i8 now applied to.the receive data memory register in con
junction with the RSA and RSB signal3 on conductor 100. At
this time the RSAl si~nal is a binary 0 and the RSB1 signal
is a binary 1 (RCD is a binary 0 and RCE is a binary 1~.
Thus, the third data character is selected out of the re-
ceive data memory register and transferred via the multi-
plexer 98 into the parallel in-serial out-register. At this
time, the function code is to be checked to see if the mes-
sage from the RCC is of that type which dictates a response
from an MTU(s). This is accomplished by the generation of
a check function (third character) signal on a conducto~: 138
from an AND gate 140 of he group of AND gates 82 ~or appli
cation to an MTU response function compare gate structure 142
¦ (see Fi.g 13C),
Referring to AND gate 140 and to Fig. 9B, the
chec~ function signal is generated as a result of the decode
of the binary 1 RCD and RCE signals along with the 48 kHz
clock applied to AND gate 142, the output of which is applied
as one input to AND gate 140 along with the read enable 1
signal on conductor 86. The generation of the check function
signal effects a comparison of a hardwired coding in the MT~J
response function compare gates 1~2 with the coding of the
third character now applied in parallel to that gating
structure from the receive data memory reyister 60. If
there is no comparison between the SCU/MTU function code
and the wired unction code, a normally binary 0 signal on
a conductor 144 applied to a set(s) input terminal of a
response expected flip-flop 1~6 remains at binary 0, thus
leaving that flip-flop in the reset state.
With the response expected flip-flop 146 in the
reset state, its one (1) output terminal i6 a binary 0
s~gnal R~E`F on a conductor 148; which 1~ applied to an
C - 27
~ 3
: 5
~3
~i ,
inverter 150. The output of the inverter 150 is a binary 1
signal REFF, applied as one input to an AND gate 152. If
no response is expected, AND gate 152 w~ll be enabled at a
later time by a signal designated PL34 to apply a reset (no
response expected) signal to the system control flip-flop
via a conductor 154 and OR gate 30. The generation of the
PL34 ~ignal will subsequently be described.
Let it now be assumed, however, that the function
code of the command specifies that a response is expected
from a meter terminal unit(s). In this case, the resp(nse
expected signal on conductor 144 will go to a binary 1
causing the response expected flip-flop 146 to set. Flip~
flop 146 now generates a binary 1 REFF siynal on conductor
! 148. The REFF signal is applled via conductor 1~8 and 156
as one input to an AND gate 158 of Fig, 13~ The other
input signal to AND gate 158 is the PL34 signal to subse-
quently be described. As can be seen (Fig. 13Bj, when the
~L34 signal is generated, a power line receiver flip-flop
PLRFF 160 will be set generating a binary 1 output signal
designatcd PLRF to turn on all of the SCU power line re-
ceivers. The operation of the PLRFF flip-flop will be
described in more detail later.
It should also be noted at this time that the
REFF binary 1 signal is also applied via a conductor 161
to a transmitter modulator 162 of the modem to turn on the
carrier signal for the transmission of a data message to
subsequently be received from the addressed MTU or MTU's.
It should also be noted that when the REFF signal is a
binary 0, the transmitter modulator carrier signal is
turned off or diabled. This would be the situa-tion when
the response expected flip-flop 146 is reset~
Reference is now made back to Fig. ~R. After
the SCU/MTU function code has been checked and the response
expected flip-flop ei~her set or left in the reset state,
~ .
` C - 28
.~
~ ~ 21-Mæ-15
.. , . :
the fourth read enable 1 signal is generated to effect the
transfer of the 4th character from the receive data memory
register 60 into the parallel in-serial out-data-register 92.
As can be seen in Fig. 2, this 4th character is the parity
character. At this time the selection of that 4th character
from the receive data memory register is effected by khe
two binary 1 states of the RSA and RSB signals (RCD and RCE,
both binary l's). It will be noted, however, that parity
is not checked concurrently with the presence of the read
enable 1 signal, as in the case of the first and third cha-
racters of the message. A check parity (4th character) sig-
nal is applied via a conductor 164 to a parity ch~ck generate
circuit 166 from the output of an AND gate 168. The genera-
tion of the check parity signal is the result of the ANDING
in an AND gate 170 of the RCA, RCB, RCC and the ANDING in
an AND gate 172 of the RCD, RCE and 48 kHz clock signals. ~;i
The output of ~D gates 170 and 172 enable AND gate 168 to -
generate the check parity signal on conductor 164. The
operation of the SCU under a parity check fail condition
will be described later in more detail.
In order to further understand the operation of
the SCU, it is now necessary to refer to a shift register
control flip-flop 174 as shown in Fig. 13C. Referring now
to Figs. 13C and 9B, it is shown that the shift register
~5 control flip-flop 174 is set via a conductor 175 from AND
- gate 176 enabled by the binary 1 signals RCD, RCE and read
enable 1. Flip-flop 174, now generating a binary 1 output
signal on conductor 178 from its 1 output terminal, enables
; an AND gate 180 also receiving the 48 kHz clock signal.
The output of AiND gate 180 is a gated 48 kHz signal desig-
nated G48K-HZ on a conductor 182. The G48KHZ signal is
applied to an OR gate 184 of Fig. 13A. The output of OR
" ,.~
~ 7 ~
C - 29 ~/
21-ME-15
1L~38~6~39
gate 184 is applied as a clock data signal on conductor 186
to a trigger (T) input of the parallel in--serial out-register
92. The purpose of the clock data signal is to control the
parallel loading and serialized shifting of the parallel
in-serial out-register.
Reference is now made to Figs. 9A, 9B and 13A.
As previously described, the read enable signal on conductor
88 is also applied as a shift/load signal on conductor 94
to one input of the parallel in-serial out-register. As
shown in Fig. 9B, when the read enable signal (also shift/
load signal) is a binary 0, the shift register 92 is enabled
to be serially shifted. On the other hand, when the read
enable (shift/load) signal is a binary 1, the parallel in-
serial out-register 92 is enabled to be parallel loaded from
the receive data memory register 60. The actual parallel
clocking of data into the parallel in-serial out-register
from the receive data memory register is performed with the
G48KHZ clock data signal via gates 180 and 184. It will be
noted that the G48KI-IZ signal falls in the middle of the read
enable 1 pulse. The set/reset timing of the shift register
control flip-flop 174 is shown in Fig. 9B and how that flip-
flop controls the application of the G48KHZ signal to the
trigger input of the parallel in-serial out-register 92.
When data is serially shifted out of register 92,
that data is shifted in response to the G48KHZ pulses on
conductor 186 starting at the time immediately following
the return of the shift/load signal from a binary 1 to a
binary 0 as shown in Fig. 9B. As can be seen, the spacing
between the read enable 1 signal allows 7 G48KHZ clock
signals to be applied to the parallel in-serial out--register
each time a character is shifted out of that register. In
other words, for each read enable signal generated, the
:
~ C - 30 ~8
21-ME-15
g;~
eight bits in each character residing in register 92 are
shifted out in a serial data stream via a conductor 188
and fed to one input of the parity check/generate circuit
166. It is to be noted that this serialized shifting of
data out of the parallel in-serial out-register is taking
place substantially simultaneously with the parallel check-
ing of the SCU address and the MTU response function code.
The obvious reason for the serialized shif-ting of the data
into the parity check generate circuit 166 is so that the
circuit can check parity of the entire message coming from
the RCC. This type of checking in conjunction with the
decoding of the message saves time causing the SCU to ex-
pedite overall operations.
After the entire message has been checked, the
shift register control flip-flop is reset from an AND gate
190. That AND gate is enabled as a result of the ANDING of
signals RCE and RCD with the output of AND gate 170 receiving
the RCA, RCB and RCC signals.
Reference is now made back to the parity check
generate circuit 166 wherein that circuit, in response to
the check parity signal on conductor 164, will generate a
parity check fail signal which goes from a binary O to a
binary 1 if parity of the message is invalid. If the parity
check does fail, the parity check fail signal on conductor
192 will go to a binary 1 resetting the system control flip-
flop via OR gate 30, thus immediately placing the SCU back
in the standby mode.
Let it now be assumed that the message parity
check is valid. In this case, the parity check fail signal
on conductor 192 remains at a binary 0. This signal is
applied to an inverter 194 of Fig. 13D via conductors 192 and
196, where it is inverted to a binary 1. The output of
:' '
C - 31
.~:
~8~ 21-ME-15
inverter 194 is applied as one input to an A~D gate 198
along with the now present check parity signal on a
conductor 200 to enable that gate. Since parity is valid,
it is now proper to transfer the message rom the SCU to
the MTU(s) via the SCU's power line. Thls is accomplished
by the enablement of AND gate 194, which applies a binary 1
set signal to the S input terminal of a power line trans-
mitter flip-flop 202. As noted in Fig. 9B, the fourth
character (parity check) signal is utilized to set the power
line transmitter flip-flop.
With the power line transmitter flip-flop now set,
its one output terminal generates a binary 1 PLXF output
signal on a conductor 204. The PLXF signal, previously a
binary 0, now removes an inhibit clear inpu-t from a power
line control counter 206 of Fig. 13B. With the PLXF binary
1 signal now present at the input of the power line control
counter, the latter is enabled to now begin counting at a
30 Hz rate as shown in Figs. lOA and lOB.
The power line control counter is a six-stage
conventional binary counter generating binary count output
signals PLCl - PLC32 on a plurality of conductors 208.
Certain ones of the PLCl - PLC32 output signals are applied
directly to a control counter decode 210 and other ones of
those output signals are applied to three AND gates 212,
214, and 216 via conductors 218, 220 and 222, respectively.
; The logic structure of the control counter decode 210 is
defined in the following Table 3, which is a listing of
Boolean equations defining that structure.
~'
C - 32
~a
~ 33~
TABLE 3 :
SCU
POWER LINE CONTROL COUNTER
DECODE EQUATIONS
SRTSF = PLCl r PLC. . PLC4 . PLC8 . PLC].6 . PLC32
~CD = PLC4 . PLC8 . PLC16 . PLC32;
3RD SYNC BIT = PLCl . PLC2 , PLC4 . PLC8 . PLC16 . PLC32
RC~R = ~PLCl . PLC2(PLC4 . PLC8 . PLC16 . PLC32) + ~PLC4 .
PLC8 . PLC16 . PLC32)~
PL34 = PLCl . PLC2 . PLC4 . PLC8 ~ PLC16 . PLC32
PL27 = PLC1 . PLC2 . PLC4 . PLC8 . PLC16 . PLC32
As previously described, before the binary 1
PLXF signal is applied to the power line control counter
206, that counter is held in the reset state. Thus, prior ~ -
15to the occurrence of the first 30 Xæ ~ignal to counter 206,
a PLCl binary 1 signal is applied via conductor 218 to AND
gate 212 in conjunction with the 30 Hz signal. These two
signals now enable AND gate 212, which in turn enables an
AND gate 224 now receiving a binary 1 SCU REsrT signal from ~ :
20the system control flip-flop 28 of Fig. 13A. The output of : :
AND gate 224 applies a binary 1 reset signal via conductors
226 and 228 to two flip-flops SAXFF 230 and GRFF 232,
respectively.
Reference is now made to AND gates 214 and 216
of Fig. 13D. A second input to each of these ~ND gates is
; the now binary 1 PLXF signal on a conductor 234 from the
. . power line transmitter flip-flop 202. Since that flip-flop
is ~et ~t this time, these two AND gates are in a condition
~: . to be enabled when their respecti~e input signals PLC8 and
PLC16 from the power line control counter become binary 1 t S
. C - 33
~ ~ 41
.
3~
It will be noted khat the outputs of the two AND gates
214 and 216, designated as ~SB2 and RSA2 on conductors
236 and 238, are applied to the two OR gates 102 and 104 il
of ~ig. 13C.
S The RS~2 and RSB2 signals are utilized to enable
OR gates 102 and 104 ir.t the same fashion as previously de-
scribed for the RSAl and RSBl signals. These two si~nals
(RSA2 and RS~2~ will generate the proper logic levels for
signals RSA and RSB on conductors 100 to the receive data
memory register to effect the proper retrieval of message
characters from that memory during the transmit sequ~nce
of the messa~e, It will be noted at.this time that t~le
two signals PI.C8 and ~LC16, applied to ~ND gates 214 and
216, are now binary 0's; thus, the RSA and RSB signals
applied to the receive data memory register are likewise
binary 0's.
Reference is now made back to the control counter
decode 210 (Fig, 13B) now providing a plurality of output
signals wh.ich are ~cnerated at the ~roper times to e~fect
the serial transmissi.on of the messaye from the section
control unit (SCU) to the power lines and on to the meter
terminal unit(s). In aescribing the operation of the
transmit sequence of the SCU now under discussion, reer-
ence will be made to Figs. 10A - 10D and 13A - 13F and to
the previously mentioned Table 3. ~s pre~iously described,
,
at the beginning of a transmit sequence, the power line
. transmitter flip-flop 202 is set, enabling the power line
,.
counter 206 to count. As shown in Table 3, the first sig~
~ nal to be generated by the counter decode 210 is an SRTS~
: 30 (set xeady to send flip-flop) si~nal on a col~ductor 2~0.
The SRTSF binary 1 signal sets an RTSFF flip-flop 242
C - 3~
~! I!t~. 42
~,, ~ ,
causing its l-output terminal to generate a binary 1 RTSF
signal on conductor 244 at the time shown in Fig, 10C. The
~TSF sign~l is applied to an AND gate 2~6 on a conductor 248.
A binary 0 signal DCD ~data control delay) on a conductor
250 from an inverter 251 is keeping gate 246 disabled at
this tLme because of the binary 1 DCD signal from decode
210 (see Table 3), The purpose of the DCD signal will sub~
sequcntly be describedO The RTSF signal is also applied as
one input to a transmit AND gate 252 of Fig, 13F. One other
input to this latter AND gate.is the output frequency fo
of a crystal oscillator 253 in the SCU.. It i5 this oscilla-
tor which generates the high frequency pulse bursts of the
,' message bits transmitted onto the power line from the SCU.
j . RefeLence is now made back to the RTSFF flip-flop
242 of Fig. 13D. The zero ~0) output terminal of that flip-
flop is now a binar~ 0 applying a signal RTSF to an OR gate
254 ~ia a conductor 256, OR gate 254 is disabled at this
time xemo~ing a reset input signal from the R terminal of a
flip-~flop FFDF 258. The binary 0 RTSF signal on a conductor
260 also remo~es a resct signal from the R terminal of a
flip-flop FFEF 262, These latter two flip-flops are now in
a condition to be set at the propex time. . ... -
. The next output signal to be generated by the
control counter.decode 210 of Fig. 13B is a 3rd sync bit
binary 1 signal on a conductor 264. The equations for the
generation of this signal are shown in Table 3 and the timing
:~ I ox the generation of that signal is shown in Fig. 10C. As
can be seen, the 3rd sync bit signal has a pulse width of one ,-
bit time and is generated at the count of three by countex
20~. The generation of the 3rd ~ync bit signal at this time
effccts the generatlon of the 001 ~yne bit~ which arP appencled
. C ~ 35
, L;3
,
to the front of the message going to the MTU as shown in
Fig. lOC on the data bits XMITD. line. The binary 1 in the
001 sync bits is transferred to the power line by the 3rd
sync bit signal enabling an OR gate 265 ~Fig. 13F). The
S 3rd sync bit is passed through OR gate 265 to AND gate 252
via a conductor 267.
Referring to Fig. 13D, the 3rd sync bit signal
is also applied to an AND gate 266 in conjunction with a
- 0D signal from the clock generator 36 of Fig. 13E, enabling
that AND gate to set FFDF 258. Setting FFDF performs t-wo
functions. Its one (1) output terminal now applies a
binary 1 signal FFD via conductor 268 to an AND gate ~70 of
Fig. 13F. AND gate 270 is also receiving a ~B signal to
now allow the generation of parity clock signals for appli-
cation to the parity check generate circuit 166 through an
OR gate 272 via conductors 274 and 276. Thc binary 1 FFD
signal from FFDF 258 is also applied via conductor 278 as
one input to an AND gate 280 of Fig. 13A in conjunction with
a 0A signal. This latter AND gate is now ena~led to generate
a gated 30 Hz signal (G30HZ of24 pulses) on a conductor 282.
As shown in Figs. lOD and 13D, the FFDF flip-flop which
controls the G30HZ signal will be reset after a period of
24 counts by a PL27 siynal, thus covering a period of 24
bits to be shifted onto the power line from the 5CU. The
G30HZ signal will be applied via OR gate 184 to the T input
terminal of register 92 to control the shifting o~ data
through that register for this ~4-bit period.
Reference is now made back to the control counter
decodc of Fiy. 13B and to Table 3. The DCD signal will
enable AND gate 246 (still receiving the RTSF signal) when
the power line control counter 206 achieves a b:inary count
of 4 (the end of the three sync bits). The output of AND
gate 246 is a binary 1 DCT signal on a conductor 284 applied
C - 36
'~ 4
. . .. .
3G~9
`
to an ~ND gate 286 in conjunction with serial data ~oming
from the parity check generate circuit on a conductor 288
(Figs. 13E, 13F and 13D). It should be noted that AND
gates 246 and 286 are not enabled until the 4th bit of the
message is to be transmitted onto the power line. Simul-
taneously, the 3rd sync ~it signal goec, to a binary 0.
Referring to Fig. 10C, to the line designated data bits ,~
XMITD., it can be seen that the 3rd sync bit is transmitted
just prior to the first eight message data bits designated
SCU ~ixed address. AND gate 286 is now enabled to allow the
2~-bit message of serial data to be transferred through that
AND gate out to the power lines 18 via OR gate 265, AND
gate 252, a power line tran~,mitter 290 and a power line
coupler 292.
Refercnce is a~ain made )~ ck to the control counter
decode 210 of Fig. 13B to the 3rd sync bit signal line. This
signal is also applied via a conductor 294 to an ~ND gate 296
also receiving the 30Hz signal. As shown in Figs. 10C and
13B, AND gate 296 is enabled with the 3rd sync bit signal to
set a flip-flop SAXFF 230. The SAXFF flip-flop now genexates
a binary 1 signal SAXF on a conductor 298, which is applied ~:
to an OR gate 300 to generate a xead enable 2 ~shift/load)
signal on a conductor 302 at the time shown in Fig. 10C.
In Fig. 13A, the read enable 2 signal is applied via OR
gate 90 to the registers 60 and 92 on conductors 88 and 94,
respectively. The first read enable 2 signal is generated
at the time shown in Figs. 10C and 13B by the application
of the 3rd sync bit signal to the S~XF flip-flop via AMD
gate 296.
It will also be noted that the SAXFF flip-flop
1~ re~ct one 30llz clock aftcr it i~ set. This i~ due to
the PLCl signal going to a binary 1 at a count of 4, thus
.'
- C - 37
:~
,, 45
l~iS3~
enabling AND gates 212 and 224 to apply a reset signal to
the SAXF flip-flop 230 via conductor 226. This resetting is
illustrated in Fig. 10C. The generation of the read enable
2 sigslal via OR gates 90 and 300 effects the reading of the
first message data character to be transmitted into the
parallel in-serial out-register 92. This character is the
5CU fixed address on conductors 306 labeled TSCUA. It will
be noted in Fig. 13A that the m~ltiplexer 98 receives the
S~Y~ signal from the SAXFF flip-flop on a conductor 304.
The multiplexer 98, which i5 basically a two-way switch,
normally channels data from the recei~ed data memory regis-
ter into the parallel in-serial out-register 92 when the
,' SAXF signal is a binary 0. As previously mentioned, however,
j the SCU does not pass on the address which it receives from
the RCC, but rathcr it regenerates its own fixed address for
trans~ission to the MTU(s). This is accomplished by the
SAXF signal. With the SAXF signal now a binary 1, the multl-
plexer 9S directs the TSCUA signals (SCU fixed address) via
conductors 306 througll the multiplexer into the input of the
parallel in-serial out register. The TSCUA signals are
clocked into register 92 in response to the shift/load and
clock data signals on conductors 94 and 186, respectively.
As shown in Fig, 10C, when the shi~t/load signal goes to a
;~ binary 1, the TSCUA is parallel loaded through the multi-
plexer into the parallel in-serial out-register. The SCU
fixed address is now shifted out of register 92 as the first
eight bits of the message on conductor 188 and applied to the
parity check generate circult 166. These bits of the fir~t
character are fed into the parity generate cixcuit where
that circuit monitors the~e bits as~d all subsequent bits of
the message in order to generate the proper parity in the
;~ last character of the ~e~sage; The first character (SCU
C - 38
~ ~ 4~
. . .
33~39
. .
fixed address) is shifted out o~ the parity check generator
circuit as serial data on conductor 288, and applied to the
power lines 18 via AND gate 286, OR gata 265, AND ga~e 252,
power line transmitter 290 and the power line coupler 292.
As shown in Fig. 10C, as soon as the SCU fixed
address has been shifted ou~ of register 92, the second
read enable 2 (shift/load3 signal is generated and applied
to registers 60 and 92 via conductors 88 and 94 to load and
shift the MTU address to the power line, A third enable 2
1~ (shift/load) signal is also generated to load and shift the
MTU function code onto the power lines. The generation of ~-
these two read enable 2 tshift/load) signals is described
by reference now back to the control counter decode 210 of
Fig, 13B, The signal which controls the generation o these
two read enable 2 signals is a read character ~ignal RCHR
coming out of the control counter decode on conductor 308.
By observation of Table 3 and of the timing diagram of
Figs. 10A - 10D, it can be seen that the RCHR signal is
generated at binary counts of 11 and 19. In reality, the
count of ll is actually representative of a count of 8
message bits and the count of 19 i,s representative of 16
message bits, This is due to the necessity o~ having to
count the three sync bits previou~ly appended to the front
of the message, The ~irst RCHR signal is applied to an AND
gate 310 in conjunction with the 30Hz signal, The RCHR and
30Hz signals now enable AND gate 310 to apply a binary 1
; set signal to the S input terminal of the GRFF flip-flop 232.
The GRFF flip-flop l-output terminal now goes to a binary 1
on conductor 316 to enab1e OR gate 3~0 to generate the
second read enable 2 signal for application to registers 60
and 92, As shown in Fig, 10C, the generation of the second
read enable 2 ~ignal allows the second character (8-bit MTV
C - 39
' ~7 `~
1~3~
address) to be transferred in parallel from the receive
data memory register via the multiplexer into the parallel
in-serial out-register.
It should be mentioned at this time that the
SAXFF flip-flop is in the reset state; t'hus, the SAXF signal
i~ a binary 0 allowing the messa~e data to now be trans-
ferred through the multiplexer 98 from the receive data mem-
ory register into the parallel in-serial out-register. Since
the FFDF flip-flop is still set, the G30Hz clock pulses are
1~ still being applied to the parallel in-serial out-data-
register via AND gate 280, OR gate 184 and conductors 282
and 186. Thus, the second character is shifted out of
register 92 to the power line as previously described.
The addressing of the second character just loaded
into register 92 from the memory register 60 is effected by
the enabling of AND gate 216 with the PLC8 binary 1 signal
on conductor 222 from the power line control counter. With
the PLC8 signal at a binary 1, AND gate 216 generates a
binary 1 RSA2 output signal, which now enables OR gate 104
2Q to provide an RSA binary 1 signal to the receive data memory
register. AND gate 214 is presently disabled, generating a
binary 0 RSB 2 output~ Thus, OR gate 102 is disabled to
make the RSB signal on conductors 100 a binary 0O This
; ~inary combination of the RSA and RSB signals addresses
the second character location in memory register 60.
Counter 206 will now continue to count, and at a
count of 19, the second RCHR signal is generated. The RCHR
signal will again effect the setting of the GRFF flip-flop
via AND gate 310 as previously described. This will again
ca~se the yeneration o the read-enable 2 signal to this
time load the third character (function code) from the
receive data memory register into the parallel in-serial
~ - 4~
A.
' . ' ' ..
~836~ 21-~lE-15
out-register. As shown in Figs. 10A, 10B, 10D and 13D, -
the addressing of this third character is effected by the
PLC16 signal on conductor 220 from the power line control
counter 206 now being a binary 1 and the PLC8 signal being
a binary 0~ These two signals cause the RSA and RSB sig-
nals to become binary 0 and 1, respectively, to effect the
addressing of the third message character for transfer from
the receive data memory register into the parallel in-serial
out-register. This third data character is serially shifted
out of register 92 on out to the power line as previously
described.
After transmission of the first three characters
(24 bits), the control counter decode now generates an
output signal designated PL27 (PL27 minus 3 sync bits = 24 ;:
bits). The equation for the generation of the PL27 signal
is shown in Table 3 and is correspondent with the 24th bit
; of the message (see Fig. 10D). The PL27 signal is applied
via conductor 318 to AND gate 320 in conjunction with a 0D
signal to enable that AND gate at 0D time to set the FFEF
flip-flop 262 and reset the FFDF flip-flop 258 via OR gate
254. Resetting the FFDF flip-flop now applies a binary 0
signal to AND gate 280 of Fig. 13A, thus disabling the
G30HZ signal being applied to the parallel in-serial out-
register and preventing further shifting of that register.
Additionally, when FFDF resets, the FFD signal on conductor
268 goes to a binary 0, disabling A~D gate 270 of Fig. 13F
preventing the 0B signals from being applied as parity clock
signals to the parity check generate circuit 166. However,
at this time, since FFEF is set, its binary 1 output terminal
applies a binary 1 signal via conductor 322 to an AND gate
324 of Fig. 13F. The parity clock signals now continue to
be generated as a result of the coincidence between the FFE
C - 41 ~
21-ME-15
~(1 8~368~1
and the 0A signals at AND gate 324. With each 0A signal,
AND gate 342 applies a generate parity clock signal via OR
gate 272 to the input of the parity check generate circuit.
In this manner the necessary clock pulses will be generated
to allow the parity check generate circuit to generate proper
parity in accordance with the determined from the previously
transmitted message bits. The parity check generates cir-
cuit as shown in Fig. lOD will now generate the six parity
bits of the message and place them onto the power lines 18
as previously described.
Reference is now made back to the control counter
decoder 210 of Fig. 13B for a description of the last opera-
tion performed during the transmit sequence of a message from
the SCU to the MTU(s). The signal to be generated by the
control counter decode 210 is a PL34 binary 1 signal. The
equations for the generation of this signal are shown in
Table 3. The PL34 signal is applied via conductor 326 to
an AND gate also receiving the K~ signal from inverter
150. If the function code, as previously described, speci-
fied that no response is expected from the MTU(s), the
REE`F signal will be a binary 1 at this time. Thus, the PL34
signal will enable AND gate 152 to apply a binary 1 reset
signal to the system control flip-flop via OR gate 30,
placing the SCU back in the standby mode. The reset timing
is shown in the last line of Figs. 10C and lOD.
If, however, the function code indica-ted that a
data message response is expected from the MTU(s) the REFF
signal will be a binary 0, disabling AND gate 152 and the
SCU will go into a wait mode for receipt of the data message.
This wait mode is accomplished by the application of the
PL34 signal via conductor 330 to the input of an AND gate 158
C - 42
~ ~0
~83689
also receiving the binary 1 R~FF signal~ In this case,
if a response is expected, AND gate 158 will be enabled to
apply a binary 1 set signal to a power line receiver flip-
flop PLRFF 160 at the time shown in Fig. 10D.
Reference is now made to Figs. llA - llH, which
show the SCU timing for rhe receipt of a data message from
one or more MTU's. With the PLR~F flip-flop now set as
shown in Fig. llA, a binary 1 PLRF output signal from its
l-output terminal is applied via conductors 332 and 336 to
an OR gate 334, which applies a binary 1 reset signal to
the power line transmitter flip-flop 202. The time of re-
setting this flip-flop is noted in Fig. llA as the leading
edge of the PLRF signal. When flip-flop 202 resets, its
binary 1 output te~minal goes to a binary 0 disabling AND
gates 214 and 216 and replacing the inhibit/clear signal
on the pow¢r line control coun~er. Counter 206 is now re-
set in preparation to receipt of the next message from the
RCC. Resetting counter 206 causes the DCD signal on con-
ductor 250 to ~o to a binary 0, thus preventing any further
2 transmission of me~sage data through AND gate 2S6 to the
power line. This now frees the SCU to receive data messages
via the power line coupler 292.
Referring now to Fig. 13B, the PLRF signal is also
applied to a plurality of receivers 338 and to a common data
path switch 340 in a power line receiver common logic
block 342. The PLRF signal in essence simultaneously turns
on all receivers 338 and enables switch 340 for receipt of
data from the power lines 18 via the power line coupler 292,
conductor 344, and conductor 346. After an MTU (s) has decoded
the function code of its received message as a transmit data
command, it will serially transmit the meter data onto the
power lines for receipt by the SCU. The serializecl meter
C - ~3
- ~1
': ' . .: .
~8361 3~
data appears at switch 340 after passing through coupler
292 and is transferred therethrough at frequencies fl through
f8, with each frequency corresponding to a separately ad-
dressed MTU. The meter data on conductor 346 is applied in
common to all of the receivers 338. Each receiver will
accept only the meter data being received at its tuned
frequency (one f fl ~ f8). The timilig signals for con-
trolling the transfer of data into the receivers and to the
RCC are controlled by a plurality of clock signals DeA, DeB
and DeC generated by common logic 342 on conductors 348, 350
and 352, respectively. The common logic 342 also receives
a strobe signal from each of the receivers 338 via conduc
tors 354 and 356 when a receiver detects the receipt of a
message of meter data, The meter data is trans~erred in
parallel from each of the receivers via conductors 554 to
the data transrnitter receiver 40. The DeC signal clocks
the meter data into the tr~nsmitter ~eceiver, which trans-
fers that data to the RCC via the transmitter 162.
; SCU REC~IVER OPE~ATIONAL DESCRIPTION
Reference is now made to Fig. 14, which is a
legendary drawing showing the inter-relationships between
Figs. 14~ througll 14D. In order to follow the operational
description of the recèiver portion of the SCU, it is rec-
ommended that Figs. lAA through 14D be organized as shown
in accordance with Fig. 14. In a similar fashion, it is
recommended that Figs. llA - llH be positioned in accordance
with the legendary drawing of Fig. 11.
The previously mentioned power line receiver
common logic 342 is illustrated in detailed block diagram
form in Figs. 14C and 14Dr Each of the previously mentioned
receivers 338 in Fig. 13B is similar with the exception of
C - 44
~2
36~39
their ability to receive data me~sage~ from the MTU's at
a specified frequency for a particular MTU. Since all of
the receivers 338 are substantially the same, the operation
of only one of those receivers will be describecl. The de-
tail logic for a typical one of the receivers 338 is shownby Figs.~14A and 14B.
Reference is now made to Figs. llA - llH. Figs.llA
and llB show the basic timing of the various clock pulses
provided to the receiver logic from the master clock genera- -~
tor 36 of Fig. 13E. Figs. llC and llD illustrate the timing
of a typical one of the receivers 338, which is receiving
- message data from the power line. In thc illustrated embodi-
ment, it wil] be recalled as previously described in connec-
tion with Fig, 1, that as many as eight MTU's can be trans-
mitting information onto the power line simultaneously.
Because of various delays in the system caused, for example,
by the physical displacement o~ MTU's along the power line
and the turnaround or ~esponse time in each of the various
., .
MTU's to received messages, the message data from each of
eight addressed MTU's may not reach the SCU at exactly the
same time. For this reason, the SCU must be capable of in-
-~ suring that the ~irst message received rom an MTU and the
lat~st message received from an MTU is captured by the SCU
and transferred to the RCC. In Figs llC and llD, it will
be noted that that timing diagram specifies the receipt of
the earliest power line data from a receiver ~1, which could
be any one of the receivers 338. Figs. llG and llH are
somewhat similar to Figs. llC and llD; however, Figs. llG
and 11~ show the operation of a receiver #N, which can be
any one of the receivers 338, receiving the latest power
line data from an MTU. The power line receiver common logic
timing is illustrated by Figs. llE and llF.
C - 45
~3
~083~89
In the ensuing description, the receiver opera-
tion will be described by first assuming that a message
has been transmitted onto the power line by an SCU to
address only one MTU on that power line. Thus, that one
MTU will be the only one to respond with a data message
back to the SCU. In this particular instance, that message
could be considered to be the earliest power line data illus-
trated by the timing diagram of Figs, llC and llD. The com-
mon logic for the receiver as illustrated by Figs. 11~ and
llF will also be described in connection with this one ad-
dressed MTU, Following that description, the operation of
the receiver logic will be described, utilizing Figs. llG
i and llH with the assumption that a message transmitted to the
MTU ' s is a message which addresses a plurality of MTU's (e.g.,
eight MTU's) to ~ransmit their meter data simultaneously to
the SCU. In this particular instance, the description of
Figs, llG and llH will entail the reseipt of an SCU of the
latest data from one of the addressed MTU's. Figs. llE and
llF will also be described in connection with Figs, llG and
, 20 llH,
Reference is now made to Fig, 14C. In that figure
the PLRFF flip-flop 160 has been re~illustrated as a portion
of the power line receiver common logic 342 to make it easier
to understand the overall operation of the power line re-
; 25 ceiver logic.
As previously described in connection with Fig. 13B,
the pximary purpose of the PLRFF ~lip-flop is to turn the
power line receivers on and off, Let it first be assumed that
the PLRFF flip-flop is in a reset state. As a result, its
æero output terminal is generating a ~inary 1 PLRF signal on
conductor 358, The PLRF signal is utilized to keep each of
the receivers and the receiver COmmQn logic in the reset, or
C - 46
~4
. .
,. ,: ,. ,. , .. ` ` ;` : ~
~``
off, state when a message is not to be received from an
MTU(s). A plurality of flip-flops, 0 AF/F 360, 0 BF/F 362,
,0 CF/F 364, and 0 DF/F 366 are all held in the reset state
by the PLRF signal applied to the reset terminals of those
flip-flops via a conductor 368, The PLRF si.gnal is like-
wise applied on a con~uctor 370 to a reset ~ terminal of a
remove start bits discounter 172 to reset that counter and
simultaneously inhibit it ~rom counting. Three other flip-
flops, F/FlA 374, F/F2A 376, and EOMF/F 378 of Fig. 14D,
are lil~ewise held in the reset state by the PLRF signal on
a conductor 380. Further, a flip-flop 50MSF/F 382 is he].d
in the reset state by the PLRF signal's being applied to the
reset terminal of that flip-flop via an OR gate 384 and con-
ductors 3~6 and 3,88, Additionally, a message length counter
: 15 390 is inhibited from counting and held in the reset state
by the PLRF signal on conductor 392 being applied to a reset
input terminal of ~hat counter. A 3011z strobe clock counter
394 is held in the inhibited reset state indirectly by the
PLRF signal, which resets f].ip-flop 376 to apply a binary l
signal from its zero output terminal via a con~uctor 396
and an OR gate 398 to the reset tel~inal of counter 394. In
a similar fashion, a 50 MS delay divide by 12 counter q00 is
held in a reset inhibit count state indirectly by the PLRF
siynal from the æero output terminal of flip-flop 374 via
conductors 402 and 540~
Fteferring to Fig. 14C, the PLRF signal is also
applied to a reset inhibit input terminal of a 267 MS delay
divide by 8 counter 404 on a conductor 406 holding that
counter in a reset.inhibit count state. Four additional
flip-flops, a 25MS Delay Control f].ip-flop 408, a STATE F~F
flip-flop 410, a STORE A flip-flop 412, and a STORE B flip-
flop 4l4 of ~ig. 14B are also held in the reset state by the
.. . .
C ~ 47
, ,~5
~336~
PLRF signal. It will be noted that the PLRF signal applied
~,~
'' to the reset input terminal of each of these latter flip-
flops is the complement of the binary zero PI,RF siynal now
present at the one output terminal of the P'LRF flip-flop 160
on conductor 416. The PLRF signal on conductor 415 is in-
vertea through an inverter ~1~ to the PLRF binary 1 si~nal on
conductor 420. An OR gate 422 passes the P'LRF signal to the
reset R input texminal of flip-flop ~10 via conductor 4240
In a similar manner, the PLRF signal is applied to the reset
input terminal of flip-flop 408 via conductors 426, 428 and
an OR gate 430. Flip-flops 412 and 414 are reset by the PLRF
signal from inverter ~18 via conauctors 432 and 434 appliecl
to reset input terminals of those flip-flops. ,~
As previously described, the receivers illu~trated
by Figs. l~A and 14B are representative of a one of the
plurality of receivers 33~ in the SCU. As shown i~ Fig. 14C,
the PLRF and PLRF signals zre prov;ded to all other power
line receivers in the SCU in the same manner as just shown ,
and descxibed in connection with Fi~s. 14A - 14D. The PLRF
and PLR~' signals are shown going to all of the other receivers
(not shown) on conductors 436 and 438, respectively. Also,
for a more easy understanding of the description of the SCU
receivers, the data message switch 340 has been duplicated
, in Fig. 14C receiving the PL~F signal via conductors ~16 and
440, ' '~
Prior to proceeding with a further description of
the SCU receiver operation, it is considered advantageous
to reconsider the message format of Fig. 4 showing the format
of meter data whibh is received by the SCU from any one of
the MTU's. As shown in Fig . ~, that message is comprised of
45 bits, of which the first three bits are the sync, or
start, blts and 42 bits comprise meter data and parity. This
:.
C ~ 48
.~ .
~56 :'
~, lCi ~3~jB9
message is received by the SCU in the order shown in Fig. 4
froM the left to the right, starting with the three sync
bits.
Let it now be assumed that the SCU has just decoded
a command and transmitted it to an addressed MTU that speci- ~
fies that the MT~ is to transmit meter data back over the l;
power lines to the SCU. As such, the PLRF f:Lip-flop 160 is
in the set state, placing the SCU in a message receive wait
mode by removing the prev.iously described reset signals from
the various flip-flops and counters in the receiver logic.
This has the effect of basically turning on all of the re-
ceivers s,imultaneously in preparation to the receipt of a
message from the addressed MTU. As previously mentioned,
the operation of the receivers ~lill first be descri~)ed with
the receipt of a message from a single MTU.
Reference is now made to Fig. 14C ~o the data input
(fl ~ f8) on conductor 34~ coming into switch 340. Since the
PLRF flip-flop is now set, switch 340 is enabled by a binary
1 PLRF sicJnal on conductor ~40 applied to that switch. As
soon as ~he meter data arrives at the SCU from the MTU, it
will be passed through switch 340 via conductor 346 and
applied to a narrow band recciver/ampli~ier circuit 4~2.
The message data is amplified in receiver amplifiers 442
and provided to the input of a band pass co~nutating filker
444 via corlductor 446. It will be recalled that the MTU is :
capable of transmitting its metered data at its own speci- .
fied frequency. These ~requencies were previously described
as fl - f~. Further, it was also pointed out that the SCU
is capable of receiving in each of its receiver circuits a
meter data message at the frequency corresponding to that
. being transmitted by one of the MTU's. In Fig. l4A there is
shown an fx crystal oscillat.or 448 providing an fx RF sic3nal
C - 49
57
~3~ 21-Mæ-15
on a conductor 450 to one input of the band pass commutating
filter 444. The frequency of the fx signal on conductor 450
can be representative of any one of the previously mentioned
frequencies fl ~ f8, depending upon which receiver is being
considered. The purpose of the band pass commutating filter
444 is to allow the receiver to receive only the message data
corresponding to that frequency fx by filtering out all un-
wanted frequencies and passing the message data out of the
filter 442 corresponding to the desired message.
Reference is now made to the two top lines of
Figs. llC and llD designated earlies power line data
(receiver #l) and one-shot ~1 (lOMS). To understand the
operation of the receivers of the SCU, it is important to
realize that in the present system, the presence of a pulse
burst of energy on a power line is representative of a binary
O, whereas the absence of a pulse burst is representative of
a binary 1. As shown in Fig. llC, the first three bits of
information from the MTU entering the SCU receiver of Fig. 14A
are the three sync bits designated Sl, S2 and S3. It will
also be noted that the message data transferred over the
power lines between the MTU and SCU and from the SCU to the
MTU is at a 30Hz rate; thus, the pulse spacing between each
of the data bits in the message is 33.3 milliseconds as
shown in Fig. llC. As shown in Fig. llC, the power line
data is normally at a binary 1 state and when a pulse burst
(binary O) is placed on the power line by the MTU, the output
of the band pass filter 444 will generate a negative signal
as shown in the earliest power line data line of Fig. llC.
This negative going pulse is applied via a conductor 452 to
a trigger (T) input of a one-shot, 10 millisecond multi-
vibrator 454. The output of multivibrator 454 is shown in
:~ ' ,
C - 50 '~
1~36~ 21-ME-15
Fig. llC on the one-shot #l line as two pulses correspond-
ing to the -Eirst two binary 0 sync bits and the absence of ~ ;
a pulse shown as a dotted or phantom pulse representative
of the binary 1 sync bit. All message bits following the
three sync bits are shown in cross-hatched form as those
bits are indeterminate, dependent upon the contents of the
message. These cross-hatched bits are shown as data bits 1
` through 42. For each data bit which is a binary 0, one-
shot 454 will be fired to generate a 10 millisecond output
pulse as shown in Fig. llC. The data bits from the output
of one-shot 454 are applied to an AND gate 456 via a conduc-
tor 45~.
The other input to A~D gate 456 is a binary 1 sig-
nal on a conductor 460 from the output of an inverter 462.
Inverter 462 is presently receiving a binary 0 input signal
from an OR gate 464 now disabled. This is explained as
follows: Prior to the reception of a message from the ~TU,
the four flip-flops 360 through 366 are in the reset state.
Thus, their binary 1 output terminals are each providing a
binary 0 signal on conductors 466 to the input of OR gate 464.
Thus, it can be seen that with the appearance of the very
first sync bit in ihe message, AND gate 456 will be enabled
to apply a binary 1 signal as one input to each of four AND
gates 468, 470, 472 and 474 via a conductor 476. The second
input to these AND gates are the 0A through 0D signals from
the master clock generator 36 of Fig. 13E.
Reference is now made to Figs. 11A and llB, which
illustrate the timing relationships between the 0A through
0D signals. It will be noted that there are four phase sig-
; 30 nals (~A thrOUg11 0D) generated for each bit time of the in-
coming message. This is seen by comparing the 0A through
59 ,
C - 51
~^`~ 33~
~D si~nals with the pulse width of the 30Hz signal shown in
Fig, llA. The reason for the ~A ~hrough 0D signals and the
circuitry in Fig. 14A is to be able to synchronize the
cloc~ing of the data bits into the receiver with a 30Hz cloc~
~5 signal. The majority of the circuitry shown in Fig. 14A com~
prises basically a strobe sync det~ctor circuit for develop-
ing the just-mentioned synchronization. As will be seen, this
circuitry is capable of synchronizing any one of the 30Hz
0A through ~D signals with the 30Hz incoming data to generate
.0 a synchronization stxobe A signal shown in Figs. llC and llD.
As shown in Fig. llC, it will be noted that one-
shot 454 generates the first sync pulse output signal approx- ~
imately in the middle of the ~B signal. Referring now to ~ ;
AND gate 470 of Fig. 14A, the coincidenc~ between the first
L5 sync bit on conductor 476 and the ~B signal applied to AND
gate 470 enables that AND gate to apply-a binary 1 set sig-
nal to tlle input of the ~B F/F 362. Fig. llC shows the
setting of the 0B F/F ~1 on the leading edge of the output
o~ one-shot #1. The one-output terminal of the 0B F/F 362
is connected via a conductor 478 as one inpu-t to an AND
gate 480. The other input to AND gate 480 is the 0C signal
on a conductor 4S2. With the ~B F/F now set, the first 0~
signal ollowing the setting of that flip-flop will enable
AND gate 480 to generate a binary 1 output signal on a con-
2S ductor 48~ to an OR gate 486. The OR gate 4 86 now passes
its input signal, via a conductor 488, to an AND gate 490.
The other input to AND gate 490 is presently a binary 1
signal from an inverter 492 now receiving a binary 0 input
on conductor 494 from disabled AND gate 496.
AND gate 496 is connected to the output of the
xemove start bits counter 372 and decodes the output o~ that
counter to generate a binary 1 slgnal on conductor 494 when
C - 5~ :
'
EO
3~39 .:
the counter xeaches a count of three. At the present time ~,
this counter is zeroed out; thu5 the output of AND gate 4g6
is a binary ~ero, causing inverter ~92 to apply a binary 1
enable signal to AND gate 490. Reference is now made back
,to Figs. llC and 14A, which show the start bits strobe ~1 ;
being ~pplied to the trigger T input of counter 372 via
conductor 498. It will be noted that the start bits strobe
- coinci~es with the 0C signal applied to AND gate 480.
' ' It will be noted in Fig. 14A that when the 0B
0 F~F 3-62 sets, its one-output terminal provides a binary 1
signal on one of the conductors 466 to OR gate 464. This
binary 1 signal is passed through OR gate ~64 and inverted
to a binary 0 signal by inverter 462, thus applying a disable ''
inpu~ signal to AND gate ~56 via conductor 460. Disabling
AND gate 456 applies a binary 0 disable signal to each of
the ~D gates 468 through ~74. Since these AND gates are '
disabled, those ~ND gates can no longer apply set signals to
any of the other ~lip-flops 360 through 366. It is siqnifi-
cant to note that the circuit of Fig. 14A is capable of ^~
'0 synchronizing any one of the ~A through 0B signals with the
~irst data or sync bit coming into the receiver, Further,
it will be noted ~hat whenever a particular one of the 0A
through 0D flip-~lops is set, the strobe A signals will be
generated at the phase (0) signal immediately following that
!5 which set the particular flip-flop. In the example shown in
~igs. llA throùgh llD, the ~B flip-flop is set at ~B time
and the strobe A (#l) signals are generated at 0C time, thus
locking in the system to generate the strobe A signal with
each ~C signal. If ~he first sync bit (Sl) had happened to
~0 coinclde, for example, with the 0A signal, AND gate 468
would have been enabled to set flip-flop 360. This would
cause the blnary 1 output of the ~A F/F 360 to enable an
C - 53
~3~, 6 1
~ ;
. - .. . . .
33~
. .
A~D gate 506 to begin generatirlg the start bits strobe and
the strobe A signals at 0B time.
Reference is again made to Fig. llC to the start
bits strobe #l line. It is seen there that three sync, or
start, strobe signals are generated by AND gate 490 and
applied to countcr 372 (Fig. 14A). When counter 372 reaches
a count of three, ~ND gate 496 is enabled to apply a binary
1 signal as one input to an AND gate 500 on a conductor 502.
The binary 1 signal is also applied to inverter 492, which
now disables AND gate 490 preventing application of the ~ ;
start bits strobe to the counter 372. It will be noted that
the output of OR gate 486 is also connected as one inpu~ to ~,
,i AND gate 500. AND gate 500 will now begin to generate the ~,~
I previously mentioned strobe A signal on a conductor 5Q4 in
response ,,to each ~C signal as shown in Figs. llC and llD on
the strobe A(~13 line. The strobe A signal on conductor 504
is applied as one lnput to an AND gate 508, which is now en~
abled by the binary 1 PLRF signal also applied to that ~ND
gate. The output of AND gate 508 is utilized to strobe or
cloc]c the meter data from the MTU into a STORE A F/F 412
via a con~uctor 510. The serialized message data fr~m one-
shot 454 is also applied to a data t~xminal D of flip-flop 412
via conductor 512. Referring to Fig. llC, it can be seen
that the strobe A t#l) signal at 0C time always falls in
coincidence with the output of one-shot #1 454. If one-
- shot 454 is generating a binary 1 output signal, the strobe
A signal on conductor 510 will cause flip-flop 412 to set.
If the output signal from one-shot 454 is a binary 0, flip-
flop 412 will reset. In this manne~, binary 1' 5 and 0's
are shifted from the pow~r line into the data receiver
flip-flop 412.
C - 5
~ ~ .
The output of AND gate 508 15 also applied to
an O~ gate 514 via a conductor 516. For each strobe A sig-
nal generated by AND gatie 508, OR gate 514 passes that sig~
nal to a trig~er T input terminal of the 25 MS delay control
S flip-flop 408 causing that flip flop to set at a time as
shown in Fig, llC on a 25MSD ($1) line. Flip-flop 408 sets
at this time causing its 0 output terminal to go to a
binary 0 state on conductors 518 and 520. With the 0 out- j
put terminal on con~uctor 5i8 toin~ to a binary 0 at this
time, it has no e~fect on the state flip-flop 410. However, ~
the binary 0 signal 25MSD on conductor 520 is applied as a 5~'
release input signal to an R termlnal of the 25 MS ~elay
counter 522. This removes the reset inhibit input to
counter 522, allowing that counter to begin to count 120EI~
pulses. At the end of the ~ount of three by counter 522,
it generates a 25 millisecond delay output signal CT3 on a
conductor 524. The CT3 signal enables OR gate 514 to again .;
trigger flip-flop 408, causing it to reset. Resetting this ~;
flip~flop 408 results in ~lpplying a binary 1 signal baGk to .`
the R input of counter S22~ thus æeroing out that counter f
and inhibiting it from counting. Further, the binary 1
signal causes the STATE F/F 410 to now set at the time
shown in Fig. llC on the STATE F/F (#l) STATE line. With
flip-flop 410 now set, its 0 output terminal generates a
binary 0 output signal STATE on a conductor 526 to disable
an AND gate 528.
~he binary 1 output of flip-flop 408 on conductor
518 is also applied at this time to a trigger ~T) input sig-
nal of a STORE B flip-~lop 414 via a conductor 530. As ¦
shown in Fi~. llC, the binary 1 ~-~D s~gnal causes the pre-
viously stored data bit from flip-flop 412 to now be clocked
into the STORE ~ flip-flop 414 via a conductor 532 applied
C ~ 55
63
~ 5
. . .
to a data D input,terminal of that ~lip-flop. Si.multaneous-
ly with t.he clocking of the previously stored data bit from
flip-flop ~12 into flip~flop 414, the next data bit i5
strobed into flip-flop 412. This is always done on the
S leading edge of the sTRosE A signal as shown in Fi.g, llC.
Reference is now made bac~ to Fig, 14A to the ~ '
output of A~D gate 500 generating the st:.xobe A signal on
conductor S04. It is shown there that the strobe A signal
is also applied via a conductor 534, as one input to an OR
. gate 536 o~ Fig. l~D. ~ iS significant to note at this time
that OR yate 536 receives a strobe A input from each of the ~,
plurality of receivers in the SC~. The reason fo,r this is
explained as follows: In oxder to properly clock all of the
message data from the MT~'s into the SCU receivers, it is
desirable to develop the sync bits and strobe A signals rom
the first sync bit of the first, or earliest, incoming
message fl-om the MTU' 9. The detection o this first sync
bit, as previously described, efects the starting of th~
strobe A signals on conductor 534., Once that first strobe A ::
signal has been generated, it is necessàry to block out all
of the other reGeivers from providing stxobe A signals to
the common power line,receiver logic in Figs. 14C and 14D
so that all data will be clocked into the plurality of re-
ceivers simultaneously under control of one s~trobe A signal.
As shown in Fig. 14B, when OR gate 536 is enabled,
it simultaneously applies a ~inary 1 signal on a conductor
538 to a set input terminal of the FFl~ flip-flop 374 and
the 50 MS flip-flop 382. ~his binary 1 signal ~auses both :'~
of ~hose flip-flops to set, generating a binary 0 output
signal from each one's 0 output terminal. The timiny for
the F/FlA and 50 MS F~F is ~hown i~ Figs. llE and ll.F.
The binary 0 output signal ~rom ~l~p-~lop 374 i8 applied
C - 56
6 4
:
~836139
21-ME-15
.
as an inhibit signal via conductors 540 and 542 to an
inhibit terminal shown as a circled inverter on the input
of OR gate 536. This inhibits the passage of strobe sig-
nals from any of the other receivers through OR gate 536.
As shown in Figs. llE and llF, the FFlA flip-flop will
remain in the reset state until the complete message has
been received, at which time it will be reset. This will
be described subsequently.
Reference is now made back to the set S input
terminal flip-flop 382. Flip-flop 382, which is now set,
generates a binary O signal from its O output terminal on
a conductor 544. This signal is applied to a set S input
terminal of a flip-flop FF2A 376. As shown in Fig. llE,
this signal has no effect on the operation of that flip-
flop at this time. Referring now to Fig. 14D, it will be
noted that the binary O output signal from flip-flop 374
is also applied as a release signal on conductors 402 and
540 to an R input terminal of the 50 millisecond delay
divided by 12 counter 400. Counter 400 now begins to count
120 Hz input clock signals applied to the trigger T input
terminal of that counter. The output signals of counter 400
are applied via a plurality of conductors 546 to the input
of a 50 MS divided by 12 decode network 548. As shown in
Fig. llE, after a 50 millisecond delay, the decode network
548 will generate a binary 1 output signal on a counter
550, which is passed through OR gate 384 via conductor 388
to reset the 50 MS F/F 382. Resetting Flip/flop 382 now
causes the O output terminal of that flip-flop to go to a
binary 1 on conductor 544, thus setting F/F2A 376 as shown
in Fig. llE. With the flip-flop 376 now set, its O output
terminal now goes to a binary O on conductor 396 to now
apply a binary O release signal to the R input terminal of
C - 57
~5
~0836~9 21-ME-15
`~ the 30Hz strobe clock counter 3~4 via OR gate 398.
Counter 394 now begins to count 240 Hz input
pulses applied to the T terminal of that counter. The out-
put stages of that counter designated CCB, CCC and CCD are
applied via their corresponding output lines to the input
of a clock decode 30Hz generator circuit 552. Decode 552
also receives the 240Hz input pulses via a conductor 554.
The equations defining the internal decode logic of decode
552 are given on the timing diagram of Fig. llE on the lines
DeA, DeB and DeC. It will be noted in Fig. llE and 14D
that the DeA, D B and D C signals are sequentially generated
by the decode 552.
The generation of the first DeA signal in the
present description has no effect on the operation receiver.
However, it will be noted as shown in Figs. llE and llC that
the leading edge of the first DeB signal from the output of
decode 552 is applied as a binary 1 signal to OR gate 422
of Fig. 14B via conductor 350. OR gate 422 now paSSQS the
DeB signal to the reset input terminal of flip-flop 410 via
conductor 424. This causes the STATE F/F 410 to now reset
generating a binary 1 STATE output signal on conductor 526 ; !
to AND gate 528. It will also be noted at this time that
the 25 MS delay control flip-flop 408 is again triggered to
reset at the count of three (CT3) applying a set signal to
the STATE F/F 410, causing that flip-flop to immediately set
as shown in Fig. llC.
It is significant to note that the DeA and DeB
signals as shown in Fig. 14D are also applied to all of the
power line receivers 338, causing those receivers to all
operate in the same fashion as just described in connection
with Figs. 14A, 14B, 14C and 14D. Referring now back to
~6
C - 58
36~3~
Figure 14D, the next output signal to be generated from the
decode S52 is the D~C signal on a conductor 352. That sig-
nal is shown being developed as an output signal from the
power line receiver common logic 342 in Figs. 14D and 13
S for application to the data transmitter/receiver circuit 40.
It is this ~eC signal which effects the parallel-transfer
of data from each of the eight receivers (Fig. 13B) into the
data transmitter~xeceiver 40.
Be~erring back to Fig. 14B, it will be reca~led
that each data bit which is strobed into the STORE B flip-
flop is transferred via a one of the plurality of conductors
554 from the corresponding receivers to the input of the
data transmitter/receiver ~0 shown as 8 data lines in
Figs. 13A and 13B. As each data bit from the receivers is
transferred to the data transmitter/receiver 40, it is nec-
essary to keep track of the number of bits in the message,
which have been transferred. This is e~fected by the CCD
signal generated by the clock counter 394 in Fig. 14D.
The timing for the generation of the CCD signal is shown in
Figs. llE and llF, whercby the leading edge of that signal
triggers a message length counter 390 with a binary 1 signal
on a conductor 556. As shown in Figs. llE and llF, the mes-
sage length counter 390 is counted up by one in response to
each CCD pulse~ The message length counter output stages
are provided via a plurality of conductors 558 to a message
length decode 560, which generates an output signal CT42 on
a conductor 562 when the message length counter achieves a
count of 42. The generation of the c'r42 signal is shown in
Fig. llF. The CT42 signal, upon the detection of the 42nd
count, or 42nd message ~it, (see Fig. 4) is applied as a
binary 1 set signal to an end of message flip-10p EOM F/F
C ~ 59
~ ~7
~3~
378 via conductor 562. As shown in Fig. llF, the CT42
signal causes the EOM F/F to set, thus generating a binary 1
EOM signal from the 1 output terminal on a ~onductor 564.
The EOM signal on conductor 564 is applied to the input of
OR gate 30 o Fig. 13A, causing the system control flip-flop
28 to reset, thus generating the binary 1 SCU reset output
signal on conductor 34 to completel~ reset the entire SCU in
preparation to receipt of another message from the RCC.
It should also be pointed out that each message
bit transferred to the da~a transmitter~receiver 40 of
Fig. 13A by the DeC signal is strobed through the transmitter
modulator 162 for transfer to the RCC prior to the transfer
of the next data bit from the receiver. Referring back to
. Fig. 14D, it will also be noted that the CT42 siynal from
decode 560 is applied on conductor 562 to OR gate 398 to
immediately reset countex 394 after it has generated the
l.ast CC~ signal shown as a very short signal in Fig. llF.
Referring to Fig. 13B, it will be noted that the SCU reset
- signal is now applied t~ the PLRFF ~lip-flop 160. The
PLRFF 1ip-flop will no~ reset as sh~wn in Fig, llB, causing
that flip-flop to generate a PLRF ~inary 1 signal on con-
ductor 3S8 as shown in Fig. 14C to rese~ the entire receiver
section in the manner as previously described at the outset
of this discussion,
The operation of the SCU receiver section will now
be descri~ed with the assumpt~on that the message command
previously transmitted to the power lines addresses eight
MTU's and specifies in its function code that all of the
MTU's are to simultaneously transmit their meter data over
the power lines 1~ to the SCU. These eight messayes will
each be at a different fxe~uency and wlll be received by
the eight receiver~ corresponding to ~he fre~uency o each
C - 60
~ 6B
.
~`'-` .
of the messages fxom the addressed MTU ' s . It will be re-
called, as previously mentioned, because o inherent delays
in the systern, that the data from several MTU's may not
arrive simultaneously at the 5CU. This non-simultaneous
arrival of information at the SCU receiver section from the
plurality of MTU's is illustrated in the timing diagrams of
Figs. llC, llD, llE, llF, llG and llH. Figs~ llG and llH,
in particular, illustrate the latest power line data being
received by a one of the receivers designated recei.ver #N
in Fig. llG approxim~tely 40 milliseconds after receipt of
the earliest power line data being received by receiver ~1
as shown by Figs. llC and llD. To understand the operation
of the plurality of receiver~ rece;.ving the earliest and
latest data, it is necessary to visualize that the receiver
of Figs. 14A and l~B is representing a receiver (receiver ~13
lS receiving the earliest power line data, as well as another
receiver ~receiver ~,N) rece.iving the latest power line data.
Let it now be assumed that all MTU's have been
commanded to transmit their meter data over the power lines
18 to the SCU. The first receiver to receive the first sync
or start bit of the SCU message is illustrated by the earli~
est power line data (re~ceiver ~1) timing diagram of Figs. llC
and llD. The operation of receiver ~l has already been
described in connection with the timing diagrams of Figs. llA
- llF and will operate in the same manner as previously de-
scribed. However, it will be noted that the receiver #Nreceiving the latest power line data illustrates certain
differences in the timing in Figs. llG ~nd llH compaxed to
that previously described in connection with Figs. llC and
llD of receiver ~1.
Referring to F~gs. 14C and 14D, it is significant
to point out, as previou~ly de~cr~bcd, that tle power line
receiver common logic will always ~elect the ~irst strobe
C ~
~9
~ 333~39
-
signal generated by the receiver r~ceiving the earliest
power line data. When this occurs, OR gate 536 is in-
hibited rom receiving the strobe A signal from any other
receiver later receiving data from an ~iTU. Let it now be
assumed that the receiver illustrated in Figs. 14A and 14B
is that shown by the timing diagram of F'igs. llG and llH
receiving the latest data, It will be noted that the ~-
strobe A ~N signal is generated in the same manner as pre-
viously described or the strobe A #l signal. However, for
illustrative purposes, it is shown that the strobe A ~N
signal is being generated at ~A time instead of 0C time as ~;
previously described in connection with Figs. llC and llD.
This was done merely to show how any receiver can lock in
! on any one o~ the 0~ - 0D pulses. The operatioll of the
remove start bits counter 372 in Fig. l~A to stop that
counter at the end of three start bits strohes and to en-
able AND gate 500 i5 the same as previously described in '~
connection with Figs. llC and llD. As previous}y described,
the first strobe A signal ~$N) will simultaneously clock
the first data bit (latest received da~a bit) into theSTORE A F/F 412 and trigger the 25 millisecond delay con-
trol flip-~lop 408, causing that flip-flop to go into a
set state generating a binary 0 25MSD signal on conductor
520, The next significant action to note i~ that the first
strobe A signal generated by receiver ~1 at 0C time has
effected the starting of the 30H2 strobe clock counter 394
to begin the generation of the DeA, DeB and DeC signals a~ter
the 50 millisecond delay ~50 MSF/~) as shown in Figs. llE
and llF. It will be noted at this timc that the STATE F/F
410 as sho~n in Fig. llG is in a reset state, thus generat-
i ing a binary 1 STATE signal on conductor 526 to now enable
AND gate 528 to be enabled upon the occurrence of the D~A
C - 62
~ 70
... .
. . . . . . ... ;. . . ~
3~
signal. As shown in F~ys~ 14B, llE~ , llG, the leading
edge of the DeA signal on conductor 348 causes AND gate
528 to be enabled, generating a binary 1 output signal on
conductor 566. This latter signal is passed through OR
gate 430 to now set the 25 millisecond clelay control flip- :~
flop ~08 at a time as shown on the ~ S (#N)line of Fig.
llG With flip-flop 408 now reset, its binary 0 output
terminal goes to a binary l on conductox 518, causing flip-
flop 410 (STATF. F/F #N) to set, disabling AND gate 528.
However, flip-flop 410 will immedi.ately be reset at leading
edge of the DeB signal as shown in Figs llG, 14B and l~D,
in preparation for the repeated cycle of the 25 millisecond
delay and STATE F/F (#'s N)operations as just descrihed.
By comparing the timing of the 25MSD signals shown
in Figs. llG and llC, it can be seen that this timing allows
the data in the latest power line receiver ~ to be clocked
into its STO~ A F/F 412 and from that flip flop into its
STORE B F/F 414 prior to the occurrence of the DeC signal
shown in Fig. llE, so that the lat~st receiYed data is in the
buf~-cr s~ore flip-flop 4~4 of all r~ceivers in time to be
; . simultaneously transferred from the receivers via conductors
55~ (Fiy, 13B) into the data trans~i~er/receiver ~0 for
trans~er to the RCC via the transmitter modulator 162.
By referring to Figs, llD, llF and llH, it can
2S be seen .that the 42nd data message bit from each MTU is
clocked from the eight receivers into the data transmitter/
receiver ~0 for transfer to the RCC upon the occurrence o
the last DeC pulse appeariny in Fig. llF. Immediately fol-
lowing the shifting of the 42nd data bit out of the SCU to
the ~CC, the CCD siynal aB shown in Flg. llF causes the
message len~th counter to be triggexecl to generate a count
C - 63
71
1~836~ 21-ME-15
of CT42 from decode 56 to thus set the EOM F/F 378. The
EOM F/F, now generating the EOM binary 1 signal on conductor
564, will effect a complete total reset of the SCU in the
same manner as previously described, thus preparing the SCU
for receipt of another command from the RCC.
One remaining portion of the SCU remains to be
explained. Reference is now made to Figs. 12, 14C and 14D.
There may be circumstances whereby an MTU or MTU's do not
respond to a message transmitted to those units from an SCU.
These may be situations where an invalid function code or
an invalid address is transmitted to MTU(s), in which case
the MTUts) will not respond with a message back to the SCU.
If the SCU is in the wait mode, expecting a message. response
from the MTU(s), that unit will hang up in the wait mode
until a message is received. In order to prevent the SCU
from hanging up in this mode, a provision has been made
whereby, if a message is not received within a specified
period of time, the SCU will automatically send a message of,
for example, all binary l's or all binary 0's to the RCC.
This message can be xecognized by the program in the RCC as
an invalid message. The SCU will reset after -that message
is transferred to the RCC,
Referring to Flg. 14C, let it now be assumed that
the PLRFF 160 is in a set state. With PLRFF 160 in a set
state, the PLRF signal applied to the 267 millisecond delay
counter 404 via conductor 406 is a binary 0 enabling the
counter to begin counting the 30Hz signals applied to an
AND gate 570. AND gate 570 is enabled by the binary 1 FF2A
signal from flip-flop 376 via conductor 572. The timing
for the operation of the 267 millisecond counter 404 is
shown in Fig. 12 on the 267 MSD line. It will be noted
that after 267 milliseconds, an AND gate 574 decoding output
~2
C - 64
1;~8368~ 21-ME-15
signals on conductors 576 from counter 404 generates a
267 MSD binary 1 signal when that gate detects a count
representative of a 267 millisecond delayO The 267 MSD
signal is simultaneously applied to a preset input PR of
flip-flops 374 and 376 via a conductor 578. As shown in
Fig. 12, the two flip-flops FFlA 374 and FF2A 376, when
set by the 267 MSD signal, will generate binary 0 output
signals on their corresponding conductors 540 and 572.
The binary 0 signal from the 0 output terminal of FF2A now
allows the output of OR gate 398 to go to a binary 0 signal
releasing the 30Hz strobe clock counter 394 to begin count-
ing the 240Hz clock signals. As can be seen in Fig. 12,
the clock decode 552 of Fig. 14B will now begin to generate
the DeA, DeB and DeC signals in the same manner as previously
described. The DeA and DeB signals are applied to all of the
power line receivers; however, those two signals have no ef-
fect on any of the receivers because a message has not been
received by any of those receivers to effect the generation ~ -
; of a strobe A signal, which starts those receivers into op-
eration. The one signal which is significant coming out of
the clock decode 552 in this particular instance is the
DeC signal on conductor 352. That signal, as previously
described, is applied to the data transmitter receiver 40
of Fig. 13A via conductor 352 to parallel transfer the in-
formation from the STORE B F/F 414 in each of the receivers
onto the trunk line 14 going to the RCC from the transmitter
modulator 166. The information transferred to the transmitter
receiver 40 will be either binary l's or binary 0's depend-
ent upon the state chosen for the STORE B F/F 414. The state
of the STORE B F/F is shown in the example of Fig. 14B to
be reset at all times, except when data is being received
from the STORE A F/F 412. In this example, all binary 0's
~3
C - 65
~8368~ 21-ME-15
would thus be transferred to the RCC as an invalid message
for use by the program. However, if the design so dictates
that all binary l's are to be transferred to the RCC, the
STORE A F/F 412 would merely have to be in the set state
to effect the transfer of all binary l's from the STORE B
F/F to the RCC.
Referring again to Figs. 12 and 14D, it can be seen
that the CCD signal will cause the message length counter 390
to count each bit being transferred (each D C pulse generation)
to the RCC. When the message length counter decode 560
generates the CT42 pulse on conductor 562, the EOM F/F 378
is set, thus effecting the SCU reset through OR gate 30 by
resetting the system control flip-flop 28.
METER TERMINAL UNIT
(MTU)
OPERATIONAL DESCRIPTION
The detail logic and timing for the MTU is illustrated
by Figs. 15 through 22. By referring to Figs. 15, 19, 21 and
22, it can be seen that each of those figures is a legendary
drawing showing the interrelationships between several figures
with corresponding numbers. Each of the legendary drawings
comprise a designated portion of the MTU. The MTU operates in '
basically four modes. These modes are (1) a receive message
mode, (2) a control mode, (3) a read and store mode and (4) a
transmit mode. A great deal of the MTU logic is time shared
logic and the MTU utili~es this time shared logic in each of
its operating modes. For this reason, the drawings illustrating
the detailed logic of the MTU have been segmented into figures
which correspond to each of the MTU operating modes. Further,
as the ensuing description proceeds, it will be noted that
some of the time shared logic is duplicated on some of the
figures. This was done for clarity and to simplify the
complexity of the drawings. The number designations of the
C - 66
74
1~8.~6~39
components on the drawings having like numbers a~e duplicated
in the various drawings.
The MTU's are preerably fabricated ~rom commerciall~
available integrated circuit packages. A complete listing o~
the major operational blocks as shown in the lo~ic drawing
is listed in the following Table 4. Tak,le 4 provides a circuit
name or description of the major circuit packages, ~he
manufacturers' names, the manufacturers' part number for those
packages and a reference to a manual or the like which provides
detailed information on the use of each of those packa~es.
TABL~ 4
METER TE~1INAL UNIT
M~NUFACTURERS' CIRCUIT IDENTIFICATION
CIRCUIT N~ME/
DESCRIP_ION MAN11FACTIlRER MANUFACTURERS' NO.
MULTIPLEXERS (MPX's) MOT~ROLA MCl4539
RCA CD40l9A
DEMULTIPLEXERS ~DMPX7s) RCA CD4555B
ALL FLIP FLOPS RCA CD4044A
RECEIVE MESSAGE RC~ CD4015A
REGISTER
MTU AND SCU ADDRESS RCA CD4030A
COMPARATORS
CLOCK SYNC REG & XMIT 'RCA CD4035A
CLOCK REG
SYNC BITS COUNTER RCA CD4027A
CLOCK COUNTER RCA CD4518B
ALL ONE SHOTS MOTOROLA MCl4~28
l/2 SEC DELAY COUNTER RCA CD4024A
PARITY CI~ECK GENERATE NATIONAL MM74Cl74 ~PLUS
GATING NOT SHOWN)
LOAD SELECT DECODE RCA CD4556B EOR LOADS
CD4555 FOR LIGIITS
PHASE LOCKED LOOP RCA CD4046A
DIVIDE BY 48 COUNTER RCA CD4024A
C - 67
" ~5
.. . . , . . :
1~83689
~Table 4 -- continued)
DIVIDE BY 5 DOWN MOTOROLA MC14522
COUNTER
36 BIT SHIFT REGISTERS MOTOROLA MC14557
~TER SELECT DECODE RCA CD4555B
lAll Motorola circuits can be found in the manual
entitled McMOS Integrated Circuits Data Book,
copyright 1973 by Motorola Corp.
2All RCA circuits can be found in the manual entitled
COS/MOS Integrated Circuits, copyright 1974 by RCA Corp~
This circuit can be found in the manual entitled CMOS
Integrated Circuits, copyright 1975 b~ National
Semicollductor Corp.
.
The operation of th~ MTU will now be described
; in the ahove sequence as previously mentioned. First, going
throuyh tlle message receive mode, then the control mode, the
read and store mode and ~inally the transmit mode.
P~rior to proceeding with the operational description
o~ the MTU, it is considered advantageous at this time to
review the format o~ the messa~e transe~rred over the power
lines from each of the SCU's to the MTU's as shown in Fig. 3.
The r~lessage entering an ~TU ~rom an SCU ellters in the format
as shown from the left to the right of Fig. 3. The first
three bits of the message are the start code (001) bits, which
are utilized by the MTU to detect the start of a message. The
following eight bits are the SCU address which,as previously
described, were reconstructed b~ the SCU's address generation
logic. This SCU address is utilized by the MTU as a part of
its address during the receive mode operation. Following the
SCU address is the previously mentioned 11 bit MTU address.
As will be described in detail, the MTU address is decoded by
the MTU to select either one MTU, a ~roup o~ eight MTU'~, one
C - 68
u~ i6
.
1~83~39
section of MTU's (e.g., one-eighth o all MTU's on a power
line) or all of the MTU's on a power line or in a complete
system. Following the MTU address is the MTU flmction code
previously noted in connection with the SCU as the SCU/MTV
function code. The MTU function code is decoded by the MTU
to place that unit into a specified one of its modes of
operationO Following the MTU function ~ode is a 6 bit parity
field, which is checked by the MTU during the receive mode
to see if the message contains valid parity. As previously
described, the parity check and generate function of th; MTU
plays no part in the operation o~ the invention, it merely
is being shown to complete the description of the prese
disclosure.
MTU RECEIVE MODE OPE~ATIONAL DESCRIPTION
In the ensuing description it should be assumed
that all flip-flops, registers, counters, etc. in the MTU
have been reset or initialized at the time of power
application to the MTU from a source not shown.
Reference is now made to Fig. 15, which illustrates
the interrelationships between Figs. 15~ - 15D. These latter
figures illustrate in detailed block diagram form the MTU
logic which controls the,message receive mode of operation.
It is suggested at this time that Figs. 15A - 15D be placed
as shown by Fig. 15, since those drawings interconnect with
each other by interfacing lines. Additionall~, the timing
diagram which illustrates the operational timing of the MTU
during the message receive mode is illustrated by Fig~ 16.
~ eference is now made to Fig. 16 to an RE' data line
illustrating the message format of data being provided to the
MTU over the power lines. As previously described, a ~urst
of energy on the power line represents a binary 0, whereas a
binary 1 is represented by the ab~ence of a burst of energy.
C 69
` " ~7
21-ME-15
368~
In Fig. 16 the first three bits of RF data which enter the
MTU are the sync bits 00 shown as bursts of energy and a 1,
followed by the remainder of the message. It will be noted
that the message excluding the three sync bits, is comprised
of 30 data bits shown as dotted blocks, since these data bits
are indeterminate depending upon whether they are binary l's
or binary O's.
Reference is now made to Fig. 15A, which shows the
MTU receiving the RF data into a capacitive power line coupler
low frequency attenuator 600. The power line coupler, which
isolates the 60 Hz line voltage from the input of the MTU,
passes the RF data pulses to a conventional operational
amplifier 602 via a conductor 604. The output of amplifier 602
designated RF data is on a conductor 606. The RF data from
amplifier 602 is provided to a commutating band pass filter
608 similar to that previously described in connection with
the SCU. Band pass filter 608 is also receiving an fO signal
on a conductor 610 from an AND gate 612. It will be recalled
that the frequency of the fO signal is that frequency at which
the SCU's transmit their messages over their corresponding
power lines to the MTU's. It should be mentioned that the
frequency of the fO signal may be any one of several frequencies
as listed in the previously mentioned Table 1, which allows the
MTU's on various power lines to operate at different receive
frequencies.
Still referring to Fig. 15A, the fO signal is
generated by a receive oscillator 614 on a conductor 616 and
provided to a multiplexer (MPX) 618 illustrated as an electronic
switch. ~PX 618 receives two control inputs, mode A and mode B,
via conductors 620 and 622. The control inputs to MPX 618 are
generated by function decode logic illus-trated in Fig. l9B.
The generation of mode A and mode B signals will be covered
C - 70
7a ;
~8~ 21-ME-15
subsequently in more detail; however, for the present let it
be recognized that the mode A and mode ~ signals are both
binary l's at this time. These two signals enable MPX 618
and a demultiplexer ~DMPX) 624 to activat:e their corresponding
switches to connect the f0 signal from the receive oscillator
614 to the input of AND gate 612 via conductor 630. AND gate
612 is enabled at this time by a binary 1 signal on a
conductor 632 from a now enabled AND gate 634 also receiving
the mode A and mode B signals via conductors 636 and 638,
respectively.
A digression is momentarily made back to the MPX
618 of Fig. 15A, also receiving an fl input signal from a
transmit oscillator (XMIT OSC) 640 via a conductor 642, and
a 60 Hz pulsating signal via a conductor 644. In the present
description, these two input signals have no effect on the
operation of the MTU in that those signals are utilized during
the operation of two other modes to be explained in the
subsequent description. However, it should be noted at this
time that, as the binary configurations of the mode A and
mode B signals applied to MPX 618 and DMPX 624 change during
subsequent operations, the switches of those two circuits
will likewise change to the appropriate positions in accordance
with the binary configurations of the mode A and mode B signals.
The description now continues by reference back to
the commutating band pass filter 608, which now selects the
message coming from the SCU and passes that message via a
conductor 646 to a detector circuit 648. The output of
detector 648 is applied to a one-shot multivibrator 650 on a
conductor 652. One-shot 650 is triggered upon the detection
of each binary 0 in the input message data stream as shown
on the data line of ~ig. 16. Thus it can be seen that each
time one-shot 650 is triggered, a binary 0 data bit is clocked
C - 71 79
,
~ 6~i83~
out of that one-shot, whexeas i a binary 1 is detected,
one-shot 650 is not fired and its output is representative
of a binary 1.
The output of one-shot 650 is simultaneously applied
to three elements. One connection rom one-shot 650 is the
receive data (REC DATA) on a conductor 654 applied to a D or
data input terminal of a message receive reyister ~56 of
Fig. 15B. The manner in which the receive data is clocked
into register 656 will subsequently be described. The receive
~ data is also applied from one-shot 650 to a data input (~ATA IN~
terminal of a parity check generate circuit 658 of Fig. 15D
via a multiplexer MPX 660 and conductors 662 and 664 (the
latter conductor traverses through Fig. lSC to Fig. 15
Reference is now made back to Fiy. 15A and to an
SOM line of Fig. 16, where it is shown that the f:irst binary 0
detected by the MTU fires one-shot 650 and applies the negative
going edge of first data bit to a set input terminal of a
start-o~-mcssage flip-flop SOMFF 666 on a conductor 668. ~s ;~
shown in Fig. 16, the SOMFF 6G6 sets at this time generating
a binary 1 OUtp~lt signal on a conductor 670 to ~ire another
one-shot designated SOM re~et 672. The output o~ one-shot 672
is shown in Fig. 16 as a ~hort binary 1 pulse ap~lied as a
SOM reset signal to a common reset CR input terminal o~ a
clo~k Syllc register 674 via conductors 6i6 and 678. The
purpose of the clock sync register 674 will momentarily be
~escribed. The SOM reset signal on conductor 676 is also
applied to a reset terminal of the parit~ chec3c generate
circuit 658 of Fig. 15D through the multiplexer 650 via
conductors 680, 682 and an OR gate 684 of Fig. 15C. The
parity chec]c generate ~ircuit 658 is^now reset to recei~e a
parity receive data on conductor 664 to check parity of the
incoming message ~rom the 5CU.
..;~
- 72 ~'
.
aG
Reference is now made back to Fig. 15A to the clock
sync register 67~ and to the timing diagram of Fig. 16. It
will be noted in Fig. 16 that a 120 Hz pulsating signal is
applied to a T input terminal of the clock sync reyis-ter on
a conductor 686. The 120 Hz signal is generated from a master
clock generator 688 shown in Fig. l9C. The master clock
generator receives a 60 Hz sine wa~e input signal on a
conductor 690 from any 60 Hz source not shown ~e.g., the power
; lines 18). It will also be noted that the master clock
generator 688 generates a 60 Hz pulsating output slgnal Oll a
conductor 692, As will subsequently be described, the 60 Hz
signal is also utilized in the MTU to deri~e the appropriate
timing for that unit.
Reference is now made back to ~ig. 15A and Fig. 1~.
The purpose of the clock sync register 674 is to synchronize
the incoming data bits with clock pulses generated by that
circuit. It will be recalled that the SOM reset signal caused
the clock sync register 674 to reset upon the detection of
the ~cry first binary 0 in the sync bits of the message. With
the clock sync register 674 now reset, the output si~nal from
the 0 terminal o~ the first ~hree flip-flops of that register
on conductors 69~ are now binary l's. These three binary 1
signals on conductors 694 now enable an AND gate 696 to apply
a binary 1 signal to a S input terminal of the first flip-flop
of register 674 via conductor 698. As shown in Fig. 16, the
first 120 Hz pulse following the SOM reset pulse causes the
j first flip-flop of register 674 to be set generating a
positive going basic clock signal at the output of an inverter
700 to trigger a sync bits counter 702 via conductors 704 and
706.
The clock sync register 674 i~ a convent:ional shift
r~g~ster which will cause a binary 1 fxom the first register
; C - 73
8 1
3~
to be clocked sequentially through each of the flip-flops in
that register upon the occurrence of each 120 Hæ signal on
conductox 686, thus generating a basic clock out~ut signal
from inverter 700 as shown ~In Figs. 15A and 16. Xt wi~1 be
noted that AND gate 696 is enabled only when the irs~ three
flip-flops o register 674 are binary 0~;. Thus, upon the
occuxrence of the fourth 120 Hz input signal, the fourth flip-
flop of register 674 will be set and the first three flip-
flops will be reset, ~hus causing AND gate 6~6 tv be enabled
to repeat the cycle as previously described. The reset si~nal
to the clock sync register 674 is applied from AND gate 69G
when that AND gate is disabled by the application of a binal-y
1 signal to a reset R input terminal of the first flip-flop
of register 674 via an inverter 70~ and a conductor 710.
Reference is now made to the sync bits counter 702
of Fig. 15A, which is now counting the basic clock signals on
conductor 706. When the Syllc bits counter 703 ac'nieves a !~
count of three, an ~ND gate 712 receiving input signals from
the counter 702 on conductors 714 is enabled to generate a
count of three, CT3, output signal on conductor 716. The
timing for the generation of the CT3 signal is noted on the
basic clock line of Fig. 1~. The CT3 signal now sets a sync
flip-flop 718 by the application of a binary 1 signal to a
se~ S input terminal of that flip-flop. With the sync flip-
flop 71~ now set, a binary 1 signal is generated from thatflip-flop's 1 output terminal on a conductor 720 to now enable
an AND gate 722, also receiving the basic clock signal at a
30 Hz rate from inverter 700 on a conductor 724. ~eferring
to Fig. 16, it can be seen that ~ND gate 722 now begins to
generate receive clock signals (~EC clock) on a condllctor 726.
The purpose of the ~EC clock is to geJIerate two additional
~ignals shown in Fig. ~6 as a xeceiver shift register clock
C - 74
~RE.C S/R clock) and a parity receive clock (PARITY REC CLOCK~.
These two clock signals are generated as follo~s.
The REC clock of conductor 726 is now applied
through a multiplexer MPX 728 of Fig. 15(' on a conductor 730
.5 to a trigger T input terminal of a clock counter 732. Clock
counter 732 will now begin to count the ~C clock pulses and
provide count output signals on a plurality o~ ~onductors 734
to a clock counter decode logic 736. Three output signals
representative of binary counts in counter 732 are genex~ted
by the clock counter decode 736~ It will be noted that the
clock counter 732, when in a reset state, generates a binar~ 1
00 count output signal on a conductor 738 to apply set signals :.
to a receive control flip-flop (~EC CONT F~ 740 and a paritv
con~rol flip-flop (PARITY CONT FF) 742, placing each of those
flip-flops in a set state. Flip-flops 740 and 742 at this time
are now providing binary 1 output signals from their 1 terminal
on conductoxs 744 and 7~6 as one input to two AND gates 748 and
750, respectively. Stlll ref~rring to Fig. 15C, it will be
noted that AND gates 748 and 750 are now enabled to generate
the REC S/R clock signals on a conductor 752, and AMD gate 750
is enabled to generate the PARITY ~EC CLOCK signals on a
conductor 75~. Tli~ enabJ.~ment of these two AND gatc~; is
effected by the previously mentioned inpu~ signals on conductors
744 and 746 in conjunction with the REC clock signal now applied
25. on a conductor 756 f.rom an AND gate 758. AND gate 758 is
receiving the binary 1 mode A and mode B input signals o~
conductors 636 and 638, along with the REC clock signals on
a conductor 760. The timing for the ~eneration of the REC S/R
clock an~ PA~ITY REC CLOCK signals is shown in Fig. 16.
The PARIT~ REC CLOCK on conductor 754 is applied
fxom the output of AND gate 750 from Flg. 15C to a CL clock
input terminal of the ~arity check genexate circuit 658 of
C - '~S
.
~3
~0~368~ 21-ME-15
'
Fig. 15D via the MPX 660 on a conductor 762. It should
be noted at this time that the PARITY REC CLOCK signals
now allow the PARITY REC DATA to be clocked into the parity
check generate circuit 658 to allow that circuit to now begin
checking message parity. Simultaneously with the clocking of
the PARITY REC DATA into the parity check generate circuit,
the REC DATA from the one-shot 650 of Fig. 15A is clocked
into the message receive register 656 under control of the
REC S/R clock signal applied to that register to a CL clock
input terminal as shown in Fig. 15B.
It is significant to note at this time that the
three sync, or start, bits ~001) of the incoming message have
been stripped off of that message under control of the sync
bits counter 702 in Fig. 15A. This removal of the three sync
pulses is illustrated by the delay in the generation of the
REC CLOCK signal after the three sync pulses have been counted
as a result of the generation of the CT3 signal on conductor
716 in Fig. 15A. This prevents the three sync bits from being
clocked into the message receive register 656.
Reference is now made back to Fig. 15C to an output
conductor 780 from the clock counter decode 736 generating a
binary 1 signal at a count of 24 of the clock counter to
provide a reset input signal to the REC CONT FF 740. The
flip-flop 740 is reset at a count of 24 to prevent the six
parity bits of the 30-bit message from being taken into the
message receive register 656. When the receive control flip- ;
flop 740 resets, a binary 0 output signal on conductor 744
disables AND gate 743 to thus prevent the further application
of the REC S/R clock signals on conductor 752 to the CL input
terminal of the message register 656. Thus, it can be seen
that the message register 656 receives only the 24 data bits
of the incoming message from the SCU.
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, . , .. , .. , ~
~83~ 21-ME-15
The message will not continue to be clocked into
the message register 656 of Fig. 15B until the clock counter
decode 736 of Fig. 15C decodes a count of 30 from the clock
counter 732. Referring to the clock counter decode 736, a
signal T30 is generated by that decode on a conductor 764
when the 30th message bit is received (see T30 of Fig. 16).
The T30 signal is applied to a reset R input terminal of the
parity control flip-flop 742 at this time causing that flip-
flop to reset, generating a binary 0 output signal on con-
ductor 746 to disable AND gate 750. Disabling AND gate 750
now removes the PARITY REC CLOCK signal to the parity check
generate circuit 658 of Fig. 15D inhibiting the further
clocking of the message through that circuit.
At time T30 the entire message is now loaded into
the message receive register 756 of Fig. 15B. 15B. It will
be noted that the T30 signal from the clock counter decode
736 of Fig. 15C is now applied to an AND gate 798 of Fig.15D
via conductors 764 and 800. AND gate 798 will be enabled at
this time to generate a function strobe enable (FUNC.STROBE
EN.) signal on a conductor 802 to set the FSFF flip-flop 792,
~,
provided that all inputs to AND gate 798 are binary l's at
this time. At the leading edge of the T30 pulse, if the
parity check generate circuit 658 of Fig. 15D has determined
.'.'; .
,,
~ .
~ C - 77
21-ME-15
~83689
'
that the message contains good parity, that circuit will
generate a GOOD PARITY binary 1 output signal on a conductor
804 to AND gate 798. The other inputs to AND gate 798 come
from various decode functions from the message receive
register 656 of Fig. 15B. The decoding of these input
signals applied to AND gate 798 will now be described.
:
Register 656 is 24 bits in length having bits or
stages 3 - 26 illustrating the format of the message as it
resides in the register at T30. Bits 0, 1 and 2, not shown
correspond to the three sync bits removed from the received
message. Reference is now made to the SCR address field
shown in Fig. 15B comprising 7 bits (3 - 9). As previously
described in connection with Fig. 3, the SCU address was shown ~
as eight bits; however, in the SCU the eighth bit ~bit 10) is ~ '
designated as a mode bit having a purpose to be described. --
It will be recalled from the previous description that an
MTU must recognize the SCU address from which it is receiving
a message before that MTU can be activated. This is accom- ~ ;
plished by an SCU address comparator 806 monitoring bits 3 -
9 of the SCU address from register 656 on a plurality of con~
ductors 808 and comparing that SCU address with a fixed SCU
address provided to the comparator 806 on a plurality of
conductors 810 from an SCU address switches block 812.
Switches 812 are set to duplicate the SCU address of that SCU
in communication with the MTU. If the SCU address switches
compare with the SCU address from register 656, the SCU
~ .
.
C - 78
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~8368~ 2l-ME~l5
address comparator will generate a binary 1 output signal
designated SCU ADD. COMPARE on a conductor 814. The SCU
ADD. COMPARE signal on conductor 814 will thus provide one
of the enable inpu-t signals to AND gate 798.
Reference is now made back to Fig. 15B to that
field of the message register 656 designated FUNC. CODE.
The function code field of the message is comprised of five
bits (22 - 26) as previously described in connection with
Fig. 3. These five bits are d0coded as bits FC0 - F 4 by
a valid function decode (VALID FUNC. DECODE) circuit 716
receiving those signals via a plurality of conductors 818 and
820 from the output of the message register 756. If the
VALID FUNC. DECODE 816 determines that the binary bit con-
figuration of the function code is a valud MTU operation,
that circuit will generate a binary 1 VALID FUNC. output
signal on a conductor 822 as an additional enable input sig-
nal to AND gate 798.
Reference is now made back to Fig. 15B to the
message register 656. That which remains to be described in
connection with the decoding of the message register 656 is
a determination as to whether the MTU is receiving an address
designated for that MTU. , AS previously mentioned, each MTU
in the system is capable of being individually selected, se-
lected as a group of MTU's, a section of MTU's or selected
in conjunction with all MTU's in the system or on an SCU
power line. Referring to the MTU address field of register
656 of Fig. 15B, it will be noted that that address field is
comprised of bits 11 - 21 making up the entire ll-bit MTU
address as previously described in connection with Fig. 3.
Bits 11 - 18 are applied via a plurality of conductors 824
to an ALL MTU GATES 826 and to a comparator 828 of a pair
of comparators 830. Bits 19 ~ 21 of the MTU address are
C - 79 ~7
21-ME-15
33~
applied to a comparatol~ 832 of comparators 830 via a
plurality of conductoxs 834. The comparators 830 re~eive
fixed MTU address input signals from an MTV ADD. SWIqlCHES
block 83~ comprised of a set of switches 838 and 840 via a
S plurality of conductors 842 and 8~4, xespectively, connected
to the comparators 828 and 832. Each o the comparators 828
and 832 has its own respective output signal lines, whi.ch
will become binary l's whene~er the MTU address from regis~ ;
tex 656 compares with the corr~sponaing address in the MTU
ADD. SWITCHES 836,
To select a single MTU, the comparators, when de-
coding the proper binary bit configuration of the MTU address,
,! will generate a binary 1 ou~put signal on each of two conduc-
tors 846 and 8~8 to enable an AND gate 850, whi.ch in turn
generates a 1 MTU binary 1 output signal on a conductor 852.
To select 1/8, or a section, of the MTU's on rl.designated
power line, r~n AND gate 854 is enabled by a binary 1 signal
on conductor 848 from the comparator ~32 and a binary 1 sig-
nal on conductor 856 from the ~L MTU GATES 826.
The ALL I~TU GATES monitor bits 11 -18 to generate
a binary 1 output signal on conductor 856 whenever the ad- :
dress as speci~ied by bits, 11 - 18 specify an all MTU address.
Reference is now made to bit 10, designated MODE
of register 656. Bit 10 will be eithex a binary 1 or a bi-
nary 0 dependent upon the type of mode addressing specif.ied
~: to the M~U by the message. When bit 10 is reset, a binary C
on a conductor 858 will disable two AND gates 860 and 8~2.
- This will prevent the selection of a group of eight Mrruls
and all MTU's. However! when the MODE bit 10 is a binary 1,
AND gates 860 and ~62 axe conditioned to be enabled to
generate a binary 1 QUtpUt S ~ gnal in accordance with an
address signal provided to each of those gates~ :~eferring to
C ~ ~0
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21-ME-15
836139
AND gate 860, it will be noted that -that AND gate is enabled to
generate an eight MTU's binary 1 signal whenever -the MODE bit
is set and when the output of comparator 828 generates a binary
1 on conductor 846. Comparator 828, which monitors bi-ts 11 - 18
of the MTU address, can thus generate a binary 1 output signal
to select any number of groups of MTU's on a designated power
line limited only by the size of the MTU address field. When
AND gate 860 is enabled, the 8 MTU's binary 1 address signal
is generated on a conductor 864. AND gate 862 is similarly
10 enabled when the MODE bit is a binary 1 and bits 11 - 18 specify
to the ALL MTU GATES 826 an address common to all MTU's on a
power line or in the sys-tem. The combination of the binary 1
signals on conductors 856 and 858 will cause AND gate 862 to
generate an ALL MTU's signal on a conductor 866.
Whenever the MTU decodes an acceptable address, one of the
AND gates 850, 852, 854 or 860 will be enabled to apply a
binary 1 signal on their corresponding conductors to an OR gate
867 to allow that OR gate to provide a binary 1 MTU ADD.
ENABLE signal to AND gate 798 via conductor 868. It can now
be seen how AND gate 798 will be enabled at time T30, as shown
in Figs. 15D and 16 to set the FSFF 792 with the FUNC. STROBE
EN. signal at the time the message is decoded. Assume now that
all inputs to AND gate 798 are binary l's, thus indicating the
received message has good parity, an SCU address compare, a
recognized MTU address and w valid function code. As a
result, the AND gate 798 will generate a binary 1 FUNC. STROBE
EN. signal on conductor 802 to set FSFF 792. The setting of
FSFF 792 is shown in Fig. 16 on the FUNC. STROBE line, whereby
-that flip-flop is providing a binary 1 FUNC. STROBE signal on a
conductor 794 to a function code gating 796. The FUNC. STROBE
signal now enables the function code gating circuit 796 to pass the
FCO - F 4 signals on conductors 818 through that gating network
~ '
C - 81
89 ``~
`
~````` ~L~33~39
generating binar~ output signals FC0' - Fc4' on a plural~
ity of conductors 870. The FC0' - FC4l signals are pro-
vided to various decode logic in the MTU to subsequently be
described. It is these signal~ which ar~e decoded to deter-
mine the subsequent mode of operations that the MTU will gointo.
Reference is now made to Fig. 15~ to one-shot 1022
receiving the FUNC.STROBE signal on conductor 1020. The
binary 1 signal genera~ed on FUNC.STROBE when FSFF 792 is
set also triggers one-shot 1022, and a binary 1 RESET CLX CTR
signal appears on the 1 output. This signal is applied to
an input of OR gate 785 shown on Fig. 15C via conductor 784
and produces a binary 1 signal at the output of OR gate 785
which resets clock counter 732 via conduct~r 772. The T30
pulse is foreshortened by the resetting action. Cloc~ counter
732 is thus reset and ready for use by other portions of
the MTU.
Consider now what will happen in the MTU if any
~f the inputs to AND gate 798 on Fig. 15D are not binary l's
when the T30 signal becomes a binary 1. In such a case of
an invalid message, FUNC.STROBE EN on conductor 802 remains
.
at a binary 0, FSFF 792 remains reset and its 1 output
FUNC.STR~BE signal on conductor 794 remains at a binary 0.
Referring to Fig. 15C, note that the REC CLOCK
signaI on conductor 996 causes clock counter 732 to advance
beyond the count of 30, thereby dropping the T30 signal on
conductor 764 to binary 0. One-shot 766 is fired on the
trailing edge of the T30 pulse as illustrated in Figs.
15C and 16. The binary 1 REC RESET signal is now applied
to a reset R input terminal of the clock counter 732 via a
multiplexer MPX 770 and conductors 772 and 774. It will be
noted that the MPX 770 is also receiving at this time the
m~ and mo~e B input signals to establish the proper
C _ 82 90
21-ME-- 15
3~
i
switch position for MPX 770. The application of the REC
RESET signal to the clock coullter 732 now cause~ that
counter to be reset back to a binary 0 state in preparation
to the receipt of another message from t~he SCU or other
use as wil]. be describad. It will also be noted as shown
in Figs. 15A, l5C and 16 that the REC RESET signal is
a~plied to an R reset input terminal of the SOM flip-flop
666 via conductor 776, resettlng that flip-flop. Additionally,
~ .
the REC ~ESET signal is applied to the RESET input terminal
of the parity check generate circuit 658 via the multiplexer r
660, conductors 680, 682, OR g~es 684 and conductor 778.
The parity check generate circuit is now ~n a reset state
~ . ~
in preparation to the receipt of another message from
the SCU.
This completes the message receive mode description
for the MTU for both valid and invalid messages. In all
subsequent de~cription~ the assumptl~n should be made that
a message has been loaded into the message receive register
656 and that that message has been decoded as a valid
message with a proper address, good parity and valid r
unction code to activate the ~unction code gating to allow
the MTU to go into the mode specified by the Fc0' - Fc4
signals.
Reference is now made to Figs. 17 and 18, wherein
Fig. 17 shows a detailed block diagram of the load control
logic for controlling a plurality of loads, or lights, ex-
-ternal to the MTU at a designated customer residence, and
Fig. 18 shows the opexational timing of the load control
~`~ logic. In Fig. 17 the time-shared logic comprised of OR
gate 788 and the ~SFF 792 has been duplicated for simpliciry
purposes to provide a better understanding o~ the M~U
control mode.
C ~ 82A
~1
., . , ,. . . - , , : ~
3~
As sho~ in Fig 18, the decode of the functlon
code takes place at 1'30 as just described ~or the receive
mode. Let it now be ass~ed that the FSFF 792 l~ in the
sst state gener~ting the FU~C STROBE signal a~ shown in
Fig. 18. This allows the application of the FC0' - Fc4'
. signals on conductors 870 to be simultaneously applied to a
load select decode circuit 872 via a plurality o~ conductors
874, a drop load decode ~76 v.ia a plurality of conductors 878
and a set load decode 880 via a plurality of conductors 882.
10 The load select decode 87~ is a convèntional type of binary .;
decode logic for decoding the binary configurations of the
Fc0' - Fc4l signals. The input signals FC0' - Fc4', when
decoded by the load seleat decode, cause that decode to gen-
~érate a binary l output signal to either se~ or reset a par~
i5 ticular load or light 1ip-flop to that decode. It will be
noted that each of a plurality of LOADFF ' s 886 reGeive se t
and reset input signals to their S and R terminals on respec
tive conductors 88~ and S90. ~nnenever a one of the LOADFF's
886 is set by it5 correspondincJ binary 1 input sicJnal on con-
~0 ductor ~88, tllat flip-flop will generate a binary l output
- signal on a corresponding conductor 892 to activate a corr~-
spon2,..ng one o a plurali.ty of switches 894. Each of the
sw~tches 894 is illustrated as a TRIAC semi-conductor type
witch receiving a 24 volt AC input signal from a source not
~hown. ~hen a binary 1 signal is applied to one o~ the
~witches 894, the 24 Yolt AC signal i~ applied through that
switch to a load connected thereto by correspondiny one of
conductors 896~ The loads in Fig, 17 are illustrated as having
theix own power source, not shown, and being external to the.
MTU, as these loads are qenexally located in the building of
the residence where the MTU i5 installed. Typical loads which
can be controlled by the MTU, as preYiously descr.ibedl are
C - 83
92
air conditioners, hot water heatexs, electric clothes
dryexs, etc.
The load select decode 872 also provides a set
and reset input signal to;each o~ a plurality of LIGHTFF's
8~8 on corresponding conductor~ 899. These flip-flops
operate to activate their ~orresponding TRIAC switches 895
in a fashion similar to that just described for ~le ~O~DFF's.
.The switches 895 likewise control a light in the customer's
residence which contains its own power ~ource. As previously
described, the present system is capable of turning on and off
warning lights for the benefit of a custome3r to let him ~now
, when he is utiliziny power during peak periods so that h~ may
¦ reduce his load voluntaril~ to cut down on his power bill.
It will also be noted that each of the load flip-flops 886
.
and 898 can be reset to disengage their corresponding loacl(s)
. or turn out their corresponding light(s) by the application
o~ a binaxy 1 reset signal to the R terminal of those flip-
flops.
Referring to Fig 18, there is shown a load or
light control reset line, which illustrates the timing for
the activation of ei~her a load(s) or a light(s) flip~flop(sj.
A slight delay is shown bctween the li.sing edge of the Fc0'
; Fc4l signals compared to the load or light control set or
reset signals merely to indicaté that there is a slight ~elay
for the loads connected to fli.p-flops 886 and 898 to activate
or deactivate their corxesponding loads.
Reference is now made to Fig. 17 to the set load and
drop load decode circuits 876 and 880. These two ci.rcuits
receiving the FC0' and YC4l lnput signals will yenerate a
~inary 1 output signal on the.ir corresponding output conductors
90~ and 902 to activate an.OR ga~e 904 whene~er the messaye
function code specifi2s that a l~ad(s) is to be set o:r droppecl
out, ~he bina.ry 1 slgnal on either of conductoxs 900 or 902
C ~
93
, ~
3~
will be passed through OR gate 904 on a conductor 906 to
activate a guaranteed delay 908. The purpose of this delay
908 is to al~ow sufficient tinte ~or all of the loads to be ;~
either set or dropped out prior to resetting the FSF~ 792. ;~
After a specified delay, delay 908 will provide a binary 1
trigger signal to an S input te~ninal of a control reset
one-shot (CONT RESET OS) 910, causing that one-shot to gen~
erate a control reset pulse on a conductor 912 ~ the time
as shown in Fig. 18. The control reset pulse on conductor
lQ gl2 is a~plied to OR gate 788, causing that OR gate to now
provide a binary 1 reset signal on conductor 790 to the FSFF
792. ~esetting the FSFF causes the function strobe signal
to go to a binary O as shown in Fig. 18. The function strobe
signal now disables the function code gating on Fig. 19B,
and the ~ITU is in standby ready to receive another message
from th~ SCU.
MTU Read
The MTU read and store operation is best illustrated
by Fig. l9, which is a l~gendary drawing showing the inter-
rela~ionships ~etwe~n Fig!~. 19A - 19D. In the following dis~
cussion, Figs. 19~ - 19D should be positioned as shown in
Fig. 19. Figs. 20, 21~ and 21B are the timing diagrams which
will be used in the subseqllent discussion of Figs. 19A - l9D.
It will be noted in Figs. l9A ~ 19D that the time shared
logic previously described in co~nection with Figs. 15 and 19
is duplicated r wherein like numbers are assigned to like num-
bers of those previously discussed logic elements.
Let it now be assumed that the MTU has just complèted
the receive message mode and that a message is in t}le message
receive register 656, which specifies in its function code
that the MTU is to read and stoLe the me~er information from
C - ~5
. 9l~ .
~ .
~36~ 21-ME-15
one of several meters as shown in Fig. l9D. In Fig. l9D
there is shown a plurality of auxiliary meters 914 desig-
nated meter Al - meter AN, each having an encoder 916.
Meters 916 represent any number of meters at a customer
residence such as gas meters, water meters, oil meters, etc.
Also shown in Fig. l9B is a main meter 918, having its
associated encoder 920. The main meter 918 customarily would
be the main watt-hour meter found in a customer residence for
recording the consumption of power. As previously mentioned,
each of the encoders 916 and 920 preferred by the present
embodiment contemplates the use of an optical, serial-type
read-out encoder for providing binary output signals repre-
sentative of the amount of consumed commodity as documented~
in the aforementioned U.S. patent 3,846,789. In the ensu~ing de-
scription, the read and store command, which is now in the
message register, will selectively specify which of the meter
encoders 916 through 920 will be read in accordance with the
function code as previously described in connection with Fig. 3.
Reference is now made to Figs. l9B and 20. Let it
now be assumed that the MTU has just completed the received `~
message mode of operation as shown in Fig. 20 by the genera-
tion of the T30 pulse, which effects the decoding of the
FC0' - Fc4' signals now containing the proper function code
for a read and store main meter or one of the auxiliary meters
Al - AN. Referring to Fig. l9B, the function strobe signal
on conductor 794 at this time is enabling the function decode
796 to allow a function code decode logic 922 to decode the
Fc0' - F 4' signals to provide the proper output signals to
read and store the one of the meter encoders to be selected.
Since the function code of the message now specifies the read
and store operation, the function code circuit 922 generates
a binary 1 read and store (R & S) output signal on a conductor
924 to set a MODE A FF 926~ The function decode 922 will
C - 86 ~5
21~ 15
3~i8~
al~o genera~e one ~ t~o ~.tnary 1 vut~u~- signals to read
2~nd store e~:ther the ma~n meter c~r ~ selected one of t:he
aux~l~ary me~ers in accoxd~nce wi~h the function code on two
sigrlal l~nes 928 and 930, des~gnated R ~ S MAIN and ~ ~ S
S EXT~ xespec~iYely~
Re~rence is now made ~o the MODE A ~ 926, which
~s r.o~ set, That flip~l~lop ~:,5 now proYiding a bin~ry 1 out~
put signal on a conductor ~32 ~o generate a 3:~inary 1 mode A
signal on a conductor ~34 as shown in Fig. 20. The instant
that the MODE A FF 926 sets, lts ~inary 1 output signal also ~ ,
tr~g~rs a one~shot mult~;Yibrator 936 via conductors 932 and ~ . :
9380 One~shot 936 generates ~ narrow binary 1 pulse to reset
~ 1/2 second delay counter 940 and set a MODE B FF 94~ via a
conductor 9~4, ~ith the MODE B ~F ~42 now set, its 1 output
tenninal generates a binary 1 signal on a conductor 946,
~hich is ~assed through an OR gate 948 to generate a.binary 1
mode B s~gnal on a conductoi- 9 50 as shown in Fig ~ 20,
Still referring to Fig. l9B, it will be noted that
the bin~ry 1 output signal from the MODE A FF 92G is inverted
to a binary Q through an inYe.rte;. 952 to generate a binary O
.
mode~A sign~1 on conductor 936, In a similar fashion, binary
1 mode B signal from OR gate ~ is inYerted to a binary O
through an invertex 954 to generate a binary O nïode B signal
on a conductor 938, At this timP, the binary 0. mode A and
~5 mode B signals are applied to the inputs of ~he MPX 61~ and
DMPX 624 of Fig. l9B, causing those two logic circuits to
take on the switch positions as shown by the soli~ line there--
in. As shown in Figs, 2~ and l9B, the 60Hz c1ock pulses on
conductor 644 are no~ applie~ thr~ugh MPX 618 and DMPX 624 to
~xigger the input of the 1/2 second delay counter 940 via a
conductor 956, Delay countex 9~0, as shown .in Fiy. 20, will
cont~nue to count the 60Hz pulses and, aftex a 1/2 second de-
l~y~ will gene.r~te a 1~2 SEC DELA~(DI.) pulse on a conductor
~ ~ 87
~6
,
~ 36~
958. The 1/2 SEC DL pulse i~ now applied to an AND ~ata 960,
enabl.in~ that AND gate, due to ~he presence of the binary
si~nal ~rom ~he MODE A FF. AND gate 958 now applies a bi-
nary 1 signal on a conductor 962 to reset the MOD~ B FF 942
at the time shown ln Fig. 20.
Resetting the MO~E B FF g4~ applie~ a binary 0
signal on a conductor 946 to OR gate 948, now causing the
mode B signal on conductor 950 to go to a binary 0 and the
mode B signal on conductor 938 to go to a binary 1. Reerring
now to the MPX 618 and the DMPX 624, it can be seen that the
mode A signal applied to those two logic circuits is still a
binary 1, and the mode B signal i~ now a binary Thi~
combination of binary inputs now cau~es the MPX 618 and *he
DMPX 6~4 to switch from the position shown by the solid switch
arrow to the position now shown ~y the dotted switch arrow
to allow the continued applicatibn of the 60H~ pulses on .~
conductor 644 through those ~wo logic units to the input of i: ~ :
`,
the 1/2 second delay counter 940
The purpose of the 1/2 se~ond delay can bes t be
described by referring to Fig. 19D. In that figure, there
i5 shown a meter select decode 964 similar to the previously
described load select decode recei~ing the FC0 ' - Fc4 ' signals
on conductors ~70 from the function code ga1:ing 796 o~ Fig. ~;
l9B. The meter select decode will generate a binary 1 output
signal on one of a plurality of conductors 966 in accordance :~
with the function code to activat~ a corresponding one of a
plurality o~ TRIAC switches 968, each having its own 24 volt
AC input from a power source no~ shown. The activat2d TRIAC
switch will apply 24 ~olt AC to its corresponding encoder 916
to start a motor in th~t encoder in order to read out the in-
~Eo~mation from an optical disc. Since ~t take~ a certain
~mount o~ time for the.motor in the selected encoder to come
C ~ 88
97
. ~ ,
21-ME-15
`~````` ~0836~9
up to speed, the 1/2 second delay has been provided in the
system to allow the motor to come up to speed prior to the ,~;
reading oE the optical encoder. Reference is now made back
to Fig. 20 to the mode B line of that figure to the point
showing where the MODE B FF last reset. Immediately follow-
ing the resetting of the MODE B FF, there is a note between
arrows, which says Read. It is during this period that the
MTU will now read the meter information from the selected
encoder.
Reference is now made to Figs. 21A, 21B and l9A.
In Fig. l9A the 60Hz pulses are shown being applied on con-
ductor 644 to a phase lock loop circuit 970, generating
2880Hz output pulses on conductors 972 and 974. The 2880Hz
signal is applied to a trigger (T) input terminal of a
divide by 48 counter 976, which divides the 2880Hz down to
regenerate a 60Hz pulsating signal on a conductor 978 for
feed-back to the phase lock loop 970. The 2880Hz signal is
also applied to an AND gate 980, also receiving a binary 1
enable input signal at this time from an AND gate 982 via a
conductor 984. It will be recalled that the mode A signal
is now a binary 1 and the mode B signal is also a ~inary 1,
thus enabling AND gate 982 to provide a binary 1 input signal
to AND gate 980. The 2880Hz signals are applied on a con-
ductor 986 to a trigger T input terminal of a divide by 5
down counter 988. Counter 988 always starts out in a preset
count of 4, as a result of a decode 7ero output signal shown
in counter 988 when that counter is reset to zero. When the
MTU is first turned on, counter 988 is always zeroed out.
Thus, the binary 1 output signal from a DEC 0 terminal of
counter 988 is passed through an OR gate 992 to a PR input
terminal of counter 988 to preset that counter to a count of
four via conductors 990 and 994. Counter 988 divides the
C - 89 ge
~ 6~ ~
2880~1z input signal by 5 to reyenexate a read clock sia~al
at a 576II~ rate on a conduGtor 996 of F.ig. 19C.
As shown in Figs 21A and 21B on the read clock
576Hæ line, the read clock is constantly being re centered
in the middle of each data bit being read from the selected
meter encoder by a DATA IN tslope pulse)presetting the divide
by 5 down counter 988. The DATA IN .~slope pulse) is that
pulse coming out of a data one-shot 998 of Fig. 19~ on a
conductor 1000. It will be noted in Fig. l9D that the meter
encoder data on conductor ]000 is also being read ~rom the
!' encoder at a 576Hz rate. For each binary 0 bit of data read
from the selected encoder, the data one-shot 998 is tri~gered
j to generat~ a positive output signal to preset the down count-
er 988 to a count ~f four via OR gate 992 as shown in Fig. 13A.
15 Thus, for each data pulse out of the encoder, the 576Hz read
clock is re-centered in the center of the bit corresponding
to thak data pulse to synchronize the reading of the data fro~
the encoder with the read clock. The timing relation~hips
bctween the DATA IN (slope pulse~ on conductor 1000 from the ~ -
20 data one~shot 99~ and the read clocl; ~576H~) pulses on con-
ductor 996 are ~hown in Figs. 21~ and 21B.
As previously mentioned, the down counter 988 is
preset to a count of four upon the detection by one~shot 998
of each binary 0 from the selected encoder. However, under
25 those conditions when a binary 0 is not present (i.e., a
binary 1 is generated), there is no output pulse rom one-
shot 998. Thus, down counter 98g will not be preset. How-
ever, this is compensated for in oxder to continuously gen-
erate the read clcck on conductor 996 by the output from the
DEC 0 termina] of coun~er 988 on conductor 990 to OR gate 992.
; If a binary 0 is not recei~ed at ~R gate 992, when t:he do~tn
counter achieves a binary count of 0, it is preset Erom the
C ~ 90
~9
21-ME-15
33~
output of the DEC 0 terminal via OR gate 992. In this manner
the 576Hz read clock signal is continuously generated in the
center of the DATA IN (slope pulse) as inclicated in Figs. 21A
and 2lB.
Reference is now made to Figs. 21A and 21B to the
data from encoder line in that timing diagram. It will be
noted that digits 4 and 5 from the selected encoder precede
a start code comprised of ten l's, a 0 and a 1. This field
of bits is read from the selected optical encoder and is
utilized by the MTU to detect the start of the meter data
indicated by the six 6-bit fields designated ID # and digits
#1 through #5.
Referring to Fig. l9D, let it now be assumed that
one of the encoders 916 or 920 has been commanded by the meter
selected decode 964 to start that encoder's motor and thus begin
reading out the meter data in serialized message form to the
MTU. If the main meter 918 has been commanded to read its
encoder, the encoder optical read-out disc will begin to
generate a message on a conductor 1002 to a multiplexer
MPX 1004. On the other hand, if either one of the meters Al
through AN has been commanded to read its encoder 916, those
encoders will provide their meter data on corresponding lines
1006 and 1008 to their corresponding inputs of the MPX 1004.
It should be noted at this time that the two signals FC0'
and Fcl' are applied simultaneously to the MPX 1004 and to
and MPX 1010 from the function code gating 796 on conductors
1012 and 1014 to select the appropriate one of the meter en-
covers as determined by the meter select decode 964. It
should be noted that the MPX 1004 has a plurality of positions
which can be selected by the binary configurations of the
FC0' and Fcl' signals to select any one of the meter lines
coming in to MPX 1004. Thus, the MPX will pass the meter
100
C - 91
1~36~ 21-ME-15
:
data from the selected one of the meters via conductor 1016
to the S input terminal of the data one-shot 998.
As previously mentioned, for each binary 0 read by
the selected encoder, one-shot 998 is fired to generate a
narrow data out pulse as shown on line 1000. These data
pulses are applied via line 1000 to the input of an AND gate
1018 of Fig. l9A. That AND gate is now enabled to pass any
DATA IN (slope pulses) which appear at the input to that gate.
This is explained as follows:
Reference is now made back to Fig. l9B to the out- ;
pùt of the FSFF 792 generating the function strobe signal on
conductor 794. With the FSFF 792 set at the time shown in
Fig. 20, the leading edge of the function strobe signal is
applied via a conductor 1020 to a set S input terminal of a
one-shot multivibrator 1022. One-shot 1022 generates a nar- ;
row positive going output signal as shown in Fig. l9A, which
is passed through an OR gate 1024 to a set S input terminal
of a ten l's FF 1026 via a conductor 1028. It can now be
seen that the ten l's FF 1026 is in the set state generating
a binary 1 signal at its one-output terminal on conductor
1030 to AND gate 1018, to thus allow the DATA IN (slope pulses)
to pass through that A~D gate each time the data one-shot 998
of Fig. l9D is fired.
Flip-flop 1026 is that element of the MTU which
controls the detection of the start code shown in Figs. 21A
and 21B comprised of ten l's, a 0 and a 1. Let it now be
assumed that the selected meter encoder is providing meter
data via line 1000 to the input of AND gate 1018. Whenever
a binary 0 is detected by data one-shot 998 of Fig. l9D,
that one-shot generates a data out pulse, which is applied
to AND gate 1018 enabling that AND gate. AND gate 1018
applies a binary 1 pulse to an OR gate 1032 via a conductor
1034. OR gate 1032 passes that binary 1 pulse on a
C - 92 101
~ 836~9 21-~-15
conductor 1036 as a read reset signal through the now selected
read input terminal of MPX 770 via an OR gate 785 and on to a
reset R input terminal of clock counter 732 via conductor 772.
This will cause the clock counter 732 to reset. It should
be noted at this time, as shown in Figs. l9A and l9C, in
conjunction with Figs. 21A and 21B, that the read clock
(576Hz) signal from AND gate 1038 on conductor 996 is applied :
to the trigger input terminal of the cloclc counter 732 via
the MPX 728. The timing relationships between the read
clock signal on conductor 996 and the DATA IN (slope pulses)
are shown in Figs. 21A and 21B. The DATA IN (slope pulses) :
are shown in dotted form indicating that their presence is
indeterminate because it is not known whether the~ are bi-
nary 0's or binary l's. Also shown in Figs. 21A and 21B,
in dotted orm, are the read reset pulses derived from the
DATA IN (slope pulses) to reset the clock counter 732 of
Fig. l9A.
Reference is now made back to AND gate 1018 of
Fig. l9A. Let it now be assumed that the encoder is pro-
viding a binary 1 signal on conductor 1016, which has no
effect on the data one-shot 99 8 of Fig. l9D. Thus, the
DATA IN (slope pulse) is a binary 0 disabling AND gate 1018. ~:
The output of OR gate 10 32 in turn goes to a binary 0, remov-
ing the binary 1 read reset signal from the clock counter 732.
However, the presence of the read clock signal on conductor
996 now causes the clock counter 732 to count for each bi-
nary 1 read from the encoder. It can now be seen that for
each binary 0 read from the encoder, the clock counter 732
will be reset, and for each binary 1 read (the absence of a
pulse) the clock counter 732 Will count up by one.
Let it now be assumed that the~encoder as shown in
Figs. 21A and 21B has just provided the binary bit configura-
tion from digits 4 and 5 to the input of AND gate 1018 of
C - 93 1 02
.. , ~ .
- 1~8;~
Fig. l9A. At the end o~ digit $5 as shown in Fig. 21A, the
A~D gate 1018 detects the fir~t binary 1 in t~e start code
from the encoder. Since the start code is comprised of ten
l's, the AND gate 1018 will be disabled, removing the reset
input to clock counter 732 and allowing the read clock on
conductor 996 to trigger the counter. Referxing to Fig. l9A,
it can be seen that when the clock cQunter 732 achieves a
binary count of 10, the clock counter decode 736 generates a
cou ~tof 10 output signal on a conductor 1040. The count of
10 signal on conductor 1040 resets the ten l's FF 1026,
causing its output conductor 1030 to go to a binary 0, dis-
abling AND gate 1018.
As shown in Fig. 21A, following the ten l's in
the start code are bits 0 and 1 just prior to the fir~t bit
of the ID # field. The purpose of the 0 bit is to ensure
that the beginnislg of the meter data message (ID~ - digit #5)
is always detected at the~proper time so that the entire
3~-bl~ message is clocked into the selected one of a plurality
o~ stor~ge registers 1084 and 1058 of Figs. l9C and l9D, The
state of the bit 1 is insignificant. It could also be a bit 0
as it is not used. Referring now to Fig. l9A, there is shown
an OD~TFF 1041, which is utili~ed to detect the presence of
the first binary 0 after the clock counter 732 has counted 10
consecutive binary l's in the encoder data message. The DATA
~N (slope pulses) are applied to the set S input terminal of
the OD~TFF 1041 from co~ductor 1000. Flip-flop 1041 is reset
by a binary 1 signal on a conductor 1045 from the 1040 con-
ductor output of decode 736 when the counter 732 achieves a
count o~ te~.
The operation of the ODETFF 1041 is as follows:
Let it be assumed that a meter encoder is being read and
providing binary 1 and ~ DATA IN (slope pulses) to AND gate
C - 9
, ~0~
lLi~836~9
1018 to control the operation of the clock counter 732 as
just described. These DATA IN ~slope pulse~) are also
: applied to the ODE~FF 1041~ It should be noted, for each
binary 0 DATA IN (slope pulse) a positive going set signal
is applied to flip-flop 1041. With flip-flop 1041 ~et, a
binary 1 signal from its 1 output terminal on a aonductor
1047 keeps AND gate 1038 enabled to gene:rate the read clock
. pulses. It should also be noted that a binary 1 (negative
level) DATA I~ (slope pulse) has no effect on flip-flop 1041.
~lip-flop 1041 can only be set or reset on a positive going
: pulse.
So long as AND gate 1038 is enabled by the ODETFF
1041, the read clock pulses are applied to the T input termi
nal of the clock counter 732 allowing it to count binary 1
DATA IN (slope pulses). Assume now that the cloak counter
has countecl. ten consecutive binary 1 DArrA IN (slope pulses)
from the selected meter encoder. At the count of ten, the
¢ounter decode resets tlie ODETFF 1041 by the generation of
a ~inary 1 signal on conductors 1040 and 10~5. IYith flip-
flop 1041 now reset, its 1 oùtput terminal goes to a binary 0
disabling AND gate 1038 via conductor 1047. This stops the
~3enera~ion of the read ciock pulses and prevents the clock
coun~er 732 from counting until a binary 0 (positive going
pulse3 DATA IN ~slope pulses) set the ODETFF 1041.
Reference is now made to Fig. 21A to the digit #5
field of the Data From Encoder line. It is significant to
note at this time that the code utilized by the metex encoder
to transmit the meter data (digits #l - #5) i5 a 5 bit trun-
cated reflected binary code which does not use the all binary
l's configuration. Thus, at least one binary 0 is guaranteed
~n each digit transmitted from a selected encoder to the MTU.
C - 95
, . 1 D4
.
,, . ........... ,. ,.,.. .. , . `.. ,,~ .. ,~.. ...
83~8~
Utilizing the at least one binary O, when reading a se-
lected encoder, will guarantee that the clock counter 732
is reset at least once for every digit read by the encoder
until at least ten consecutive l's are counted by the clock
S counter.
Referring to Fig. 21A to the digit #5 message
field, it can now be seen that a worst case condition for the
numbcr of binary l's preceding the start code would be five
binary l's in each of bits 2 - 6 of digit #5, because a bi-
nary 0 would have to reside in bit 1 (the all binary l's
code is not used). Under this worst case condition, the
clock counter 732 of Fig. l9A will be~in counting binary 1
pulses starting at the 2nd bit of digit #5 and will effect
the generation of the count of ten signal on conductor 1040
ten counts later (5 counts into the start code 10 l's field)
to reset flip-flops 1026 and 1041. This will have no e~fect,
however, on the proper detection of the start of the message
at tl~e beginning of the ID # field. This is explained in
~he following parag~aph.
Reference is now made to the ODETPF 1041 of Fig.
l9A. Let it now be assumed that the clock counter 732 has
counted ten binary l's from the encoder under the worst
case condition as just described. As a result, flip-flop
1041 is reset, disabling AND gate 1038 stopping the read
pulses on conductor 996. Thiq stops the clock counter 732.
Referring to Fig. 21A, it is noted on the Data From Encoder
line that the ODETFF is reset at approximately the middle
o~ the start code if worst ca~e. If it is not worst case,
the ODETFF will be reset at some time between the point
shown and the bit 0 of the ~tart code, depending on how
many consecutive binary 1'~ have b~en counted by the clock
counter 732. After the ODETFF 1041 i8 reset, five more
C ~ 96
1n~
. . .
~L~1836~3~
binary l's of the start code are read from the encoder.
~; As previously noted, a binary 1 DATA IN (slope pulse) has
no effect on the ODETFF. Thus, it will remain reset until
; a binary O (positive pulse) is applied to its set terminal.
During the period of these last five binary l's of the start
code r the clock counter is inhibited from counting the read
cloc~ pulses because AND gate 1038 is disabled. When the
start code bit O is read from the selected encoder, the
positive DATA IN (slope pulse) will set the 03ETFF at the
time shown in Fig. 21A. The ODETFF now re-enables AND gate
1038 to re-apply the read clock pulses to the clock counter
732, The clock counter will continue to count until it
achieves a count of 4g as detected by the clock counter de-
code 736 on a conductor 1042 to reset the MTU after the
complete 36-bit meter data message has been stored in the MTU.
The reset operation will subsequently be described.
Reference i5 now made t~ Fig. l9A to a clock EN
~ flip-flop 1044. It will be noted that flip-flop 1044 receives
; a binary 1 signal on a conductor 738 at its set S input termi
nal whenever the clock counter decode 736 decodes a binary
count of O in the clock counter 732. Thust it can be seen
that the clock enable flip-flop 10~4 is set each time the
clock counter is reset to generate a binary 1 R ~ S clock
enable signal (read ana store) at its 1 output terminal on a
conductor 1046. The R ~ S clock enable signal is that sig-
nal which is utilized to enable the appropriate lo~ic to
allow the information from the selected meter encoder to be
shifted into a selected one of the previously mentioned
storage registers 1084 or 1058,
In Figs. 21A and 21~ the R & S clock enable sig-
nal is shown to be at a binary 1 at the start of the timing
sequence, because the clock ENFF 1044 is set upon MTU power
C - 97
~ .
21-ME-15
~8368g ~ ~ :
up initialization. The R & S clock enable signal is applied
to two AND gates 1048 of Fig. l9D and 1050 of Fig. l9C via
conductors 1046 and 1052, respectively. Reference is first i
made to AND gate 1048 of Fig. l9D. It will be noted that
that ~D gate is also receiving the 576Hz read clock signal
on conductor 996 as well as the R & S clock enable signal on -
conductor 1046 and the R & S EXT signal on conductor 930 from
the function code decode 922 of Fig. l9B. If the message
function code specifies that one of the auxiliary meter encod- `
ers 916 is to be read, the R & S EXT signal 930 will be a
binary 1, thus enabling AND gate 1048 to provide a READ EXT
CLOCK signal on a conductor 1054 to a multiplexer MPX 1056.
MPX 1056 is receiving as an address control input a transmit
external input signal XMIT EXT on a conductor 1058 from the
function code decode 922 in Fig. l9B. Since in the present
discussion, the function code specifies that a read and store
operation is being performed, the XMIT EXT signal on conduc-
tor 1058 is a binary 0, causing the MPX 1056 to switch to the -
position shown in Fig. l9D. Thus, the READ EXT CLOCK signal ;
on conductor 1054 is passed through MPX 1056 to a clock CL input
terminal of an Aux. 36-bit recirculating shift register 1058
via a conductor 1060.
If it is assumed at this time that one of the auxiliary
meters Al through AN has been addressed to transfer its encoder
data to the MTU, the data from the selected one of those meter ~ !
encoders will be routed through an MPX 1010 of Fig. l9D via
one of the conductors 1062 or 1064 into a data DA input terminal
of the register 1058 on a conductor 1066.
Referring to Figs. 21A and 21B, it can now be seen
how the timing relationships between each of the DATA IN
(slope pulses) and the read clock (576Hz) pulses are syn-
chronized to shift the 36-bit message from a selected one
C - 98 1~7 :
~ 33~
of the encoders into register 1058. It should also be
pointed out at this time, as shown in Fig. l9D, that the
XMIT EXT signal applied to MPX 1056 is also applied as a
binary 0 at this time to an A/B input terminal of register
1058 on a conductor 1068. Register 1058 has as its primary
input the auxiliary meter data at its DA terminal. Register
1058 is also provided with a re~irculating input fed back
from that registerls output line 1070 ~o a DB input terminal.
When the input signal ~o the A/B texminal is a binary 0, as
in the present discussion, the register 1058 serves as a
straight shift register with no recirculatin~ capabilities.
However, when the input signal on conductor 1068 to the A/B ~,
terminal is a binary 1, that register functions as a shift
register as well as a recircula~ing register whereby the
output data on conductor 1070 i~ recîrculated back into reg-
ister 1058 via the D/B terminal. The purpose of recirculat- i~
ing the data in register 1058 will be describea in connection
with the transmit mode of operation.
Reference i5 now made to Fig. l9C to AND gate 1050
now ~eceiving the R ~ S clock enable signal on conductol- 1052
in conjunction with the read clock 576Hz signal via conduc-
tor.s 99G and 1072. If the message function code speclfies
~hat the main meter encoder 920 is to be read, AND gate 1050
wi.ll be enabled by the R & S MAIN signal on conductor 928
~rom the function code decode 922 of Fig. l9B. ~ssuming AND
gate 1050 is enabled, a read main clock signal on a conduc-
tor 1074 is applied to the input of a multiplexer MPX 1076.
MPX 1076 is receiving as its control input a binary 0 XMIT
MAIN signal on a conductor 1078 ~rom the unction decode 922
of Fig. l9B, thus causing the MPX 1076 to be switched to the
position shown The read main clock is thus routed through
MPX 1076 into a demultiplexer DMPX 1080 v~a a conductor 1082.
C - ~
,,,, . 108
, ;,. . .. ` . .. .
21-ME-15
36139 ~
It will be noted that the DMPX 1080 reeeives the FCO' and
Fcl' signals on eonduetors 1014 and 1012, respeetively. As
previously explained in conneetion with the two multiplexers
MPX 1010 and 1004 of Fig. l9D, the binary configuration of
the FcO' and the Fcl' signals will e~fect the switch selection
of the DMPX 1080 to route the read main clock into the appro-
priate one of a plurality of 36-bit shift registers 1084,
designated 36-bit S/R A through D.
Registers 1084 operate in the same fashion as pre-
viously deseribed for the auxiliary 30-bit shift register 1058
of Fig. l9D. The read main clock signal from D~PX 1080 is
routed into an appropriate one of the clock CL input terminals
of registers 1084 via a one of a plurality of corresponding
conductors 1086 as selected by the DMPX 1080. Referring now
to Figs. l9C and l9D, it will be noted that the main meter
data on conductor 1002 is provided to the DA input terminal
of each of the registers 1084 via conductor 1088. It will be
noted in Fig. l9C that the XMIT MAIN signal, which is now a
binary 0 on conductor 1078, is applied to each of the registers
1084 via conductor 1090 to the A/B input terminal of each of
those registers to now control their straight forward shifting
as previously described in eonneetion with register 1058 of
Fig. l9D.
Reference is now made baek to Fig. l9A to the out-
put of the clock eounter deeode 736. Reference is also made
to Figs. 21A and 21B where it is shown that the clock counter
732 will eontinue to receive the read clock 576Hz input sig-
nals from MæX 728, eausing that eounter to eount one for eaeh
bit of the 36-bit message word from the encoder clocked in-to
the one of the selected 36-bit shift registers in Figs. l9C
and l9D. As shown in Fig. 21B, at a count of 48 (36 message
bits plus 12 start code bits) by the clock counter 732, the
109
C - 100
10836139
clock counter decode 736 generates a binary 1 48-count
output signal on a conductor 1042, which is applied to a
set S input terminal of a R & S RESET OS 1092 (read and
store reset one-shot), The R & S RESET OS 1092 now generates
S a binary 1 output signal R & S RESET on a conductor 1094,
which is slightly delayed by one-shot 1092 from the leading
edge of the 48-count pulse as shown in E'igs. l9A and 21Bo
The R & S RESET pulse is now applied from one-shot 1092 to
a reset R input terminal of the CLOCK ENFF 1044 via conduc-
tor 1096, resetting that flip-flop to thus cause a R ~ S
ChOCK ENABLE signal on conductors 1046 and 1052 to go to
binary 0 state to stop the shifting of meter data into the
recirculating registers 1084 and 1058. Additionally, the
R & S RESET signal is applied via conductors 1098 and 1099
to an OR gate 1024 of Fig. l9A. The R & S RESET signal is
passed through OR gate 1024 via conductor 1028 to set the
ten l's FF 1026 in preparation to receive another read
and store command from the SCU. ~he clock counter 732 is
also reset by the R & S RESET signal via OR gates 1032, 785
and MPX 770.
Reference is now made to Fig. l9B to OR gate 78~
also receiving the R & S RESET signal on conductor 1098 to
now enable that OR gate to reset the FSFF 792 via conductor
790O With the FSFF now reset, its 1 output terminal is a
binary 0 on conductor 794, removing the FUNC.STROBE signal
from the function code gating, thus causing all output sig-
nals from the function code decode to go to a binary 0.Also in Fig. l9D, the R & S RESET signal is applied from
conductor 1098 to a R reset input terminal of the MODE A
FF 926 via conductor 1100. Resetting the MODE A FF causes
the Mode A signal on conductor 934 to go to a binary 0 and
the mode A signal on conductor 636 to go to a binary 1 state
to place the MTU back into the receive mode in preparation to
receipt of another message from the SCU.
C - 101
~836~ 21-ME-15
.
This completes the read and store mode operational
description of the MTU. The MTU now contains the meter data
stored in one of the selected registers 1084 or 1058 ~rom a
selected one of the meter encoders 916 or 920 for subsequent
transfer to the SCU in response to a transmit command pre-
sented to the MTU from the SCU. The operation of the transmit
mode will now be described.
MTU Transmit Mode Operational Descriptio_
Reference is now made to Fig. 22, which is a legen-
dary drawing showing the inter-relationships of Figs. 22A
through 22D, the latter illustrating in detailed block dia-
gram form the logic in the MTU for executing the transmit
mode sequence. Like that logic previously described in con-
nection with Figs. 15 and 19, like logic elements in Figs. 22A
through 22D have like numbers to those corresponding numbers
in Figs. 15 and 19. To aid in the understanding of the opera-
tion of the transmit mode sequence, it is suggested that Figs.
22A through 22D be positioned as shown by Fig. 22. ~ig. 23
will also be referred to in the subsequent description. Fig. ;~
23 is a timing diagram showing the operational sequence of
the transmit mode.
Reference is now made to Fig. 22D. Let it now be
assumed that the MTU has just executed a read and store com-
mand which has caused meter data to be stored in one of the
selected registers 1084 or 1058 as previously specified by
the function code of the read and store command. The purpose
of the transmit command is to place the MTU in the transmit
mode to transmit the data from its selected one of registers
1087 or 1058 of Fig. 22D via the power lines to the MTU's
connected SCU.
Reference is now made to Figs. 22B and 23. Let
it now be assumed that the MTU has just gone through the
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1~83689 21-ME-15
message receive sequence and the FSFF 792 is set at T30
time as shown in Fig. 23 by the FUNC STROBE ENABLE signal
on conductor 802. As it will be recalled from the previous ~ ;
description, the function code and address portions of the
message are decoded at the time the funct:ion strobe on con-
ductor 794 is provided to the function code gating of Fig.
l9B. Referring to Figs. l9B and 23, there is shown now
being generated by the function code decode 922 an XMIT mode
signal on a conductor 1002 to OR gate 948 causing the mode B ~ ;
signal on conductor 950 to become a binary 1 and the mode B
signal on conductor 638 to become a binary 0. Fig. 23 shows
the mode B signal going to a binary 1 state at the tim~ oE
the function strobe. It will be noted at khis time that the
mode A signal is a binary 0. The binary states of the mode A
and mode B signals will be utilized during the present de-
scription to properly switch the various multiplexers (MPX's)
in the MTU to direct the clock pulses and data to the proper
logic elements. ;
The XMIT mode signal is also provided on a conduc-
tor 1004 to various logic elements to be discussed. Still
referring to the function code decode 922 of Fig. l9B, the
appropriate one of the XMIT MAIN or XMIT EXT lines will be ~ ~;
a binary 1 dependent upon the contents of the message func-
tion code. If the message is to be transmitted from one of
the main meter registers 1084, the external main signal on
conductor 1078 will be a binary 1. On the other hand, if the ;
meter data is to be transmitted from the auxiliary 36-bit
shift register 1058, the XMIT EXT line 1058 will be a binary
1. The manner in which these two signals control the shift-
ing of data out of those registers will subsequently be
described. The XMIT MAIN and XMIT EXT signals are generated
at the same time as the XMIT MODE signal shown in Fig. 23.
1 12
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Reference is now made to Fig, 22B to the function
strobe output on conductor 794, which is applied to a set S
input terminal of a start code one-shot 1104. One-shot 1104
now generates a binary 1 output pulse as shown on a conductor
1106. The signal on conductor 1106 is shown in that figure
as a START CODE S/R PRESET signal, appliled to preset inputs
of the flip-flops of a 3-bit start code shift register 1108.
The first flip-flop of register 1108 receives the start code
shift register preset signal on a PRl input terminal setting
that -fli.p-flop to a binary 1. The two remaining flip-flops
in register 1108 each receive the preset signal on correspond-
ing PR0 terminals, presetting those two flip-flops to binary
O's. As will subsequently be described, and as shown in Fig. 4,
the three sync blts to be transmitted with the MTU message are
001. These bits now exist in the start code shift register
1108 for subsequent ~ransfer to the SCU.
Reference is now made to a transmit clock register
1111 of Fig. 22C. That register is now reset to all binary 0's
on a conductox 1112 by a binary 1 output pulse from the 1 out~
put termi~lal ofa transmit reset one-shot 111~. One-shot 1114
receives the XMIT MODE signal on conductor 1116 to reset the
clock register 1111 at the leading edge of the XMIT mode sig-
nal at the time shown in Fig. 23. Resetting register 1111 now
synchronizes that register to begin counting the 120Hz pulses :
applied to the register on conductor 686. Register 1111 func-
tions in the same manner as previously described for the clock
sync register 674 of Fig. 15A during the receive mode sequence
to shift a binary 1 through the four stages of that register.
The 0 output terminals of register 1111 are connected to an
AND gate 118 via a plurality of conductor~ 1120 to control the
setting and resetting.of the first stage of the reg.ister via
conductors 1122, 1124 and an inverter 1126.
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1 1 3
.
. . . .. ~ .. .. . ..
8361~3~
: .
; It will be noted that the 0 output terminals of
the second and third stages of the transmit clock regi~ter
1111 are provided as input~ to an AND gate 1128 in conjunc-
tion with the now binary 1 XMIT MODE signal on conductor
1004. The inputs on conductors 1120 to AND gate 1128 gen-
erate a transmit (XMIT) clock signal at a 30Hz rate on a
conductor 1130. The genexation of the XMIT clock signal is
shown in Fig. 23. AND gate 1128 generates one 30Hz XMIT
clock pulse in response to each four 120Hz input clock pulses
to register 1111 on conductor 686~ Referring to Figs. 22C
and 23, the first XMIT clock signal generated by ~ND gate 1128
is applied via conductors 1130 and 1132 to the input of
MPX 728. MPX 728 is now addxessed by the m~ and mode B
signals on conductors 636 and 638 to switch MPX 728 to the
position shown. The binary states of the mode A and mode B
signals are shown in Fig. 23. Thc first transmit clock sig-
nal is now passed through MPX 728 to the trigger T input
terminal of clock collnter 732, causing that counter to count
to a count of one. The output of clock counter 732 is now
decoded by clock counter decode 736 to generate a binary 1
; output signal representative of the count of 01 on a conduc-
tor 1134. The 01 count,signal is applied to the set S input
terminal of three ~lip-flops TXDATAFF 1136, PARITY CLOCKFF
1138 and STARTCODEFF 1140, placing each of those flip-flops
in a set state. The 1 output terminal of each of these flip
flops is applied as an enable input to each of three corre-
sponding AND gates 1142, 1144 and 1146. Further, each of
' AND gates 1142, 1144 and 1146 is now receiving the trans-
mit clock signal from AND gate 1128 via conductors 1130 and
1148. As can be seen in Fig, ~3, three clock signals are
generated by the~e AND gate~ de~ignated XMIT S/R cloek,
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.. .
~83689
PARITY XMIT CLOCK, and START CODE S/R CLOCK. The start
code shift register clock signal i~ generated by AND gate
1146 and applied to a CL clock inp~t te~inal of the start
` code shift register 1108 via a conductor 1150. The parity
transmit clock signal is generated by AND gate 1144 on a
conductor 1152 and applied to the clock CLK input terminal
of the parity check generate clrcui~ 658 via conductor 762 ~`
and MPX 660. It should be noted at thi~ time that the XMIT
MODE s~gnal on conductor 1004 applied to MPX 660 is now a
binary 1 causing MPX 660 to switch to the position shown.
Referring now back to Fig. 22A, AND gate 1142
now provides the XMIT S~R CLOCK on a conductor 1154 to the
input of MPX 1076 and MPX 1056 of ~ig. 22D. The MPX 1076
of Fig. 22D receives the XMIT MAIN signal on conductor 1078 ~ !
from the function code decode 922 of Fig. l9B. If the present
command specifies that the meter data is to be transEerred
from one of the main meter xegisters 1084, the MPX 1076 switch
will be in the bottom position as shown by the dotted line
within the MPX 1076. However, if the XMIT MAIN signal is
20 a binary 0, the switch will be in the up position not allow-
ing the XMIT S/R CLOCK to be passed through MPX 1076. As-
suming that the XMIT MA~N signal is a binary 1, the ~MIT S/R
CLOCK will be passed through MPX 1076 into MPX 1080 via con- -
ductor 1082. MPX 1080 will now have its switch position
selected in accordance with the binary states o~ the function
code signals FC0' and Fcl' from the output of the function
code gating circuit of Fig. l9B. Depending upon the binary
configuration of the FC0' and Fcl' signals, the XMIT S/R
CLOCK signal will be applied to the appropriate one of the
; 30 conductors 1086 to the CL terminal o~ the selected one of
~he registers ~084. It should be noted at this time that
the XMIT MAIN binary 1 signal on conductor 107B is also
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: ' '; ' '
. ~ , , . . ~ . :, .. .
21-ME-15
1~336~3~
applied via a conductor 1156 as a recirculate on XMIT
signal to the A/B inputs of each of the registers 1084.
The application of the binary 1 signal on conductor 1156
now allows the 36-bit meter data message in the selected
one of the registers 1084 to be serially shifted out to an
MPX 1158 via the selected shift register's corresponding
output conductor 1160. Further, the binary 1 signal applied
to the A/B input terminals of the registers allows the select-
ed register to be recirculated by having the output data on
its corresponding conductor 1160 shifted back into the
register via the DB terminal. Recirculating the meter data
in the selected register preserves that data in the event the
shift register contents are needed at a later time. The data
in registers 1084 and 1058 is lost only if replaced during a
read and store operation. It should also be pointed out at
this time that no meter data on conductor 1088 is shifted
into the selected register.
Still referring to Fig. 22D, it will be noted that
MPX 1158 also receives as address control input signals the
FcO' and Fcl' signals from the function code gating of Fig.
19~ to select the output of the appropriate one of the regis-
ters 1084. The output fr~m the selected register is trans-
ferred through MPX 1158 into an MPX 1162. MPX 1162 is re-
ceiving the XMIT EXT signal on conductor 1058 from the function
code decode 922 of Fig. l9B. If the message is to be trans-
mitted to the SCU from one of the main meter registers 1084,
the XMIT EXT signal will be a binary 0, placing the MPX 1162
switch in the up position, allowing the data to be transferred
from the selected register through MPX 1162 on to a conductor
1164.
Reference is now made to the multiplexer 1056 of
Fig. 22D receiving the XMIT S/R CLOCK signal on conductor 1154.
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21-ME-15
~L~836~9
If the function code of the transmit command specifies that
the message is to be transmitted to the SCU from the aux-
iliary register 1058, the XMIT EXT signal on conductor 1058
will select MPX 1056 to place its switch in the down position
to allow the XMIT S/R CLOCK to pass through MPX 1056 into the ;
CL terminal of register 1058. Register 1058 also receives
the XMIT EXT binary 1 signal on conductor 1068 at its A/s
input terminal to control its circular shifting. The message
from register 1058 is transmitted out as XMIT DATA on a con- ~ ;
ductor 1070 to MPX 1162, which would now be selected by the ,
XMIT EXT signal to have the switch in the down position to
~i . .
pass the data on to conductor 1164. It can now be seen how
the MTU, through its function code and multiplexing means
(MPXIs), effects the selection of the plurality of registers
shown in Fig. 22D to transmit previously stored meter data to
the SCU.
Still referring to Fig. 22D, the output data from
the selected one of the registers 1084 or 1058 on conductor
1164 is provided through MPX 660 of Fig. 22B to the data in
terminal of the parity check generate circuit 658. The MPX
; switches are in the down position because of the binary 1
XMIT MODE signal applied to MPX 660 on conductor 1004. The
message from the selected one of the registers is allowed
to be clocked through the parity check generate circuit 658
in response to the PARITY XMIT CLOCK on conductor 1152 now
applied to the parity check generate circuit via MPX 660 and
conductor 762.
Reference i5 now made back to Fig. 22A to the 1
output terminal of the TXDATAFF 1136. That flip-flop, which
is now set, is providing a binary 1 TX DATA XMIT signal to
the REC/XMIT CONT input terminal of the parity check generate
circuit of Fig. 23B via conductors 1166, 1168 and MPX 660.
1 1 7
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836~3~9 2~ 5
This binary 1 signal enables the parity check generate
circuit 658 to allow the PARITY XMIT DATA on conductor 1164
to be passed through that circuit out to a data line 1170.
The message data from the parity check generate circuit 658
is provided via conductor 1170 to a data D input terminal
of the start code shift register 1108. It will be noted that
the start code shift register 1108 is now receiving the
START CODE S/R CLOCK pulses on conductor 1150 from now en-
abled AND gate 1146 of Fig. 22A. By referring to Fig. 23,
it can be seen that the XMIT S/R CLOCK,the XMIT PARITY CLOCK
and the start code S/R CLOCI~ pulses are all generated in
synchronism to transfer the message from the selected one
of the 36-bit shift registers in Fig. 22D out through the
parity check generate circuit of Fig. 22B and into the start
code shift register 1108.
It will be recalled at the beginning of this dis-
cussion that the start code shift register 1108 was set to
a 001 start bit configuration by the start code S/R PRESET
signal from the start code one-shot 1104. in a practical
sense, the start code shift register 1108 is a 3-bit ex-
tension of the selected one of the 36-bit shift registers
1084 or 1058. Thus, since the start code shift regis-ter and
the selected one of the registers 1084 or 1058 are synchro-
nously shifted, the start code sync bits precede the 36-
message bits as the message is shifted through the start
code shift register.
Referring now to Fig. 22B, the three sync bits are
shifted out of the start code shift register 1108, followed
by the 36-message bits from -the selected one of the meter
data registers onto a conductor 1172 feeding the data mes-
sage to a transmitter 1174. Transmitter 1174 is also re-
ceiving the RF carrier input signal fl via a conductor 1178
1 1 8
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~ . . .
1~1836~9
21-ME-15
from the output of a DMPX 624 of Fig. 22C. The mode A
and mode B signals applied to DMPX 624 and MæX 618 are now
binary l's, causing each of those units to select their
switches in the position shown. As a result, the fl carrier
output signal from transmit oscillator 640 is passed through
MPX 618, and DMPX 624 and on to the transmitter 1174 where
that carrier is modulated by the binary 1 and 0 data mes-
sage output from the start code shift register 1108. The
message is now passed through transmitter 1174 on to the
power line 18 via conductor 1176 and the power line coupler
600 for receipt by the SCU.
Reference is now made back to Fig. 22A to the
TXDATAFF 1136. That flip-flop receives a binary 1 reset
signal via a conductor 1178 when the clock counter decode 736
detects a bit count of 36 in the clock counter 732. At a
count of 36 t~he last bit of the 36-bit message is shifted
into the first stage of the start code shift register. It is
at this time that the TXDATAFF 1136 is reset, thus providing
a binary 0 signal to AND gate 1142 preventing the further
generation of XMIT S/R CLOCK signals and simultaneously
; applying a binary 0 signal via conductors 1168, 1166 and
MPX 660 to the REC/XMIT CONT terminal of the parity check
generate circuit to inhibit the further transfer of the mes-
sage to the start code shift register.
Referring still to Figs. 22A and 23, it can be
seen that the XMIT PARITY CLOCK signal continues to be gen-
erated after the XMIT S/R CLOCK signal is terminated. The
purpose of this is due to the fact that the MTU must generate
the proper parity for the 36 message bits previously trans-
ferred through the parity check generate circuit 658. Re-
ferring to Fig. 22A and 23, -the PARITY CLOCKFF 1138 is reset
at a clock count of 42 (36 message bits plus 6 parity bits).
1 1 9
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21-ME-15
~ 3~89
When flip-flop 1139 resets, AND gate 1144 is disabled, thus
inhibiting the further generation of the PARITY XMIT CLOCK
signals to the parity check generate circuit.
Reference is made now to Fig. 22B. In order to
transmit the entire message (last three parity bits) out of
the MTU onto the transmission lines 18, it is necessary to
generate three additional start code shift register clock
signals to pass those three bits out of the start code shift
register 1108. The generation of these three additional
clock bits is shown in Fig. 23. The manner in which these
three clock bits are generated is shown by the logic in
Fig. 22A. Referring to the output of the clock counter decode
736, at a count of 45, as decoded by the clock counter decode
736 from the clock counter 732, a binary 1 output signal resets
the start code FF 1140 via a conductor 1180. When the start
code FF 1140 resets, it disables AND gate 1146 and inhibits
the further generation of the STATE CODE S/R CLOCK signals on
conductor 1150 to the start code shift register 1108. At a
count of 45, the last message bit of meter data is shifted
out of the transmitter 1174 onto the power transmission lines
18.
Referring back to Fig. 22A, the clock counter 732
now counts one more count to a count of 46 as detected by
clock counter decode 736. The clock counter decode now
generates a binary 1 XMIT RESET signal on a conductor 1182
at the time shown in Fig. 23. The XMIT RESET signal on con-
ductor 1182 is simultaneously applied to the MPX 770 to reset
the clock counter 732 via OR gate 785 and to the reset input
terminal of the parity check generate circuit 658 of Fig. 22B via
MPX 660 to reset that circuit in preparation to receipt of
another message from the SCU. The XMIT RESET signal is also
applied via conductors 1182 and 1184 to OR gate 788 to in
1 2 D
C - 111
836~9
turn reset the FSFF 792. Resetting the FSFF 792 causes
the function strobe signal on conductor 794 to go to a
binary 0 state as shown in Fig. 23. The function strobe
signal now going to a binary 0 disables the function code
gating in Fig. l9B to thus cause the transmit mode and
mode B signals on conductors 1004 and 950 to each go to a
binary 0 as shown in Fig. 23.
The MTU is now in the standby receive mode in
preparation to receipt of another message from the SCU as
described in the receive mode operation.
While the principles of the invention have now been
made clear in a preferred embodiment, there will be immediate-
ly obvious to those skilled in the art many modifications of
structure, arrangement, proportions, the elements, materials
and components used in the practice of the invention and
otherwise, which are particularly adapted for specific en-
vironments and operating requirements without departing from
those principles. The appended claims are, therefore, in-
tended to cover and embxace such modifications within the
limits only of the true scope of the invention.
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