Note: Descriptions are shown in the official language in which they were submitted.
~0~682t7
Heretofore measurements of units representative of
the amounts of power consumed in 3-wire single phase systems
have generally been performed by complicated, and expensive
instruments. By nature of their being mounted externally to
habitations, and their having calibrations not easily under-
stood by lay persons, however, they have never been instrumen-
; tal in allowing such persons to satisfactorily evaluate and
hence, effectively control their usage of electrical energy.
Recently, digital electronic power and energy meters
have been devised but their complexity precludes to an extentgreater than that of the present invention their household use
by lay persons, not only in that they are necessarily expensive
but also that they are difficult to install due to their having
a plurality of lines connecting the sensor transformers to the
body of the meter.
It is the object of the present invention therefore
to provide a simple and straightforward conversion from a sample
of the current flowing in a 3-wire single phase power system to
a string of digital pulses the frequency of which is function-
ally related to said sample.
It is a further object of the invention to provide thecount of these pulses in a ~orm which the lay person can readily
appreciate, either in electrical units or in monetary ones.
It is a further object of the invention to utilize
an electronic clock integrated circuit to provide not only a
time display function which may be useful in conjunction with
the energy monitor function, but also to provide all timebase,
counter gating and resetting, and display multiplexing functions,
-2-
' '
1~682~7
thereby abrogating the requirement to provide these functions
in a separate embodiment.
It is a ~till further object of the invention to pro-
vide an embodiment whereby means is provided that facilitates
interconnection between sensor transformers for a 3-wire system
and monitor by only one electrical conductor.
DRAWI~GS
Figure 1 is a block diagram showing the interconnection
between various components comprising apparatus for metering cur-
rent in a 3-wire single phase system.
Figure 2 illustrates in detail the elements comprising
the analog to pulse conversion circuits, the block numbered 34
in Fi~. 1.
Figure 3 shows input and output lines required of the
digital clock integrated circuit and illustrates circuit to con-
vert signal fr~m an activated touchplate to a signal which may
be recognized as valid by the integrated clock circuit for the
purpose of setting time function.
Figure 4 illustrates in detail the elements comprising
the block numbered 24 in Fig. 1 which route counter decades to
appropriate display digits.
DESCRIPTION OF THE PREFERRED EMBODIME~T
The invention measures current in 2 active wires of a
3-wire system and thereby arrives at a representation of the
energy being dissipated in the system during a measurement per-
iod T. Referring to Fig. 1, current flowing in wire 1 to
ground through load resistor 5 is measured by current trans-
former 3 and likewise current flowing in wire 2 through load
~0~3~82~
resistor 6 is measured by current transformer 4. In addition,
current flowing through load resistor 7 i8 measured by both cur-
rent transformers 3 and 4. Thus the current sample is repre-
sented as iS + i6 + 2i7. Since in this application the volt-
ages of the system are not considered to drop significantly dueto loads, i.e., the source impedance is minimal, energy dissi-
pated by the system in the measurement period T can be seen
thusly:
E = k ~Vsis ~ V6i6 + V5i7 + V6i7)T
= kV(is + i6 + 2i7)T,
since the energy dissipated in load resistor 7 is ki7(V5 + V6)
and V5 = V6. V and T are fixed constants, and k is a fixed
one, so the variable is the measured value.
Current transformers 3 and 4 are of low impedance, but
they feed a high impedance 101 in Figure 2, through line 10.
If these sensor transformers fed a matched impedance they would
serve as current sources, and their signals would not have been
additive. ~ mismatched impedance however makes them voltage
sources described by Zctii + ZCt2i = R101 i + Vbi Due to
the linear nature of the resistor 101, current through it into
non-inverting input of operational amplifier 104 is proportional
to instantaneous power flowing through the system in one phase
of the signal cycle. Variable resistor 102 serves to set out-
put of ampli~ier 104 and diode 106 to just the voltage at which
transistor 110 starts to conduct, and variable resistor 105
serves as gain adjusting means by which the present invention
may display various engineering or monetary quanta. Capacitor
107, discharged by resistor 108 is charged by diode 106 to ap-
--4--
;8Z7
proximately the peak level of the output of amplifier 104.That the present in~ention uses a peak representation rather
than an RMS value is not of significance here since the rela-
tionship between the two values is a constant. ~lso, the period
T is longer than the period between peaks by a large factor.
Current through resistor 109 is proportional to voltage across
capacitor 107.
When current through resistor 111 to amplifier 114
falls below the bias level required to keep its output low, due
to the linear discharge of capacitor 120 through transistor
110, amplifier 114 switches output state from low to high to
fill capacitor 120 very quickly so that current through resis-
tor 111 again forces the output of amplifier 114 low. ~esistor
113 provides hysteresis to amplifier 114. Since in charging
capacitor 120 the output of amplifier 114 may reach a level in-
sufficient to drive a pulse counter, Schmidt trigger comprising
; resistors 115 ~d 117 and amplifier 116 serves as a level shift-
er and outputs a suitable pulse via line 33.
Power transformer 28, which feeds rectifier 29 and
filter capacitor 30, also feeds amplifier 16 through lines 32
and 36 and resistors 118 and 119 to serve as a timing signal
wave source to drive the timing input 17 of clock circuit 15.
Figure 3 shows the inputs and outputs required of a
digital integrated circuit clock 15, such that it may be used
for the functions described in Paragraph 3 of BRIEF ST~TEMENT
OF THE INVENTION. These are limited to fourteen lines, includ-
ing 2 power supply lines 31 and 45, 2 timesetting lines 42 and
, 43, a timing input 17, a 1 pulse per second output 41, four
: - - - :.: -: ,.
10~682~7
coded segment output lines 18, and four digit output lines 46,
21, 22 and 23. Two identical networks comprising a CMOS inver-
ter 348, resistors 345 and 346, capacitor 347 and touchplate 344
replace a mechanical switch for the purpose of providing clock
5 circuit 15 with timesetting signals on lines 42 and 43. Pullup
resistor 345 maintains a high level on input of inverter 348,
and a protective network comprising resistor 346 and capacitor
347 absorbs static transients that may be induced as a finger at
a different floating potential resistively brings input of said
inverter low through touchplate 344.
Figure 4 is a detailed amplification of the display
multiplex decoding logic block 24 in Figure 1, and comprises in
the main part three identical logic bloc~s 201, 205 and 206 each
of which in turn comprise 2 identical quadruple "and" gate blocks
202 and 203 and a quadruple "or" block 204 such that a high
signal on control lines 22 and 23, 21 and 212, and 13 and 213
may cause data appearing on pluralities of input lines 39 and
40, 38 and 208, and 18 and 20g to appear on pluralities of lines
208, 209 and 210, respectively. "Or" gate 214 permits data on
either lines 39 or 40 to be present on lines 209 whenever 22 or
23 go to a high level. When a control signal on line 13 from
counter 14 in Fig. 1 causes the data on plurality of conductors
18 to appear on plurality of conductors 210 the readout 26 dis-
plays time of day; and counter bank 12 is enabled to count pulses
from network 34 after having been reset by differentiator 11.
I When said control line 13 shifts to the opposite control level,
data on plurality of conductors 209 appears on the plurality of
conductors 210, counter bank 12 is frozen at its last count, and
1~868Z!7
as each decade of counter bank 12 is coupled to multiplex de-
coding block 24 by pluralities of lines 38, 39 and 40, this
count is stepped to each readout digit by signals on lines 21,
22 and 23 as these same lines illuminate display digits 26 syn-
chronously and sequentially through a plurality of digit driv-
ers 27. Inverter 215 permits data on pluralities of lines 18
or 209 to be present at the output of block 206. Seven segment
decoder 207 translates data on plurality of lines 210 to segment
drivers 25, by pluralities of lines 20.
--7--
