Note: Descriptions are shown in the official language in which they were submitted.
Field of the Invention
The present invention relates to filters in general
and particularly to a class of filter known as sampled analog
filters. More particularly still, this invention relates to
first order switched integrators.
Background and Summary of the Inven-tion
In a class of filters known as state variable filters
both positive and negative integrator units are required. An
integrator unit usually consists of an operational amplifier
with a capacitor connected between its output and its inverting
input with the input signal being applied via a resistor to the
inverting input; the non-inverting input being grounded. An
advance in the art o-f realizing said integrator units has been
recently made which replaces the resistor with a switched
capacitor, thus making the integrator, and filters utilizing it,
more amenable to large scale integration manufacturing. This
advance is disclosed in a recent paper entitled: "Sampled Analog
Filtering Using Switched Capacitors As Resistor Equivalents" by
J.Terry Caves, Miles A. Copeland, Chowdhury F. Rahim and
Stanley D. Rosenbaum, published in the IEEE Journal of Solid State
Circuits, Vol. SC-129 No. 6, December 1977.
A second order switched capacitor filter utilizing
positive and negative integrator units is disclosed in a paper
by Bedrich J. Hosticka, Robert W. Brodersen and Paul R. Gray,
in the same publication, supra, at page 600. In switching a
capacitor to yield the equivalent of a resistor MOS type
transistors are utilized as switches, while the capacitor itself
is also realized in MOS technology. Since only the resistor
between the integrating capacitor and the switched capacitor
matters, the capacitors can be made quite small in value and size,
which result lends itself well to large scale integration.
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For reasons that will be better understood
when describing a preferrecl embodiment of the present invention
in detail, it is desirable to have positive and negative integrating
units that have their transfer functions insensitive to stray
capacitance. In addition, due to finite switching frequencies of
the switched capacitors, the transfer function of an integrator
contains a finite real part in the denominator which limits the
Q-factor of the unit and causes an undesirable phase shift in a
filter~ It is desirable that the transfer function of both the
positive and negative integrators, apart from the algebraic sign,
be identical but for the sign of the real part in the denominator,
in which case the phase shifts of positive and negative integrators
will cancel to a first order approximation in a composite filter.
Of course, this advantage diminishes in importance the higher
the switching frequency relative to the upper cut-off frequency
of the filter.
The present invention provides a novel negative
integrator unit identical in circuit topology to the prior art
positive integrator unit, but when in actual operation functioning
differently - by the manner in which the switched capacitor is ;
operated - to provide a negative instead of positive integrating
function. Practical and improved second and higher order
~ilters are now possible.
Thus, according to the present invention there is
provided an integrator circuit of the type having an operational
ampli~ier with an ;ntegrating capacitor in a feedback loop from
its output to its input and having a switched capacitor as
equivalent of a resistor connection between a signal source and
said input, characterized in that said switched capacitor is
alternately discharged and connected between said signal source
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and said input with a predetermined frequency.
Brief Description of the Drawings
A preferred embodiment of the present invention
will now be described in conjunction with the accompanying drawings
in which:
Figure l(a) is a prior art circuit schema~ic for
a negative integrator unit;
Figure l(b) is a prior art circuit schematic for
a positive integrator unit;
Figure 2 is a circuit schematic for a negative :-
integrator unit according to the present invention;
Figure 3(a) is an explanatory schematic for the ..
c;rcuit of Figure l(b) when ~1 clock is on and ~2 clock is off;
Figure 3(b) is an explanatory schematic for the
circuit of Figure 2 when ~1 clock is on and ~2 clock is off, -~
Figure 4(a) is an explanatory schematic for the
circuit of Figure l(b) when ~1 clock is off and ~2 clock is on;
: Figure 4(b) is an explanatory schematic for thecircuit of Figure 2 when ~1 clock is on and ~2 clock is on; and
Figure 5 is a circuit schematic of a second order
filter utilizing the circuit of Figure l(b) and the circuit of
Figure 2 according to the present invention. ~ .
: Description of the Preferred Embodiments
With reference to Figures l(a) and l(b) of the
drawing a brief description of the prior art will be given leading
to a better understanding of the preferred embodiments of the
present invention. Figure l(a) shows a negative integrator unit
utilizing the switched capacitor technique. The transfer function - .~ -.-
of a negative integrator is generally given byo
VO( ) 1 : .
V j S T
_ 3 - : :
when S = j~, and I is the time constant, in the case of the
circuit of Figure l(a) this being C2 multiplied by the resistor
equivalent value. Actually, however, due to the finite switching
frequencies the transfer function of the switched capacitor
integrator of Figure l(a) is~
C2 "
VO C
V; j sin(~T) ~ cos(~T) - 1
where T is the period of the switching frequency of two clocks ~1
and ~2' which two clocks are 180 out-of-phase so that when MOS
transistor Tl is on, MOS transistor T2 is off, and vice versa.
is, of course, the signal frequency.
The circuit of Figure l(b) is that of a positive
integrator unit. Its transfer function is identical to that
given immediately above except for the total algebraic sign.
Hence, C2
VO Cl :`'
Vj j sin(wT) + cos(~T) - 1
The existence of a real term in the above two
transfer functions means an undesirable phase-shift, or, to express
it differently, it means a finite Q-factor. The Q-factor is
defined as the quotient of the imaginary part by the real part
of the inverse transfer function vi(~). As the switching frequency
increases, the Q-factor also increases. For typical applications,
however, at a switching frequency of 128 KHz and a filter cut-off
(or signal) frequency of 3 KHz, the Q-factor is around -13.5 for
both circuits of Figures l(a) and l(b). Had the Q-factor of the
one circuit had the opposite sign o~ the other, a first order
cancellation of the undesirable phase shift effects would occur -~
when using both circuits in a two integrator loop of a higher
order "state variable" or "signal flow graph" filter.
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It is, therefore, desirable to use a negative
integrator having a positive Q-factor equal in magnitude to that
of the circuit of Figure l(b). Moreover, it is desirable to
use an integrator where the parasitic capacitances associated
with the drain and source electrodes of the MOS transistors
do not affect the transfer function by disturbing the ratios of
the capacitors Cl and C2. This is the case in the circuit of
Figure l(b) but not in that of Figure l(a) due to the non-symmetrical
nature oF the connection of Cl in the latter circuit.
The integrator of Figure 2, being the preferred
embodiment of the present invention, is identical with the prior
art circuit o~ Figure l(b) when not in operation. It comprises
an operational amplifier A having an inverting input, a grounded
non-inverting input and an output VO. The output VO is connected
; to the inverting input by a capacitor C2. The input signal V
being applied to the integrator via the series connection of an -
MOS transistor Tlo, a capacitor Cl and another MOS transistor T'20
which is connected to the inverting input of the amplifier A.
The junction between the transistor Tlo and the capacitor Cl is
; 20 connected to ground via an MOS transistor T20. The junction
between the capacitor Cl and the transistor T20 is connected to
ground by an MOS transistor T'lo. In operation the gate of the
transistor T~lo is driven by the ~1 clock, while the gate of the
trans~stor T'20 is driven by the ~2 clock; however, the gate of
the transistor Tlo is driven by the ~2 clock and the gate of
the transistor T20 is driven by the ~1 clock, in contradistinction
to the operation of the prior art circuit of Figure l(b). As will
become immediately clear below, this simple exchange of the
clocks ~1 and ~2 to drive the gates o~ the transistors Tlo and T20 `
has further reaching consequences.
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In Figures 3 and 4 we consider the prior art circuit
oF Figure l(b) and the circuit of the present invention in
Figure 2 under effective operating conditions, where the MOS
transistors have been eliminated for clarity. Figure 3 shows
~he effective circuits under the condition but the ~1 clock is
on and the ~2 clock is o~f. In Figure 3(a) -the prior art circuit-
the left plate of the capacitor Cl is connected to the input V
(actually via the transistor Tlo driven by ~1) and the right
plate is connected to ground (actually via the transistor T'lo
driven also by ~1) The inverting input of the amplifier A is
isolated from the left-hand portion of the circuit since the
transistor T'20 - driven by ~2' which is off - is nut conducting.
In Figure 3(b), the effective circuit of the present invention,
the Vj is disconnected From the circuit (since Tlo is driven
by ~2 in Figure 2, and ~2 is off), the capacitor Cl is shorted
to discharge via T20 and T'lo (both driven by ~1' which is on)
connecting it on both sides to signal ground, while the inverting
input of the amplifier A is disconnected from the left-hand portion
of the circuit of Figure 2. Clearly, the effective circuits shown
in Figure 3(a) and in Figure 3(b) are different. The same applies
to the effective circuits shown in Figure ~(a) and in Figure 4(b),
for the other operating condition when ~1 is off (and its associated
transistors: Tlo and T'lo in Figure l(b), and T20 and T'lo in
Figure 2) and ~2 is on ~and its associated transistors: T20 and T'20
in Figure l(b) and Tlo and T'20 in Figure 2~. Thus, in e;ther of
the alternate operation conditions the effective circuit of the
prior art and the effective circuit of the present invention are
structurally different. Hence there is also a difFerence in their
transFer functions. The transfer function of the circuit of
Figure 2 is as follows:
:: . . . . . .
~LO~
V _ C2
o =
i j sin(~T) - ~cos(~T) - 1~
Apart from the total algebraic sign, which denotes
a negative integrator, the real part of the denominator, while
identical in magnitude, has the opposite sign to that in the transfer
function associated with the integrator of Figure l(b) and given
herein above. The circuit of Figure 2 has the advantage of having
the same topology as that of Figure l(b)~ unlike the circuit o~
Figure l(a)i and also unlike -the circuit of Figure l(a) its
trans~er function has a real part in the denominator having the
opposite sign, resulting in the advantages mentioned before.
An intuitive understanding of why the prior art
circuit oF Figure l(b) is a positive integrator and the circuit
of Figure 2 is a negative integrator may be gained by considering
the manner in which the capacitor Cl (in both circuits) is
switched (connected) in Figures 3 and 4. Assume a positive
input at Vj in Figure 3(a), the left plate of Cl is then
positive with relation to ground. In Figure 4(a) the left plate
of Cl is connected to ground, so that the right plate of Cl becomes
negative with relation to ground. Hence, the signal applied to
the inverting input of the amplifier A - i.e. that held in the
capacitor Cl - is the inverted sampled input signal, and the
result of two inversions is a positive operation. In Figure 3(b)
and 4(b), however, the input signal is applied to the inverting
input of the amplifier A uninverted and a negative operation results,
as in the circuit of Figure l(a) where the upper plate o~ the
capacitor is switched between the input Vj and the inverting
input of the amplifier A.
3Q When in operation, therefore, in the circuit of
Figure 2, as clearly demonstrated through Figures 3(b) and 4(b),
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the switching capacitor Cl is alternately discharged (Fig.3(b))
and connected between the input Vj and the input of the ampli~ier A
with the frequency of switching of the clocks ~1 and ~2. ~1 and ~2'
of course, have the same frequency but are out of phase by 180.
They are preferably square-wave functions with a duty cycle of
less than 50%.
Figure 5 of the drawings shows a circuit schematic
of a second order biquad filter utilizing the circuits of
Figure l(b) and 2. The transfer function of the filter of
Figure 5 is given by:
Vo - K (1 - K K3 sin ( 2-))
1 + j 4 5; ( ) 2(2 + 4 sin ( 2)
In Figure 5, the capacitors denoted KoCl, KlCl,
K2C2, K3C2 and K4C2 are chosen such that the real constants
Ko~ Kl, K3 and K~ cause the above transfer function to have a
value as close as possible to
V' = Z 2
~oQ ~o2 ..
where G, ~z, ~O and Q are given arbitrary constants. If the
constant ~z = ~, then the circuit of Figure 5 approximating the
transfer function V'j would not contain the capacitor K3C2. It is
noted that the circuit of Figure 5 is the result of replacing
integrators in the corresponding state variable or signal flow
graph filter by the integrators of Figure l(b) and Figure 2, as .- ~
may be ascertained by inspection of the circuit in Figure 5. .-~ :
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