Note: Descriptions are shown in the official language in which they were submitted.
8 B~C~GROU~ OF THE I`rV~:'rLO;I
9 r~lere are man~ app.lications in the art requiri-.~ lar~er currents
and vol~ages than indi-~idual cells can pro~ e. Sinc~ p,.otoelectric con-
ll verters provide an output of only 0.5 to l.O volts it is often n~CesSar~J
1~ to connect sevPral converters in s~ri~s in order to get ~ ~esire(l outp~t
13 voltago. Ihe individual converters, ho-~e~er, lcse efEic_~ncy as the
1~ te~perature rises so that i~ is also desirable to bond each converter to
a large heat sink which is usually formed cf an electrirally conducting
16 material but each cell must remain electrically isolated Lhere~rom.
17 The art of building devices for lar~er voltag~s thu~ h~ratofore has
18 involved co~plex assembly and material problems. An e~2~ple of ~uch an
19 assembly is sho~n in U. S. Patent ~o. 3,833,425 wh~rein sisc.ete con-
verters are assembled with discrete electrical isolators and the combina-
21 tion is bonded to a large metal substrate for te~peratu.~ contrcl.
22 REFERENCE TO RELATED APPLICATION
23 In~application Serial No.~ ~75~IBM Docket Y09-76-024) filed
24 ~ p~ ~2~ 7~, there is disclosed a technique wherein discrete photo-
electric converters are formed on an electrically insulating material,
26 which serves as both an electrical 3solator and a thermal conductor.
YOg-76-049 -1-
:~131~
1 SUM~ Y OF T~IE II~VENTIOr~l
2 Photoelectrical conversion cell a~ra~s may be fabricated using
3 planar integrated circuit technology, i.e., epitaxial growth, lithographic
4 and masking techniques, diffusion and alloying steps on a substrate of
electrically insulating material to provide an array in which optimum
6 control of heat conductivity, electrical isolation, cell combination
7 flexibility and cell electrode spacing are achieved.
8 DESCRIPTION OF THE DRAWINGS
9 FIG. 1 is a view of an integrated photoelectric conversion
cell array.
11 FIG. 2 is a detailed view showing the vertical aspects of the
12 photoelectrical conversion cell.
13 FIG. 3 is a view showing the contact and isolation of the
14 photoelectrical conversion cell.
DETAILED DESCRIPTION
16 In accordance with the invention the cells are fabricated in
17 situ on a broad area substrate by such techniques, at this state of the
18 art, of masking, photochemical exposure, oxidation and/or nitridation
19 to control the precise horizontal introduction by diffusion or ion im-
plantation fcr precise vertical control of conductivity type determining
21 i~purities, of isolation between cells, of positioning and depth of
22 penetration of contacts to the cells and of electrical configuration of
23 the array by vapor deposited metallurgy. The broad area substrate is
24 equipped with a region of insulating material having electrical resist-
ivity properties sui~able for electrical isolation and having a thickness
26 dimension small enough to permit efficient thermal dissipation into a
27 broad area heat sink. The technique of the use of insulating epitaxial
2~ material has been shown in the raferenced copending application.
YO976-049 - 2 -
1 Referrin~ to FIG. 1 the broad area substrate 1 is sho~m
2 schematlcally as a single crys~al semlconductor wa~er. The ~"afer 15 a
3 standard e~tensively used semiconductor :intermediate manufacturinz
4 product. Much processing and handling manufacturing capital equipment
is available in the art to facilitate building devices using this inter-
6 mediate product. Other broad area manufacturing intermediate products
7 such as dendritic webs, ribbons and thin film semiconductor layers on
8 insulating substrates, currently receiving attention in the art, may be
9 employed. The broad area substrate has an active region lA in which
the photoelectrical conversion takes place and an insulating region 13
11 which serves to electrically isolate the individual cells from a support-
12 ing and heat sinking member 2. While the demarcation between the regi.ons13 1~ and lB is shown as a line, there are instances where a precise defini-
14 tion would not take place. For example, we consider the case where a
semiconductor material is employed, such as gallium arsenide (GaAs). This
16 material is capable of exhibiting insulating properties by control of the -
17 impurity concentration therein, hence there would be a more or less con- ;
18 tinuous variation as the wafer is formed, from the required impurity
19 type and concentration adjacent the photoelectrical conversion region lA
to a dif~erent value in the lnsulating region lB, hence a precise line
21 may not occur. The high resistivity gallium arsenide (Ga~s) is kno~
22 in the art as semi-insulating gallium arsenide (GaAs).
23 The heat sinking member 2 serves both as a physical support
24 and a thermal conductor. Typically it is metallic in nature. The brcad ~ -
area substrate 1 may be quite thin, of the order of 0.010 inches for some
26 materials so that physical support is needed. Good thermal conductivity
27 is essential to maintaining temperature control. These requirements are
28 satisfied with a metal which in turn may be equipped with further convec-
:29 tion or radiation heat conducting capability such as fins or liquid tubes
not shown. There should be reasonable expansion compatability between the
Yo976-049 - 3 -
',. ' .
- , , ; .
1 heat sink member 2 and the substrate 1, the requirement i9 not as
2 rigorous as it would be were the active region to be closer A low
3 melting metal bolld such as solder is generally satisfactory.
4 The individual device cells are shown schematically as arranged
in rows and columns although with the flexibility of the integrated
technology no specific conEiguration is required. Further, the array
7 may occupy only one portion of a broad area substrate member 1, the other
8 portions of which may be devoted to devices for other purposes.
9 In accordance with the invention, isolation 4 is provided
between the device cells. There are various techniques of isolation prac-
11 tised in the integrated semiconductor device technology such as the use
12 of p-n junctions, the introduction of dielectrics, the use of a differen-
13 tial in substrate surface level and the use of diffused or implanted
14 impurity species. The isolation provides the ability for flexible inter-
connection of wiring patterns.
16 In FIG. 1 the isolation 4 is shown as a channel to the depth
17 of the active region filled with a dielectric, for e~ample an oxide.
18 Where for example, the active region is at or closer to the surface such
19 as through the use of a Schottky barrier for the photoelectrical converter
the isolation may not need to penetrate the surface deeper than one or
21 two microns.
22 Tne individual device cells are shown schematically in FIG. ].
23 as connected via electrodes 6 in series paths for voltage addition, the
24 paths in turn being connectable in parallel for current addition.
The details of cell structure may be seen in connection with ~ -
26 FIGS. 2 and 3. FIG. 2 shows the contact metallization and cell passivation.
27 In FIG. 3 a cross section of the individual cell is shown illustrating the
2~ active region, the passivation, the surface electrode and the reach through29 connection techniques.
Y0976-049 - 4 - `~
,
1 Referring tO FIG. 2 the phol:oelectrical conversion cell is
2 designed for the efficient uti.li~ation of hole-electron pairs produced
3 by incident light to produce a voltage betweerL the terrni.nals. T~e
4 op~imum is to have the semiconductor junction within the diffusion len~th
of the average light produced carrier in the material chosen. The in-
6 tegrated circuit technology provides approaches to this goal by making
7 it possible to produce material of such a quality that by diffusion or
8 ion implantation a p-n junction can be provided within the diffusion ~,
9 length of the average light pro.duced carrier below the surface, or, in
the alternatïve, by a junction contact such.as a Schottky barrier at .. '
11 the surface. This is illustrated in FIG. 2 by elemcnt 7. The element 7
12 is shown as a p-n ,junction positioned for example,.by diffusion precicely '
13 at the optimum plane below the surface 8 for maximum photoelectric con-
14 version efficiency. A reach through contact 6A is shown providing an -'
ohmic connection to the n region 9. This contact is made by depositing an :~
16 n impurity doped melting metal and temperature cycling to alloy through "'~
17 the p region 10 to the n region 9 or by ion implantati.on of a suitable
18 imyurity. ~.
19 , A portion of surface contact 6B labelled 11 is illustrated as
having a plurality of fingers the purpose of which is to minimize series ':
21 resistance. A passivating coating 12 covers and encapsulates the surface. :~. . '
22 Referring next to FIG. 3 the metallization is shown wherein ...
23 conductors 6 connect to the reach through contact 6A and the surface :
24 contact 6B. The conductors 6 go over the isolation 4 and the passiva- ' ':ting layer 12 and go through into the contacts 6~ and 6B. The conductors
26 6 may be laid down by standard vacuum deposition metallization techniques ~ . .
~7 with care being taken to avoid too thin a conductor at points wh~re there
28 is a difference in level.
29 What has been described is a technique'of photoelectrical con- ,
~. ...
Y0976-049 ~ 5 ~ '' '' '
1 version device construction that fabricates planar cell devices by
2 integrated circuit assembly techniques to advantageou61y re601ve the
sometimes conflic~ing constraints in photoelectrical conversion array
4 fabrication into a superior structure.
Y0976-049 - 6 -
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