Note: Descriptions are shown in the official language in which they were submitted.
10g1342
BACKGROUND OF THE INVENTION
Field of the Invention
;
This invention relates to the processing of
periodic information signals, such as video signals, and more
particularly is directed to apparatus by which time base
errors introduced during recording and/or reproducing of such
signals may be removed.
Description of the Prior Art
Video signals are frequently recorded on magnetic
tape and subsequently reproduced for later broadcasting or
viewing purposes. During the reproduction of recorded video
signals, time base or frequency errors are usually introduced
by reason of expansion or contraction of the record medium
during or after recording, variation in the speed of the tape
relative to the magnetic head or heads during recording or
reproduction, variation between the tape recording speed
and the tape reproducing speed, and the like. Such time base
errors, when present in the reproduced video signals, cause
a frequency shift of the latter which can result in many
observable undesirable effects, particularly when the reproduced
:. 1091342
video signals are to be transmitted or broadcast and may be
- mixed with live broadcast material that do not have such
time base errors. The observable undesirable effects resulting
from relatively small time base errors are a smeared or jittery
picture with erroneous intensity variations and, in the case
of color video signals, improper color display. When the time
base errors are large, the reproduced picture will fail to
lock horizontally or vertically.
In an existing time base corrector for substantially
removing time base errors from video signals, for example, as
disclosed in U.S. Patent No. 3,860,952, issued January 14,
1975, the incoming video signals are converted from analog
to digital form and temporarily stored in a memory. Time
base errors are removed from the video signals by writing the
digitized signals in the memory at a clocking rate which varies
in a manner generally proportional to the time base errors,
and by fetching or reading out these stored signals at a
standard clocking rate. After such reading out of the
digitized video signals-, the latter are reconverted to analog
form and applied to an output terminal. The memory used in
the known time base corrector comprises a plurality of memory
units each capable of storing one or more horizontal lines of
video information. A sequence control unit controls the
selection of each memory unit for writing and reading so that
the sampled video information is sequentially stored by
cyclically enabling the plurality of memory units and serially
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!
.
storing one or more lines of digitized video informa~ on in
each selected memory unit, and further so that, contemporaneously
with the storage of sampled video information in a selected
memory unit, the sequence control unit enables the video
~nformation stored in a different one of the memory units to l - -
be sequentially fetched or read out therefrom, with the
enabling of the memory units for the reading o~ of the ~- -
information stored therein being also e fected in a cyclical
manner. However, the arrangement disclosed in the above
identified patent for preventing double clocking of a single
memory unit, that is, an attempt to read and write
contemporaneously from the same memory unit in response to an
excessive time base error, results in at least one incomplete
or deteriorated line interval signalj and possibly even two
incomplete or deteriorated line interval signals which are
out of horizontal synchronization with each other and which
are present in the output from the time base corrector.
Further, the above referred to existing time base corrector
is not capable of eliminating f~ m its output those line inter-
vals of the incoming video signals in which crop-outs may occur.
In view of the above, it has been proposed, for
example, in u.s. Patent No. 4,063,284 Issued December
13, 1977 and having a common assignee herewith, to
provide a tlme base corrector generally of the type described
above and in which those line intervals of the incoming video
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signals having drop-outs occurring therein are omitted fr-om
the output of the time base corrector and replaced by previously
stored line intervals of similar video information. In such
time base corrector, the elimination of video signals containing
drop-outs is achieved merely by extending the writing period
of a memory unit in response to a detected drop-out in the
incoming video signals so as to store, in such memory unit,
the next occurring line interval which is free of drop-out,
and, thereafter, during reading out of the stored signals,
the line interval preceding the detected or omitted line
interval is read twice to replace the omitted line interval.
The foregoLng arrangement is generally satisfactory except in
the case where drop-outs occur in two or more successive line
intervals of the incoming vid~ signals, in which case the
line interval preceding the onset of drop-out is repeated
three or more times in the output of the time base corrector
and such repetition of a single line interval may be perceptible
in the picture reproduced from the corrected video signals.
Moreover, in order to avoid double-clocking of a memory unit
in response to excessive time base errors in the incoming video
signals, the writing or reading period of a memory unit is
extended, for example, from a normal one line interval to two
line intervals, and such concept for avoiding double-clocking
may accentuate the above problem associated with the elimination
of drop-out.
- 109134Z
- Further, in the existing time base correctors, as
described above, the read out of the temporarily stored
digitized video signals is effected at a fixed, standard
clocking rate, and thus cannot compensate for velocity or
phase errors occurring within a line interval of the incoming
video signals.
O~JECTS AND SU~IMARY OF THE INVENTION
Accordingly, it is an object of the invention to
provide an ~mproved time base corrector particularly suited
for processing video signals, a~ in which the previously
described problems are effectively avoided.
- More specifically, it is an object of this invention
to provide a time base corrector, as aforesaid, having an
improved arrangement for omitting from its output line intervals
of video information having drop-outs therein.
Another object is to provide a time base corrector
as aforesaid, in which the reading of video information from
! the memory is effected at a standard clocking rate which is
modulated in accordance with velocity errors occurring in such
video information as written in the memory.
Still another object is to provide a time base
corrector, as aforesaid, in which the compensation for velocity
errors is coordinated wi~h the elimination of drop-out in the
output of the time base corrector so as not to be disturbed
by the drop-out elimination.
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In accordance with an aspect of this invention, in
a time base corrector which converts incoming video or other
periodic information signals to digital form and writes the
digitized signals in a main memory at a clocking rate varying
generally in accordance with time base errors in the incoming
: signals, whereupon the signals temporarily stored in the main
memory are read out or fetched therefrom at a standard cloc~ing
rate and reconverted to analog form for eliminating the time
base errors, and in which the main memory is composed of a
plurality of cyclically enabled memory units: a drop-out memory
is provided for storing drop-out information in respect to ~-
drop-outs detected in the incoming video information written
in each of the main memory units; the drop-outs are eliminated
by rewriting, in each memory unit storing information having
drop-out, information free of drop-out from another memory
unit simultaneously with the reading of such other memory
unit; and, upon such rewriting of information in a memory
unit, the stored drop-out information in respect to that
memory unit is erased from the drop-out memory.
Further, in accordance with a feature of this
invention, a time base corrector as described above is provided
with a velocity error memory for storing velocity error informa-
tions as to the velocity errors in the incoming video signals
as written in the several main memory units, and such velocity
error informations are sequentially read simultaneously with
the reading of the video information from the respective main
memory units for modulating the ~locking rate at which the
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reading is effected. Furthermore, when video information is re- -
written in a main memory unit for eliminating drop-out, as
described above, the velocity error memory exchanges the
velocity error information associated with the rewritten video
information for the velocity error information associated with
the video information originally written in the respective main
memory unit.
More particularly, there is provided:-
. a time base corrector for removing time base errors from video
signals comprising main memory means including a plurality ofmemory units each having a capacity sufficient to store a pre-
determined whole number of line intervals of the video signals;
input ~eans for receiving the v-ideo signals, write clock
generating means coupled to said input means for generating
write clock pulses at a variable rate dependent upon time base
errors in the incoming video signals; read clock generating
means for generating read clock pulses at a rate which is
standard at least at the beginning and end of each standard line
interval of the video signals; main memory control means for
selectively enabling said memory units to write therein the
video signals received from said input means at a clocking
rate determined by said write clock pulses and for selectively
enabling said memory units to read out therefrom, at a
clocking rate determined by said read clock ~ulses, the video
signals written in said memory units; output means for re-
ceiving the video signals selectively read out from said
memory units; drop-out detecting means for providing drop-out
information in respect to the video signals received by said
input means; drop-out memory means having a plurality of
addresses respectively corresponding to said memory units for
storing said drop-out information in respect to the video
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. . . .
signals written in the respective memory units; and system
control means including write addressing means generating
write addresses of said memory units in a repeating cyclic
order for causing said main memory control means to selec-
tively enable said memory units in said repeating cyclic order
for the writing therein of the video signals received from said
input means, and read addressing means responsive to the dr_p-
out information stored in said drop-out memory means for
generating read addresses causing said main memory control
: 10 means to selectively enable the thereby read addressed memory
units for the reading-out of the video signals stored there.n,
with each memory unit thus addressed for reading-out being
different from the memory unit then addressed for writing a_d
further being a memory unit storing video signals free of
drop-out as indicated by the drop-out information at the re-
spective address in said drop-out memory means.
There is also provided:-
a time base corrector for removing time base errors further
comprising velocity error memory means having a plurality o_
addresses respectively corresponding to said memory units f_r
storing velocity error information in respect to velocity
errors in the video signals as written in the respective me~ .ry
units of said main memory means, and means responsive to sai_
rewr~ting` of video signals in a selected one of said memory
units for substituting, at the respective address of said
velocity error memory means, the velocity error information
corresponding to the video signals being rewritten in said
selected one of the memory units for the velocity error infor-
mation corresponding to the video signals originally written
in said selected one of the memory units.
The above, and other objects, features and advantages
of the invention, will be apparent in the following detailed
~A -8a-
1091342
` description of an illustrative embodiment which is to be read
in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic block diagram of a time base
corrector according to an embodiment of this invention;
Fig. 2 is a schematic diagram illustrating a color
video signal that may be applied to the time base corrector
of Fig. 1 for removal of time base errors from such signal;
Fig. 3 is a timing chart showing the cyclic orders
in which signal information may normally be written in, and
read out of the several memory units of the time base corrector
of Fig. l;
.
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~U9134Z
Fig. 4 is a schematic block diagram illustrating
details of a write clock generator and a velocity error
memory which are included in the time base corrector of
Fig. l;
Fig. 5 is a schematic block diagram illustrating
details of a system control included in the t~me base
corrector of Fig. l;
Fig. 6 is a schematic block diagram illustrating
details of a main memory and a main memory control included
in the time base corrector of Fig. l;
Fig. 7 is a schematic block diagram illustrating
details of a drop-out memory included in the time base
corrector of Fig. l;
Fig. 8 is a schematic block diagram illustrating
details of a read clock generator included in the time base
correctox of Fig. l;
Figs. 9A-W are waveforms to which reference will be
made in explaining the operation of the write clock generator
and the velocity error memory of Fig. 4; and
Figs. lOA-L and lLA-N are waveforms to which reference
will be made in explaining the operation of the system control
of Fig. S during writing and reading operations, respectively.
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.~
. .
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring to the drawings in de~ail, and initially
to ~ig. l thereof, it will be seen that a time base corrector
10 according to ghis invent~on has an input terminal 11 for
receiving periodic information signals, such as composite
color video signals reproduced by a so-called VTR and having
time base errors. If the reproduced composite color video
signals applied to terminal 11 are not already in the standard
NTSC form, such signals are appLied to a demodulator 12 which
may include an NTSC encoder. The resulting NTSC color video
signals are applied through a buffer amplifier 13 to a s~mple-
hold circuit 14 and from the latter through an amplifier 15
to an analog-to-digital (A/D) converter 16. As shown, a D.C.
restoring loop 17 is provided between amplif~ers 13 and 15
so that the NTSC color video signa~ are sampLed in D.C.
restored form.
~- The D.C. restored NTSC color video signals issuing
from amplifier 13 are further applied to a separator 18 which
separates ho~izontal synchronizing signals therefrom, and to
a separator 19 which is gated by the separated horizontal
synchronizing signals so as to separate burst signals from
the ~TSC color video signals. The separated hor~zontal
synchronizing signals and burst signals are applied to a
write clock generator 20 which, as is hereinafter described
in detail, produces write clock pulses WRCR having a relatively
high frequency, for example, of about 10.74 MHz which is
` 109134Z
:
three times the color or chrominance subcarrier frequency fc
for NTSC signals, and with their frequency or repetition rate
and phase being varied in accordance with changes in the
frequency and phase, respectively, of the horizontal synchronizing
signals and the subcarrier burst signals extracted from the
incoming color video signals so as to closely follow, or be
dPpend~nt upon time base errors in such incominO signals.
Further, it will be seen that the write clock
pulses WRCK issuing from generator 20 and having a frequency
of approxim~tely 10.74 MHz are applied to A/D converter 16
and to sample-hold circuit 14 to control the rate at which the
, latter samples the demodulated or detected video signals and
the rate at which converter 16 converts the sampled signals
from their original analog form into digital form. ~lore
specifically, in response to each write cloc~ pulse from
generator 20, ~/D converter 16 is operative to sample the
demodulated video signal and convert the latter into a
plurality of parallel bit signals, for example, digital
information of eight parallel bits.
The parallel bits of digitized signal information
are supplied from converter 16 to main memory 21 by way of a
digital information bus 16a which, for ease of illustration, is
represented by a double line. The main memory 21 is shown on
Fig. 6 to include memory units MU-l, MU-2, MU-3 and ~U-4,
each of which is comprised of a plurality of shift registers
equal in number to the number of parallel bits making up each
1091342
word of the digit7zed video signals. Thus, in the example
being described, each of the four memory units MU-l, MU-2,
M~-3 and MU-4 is made up of eight shift registers.
Each shift register of the memory units ~-1, MU-2,
MU-3 and MU-4 is desirably selected to have a storage capacity
or memory which, in considerati~ of the frequency of the write
clock pulses from generator 20, is sufficient to store the
digitized information corresponding to one or more, and
preferably an even number, that is, 2,4,6,8---etc. of the
horizontal or line intervals of the incoming video signals.
In the case of NTSC color video signals and a write clock
p~lse frequency of about 10.74 MHz, there are 682.5 words of
digital information for each horizontal or line interval
indicated at H on Fig. 2. However, in the illustrated time
base corrector, the horizontal synchronizing signals and burst
signals occurring during the interval ~ in each horizontal
blanking period are preferably stripped from the incoming video
signals prior to-the conversion of the latter to digital form
so that, for example~ Qnly 640 words of digital information
need to be accommodated in the registers of memory units ~
MU-2, MU-3 and MU-4 for each of the horizontal or line intervals
to be stored therein.
The separated horizontal synchronizing signals are
further shown to be applied to a write start generator ~2 which
produces write start pulses WST at predetermined intervals,
for example, at the beginning of every horizontal or line
~Og~34Z
. `
interval of the incoming video signals in the case where
digital information corresponding to one horizontal or line
interval is to be stored in each of the memory units.
The write start pulses WST from generator 22, and
the write clock pulses WRCK~from generator 20 are applied to a
system control 23 which, as hereinafter described in detail,
controls the oper~tions of a main memory control 24 for effect-
ing the selective writing and reading operations of the memory
units ~-1,MU-2,MU-3 and MU-4. Generally, under normal
circumstances, system control 23 causes main memory control
24 to produce write control signals occurring in a repeating
cyclic order and which are respectively applied to the
memory units MU-1,MU-2,~U-3 and MU-4 in order to determine
the sequences in which such memory units are selected or
enabled for the writing, in the selected memory unit, of
the digitized information corresponding to the desired number
of horizontal or line intervals of the incoming video-signals.
Further, the memory control 24 receives the write clock pulses
WRCK from generator 20 and, during the writing period determined
by each write control signal, the memory control 24 supplied
the write clock pulses WRCK to the respective ~emory unit
MU-l,MU-2,MU-3, or MU-4 which is then selected or enabled
for writing, so that the digitized informat~on corresponding
to the desired number of horizontal or line intervals of the
video signals is written in the shift registers of the selected
memory unit at the clocking rate determined by the frequency
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of the write clock pulses W~CK which varies in accordance with
t~me base errors in the incoming video signals.
After momentary storage in memory units ~-1,MU-2,
MU-3 and MV-4, the digitized video signal information is read
out therefrom in a predetermined sequence to an ~nformation or
data bus 25. In order to determine the clocking rate at
which the digitized inform~tion is read out of each of the
memory units, the illustrated time base corrector lO includes
a standard sync generator 26 which supplies a carrier signal
at a fixed or sta~dard frequency, for example, the standard
chrominance subcarrier frequency fc of 3.58 MXz ~r NTSC color --
video signals, to a read clock generator 27 which, in turn,
produces read clock pulses RCK having a standard frequency,
for example, 10.74 MH2, at least at the beginning and end of
each reading period. The standard sync generator 26 is further
shown to produce read start pulses RST, for example, at intervals
corresponding to the desired number of the horizontal or line
intervals of NTSC video signals stored in each memory unit.
The read start pulses RST from generator 26 are
applied to system control 23, and the read clock pulses RCK
are applied from generator 27 to system control 23 and main .
memory control 24. Under normal circumstances, system csntrol
23 causes main memory control 24 to produce read control signals
occurring in a repeating cyclic order and which are respectively
applied to memory units MU-1,MU-2,MU-3 and MU-4 in order to
determine the sequence in which such ~emory units are selected
109134Z
or enabled for the reading out therofrom of the digitized
information corresponding to the number of horizontal or line
intervals which had been previously stored in the selected
memory unit. Further, during the reading period determined
by each read control s~gnal, the memory control 24 supplies
the read clock pulses RCK to the selected or enabled memory
unit, so that the digitized information corresponding to one
or more horizontal or line intervals of the video signals is
~: read out of the shift registers of the selected memory unit
at the standard clocking rate of the read clock pulses RCK.
- The read clock pulses RCK are also applied to a
bufrer memory 28 which receives the digitized information
sequentially read out of main memory 21, and to a digital-to-
analog (D/A) converter 29 which is operative to convert the
bu~fered digital output of memory 28 back to the original
analog form. The analog output of D/A converter 29 is applied
to a processor 30 which receives the standard frequency carrier
signal from generator 26, and which is operative to add to the
output of converter 29 the color burst and composite synchronizing
signals which were previously stripped from the incoming video
signals. The resulting composite color video signals are
then obtained at an output terminal 31 of processor 30.
In order to correct for velocity errors that may
appear ~n the incoming video signals, the tLme base corrector
10 according to th~ invention further detects the velocity
- ~ \
1091342
error at the write clock generator 20 during each writing
period and then supplies the detected velocity error to a
velocity error memory 32 by way of a velocity error hold
circuit 33. The velocity error memory 32, under the control
of system controL 23, memorizes the velocity error detected
during the writing period of each of the memory units ~U-l,
~-2,~.~-3 and ~-4, and, during the reading period of each of
the memory units, applies a corresponding velocity error
correcting signal to read clock generator 27 by which the read
clock pulses RC~ from the latter are suitably modulated to
eliminate or compensate for the velocity errors, as hereinafter
described in detail. Thus, the read clock pulses RCK, while
having the sta~dard frequency at the beginning and end of each
reading period, may vary in phase during such reading period.
Further, the time base corrector 10 according to
this invention is shown to be provided with a drop-out detector
34 which is connected with input terminal 11 for detecting any
drop-out in the incoming video signals and providing a
corresponding drop-out signal D0 to the system control circuit
23, and with a drop-out memory 35 in which information concerning
the occurrence of drop-out in the incoming video signals is
stored for influencing the reading sequences of the memory units
and for effecting writing in the latter of video information
free of drop-out so as to eliminate such drop-out from the time
base corrected video signals obtained at output terminal 31,
as hereinafter described in detail.
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'; '
As is shown on Fig. 3, in the illustrated time base
corrector 10, the cyclically occurring write control signals
for sequentially writing digital information corresponding to
any desired number of horizontal or line intervals in each of
the memory units MU-1,MU-2,~-3 and MU-4 may normally occur
simultaneously with the cyclically occuring read control
signals for sequentially reading out the digital information
previously stored in the respective memory units ~-3,~-4,~-1
and ~-2, respectively.
WRITE CLOCK GENERATOR
Referring now to Fig. 4, it will be seen that the
write clock generator 20 of the time base corrector 10 according
to this invention may generally comprise an automatic frequency
control circuit 40 having a variable frequency oscillator or
VCO 41 with its control voltsge being determined by comparison
of a suitably divided output of VCO 41 with the horizon~al
synchronizing signals received from separator 18, and an
automatic phase control circuit 42 having a variable phase
shifter 43 which receives a suitably divided output of VCO 41
and which is controlled by a phase comparator 44 comparing a
suitably divided output of phase shifter 43 wi~ the burst
signals received from separator 19.
More particularly, it will be seen that, in the
write clock generator 20 illustrated on Fig. 4, the output
of VCO 41 has a center frequency which is 2N times the chrom-
~nance subcarrier frequency of the color video signals being
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~ 1091~42
processed, for example, 6 x 3.58 ~z or 21.48 ~Mz in the case
of ~TSC color video signals and N being 3, and such output from
VCO 41 is supplied to a counter 45 which operates as a frequency
divider dividing by 455xN. Thus, counter 45 provides a divided
output at the horizontal or line frequency of 15.75 KHz, and
such divided output is applied to one of the inputs of a phase
compara~ r 46. The horisontal synchronizing signal (Fig. 9B)
separated from the incoming video signal (Fig. 9A) by separator
18 triggers a monostable mul~ivibrator 47 acting as a delay,
and the falling side of the output pulse (Fig. 9E) from
monostable multivibrator 47 triggers a monostable multivibrator
48 to provide an output pulse (Fig. 9F) from the latter which
is in predetermined timed relation to the horizontal synchroniz-
ing signal and is applied to another input of phase comparator
46 for comparison in the latter with the divided output of
VCO 41 obtained ~rom counter 45. The horizontal synchronizing
signal from separator 18 further triggers a monostable multi-
vibrator 49 to provide an output pulse (Fig. 9C) which, at its
falling side, actuates a latch circuit 50 for latching the
contents of counter 45 at such time. h digital comparator Sl
receives the latched contents of counter 45 from latch circuit
50 and detects the difference between the phase of the incoming
horizontal synchronizing signal or pulse and the phase of the
divided output from counter 45 as indicated by the latched
contents of such counter. The digital comparator 51 provides an
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output signal of a relatively high level "1" when the phase
difference detected by comparator 51 lies within predetermined
limits, such as, for example ~ 0.5 microseconds, whereas,
the output signal from comparator 51 has a low level "O"
when the detected phase difference exceeds the predetermined
limits. Such output signal from digital comparator 51 is
employed to actuate a switch or gate 52 which, so long as the
output signal from comparator 51 has its relatively high value
"1", conducts the outpu~ of phase comparator 46 to a hold
circuit 53 which, in turn, has its output connected to VCO 41
as the control voltage for the latter. The output signal from
digital comparator 51 is further applied through an inverter
54 for actuating a switch or gate 55 through which the output
signal of monostable multivibrator 48 is selectively applied
to counter 45 for resetting the latter at the falling side
of the output signal or pulse from monostable multivibrator
48. The switch 55 is in its open condition, as shown in full
lines on Fig. 4, so long as the output signal from digital
comparator 51 is at its high level "1" for closing switch 52,
whereas, when the output signal from comparator 51 is at its
low level"O", switch 55 is closed simultaneously with the
opening of switch 52.
It will be apparent that, in the automatic frequency
control circuit 40 as described above, phase comparator 46
will normally compare the phases of the incoming hori~ ntal
synchronizing signals and of the divided output of VCO 41
-19-
` 10~139~Z
as obtained from counter or frequency divider 45 and, on the
basis of such comparison, provide a control signal which is
supplied thr~ugh closed switch 52 to hold circuit 53. The
resulting output of hold circuit 53 is applied, as a control
voltage, to VC0 41 so as to adjust the output frequency of the
latter to a value which is held until the next horizontal
synchronizing signal is received from separator 18. Thus,
so;long as the phase differences detected by comparator 51
are within the predetermined limits, the output frequency of
VC0 41 will be varied in accordance with changes in the
frequency of the incoming horizontal synchronizing signals,
that is, in accordance with tLme base errors in the incoming
color video signals. However, when there is a gross or abrupt
time base error in the incoming color video signals to produce
a corresponding abrupt or gross de~iation in the timing of the
horizontal synchronizing signals, for example, when the
incoming-signals are recorded video signals being reproduced
. by a video tape recorder in which a jumping or slippage of the
tape may occur, the resulting excessive phase difference
between a received horizontal synchron~zing signal and the cutput
of counter or frequency divider 45 causes comparator 51 to
provide its output signal with the low level "0" so that
switch 52 is opened and switch 55 is closed. The opening of
switch 52 opens or interrupts the so-called phase locked loop for
YC0 41 constituted by counter 45, phase comparator 46 and
hold circuit 53 so that hold circuit 53 continues to apply
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109134Z
the previously established control voltage to VC0 41 for
maintaining the output frequency of the latter at its previously
established value for another horizontal or line interval.
The closing of switch 55 simultaneously with the opening of
switch 52 causes the output signal or.pulse fro~ monostable
multivibrator 48 to be effective, at its falling side, to
reset counter 45. It will be noted that the delay provided
by the monostable multivibrator 47 ensures that such resetting
of counter 45 will be effected only after a time interval
sufficient to allow actuation of the switches 52 and 55.
From the foregoing, it will be apparent that the described
automatic frequency control circuit 40 of the write clock
generator 20 is effective to avoid overcorrection of the output
from VC0 41 in response to the described gross or abrupt changes
in the timing of the incoming horizontal synchronizing signa~s.
In the phase control circuit 42 of write clock
generator 20, the output of VC0 41 having a central frequency
of 21.48 MHz is supplied to variable phase shifter 43 th~Dugh
a divide-by-2 frequency divider 56 so as to have a central
frequency of 10.74 MHz. The output of phase shifter 43, which
is the write clock pulse WRCK for application to sample-hold
circuit 14, A/D converter 16, system control 23 and main memory
control 24, is also applied to phase comparator 44 through a
divide-by-3 frequency divider 57 so as to have a central
frequency of 3.58 MHz corresponding to the frequency of the
burst signals (Fig. 9G) applied to phase co~parator 44 from
- ~091342
separator 19. The phase comparator 44 functions to detect
velocity error in the incoming video signal and to control the
variable phase shifter 43. More particularly, as shown, a
flip-flop (F.F.) 58 is set by each horizontal synchronizing
signal from separator 18 and is reset-at the onset of the
first of the corresponding burst signals from separator 19,
as shown on Fig. 9H. Th~ falling edge of the output (Fig. 9H)
of F.F. 58 triggers a monostable-multivibrator (M~) 59
so that the latter produces an output (Fig. 9I) having its
falling edge at about the center or later half of the separated
burst (Fig. 9G) by which time the velocity error indicated by
t~ output (Fig. ~K) of phase comparator 44 has become stable.
The output of comparator 44 is applied to velocity error hold
circuit 33 which also receives the output of MM 59 so that,
at the falling edge of the output from MM 59, hold clrcuit 33
samples and holds (Fig. 9L) the output of comparator 44 which
then accurately corresponds to the velocity error of the previous
horizontal or line interval. The output of MM 59 is also
applied to a monostable-multivibrator ~M) 60 which is triggered
by the falling edge of the output (Fig. 9I)of MM 59 to produce
an output (Fig. 9J) after the velocity error has been sampled
and held in circuit 33. The output of MM 60~ when at its high
level "1", closes a normally open switch 61 through which the
output of comparator 44 is applied to variable phase shifter
43 for controlling the latter in the direction to cause the
output of phase comparator 44 to be reduced to zero. The
109~342
.. period during which switch 61 is closed is determined by the
duration of the output of MM 60, which duration is selected,
in consideration of the time constant of the feedback loop
constituted by frequency divider 57, comparator 44 and switch
61, so that phase shifter 43 can hold the phase shift corres-
ponding to an error signal received from comparator 44 upon
a closing of switch 61 for the interval until the switch 61
is again closed for applying the next error signal from phase
comparator 44 to phase shifter 43.
SYSTEM CONTROL
.: Referring now to Fig. 5, it will be seen that, in
the system control 23 of the illustrated time base corrector
10 according to this invention, a counter 62 receives the
write clock pulses WRCK from the write clock generator 20
and the write start pulses ~T (Fig. 10C) from the generator
22. Each write start pulse WST initiates counting operation
of counter 62 which then counts 640 write clock pulses ~RCK.
The output (Fig. lOD) of counter 62 is at a high level "1" to . .
constitute 8 write command WCD during the counting operation
of counter 62, that is, duxing the counting by the latter of
640 write cloc~ pulses WP~CR, and the output of co~nter 62 is
at a relatively low level llo" during the intervals between
counting operations. The write command WCD is applied to the
main memory control 24 (Figs. 1 and 6) and to two monostable
multivibrators (~M) 63 and 64 in system control 23 which are
both triggered by the falling edge of each write command tWCD~
(Figs. 10E and R). The output ~Fig. lOE~ of ~ 63 is applied
-23-
109134Z
to a monostable multivibrator ~MM) 65 which is triggered by
the falling edge of each output of ~ 63 to provide a corres-
ponding output or pulse (Fig. lOF). The outputs or pulses
from MM 65 are counted by a two-bit binary counter 66 which
provides a two-bit binary output constituting a write control
signal or address 'WRA (Fig. lOÇ) for selecting the memory
unit of main memory 21 in which the digitized information from
A/D converter 16 is to be written. The output of MM 65 is
further shown to be applied to a monostable multivibrator
(MM) 67 which is triggered by the falling edge of each output
(Fig. lOF) of MM 65 to provide a pulse (Fig. lOH) for resetting
a flip-flop (FF) 68 after the latter has been set by a drop-out
signal DO (Fig~ lOI) received by FF 68 from drop-out detector
34 (Fig. 1). Therefore, when a drop-out is detected to cause
detector 34 to produce a drop-out signal DO, as indicated in
broken lines on Fig. lOI, for setting FF 68, the output of
FF 68 rises to a relatively high ~alue "1", as indicated in
broken lines on Fig. lOJ, and retains that value "1" until
FF 68 is reset by the falling edge of the output (Fig. lOH) from
MM 67. The output of FF 68 is applied to a fixed contact A
of a switch 69 which further has a grounded fixed contact B
and a movable contact connected to drop-out memory 35. The
switch 69 is controlled by the output (Fig. 10~) of ~ 64
so as to normally engage its contact B and to change-over to
its contact A only during each output or pulse from ~M 64. Thus,
if the output of FF 68 is at its high level "1" during the
-24-
1~9134Z
output or pulse from ~ 64~ that high lPvel "1" is transmitted
as a sensed drop-out signal SD0 (Fig. lOL), through switch 69
to drop-out memory 35. It will be noted that the.output or
pulse from MM 64 is timed to occur after the completion of
the writing of the digitized video information in a selected
one of the memory units and before changing of the write
address ~RA corresponding to that selected memory unit.
Further, the write address WRA from counter 66 is
shown on Fig. 5 to be applied to a fixed contact A of a switch
70 which is also oDntrolled by the output of MM 64 and which
has another fixed contact B and a movable contact connected
to drop-out memory 35. The movable contact of switch 70
normally engages its fixed contact B and is changed-over to
engage its contact A only during the pulse or high-level
output from MM 64. Therefore, when ~ sensed drop-out signal
SD0 is applied to drop-out memory 35 through switch 69, as
previously described, the address WRA of the memory unit being
; written-in during such drop-out is sLmultaneously applied
through switch 70 to drop-out memory 35 as a drop-out memory
address DOMA.
The system con~rol 23 of Fig. 5 is further sh~wn to
comprise a counter 71 which receives the read clock pulses
RCK from read clock generator 27, and the read start pulses
RST (Fig. llA) from generator 26. The counter 71 counts 640
read clock pulses RCK after its counting operation has been
initiated by each read start pulse RST. The output {Fig. llB)
-25-
109134Z
of counter 71 is at a high level "1" to constitute a read
command RCD during each counting operation, and the output of
counter 71 is at a relatiYely low or "O" level during the
intervals between counting operations. Such read command RCD
is applied to the main memory control 24 (Figs. 1 and 6).
Further, each output or read comm2nd RCD from counter 71
is applied to a monostable multivibrator ~MM) 72 which is
,.
triggered by the falling edge of the read co~mand RCD to
provide an output or pulse (Fig. llD). The falling edges of
the outputs or pulses from M~l 72 are counted by a two-bit
binary counter 73 which provides a two-bit ~inary output
constituting a read control signal or address RA (Fig. 11~) -
for selecting the memory unit of main memory 21 from which the
stored digitized video information is to be read or fe~ched.
The write address WRA from counter 66 and the read
address RA from counter 73 are applied to a digital comparator
74 and the latter is made operative by the high level output
or pulse (Fig. llD~ from ~ 72, that is, immediately following
the completion of a reading operation, to compare the write
address WRA and the read address RA then being supplied to
comparator 74 and, on the basis cf such comparison, to further
control or step the counter 73 for af~ect~ng the read address
RA issuing therefrom as hereinafter described.
Normally, the write address WRA and the read address
RA are changed by sequencing of counters 66 and 73, respectively,
so as to address the memory units of main memory 21 in the
repeating cyclic order MU-1,MU-2,MU-3,MU-r, ~ --etc., and
109134Z
further to provide an inoperative memory unit, that is, a
memory unit whic h is neither writing nor reading, between
the memory units in the foregoing repeating cyclic order which
are addressed by write address I~RA and read address RA for
writing and reading operations, respectively, in response to
a write command WCD and the more or less overlapping read -
command RCD. Thus, as previously mentioned with reference
to Fig. 3, during the writing in a selected one of the memory
units MU-l,MU-2,MU-3 and MN-4 identified by the write address
~RA, the read address RA normally selects and causes reading
from the memory unit MU-3,MU-4,~U-1 or ~-2, respectively.
H~wever, in correcting for excessive time base errors in the
incoming video signals, the normal se~uencing of counters 66
snt 73 may cause the read address RA and the write address WRA
to identify the same memory unit during overlapping portions
of the read and write commands RCD and WCD. In such case,
the apparatus would seek to effect simultaneous writing ana
reading operations in the same memory unit at the different
clocking rates established by the write clock pulses t~RCK
and the read clock pulses RCK, which is obviously not possible.
In order to avoid the foregoing, digital comparator
74 in the system control 23 provides a suitable control output
~o counter 73 for abo~ing or preventing the normal sequencing
of counter 73 at the falling edge of the output or pulse from
MM 72 during which the write and read addresses ~RA and RA
-27-
1091342
' . .
are being compared, whenever such comparison indicates` that
the normal sequencing of counter 73 at the fallin~ edge of the
output from ~ 72 would result in the new read address RA' then
being the same as the write address ~RA ~hich h2s been compared.
On the other hand, if the comparison of the write and read
addresses during an output from MM 72 indicates that the normal
sequencing of counter 73 at the falling edge of such output
would provide a new read address RA' tb~t is only one address
in advance of the compared write address WRA so that the
sequencing of counter 66 by the falling edge of the next
oùtput from MM 65 would result in the write and read addresses
then being the same, then the digital comparator 74 provides
a suitable control output or signal to counter 73 for an
additional sequencingof~2 latter in advance of t~ normal
se~uencing thereof at the falling edge of the output from MM
72 during which the addresses are compAred.
Thus, if for example, during an output from ~ 72,
the read address RA representing memory unit ~-1 is compared
with a write address WRA representing the memory unit ~U-3 or
MU-4, no control output is applied from comparator 74 to counter
73 as the normal sequencing of counter 73 at the falling edge
of such output from ~M 72 will result in a new read address
RA' representing memory unit MU-2 and the sequencing of counter
66 at the falling edge of the next output from M~ 65 will
result in a write address WRA representing either memory unit
MU-4 or MU-l~ respectively, which are different from the memory
u~it MU-2 represented by the read address RA'. From the
-28-
~09134~
foregoing, it will be seen that no control output issues from
comparator 74 to counter 73 so long as there is no possibility
that the read and write addresses RA and ~RA will select the
same memory unit in the interval between an output from MM 72
and the next output from the latter.
However, if, during an output from MM 72, the
read address representing, for example, the memory unit
is compared with the write address representing the same
memory unit MU-l, the comparator 74 provides a control output
or signal which sequences counter 73 in advance of the normal
sequencing thereof at the falling edge of the output from
MM 72 with the result that counter 73 is sequenced or stepped
twice to issue the new read address RA' corresponding to memory
unit ~-3. Therefore, if, during the reading of memory unit
~U-3 an output from MM 65 causes counter 66 to provide the
write address WRA for memory unit MU-2, there is no danger of
double clocking of a single memory unit, that is, the
simultaneous writing and reading of a single m~mory unit. On
the other hand, if the read address RA and the write address
~RA which are compared by comparator 74 during an output from
MM 72 respectively represent memory units ~-1 and MU-2, the
resulting control output from comparator 74 will abort or
prevent the normal sequencing of counter 73 at the falling edge
of such output from MM 72 so that the new read address RA' will
be the same as the compared read address RA and the memory unit
MU-l will be read again during the next read command RCD. Thus,
whether or not counter 66 is sequenced during the repeated reading
-29- .
34Z
of memory unit MN-l, there is no danger of writing in memory
unit ~-1 during the reading therefrom.
The system control 23 is further shown to comprise
a digital adder 75 which adds -1 to the read address RA from
counter 73 to provide an output or address (RA-l). Thus, if
read address RA corresponds to memory unit MU-l, the address
(RA-l) from adder 75 will correspond to memory unit ~ 4.
Such output or address (RA-l) from adder 75 is compared, in
a digital comparator 76, with the write address ~RA from
counter 66. The comparator 76 provides an output of high level
"1" if the compared addresses (RA-l) and WRA correspond to the
: same memory unit, and the output of comparator 76 has a low
value "O" when the compared addresses (RA-l) and WRA correspond
to different memory units. Such output from comparator 76,
that is, the result of the compariscn of addresses WRA and
(RA 1), is stored in a D-type flip-flop (FF) 77 which is
; triggered, as indicated on Fig. llF, at the r;sing edge of
each output (Fig. llD) from MM 72, that is, before the
comparator 74 may effect any change in the read address RA
from counter 73 and also before the normal se~uencing of
counter 73 by the falling edge of the output from M~ 72.
The read address RA from counter 73 is further shown to be
applied to a second digital adder 78 which adds ~1 to the read
address RA and, therefore, provides an output or address
(RA~l). The outputs or addresses (RA~l) and (RA-l) from
adders 78 and 75, respectively are applied to fixed contacts
-30-
109134Z
:. :
A and B, respectively, of a switch 79 which has its movable
contact controlled by the output (Fig. llF) of FF 77 to engage
contact A and pass address (RA~l) as a spare read address SRA
only when the oueput of comparator 76 and hence of FF 77 is
at the high level "1", and otherwise; that is, when the output
of FF 77 is at the low level "O", to engage the contact B
for passing the address (RA-l) as the spare read address SRA.
The output of MM 72 is further shown to be applied
' to a monostable multivibrator (~) 80 which, as shown on Fig.
llG, is triggered by the falling edge of the output or pulse
from MM 72 to provide a pulse which, at the falling edge of
.- the latter, triggers a flip-flop (FF) 81 and a monostable
multivibrator (MM) 82. The output of MM 82 is applied
to monostable multivibrators (~) 83 and 84 which, as shown
on Fig. llL ~md Fig. llJ, respectively, are both ~riggered
by the falling edge of the output or pulse from MM 82. The
falling edge of the output or pulse (Fig. llL) from ~l 83
triggers a flip-flop (FF) 85. As hereinafter described in
detail, the drop-out memory 35 provides drop-out information
; DOI which is applied to FF 81 and FF 85 so that the FFs 81
and 85 respectively store the drop-out information provided
by memory 35 at the times when FF 81 and FF 85 are respectively
triggered by the falling edges of the pulses from ~ 80 and
MM 83.
-31--
10~134Z
The output or pulse (Fig. llJ) from ~ 84 controls
a switch 86 having a fixed contact A which receives the spare
read address SRA, that is, the address (RA-l) or (RA~
from switch 79, and a fixed contact B which receives the address
RA from counter 73. During the output or pulse (Fig. llJ)
from MM 84, the movable contact of switch 86 is changed-over
to engage the fixed contact A thereof so that the spare read
address SRA is passed thereby to the drop-out memory 35 so
that the drop-out information DOI from the latter then indicates
whether there was any drop-out in the video information received
while writing in the memory unit identiff ed by the spare read
address SRA. In the intervals between the output or pulse
from MM 84, switch 86 engages its fixed contact B so as to
pass the read address RA from counter 73 to drop-out memory
35 with the result that the drop-out information DOI then
indicates whether any drop-out appeared in the v~deo information
received while writing in the memory unit identified by the
read address RA.
Assuming that the read addresses provided by counter
73 for successive reading intervals or periods are RA, RA',
RA"---etc., it will be seen from the respective waveforms
on Fig. 11 that the falling edge of each output or pulse from
MM 80 for triggering FF 81 occurs after the respective sequencing
of counter 73 for changing the read address from RA to RA',or
from RA' to RA", but before the output or pulse from ~ 84 so
that FF 81 is triggered while switch 86 engages its B contact
-32-
109~34Z
to pass the read address RA', RA"---etc. to drop-out memory
35. Therefore, in each instance, FF 81 is triggered prior to
a read interval to store the drop-out information DOI relative
to the memory unit identified by the read address RA', RA",---
etc. and from which the video information would nonmally be
read in the next read interval or period. Further, it will
be seen that the falling edge-of the output or pulse from
MM 83 for triggering FF 85 occurs during the output or pulse
from MM 84, that is, while switch 86 engages its A contact to
pass the spare read address SRA', SRAr',---etc. to drop-out
memory 35. Therefore, in each instance, FF 85 stores the
drop-out information DOI relative to the memory unit identified
by the spare read address SRA', SRA"---etc.
Since the triggering of FF 85 occurs after the falling
edge of the output from MM 72, that is, after the sequencing
of counter 73, i~ will be apparent that the spare read address
SRA' is either (RA'-l) or (RA'~l) and the spare read address
SRA" is either (RA"-l) or (RA"~l), with the read addresses
2A' and RA" identifying, as mentioned above, memory units from
which video information would normally be read in the following
read intervals or periods. However, since FF 77 is triggered
by the rising edge of the output or pulse from MM 72, that is,
before the sequencing of counter 73, the determination of
whether, for example, SRA' is (RA'-l) or (RA'~l) is made on
the basis of a comparison of ~RA and (RA-l) in which RA is the
address indicated by counter 73 prior to its being sequenced.
-33-
109134Z
Each of the FFs 81 and 85 provides a high level
output "1" only when the drop-out information DOI stored
therein indicates that drop-out appeared in the incoming video
~formation during writing in the memory unit identified by
the read address RA', RA",---etc., or by the spare read address
SRA',SRA",---etc., respectively, and at all other times
thP FFs 81 and 85 each provide a low level output "O".
The output of FF 81 is shown to be employed for
controlling switches 87 and 88 each having fixed contacts
A and B which are engaged by a respective movable contact
when the output of FF 81 is at its high level "1" and at its
low level "O", respectively. Further, the fixed contacts A
and B of switches 87 and 88, respectively, are connected to
switch 79 for receiving the spare read address SRA,SRA',
SRA",---etc. from the latter, while the fixed contacts B
and A of switches 87 and 88, respectively, are connected to
counter 73 for receiving the read address RA, RA',R4",---etc.
from the latter. Therefore, when the output of FF 81 is at
its low level "O", indicating no drop-out in the incoming video
information during writing in the memory unit identified by
read address RA',RA",---etc., the switch 87 delivers the
respective read address from counter 73 to the main memory
control 24 as a finally determined read address FDRA, while
the switch 88 delivers the spare read address SRA',SRA",---etc.
from switch 79 to main memory control 24 as a possible rewrite
address PRWRA. On the other hand, ~hen the output of FF 81 is
at its high level "1" ~ndicating a drop-out in the incoming
1(~913~Z
video information during writing in the memory unit identified
by read address RA',RA",---etc. from counter 73, the switches
87 and 88 respectively deliver the addresses SRA' and RA',
SRA" and RA",---etc. as the FDRA and the ~BWRA, respectively.
Further, as shown on Fig. 5, the address PRWRA obtained
through switch 88 is also applied to fixed contact B of switch
70. Therefore, when the output of MM 64 is at its low level
"O", the address ~RWRA from switch 88 is transmitted through
switch 70 to the drop-out memory 35.
It will also be seen on Fig. 5 that the outputs from
FF 8~ and FF 85 (Figs. llI and lLM) are applied to a logic
circùit 89 which provides a logic output LG at a high level
"1" whenever the outputs of FFs 81 and 85 are different, for
example, "O" and "1" or "1" and "O", respectively; whereas,
the logic output LG is at a low level"O" whenever the outputs
of FFs 81 and 85 are the same, for example, "O" and "O" or
"1" and "1", respectively.
The logic output LG is employed for controlling a
switch 90 in system control 23, and is also applied to main
memory control 24 and velocity error memory 32 for purposes
that will appear from the following detailed descriptions
of the latter components. The switch 90 is open so long as
the logic output LG is at the low le~el llo" and is closed in
response to the logic output LG attaining the high level "1".
Further, a monostable multivibrator (2~M) 91 is triggered by
each read start pulse RST to provide an output or pulse (Fig. llN)
-35-
,,
. ~ ~
~9134Z
which is passed through switch 90, upon closing of the latter,
to a fixed contact B of a switch 92 which further has a fixed
contact A connected to the output of MM 63. The switch 92 is
controlled by the output of ~ 64 (Fig. 10K) so that a movable
contact of switch 92 normally engages its fixed contact B and
is changed-over to its fixed contact A only during the high
level output or pulse from ~ 64.
It will be see~ from the above that, during the
output or pulse from MM 64, that is, when switches 70 and 92
are changed over to engage their respective contacts A, the
output or pulse from MM 63 is passed through switch 92 to
the drop-out memory 35 as a drop-out write command DOWCD
for the latter, while switch 70 passes the write address
W~A to the drop-out memory 35 as the drop-out memory address
DOMA at which the sensed drop-out SDO, if it then exists, is
to be written or stored in drop-out memory 35, as hereinafter
described in detail. On the other hand, in the intervals
between successive outputs or pulses from MM 64, that is, when
switches 70 and 92 engage their B contacts, if the logic
output LG from logic circuit 89 is at the high level "l" for
closing switch 90, the pulse from MM 91 triggered by read
start pulse RST is passed through switch 92 to drop-out memory
35 as an erase command so as to cause eras~ g, at the falling
edge of the pulse from ~ 91, of the sensed drop-out that may
have been previously written at the address in drop-out memory
35 indicated by the address PRWRA passed from switch 88 through
switch 70 to the drop-out memory.
-36-
109134Z
MAIN M~MO~Y
Referring now to Fig. 6, it will be seen that, in
the main memory 21, the digitized video information from A/D
converter 16 is applied, by way of bus 16a, to fixed contacts
A of switches 93, 94,95 and 96 which are respectively
associated with memory u~its ~-1,MU;2,MU-3 and MU-4. The
movable contacts of switches 93,94,95 and 96 are connected to
fixed con~acts B of switches 98,98,99 and 100, respectively,
which, in turn, have their movable contacts connected to the
inputs of memory units MU-l,Mn-2,~-3 and ~-4, respectively.
The outputs of memory units MU-1,MU-2,MU-3 and MU-4 are connected
by way of normally open switches 101, 102, 103 and 104,
respectively, to the bus 25, and the video information read
out of any one of the memory units is fed back, by way of a
rewriting loop 105, from bus 25 to fixed contacts A of all of
the switches ~7-100. Further, individual feedback loops 106,
107,108 and 109 extend to fixed contacts B of switches 93,
95,95 and 96, respectively, from the outputs of memory units
MU-l,MN-2,MU-3 and ~U-4 in advance of the respective switches
101,102,103 and 104. The movable contacts of switches 93-96
and of switches 97-100 normally engage the respective fixed
contacts B and are changed-over to engage the respective fixed
contacts A only when such switches receive respective control
voltages or signals, as hereinafter described in detail.
-37-
.
109134Z
MAIM ME~ORY CONTROL
In the main memory control 24, as shown on Fig. 6,
a decoder 110 receives the write address WRA from counter 66
in system control 23 and provides a suitable control output or
signal to a selected one of the switches 93-96 which is assoc-
iated with the memory unit identified by the write address
T~æA received.by the decoder 110, so as to change-over the
selected one of switches 93-96 to its contact A. Further,
the control output or signal issuing from decoder 110 in response
to the write address WRA is applied to a respective one of four
AND gates 111,112,113 and 114 for opening the one of such
gates associated with the memory unit identified by t~ write
address WRA. An AND gate 115 receives the write clock pulses
WRCX from the write clock generator 20 and the write command
WCD from the counter 62 of system control 23 so that AND gate
115 ~s opened by the write command WCD for passi~ the write
clock pulses WRCK to all of the AND gates 111-114. The outputs
of AND gates 111, 112,113 and 114 are respectively connected
to OR gates 116,117,118 and 119 which, in turn, have their
outputs suitably connected to memory units ~U-1,MU-2,~-3 and
~U-4, respectively.
It will be apparent from the above; that, upon
the reception of a write command WCD by AND gate 115 the write
clock pulses WRCK are applied through a selected one of AND
gates 111-114, as determined by the write ~ddress WR~ received
by decoder 110~ and thrDugh a respective one of OR gates 116-119
-38-
.
1Q913~Z
.
to the one of memory units MU~ MU-4 identified by the write
address WRA, while the decoder 110 simultaneously causes the
change-over of the respective one of the switches 93-96.
Thus, the digitized video information received by bus 16a
is applied through the changed-over one of the switches 93-96
and through the respective one of the switches 97-100 to the
input of the memory unit identified or selected by the write
address W~A so as to be written in such selected memory unit
at the clocking rate determined by the write clock pulses
WRCK.
The main memory control 24 is further shown to comprise
a decoder 120 which receives the finally determined read address
FDRA from switch 87 of system control 23, and which provides
a suitable control output or signal for closing a selected one
of the switches 101-104 which is associated with the memory
-
unit identified by the finally determined read address FDRA.
The outputs of decoder 120 corresponding to memory units
MU-l,MU-2,MU-3 and MU-4 are also respectively connected to
inputs of OR gates 121,122,123 and 124 having their outputs
connected to inputs of AND gates 125,126,127 and 12g, respectively.
Other inputs of AND gates 125-128 are all connected to the
output of an AND gate 129 which receives read clock pu-~ses
RCR from read clock generator 27 and read command RCD from
counter 71 of system control 23. Further, the outputs of
AND gates 125-128 are connected to inputs of OR gates 116-119,
respectively.
-3~-
109134~
It will be apparent from the above that, when the
read command RCD is received to open AND gate 129, the read
clock pulses RC~ are passed through gate 129 and through a
selected one of the AND gates 125-128 which has been opened
by an output signal transmitted by way of the respective one
of the OR gates 121-124 from decoder 120 in response to the
received finally determined read address FDRA. The read
clock pulses RCR passed through a selected one of the AND gates
125-128 are transmitted through the respective one of the OR
gates 116-119 to the one of the memory units MU~ -MN-4
which has had its respective switch 101-104 closed in response
to the output signal from decoder 120. Thus, the digitized
video information previously stored in the selected one of
the memory units identified by the finally determined read
address FDRA is read out or fetched from such m~mory unit to
the bus 25 in response to the read command RCD and at a
clocking rate determined by the read clock pulses RCK. It
will also be seen that, during the read out of stored video
information from any one of the memory units ~ ~ 4, the
read-out information is fed back to the input of the same
memory unit by way of the respective one of the feedback loops
106-109, the respective one of the switches 93-96 then engaged
with its contact B and the respective one of the switches 97-
100 also then engaged with its contact B.
-4~-
913 4Z
The main memory control 24 is further shown to
comprise a decoder 130 which receives the possible rewrite
address PRWRA from switch 88 of system control 23, and which
is operative to provide a control signal or output to an input
of a selected one of four AND gates 131,132,133 and 134 which
have their outputs connected to OR gates 121,122,123 and 124,
respectively. The outputs of AND gates 131,132,133 and 134
are also co~nected, as indicated at 0,1,2 and 3, to the switches
97,98,99 and 100, respectively, for operating the latter.
Finally, the logic output LG from logic circuit 89 of system
control 23 is connected to other inputs of AND gates 131-134.
It will be apparent from the above that, when the
logic output LG is at its high level '11", such high logic
output is passed through a selected one of AND gates 131-134
which corresponds to the possible rewrite address PRWRA
received by decoder 130 and which has been closed by the
corresponding control signal or output from such decoder, to
a respective one of the switches 97-100 for changing-over that
respective switch to its contact A. Simultaneously, the high
level "1" of logic output LG passing through the opened one
of AND gates 131-134 is further passed through the respective
one of OR gates 121-124 for opening the respective one of
AND gates 125-128. Accordingly, the read clock pulses RCK
are passed through AND gate 129 opened by read command RCD
and through the selected one of A~ gates 125-128 opened by the
high level logic output LG for passage through the respective
one of 0~ gates 116-119 to the memory unit corresponding to the
possible rewrite address PRI~. Therefore, when the logic
1091342
output LG is at its high level "1", the digitized video
information being read out of a selected one of memory units
MU-l---MU-4 corresponding to the finally determined read
address FDRA applied to decoder 120 is fed back through
rewrite loop 105 and rewritten in the memory unit which is
identified by the possible rewrite address PRWRA applied to
decoder 130.
DROP-OUT MEMORY
Referring now to Fig. 7, it will be seen that the
drop-out memory 35 of the time base corrector 10 according to
this invention may comprise four D-type flip-flops (FF)
135, 136, 137 and 138 which respectively correspond to memory
units MU-l, MU-2, MU-3 and MU-4. A decoder 139 receives the
drop-out memory address DOMA from switch 70 of system control
23 so as to provide a control signal or output for opening a
selected one of four AND gates 140, 141, 142 and 143 which
are associated with FFs 135, 136, 137 and 138, respectively.
The drop-out write command DOWCD from switch 92 of system
control 23, that is, the output or pulse from MM 63 passed
through switch 92 when the latter is made to engage its
contact A by the pulse from MM 64, is applied to inputs of all
of the AND gates 140-143. Therefore, a selected one of the
FFs 135-138 corresponding to the memory unit identified by
drop-out memory address DOMA is triggered by the drop-out write
command DOWCD passed through the respective opened one of AND
gates 140-143, so that the triggered one of the FFs 135-138 is
adapted to store the sensed drop-out signal SDO which may
:
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109134Z
' ,
then be received from switch 69 of system control 23 and which
is applied to all of the FFs 135-138. Each of FFs 135-138
provides an output of high level lll" when a sensed drop-out
SDO is stored therein, while the output from each of the FFs
135-13 8 is at a-relatively low level "0"--in the absence of a
sensed drop-out SDO stored therein. The outputs of FFs 135-138
are adapted to be applied through normally open switches 144,
145,146 and 147, respectively, to a common line 148 for trans-
mitting drop-out indications DOI to FFs 81 a~d 85 of system
control 23. Drop-out memory 35 further includes a decoder
149 which receives the read address RA and then the spare read
address SRA from switch 86 of system control 23 and is operative
to provide a control signal or output for closing a selected one
of the switches 144-147 associated with the one of FFs 135-
138 corresponding to the memory unit identified by each address
received by dec:oder 149.
It will be noted that, in drop-out memory 35, AND
gates 140-143 which are selectively opened by control signals
or outputs from decoder 139 to pass the drop-out write co~amand
DOWCD, could be replaced by normally open switches which are
selectively closed by the control signals or outputs from
decoder 139. Further, the normally open switches 144-147 which
are selec~ively closed by control signals or outputs from
decoder 149 could be replaced by AND gates which are selectively
opened by the control signals from decoder 149.
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109~34Z
It will be apparent that, in the drop-out memory 35
as described above, the drop-out memory address DO~A applied
irom switch ? of system control 23 to decoder 139 during the
: pulse or output from MM 64 is the write address WRA applied
~ from counter 66 to contact A of switch 70, while the drop-out
-` write command DOWCD then applied to drop-out memory 35 is the
pulse or output from ~ 63 applied to contact A of switch 92.
Thus, during each writing operation of main memory 21, the
sensed drop-out SDO, if it exists, is stored in the one of
FFs 135-138 which corresponds to the memory unit identified
by the write address WRA and in which the digitized video
information is being written.
In a reading operation of main memory 21, and
assuming that the logic output LG from logic circuit 89 is
at its low level "O", the read address RA' corresponding to
the memory unit from which the video informaton is to be read
~ or fetched is first applied from switch 86 to decoder 149 so
that the latter causes the drop-out information DOI to be
transmitted from the respective one of FFs 135-138 to FF 81
`~ of system control 23, whereby the output of FF 81 indicates
whe~her or not drop-out occurs in the video information stored
in the ~emory unit identified by read address RA'. Further,
in the reading operation, during the interval of the pulse
from MM 84, switch 86 is chang~d-over to its contact A to
supply the spare read address SRA' to decoder 149 with the
result that the drop-out information DOI then transmitted to
.
--44--
` lQ9134Z
FF 85 indicates whether or not drop-out occurred in the video
information stored in the memory unit identified by the spare
read address SRA'. In the reading operation, switch 70 remains
engaged with its contact B so that the address supplied through
r ` switch 70 to decoder L39 of drop-out memory 35 is the possible
rewrite address ~RI~RA obtained from switch 88, that is, the
address RA' if FF 81 indicates drop-out in the memory unit
corresponding to that address, or the address SRAI if FF 81
indicates that the ~emory unit identified by the address RA'
is free of drop-out. Furthermore, if the logic output LG
of logic .circuit 89 is at the high level "1" indicating drop-
out in the memory unit identified by the address RA' or the
address SRA1, switch 90 is closed and ~he output or pulse from
MM 91 is passed therethrough to contact B of switch 92.
Since switch 92 engages its contact B during the reading opera-
tion, the pulse from MM 91 is passed through switch 92 as an
erase command, in place of the drop-out write command D~CD,
to all of the FFs 140-143. The more command is further passed
through the one of FFs 140-143 which is opened by a control
signal from decoder 139 in response to the possible rewrite
address PRWRA then applied to decoder 139, whereby the described
erase command triggers or resets the one of the FFs 135-138
corresponding to the possible rewrite address PRh7RA for erasing
any drop-out information previously stored in such flip-flop.
1091342
VELûCITY ERP~OR MEMORY
Referring again to Fig. 4, it will be seen that, in
the velocity error memory 32 of time base corrector 10 according
to this invention, the velocity error held in circuit 33 is
applied to a fixed contact B of a switch 15û having a movable
contact that normally engages such contact B for supplying the
velocity error to a buffer amplifier 151. The switch 150 is
changed-over to engage a fixed contact A thereof only during
tke rewriting, in a memory ~mit identified by the possible
rewrite address PR~A, of the video information being read out
of a memory unit identified by the finally determined read
address FDRA, as described above with reference to Fig. 6.
More particularly, a normal~y open switch 152 is closed in
response to the high level "1" of logic output LG from logic
circuit 89 so that the read start pulse RST (Fig. 90~ is
applied through closed switch 152 for triggering a monostable
multivibrator (~1) 153. When triggered by read start puls e
RST, M~S 153 provides an output of relatively high level "1"
for about 20 microseconds (Fig. 9T), and such high level output
of ~IM 153 is applied to switch 150 for changing-over the latter
to its contact A. The output of MM 153 is further applied to
a switch 154 having a movable contact which normally engages --
a fixed contact B receiving the output of a digital adder 155
which adds (-1) to the write address lJRA from counter 66 of
system control 23, that is, adder 155 provides the address
-46-
10913~Z
(WRA-l). The switch 1~4 further has a fixed contact A receiving
the possible rewrite address PRWRA from switch 88 of system
control 23 and which is engaged by the movable contact of
switch 154 in response to the relatively high level output of
MM 153. The movable contact of switch 154 is connected to a
decoder 156 which normally receives the address (WRA-l) from
contact D of switch 154, whereas decoder 156 receives the
possible rewrite address PRWRA from contact A of switch 154
when the latter is changed-over by the output of ~ 153 in
response to the high level of logic output LG.
During a normal writing operation of main memory 21
for ~riting digitized video information successively in the
memory units thereof identified by write addresses WFUA,WRA'---
etc., switch 1~4 delivers the addresses (WRA-l),(WRA'-l),---etc.
to decoder 156 (Fig. 9Q). Thus, for example, during the writing
in the memory unit identified by address WRA, decoder 156
applies a suitable control signal or output to the one of
four AND gates 157,158,159 and 160 which corresponds to the
address (WRA-l), that is, to the memory unit in which video
information was written during the preceding writing inter~al
or operation. The falling edge of the output or pulse (Fig. 9J)
from MM 60 in write clock generator 20 is employed to trigger
a monostable multivibrator (~) 161 which produces a pulse of
40 microsecond duration (Fig. 9P) applied th~3ugh an OR gate
162 to all of the AND gates 157-160. Thus, during the existence
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109134Z
of the output from MM 161, the control output or signal from
decoder 156 can pass th~ugh the one of AND gates 157-160
corresponding to the memory unit identified by the address
(WRA-l) and can close a respective one of four normally open
switches 163,164,165 and 16~. Upon closing of a selected one
of switches 163-166, the velocity error held in circuit 33
and which relates to the velocity error occurring durinO a
- preceding writing interval, that is, the interval of writing in
the memory unit identified by address (~RA l), is applied
through switch 150, buffer amplifier 151 (Fig. 9~) and the closed
one of switches 163-166 to a respective one of four analog
memories 167,168,169 and 170, which are shown as grounded
capacitors connected to respective buffer amplifiers 171,172,
173 and 174 having high input impedances. Thus, during the
writing of digital video information in the memory units MU-l---
MU-4 of main memory 21, the velocity error infonmation held
in circuit 23 (Fig. 9L) in respect to the writing in each such
main memory unit, is stored in the next writing interval in
a respective one of analog memories 167-170. The storage of
velocity error information is in the form of a build-up of
potential (Fig. 9R) to a corresponding level on the capacitor
selected by the closing of one of switches 163-166.
In order to provide for the read out of the stored
velocity error information during the normal reading operation
of main memory 21, the finally determined read address FDRA is
applied from switch 87 of system control ~ to a decoder 175
: -48-
109134Z
`' .
in velocity error memory 32. Decoder 175 is operative to provide
control signals or outputs for selectively closing normally
open switches 176,177,178 and 179 interposed between the outputs
of buffer amplifiers 171,172,173 and 174, respectively, and a
common line 180 for applying the read out velocity error
information to the read clock gene~ tor 27. It will be apparent
that, during the readin8 of the digital video information
successively from the memory ~nits of main memory 21 identified
by the finally determined read address FDRA, FDRA'---etc. (Fig.
9S), decoder 175 causes closing of a selected one of switches
176-179 during each reading interval or period for applying
to the common line 180 the stored velocity error information
from the one of analog memories 167-170 corresponding to the
main memory unit from which video infonmation is being read.
When the logic output LG from logic circuit 89
is at its high level"l" so as to cause the rewriting in the
memory unit identified by the possible rewrite address PRWRA
of the digital video information being read out from the memory
unit identified by the finally determined read address FDRA',
such high level logic output LG closes switch 152 so that read
start pulse RST can trigger MM 153, whereupon the output (Fig.
9T) from the latter changes-over switches 150 and 154 to engage
their respective contacts A. Upon engagement of switch 150
with its contact A, the velocity error VE being read out of the
one of analog memories 167-170 which corresponds with the
memory unit identified by the finally determined read address
-49-
109134Z
~DRA' is applied through switch 150 to buffer amplifier lSl
(Fig. 9V). The en8agement of switch 154 with its contact A
causes the possible rewrite address PR~ to be applied to
decoder 156 so that the latter applies a co~ rol signal or
output to the one of AN~ gates 157-160 corresponding to such
address. Since the output of MM 153 is applied th~ ugh OR gate
162 to all of AND gates 157-160, such output from MM 153 passes
thlD ugh the one of AND gates 157-160 receiving a control signal
or output from decoder 156 so as to cause closing of the
respec~ive one of switches 163-166. Therefore, the output of
buffer amplifier 151 is applied th~ ugh the closed one of
switches 163-166 for storage in the respective one of analog
memories 160-170 corresponding to the main memory unit which
is identified by the possible rewrite address PR~RA.
It w:ill be apparent from the above that, during the
rewrite in the memory unit identified by the address PRWRA
of the digitized video information being read out of the mPmory
unit identified by the address FDRA', the velocity error being
read out of the analog memory corresponding to the adress FDRA'
is simultaneously rewritten in the analog memory identifed by
the address PRWRA. Thus, during subsequent reading of the
video information that has been rewritten in a memory unit of
main memory 21, the velocity error memory 32 will simultaneously
provide a velocity error corresponding to that which existed
dlring the original writing of the rewritten video information.
-50-
1~9134Z
.
READ CLOC~C GENERATOR
; Referring now to Fig. 8, it will be seen that the
read clock generator 28 of the time base corrector 10 according
to this invention may include a sawtooth generator 181 which
receives the velocity error signal VE from the output line 180
of velocity error memory 32. Further, the read command RCD
from counter 71 of system control 23 is applied to an inverter
182 having its output connected to sawtooth generator 181 so
that the output of the latter remains zero during the time when
the output of inverter 182 is at a high level "1", that is,
in the intervals between successive read commands RCD. A
sub-carrier signal SC, for example, having the frequency 3.58
~z in the case of the processing of NTSC color video signals,
is applied from the standard sync generator 26 to a phase
modulator 183 for phase modulation in the latter by the output
of sawtooth generator 181. Since the inclination of the sawtooth
wave forming the output of generator 181 is proportional to the
potential of the velocity error signal VE received by generator
181 from velocity error memory 32, the output of modulator 183
is the subcarrier signal phase modulated by the velocity error
signal. The phase modulated subcarrier signal is applied to
a monostable multivibrator 184 which produces a correspondingly
phase modulated s~uare wave signal and the harmonics thereof.
The output of ~M 184 is applied to a band pass filter 185 which
is tuned to the third harmonic of the subcarrier signal SC so
1091342
that the phase modulated output of band pass filter 185 has a
frequency of, for example, 10.74 M~z. Finally, the output of
band pass filter 185 is supplied through an amplifier 186 to
a square-wave former 187 to provide the desired read clock pulse
RCK modulated by the velocity error and which, as previously
noted, determine the clocking rate at which the digitized
video infonmation is read out of main memory 21.
Having described the general arrangement of the
various components of the time base corrector 10 according
to this invention and the details of such components, it will
be noted that, in such time base corrector, the control of the
sequencing of the counter 73 by the digital comparator 74
ensures that, during each reading interval, the memory unit
of main memory 21 identified by the read address RA from counter
73, and hence from which video information is being read, wilL
be different from the memory unit identified by the write address
WRA, and hence in which the video information is being written,
whereby to avoid the so-called double clocking of any one of
the memory units. Further, in the time base corrector 10, a
drop-out indication DOI is provided whenever a drop-out occurs
in the video information being written in any one of the
memory units of the main memory 21 and such drop-out indication
is stored in the drop-out memory 35 in respect to each of the
main memory units. Upon reading out of the video information
stored in the successive memory units of main memory 21, the
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. . .
109134Z
system control 23 causes reading of the video information either
from the memory unit identified by the read address RA provided
by counter 73 or, in the event that the drop-out memory 35
indicates that there is drop-out in the video information
stored in such memory unit at the read address RA, then from
another memory unit identifed by the spare read address SRA.
Thus, actual reading is effected in respect to the memory unit
identified by the finally determined read address FDRA. In
determining the spare read address SRA as being either RA-l
or RA~l, the digital comparator 76 and FF 77 of system control
23 ensure that such spare read address SRA, if it becomes the
finally determined read address FD~A, will not result in
double clocking of the~respective memory unit, that is, the
write address WRA and the finally determined read address FDRA
will not be the same to cause overlapping writing and reading
operations in respect to the same memory unit.
Furthermore, in time base corrector 10 according to
this invention, if it is determined that drop-out exists in
the memory unit identified by read address ~A so that the
finally determined read address FDRA is the spare read address
SRA, then the video information being read ou~ of the memory unit
identified by the address SRA is rewritten in t~e memory unit
having dropout, that is the memory unit identified by the read
address RA which then becomes the possible rewrite address PRWRA.
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1(~91342
''
Conversely, if it is determined that drop-out exists in the
memory unit identified by the spare read address SRA, but not
in the memory unit identified by the address RA, then video
information is actually read out of the memory unit identified
by the address RA and is rewritten in the memory unit identified
by the address SRA. In connection wi~h the foregoing rewriting,
or replacing of video information containing drop-out by video
information free of drop-out, it will be noted that the drop-out
memory 35 is effective to erase the drop-out indication in
respect to the memory unit in which the rewriting operation
is being performed.
It will be further apparent th~t, in time base
corrector 10 according to this invention,~elocity error memory
32 memorizes the velocity errors occurring during the writing
of video information in each of the memory units of main memory
21, and each such velocity error is employed in read clock
generator 28 for phase modulating the read clock pulses RCK
which determine the clocking rate on reading the video information
from the respective one of the memorg units. ~loreover, when
video information from a memory unit at address FDRA is
rewritten ~n a memory unit at address PR~RA, as described above,
the velocity err~r memory 32 is effective to store, in respect
to such memory unit PR~RA, the veloci~y error associated with
the original writing of the video informa~on in the memory unit
at the address FDRA. Thus, the phase modulation of the read
-~4-
t~
; 109134Z
clock pulses RCK will always correspond to the velocity errors
occurring during the writing of the video information which is
being read from a selected one of the memory units, whether
such video information was originally written in that memory
unit or rewritten in the latter so as to replace originally
written video information containing drop-out.
! Although a specific embodiment of the invention
has been described herein with reference to the accompanying
drawings, it is to be noted that the invention is not limited
, . to that precise embodiment, and that various changes and
modifications may be effected therein by one skilled in the
' ar~ without departing from the scope or spirit of the invention
~- . as defined in the appended claims.
'
~ '
. .
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~ ,
