Note: Descriptions are shown in the official language in which they were submitted.
1~3~33
This invention relates to player operated game appara-
tus and particularly to a game apparatus employing multiple dis-
play means actuated in response to player manipulated and con-
trolled movement of elements and particularly to a pinball game
apparatus and the like.
Pinball type game apparatus is widely employed in
various recreational establishments. Uniformly, such games employ
the ejection of a playing ball to the upper end of a downwardly
inclined playing field. The ball moves down under gravity forces
through a maze of alleys or lane forming elements, target bumper
elements of various forms and the like. The movement through the
lanes and into engagement with several bumpers, lane switches and
the like complete suitable circuits to activate suitable display
and scoring mechanisms. The operator can partially control the
movement of the ball by limited jarring of the playing field and
generally through the activation of manually operated flipper
- control means which operate one or more dispersed pivotally
mounted flipper arms on the upper surface of the playing field.
Such games are widely available in many different formats and
arrangements. They almost universally, however, employ a struc-
ture with an upright back panel on which game indicating lights,
digit scoring and the like are displayed along with general
pictoral information with suitable illumination. Audible devices
such as bells or chimes are also normally incorporated to respond
to selected targets within the playing field. In addition,
scoring openings in the playing field have switches to indicate
receipt of a ball and automatic rejecting means to propel the
ball back onto the playing field. Such devices are generally
coin-operated and may providefOr multiple operation whereby two
or more players can sequentially play the game, with individual
indication of the player, as well as individual scoring and the
like for limited competitive purposes. In such games various
10S~3~3
cc~trols must of course be provided to control the response of
the system as well as providinq interlocking controls for example
in response to insertion of proper coins and the like to activate
the system including the flipper controls. Further the game will
normally include an automatic tilt whereby an unacceptable jar-
ring of the playing field results in a termination of the game.
Such apparatus with the several elements as described
have been constructed for many years employing hard wiring of
the game system through an electro-mechanical control. Thus the
various target input switches are connected directly to selectively
control the target lights. Similarly, the flippers may be pro-
vided with release devices responsive to the proper introduction
of coins to actuate an electrical interlock. Although such sys-
tems have been widely employed, they have been relatively expen-
sive not only in initial cost but in subsequent maintenance.
Further, any single construction is essentially related to a
single game plan and thus for providing a great variety of games,
significant individual design requirements exist. Further, if a
game once designed and marketed is not readily accepted, it can-
not be readily and conveniently changed to overcome any of the
assumed undesirable features. Such games are, of course, in
such demand, however, that they are widely manufactured and sold
even with present marketing restrictions and constraints. There
is however, a need for a method of simplifying the game design
` 25 and apparatus which will permit the manufacturer to adapt to
rapidly changing market conditions and requirements. Of course,
the game apparatus should provide economy in construction as well
as in the maintenance and operating costs.
Summary of the Present Invention
The present invention ïs particularly directed to
such game apparatus wherein movement of an element is selectively
and partially controlled with respect to element activated res-
1~3ti~3
por.se devices, which in turn are connected in an isolated con-
nection to activate automatic display means such as visual and/or
audio means and the like wherein both stimulatory and numerical
scoring display are provided. As the present invention is
uniquely applied to and develops an unique pinball game apparatus,
the invention is described in connection therewith for purposes
of reference. Generally, in accordance with the present inven-
tion, the display means, the element activated response means,
and the interlocking control means are arranged into sequentially
activated element groups and connected through a matrixing or
multiplexing means to a programmed logic means such as a micro-
processor to provide a highly improved control and response of
the game apparatus. The multiplexing means sequentially couples
the activated elements in the system at a sufficiently rapid
repetitive rate to effectively present a continuous monitoring
and presentation of the several display means, producing inter-
connection of the response means and operation of the interlocking
control means to properly monitor, score, and display during each
cycle of the program. The processing system permits significant
cost reduction in the initial construction as well as convenient
changes in the basic approach of any given structure. Generally,
in accordance with the present invention, the playing field is
constructed in accordance with the usual construction to develop
a plurality of lanes, response target devices and flipper ele-
ments. The several elements activate switch means and establishsignals to a common matrixing or multiplexing circuit. A pro-
grammed logic array means rapidly and in cyclical manner scans
the input lines coupled to the switch means and detects the de-
vice operation and subsequently correspondingly activates within
each cycle the proper visual output of display means which in-
clude the conventional visual display lamp means, audible means
or visual display means as well as a digit display. In accord-
~0S`36~3
ance with a particular aspect of this invention the digit display
is developed through a suitable line segment generator. The
switch means are thus connected to place the switch information
into a memory system, the output of which is connected through
S the same matrix board to activa~e the desired visual and
audible devices including visual display lamps, scoring digit
display means as well as audible devices. The switch means fur-
ther include interlocking monitoring means to determine the status
of the apparatus with respect to, for example, the tilt condi-
tion, the receipt of an appropriate input such as coins, credit
condition, automatic additional game incentive in response to
previous games scoring and the like during each cycle and oper-
able to provide a priority type control to the program logic
array. This information is also fed through the matrix board
into the memory unit, the output of which is selectively con-
nected to the same matrix board. The output from the multi-
plexing or matrix board is further interconnected to the lamps
and to the control solenoid to release the apparatus for play
to thereby provide complete interlocking control through the
memory and the matrix unit. The programmed logic array is a
sequential logic microprocessor with the input lines of the
matrix board sequentially scanned on a repetitive basis with the
ln~ormation transmitted to the interlocks and to the display
means to activate the device or the game apparatus in accordance
with theinputs and the memory. The repetition rate or frequency
is sufficiently rapid to maintain the presentation and activa-
tion of the output means as if a direct pass through of the in-
formation from the switches to the output and control devices
was established.
The invention thus provides a convenient means for
maintaining a generalized logical control for a game apparatus
employing the advantages oi' a small memory system which can, of
1~3tj~3
course, be readily adapted to a conventional software control of
the game responsein accordance with a relatively fixed field
memory.
More particularly, in a particular unique implemen-
tation a small microprocessor is suitably housed in the back
housing wall or box of a pinball unit and coupled through a six-
teen slot matrix board to a read only memory for activating of
the displa~ means and sensing of the various switch conditions
in combination with a continuous test and interlock system to
maintain interlocking contrGl ofthe system while play is in op-
eration and storing of the condition with respect to subsequent
play of the apparatus. More particularly, in accordance with a
particular constructional novel feature and embodiment of the
present invention, a multiplexing circuit is driven from a ran-
dom accëss memory to sequentially activate a plurality of multi-
plex input lines on a continuous cyclic basis and a similar para-
llel decoder is preferably coupled to condition a main driving
power output as connected to operate the several playing compo-
nents.
Processing will further normally include a step com-
mand signal to simultaneously activate the multiplexing decoder ,
or sequencing system and simultaneously control the interfacing
drive to the display means to maintain precise synchronous re-
lationship. This is particularly significant to permit the use
of relatively minimal number of driver transistors or the like.
The multiplexing output lines are coupled to provide information
to the random access memory and to drive the several lamps, in-
terlocks and control means. The lamp circuits include suitable
low beta driver transistors in series with low voltage lamps,
with a driving voltage significantly greater than the rated vol-
tage. The circuits are completed once each programmed cycle and
produce momentary high current lamp energization. However, the
1()~3t~93
average current is normal and the lamps will operate without
adverse effect and at a significant economy. Further, the tran-
sistors of limited capacity produce inherent current limiting on
cold lamp start to further increase lamp life and are less ex-
pensive than higher capacity transistors. They, therefore, pro-
vide an inexpensive switch which can be readily and satisfactorily
applied in the game apparatus to again provide maximum economy.
The input Or response switch connection to the programmed logic
array for storage of the actuation thereof is also uniquely pro-
vided in another feature or aspect of the best embodiments toproduce noise immunity. Thus, the switches are connected to
ground the inputs through the transistor switch means. The
turn-on time of the transistor inserts a time lag in the circuit
to the input switches, which are coupled to the same scan line
of the matrix circuit, and effectively makes the response immune
to "noise" or transients created in the switching.
Generally, in a highly practical construction a four
input port responds to the several playing field inputs to record
the play while a four output port provides means for driving of
the lamps and selected auxiliary equipment. A further output
port provides a drive means to the scoring boards and other
auxiliary equipment. In addition, a separate text input line is
connected into the circuit through the multiplexing lines to
maintain a continuous monitor and an interlock of the system for
subsequent play. Thus, the credit condition, as a result of
coins, is maintained and provided to sense the activation of
such switches. The test output is connected to the computer
interrupt and operates the interrupt when a corresponding multi-
plex line is actuated to provide for the automatic recording of
such information. For example, it is, of course, essential that
any COill introduced by any player be automatically recorded and
credited. The test line will respond to such a condition to
1{~33~93
momentarily interrupt the usual sequencing and automatically
maintain a continuous record of the credit conditions. Simi-
larly, a tilt condition will take precedence and provide auto-
matic processing of the tilt condition.
The multiplexing system develops the same input-
output ports providing various functions on a timed division
multiplexing control. The scanning rate will generally be held
to a minimum of 50 or 60 cycles per second which is above the
minimum flicker rate of a conventional display means and insures
a continuous display presentation with the scanning concept.
In accordance with a further aspect and novel em-
bodiment of this invention, the interfacing between the switches
and non-lamp outputs without suitable thermal inertia includes
suitable opto-isolator devices or the like which inherently in-
troduce an automatic memory or storage function to permit the
continuous scanning or cycle control concept as applied to the
game apparatus.
Thus, generally Applicant has found that the present
invention provides a highly improved game apparatus having means
to permit significant simplification in the initial cost and
particularly pinball-type game apparatus and the like with the
production cost and maintenance of the apparatus minimized and
further readily adapts to practical commercial implementation.
Brief Description of the Drawings
The drawings urnished herewith illustrate a pre-
erred construction of the present invention in which the above
advantages and features are clearly illustrated as well as others ~
which will be readily understood from the following description. ~ -
In the drawings:
FIG. 1 is a pictorial view of a typical pinball
machine apparatus;
FIG. 2 is a block diagram showing the various portions
1093~3
of the game apparatus in block diagram with line interconnection
between the several components;
FIG. 3 is a side view diagrammatically illustrating
the component mounting and housing construction;
FIG. 4 is a diagrammatic illustration of multiplexing
arrangement for a particular pinball game unit as shown in
Fig. l-3; and
FIG. 5 is a circuit diagram illustrating a typical
known computer system interfaced with the game circuit, portions
of which are schematically shown to clearly illustrate the pres-
ent invention.
Description of the Illustrated Embodiment
Referring to the drawings and particularly to Fig. l,
the present invention is illustrated applied to a typical pinball
game machine l including an upper game field cabinet 2 supported
by a plurality of legs 3 which locate the cabinet 2 approximately
at waist height of the usual game player. The cabinet 2 includes
a glass top 4 beneath which a playing field 5 is located. A
manual ball feeding mechanism 6 is shown to the front for eject-
ing of a round ball 7 to the upper end of the playing field 5
from which it rolls downwardly under gravity forces across the
playing field. In accordance with the usual constructions, the
playing field 5 includes left and right lane walls 8 adjacent
the outer edges of the field 2, with suitable switch lever means
9, right and left bumpers lO, as well as targets ll and scoring
opening 12 with lever means, all located within the playing field
2. The bumpers lO and openings 12 operate to propel the ball with
a rapid movement depending upon the direction from which the
bumper engaged the members and establish various scores when en-
gaged. Further, when the elements are engaged by the ball 7 to
provide additional scoring, various lights and audible display
means are energized to indicate the response element. For
1(J~3~i33
example, a target or a lane lamp may be aetivated as the ball
engages a corresponding portio~ of the playing field. In
accordance with more conventional construction, the apparatus
also includes manually operated or controlled flippers 14 pivot-
ally mounted to the bottom portion of the playing field. The
flippers 14 pivot for engaging the ball 7 and returning it up-
wardly on the playing field 5. The flipper controls are conven-
tionally in the form of right and left buttons 15 provided on
the corresponding side walls of the cabinet 2 for manual opera-
tion by the operator.
Further, in accordance with conventional construction,
the apparatus shown in Fig. 1 includes an upstanding back eabinet
16 which is normally glass covered and provided with a suitable
decorative material thereon. Player indicating means 17 provides
visual presentation of whether player #1 or player #2 should be
playing as a result of the operation of the machine, a player re-
lated total score area 18 for providing a continuous updated
score in digital display for the respeetive players. A special
tilt notice 19 will normally be provided and illuminated if the
eabinet is unduly lifted jarred or the like. Various other il-
luminating lamps to indieate a partieular seore being added to
the total seore as a result of a target engagement and the like
may also be provided. Obviously, the game apparatus may vary
widely with respeet to the partieulars of the presentation in
aeeordanee with thé movement of the ball down through the field
and into engagement with the various response devices, but all
units basically require switeh input means, lamp means and digi-
tal or number scoring means which are interconnected to produce
a visual display and seoring of the play.
A typical system is diagrammatically ~llustrated in
a matrix form in Fig. 4 for purposes of fully describing a pre-
ferred embodiment of the present invention.
_g_
1~3~j~33
In addition, a coin receiving means is provided to
limit playing of the game to the introduction of coins. In the
illustrated embodiment of the invention, a pair of redundant
coin acceptors 20 are provided, to minimize service requirements.
Introduction of the coins into either coin acceptor 20 will con-
dition the apparatus for the first and second players with the
response providing for automatic and alternate play and scoring
for the two players. Access to a coin box, not shown, is
provided by a locked front door unit 21. The embodiment shown
is thus generally typical of the conventional pinball game ap-
paratus. The present invention is particularly directed to the
mounting and interconnection of such input switch means, the
lamp means, the digit scoring display means and interlocking
controls through a special connecting board 22 to a programmed
logic array means 23, as diagrammatically shown in Fig. 2 and 3.
The logic array means 23 and board 22 are constructed as a small
compact assembly which is readily mounted within the back cabinet
16. The location of these elements provides extremely convenient
construction and subsequent servicing of the interconnection
to the several components of the playing field 5, on the coin door
21 and elements located within the lower play field cabinet 2
and identified in Fig. 2 as the lower cabinet by block diagram
24. The various components and logic array means for controlling
the apparatus are coupled through a motherboard and the coin door
for main control thereof. The board further provides interconnec-
tion to drive the display of the back panel and simultaneously
to activate the panel to receive signals from the playing field
switch means and to provide control to the several components
of the playing field.
Thus, Fig. 2 is a general layout of the apparatus in
accordance with a teaching of the present invention to more
clearly illustrate and describe a preferred system shown in
--10--
3~i~3
Fig. 4 and 5, and Fig. 3 illustrates the structural mounting of
the components.
Generally a main power supply connection from a main
AC power supply line 25 such as conventionally employed in
utility distribution systems in the United States provides main
power to the system through the lower cabinet 2. The output
power is applied directly to pilot lights at the coin input units
20 to indicate the apparatus is in operating condition and si-
multaneously providing power through the mother board 22 to the
several operating components. An interlock acceptor is provided
to control the coin units 20 and to permit the introduction of
coins only if the apparatus is in proper condition for play.
If such signal is received, the apparatus will allow the intro-
duction of coins through either the left or the right coin re-
ceivers 20 and provide automatic actuating of a coin counter27a within the lower cabinet 2 which transmits such information.
This information is automatically transferred into a memory means
forming a part of the programmed logic array unit 23 within the
back cabinet 16 and which then activates the play field 5 and
associated components to permit operation of the game if all
other conditions are proper. The field 5 includes a general il-
lumination means for the playing field as well as the target
score lights which are operated when the target 11 is engaged.
The flippers 14 and the bumpers 10 have interlocking solenoids
secured to the underside of the playing field 5 and only acti-
vated during ganle play. The input or response switches of the
play field 5 are connected to baard 22 for signaling of the com-
puter means 23, the back panel 16 receives appropriate general
illumination at the start of the game to illuminate the back
board which may of course change during the play if desired.
In addition, an individual signal is transmitted to the game and
player indicators 17 and to the score indicator 18.
--11--
10~3~i93
The lower cabinet 2 within which the playing field 5
is housed will additionally be provicled with certain auxiliary
equipment such as individual audible devices such as chimes 32
to respond to certain target engagements and operable to provide
an audible as well as a visual signal. The cabinet 2 further
includes the coin switch 27a to sense the coins as received and
transmit the signal to the computer in accordance therewith.
The coin door may incorporate a switch means 33 responding to
knocking of door 21 in an attempt to artificially actuate the
coin switch. Flipper switches 34 which are coupled to buttons
15 indicate the operation of the right and left flipper and are
coupled through the lower cabinet to board 22. Similarly, a tilt
response mechanism 35 such as a rolling contact ball, a pendant,
switch arm or the like is provided in the lower cabinet to act-
ivate the apparatus and terminate operation of the game if ex-
cessive tilting or jarring Qf the cabinet 2 occurs such as would
normally be considered undesirable and indicate abnormal rough
usage.
The present invention is particularly directed to
the concept of employing a simple programmed logic and memory
device 23 in combination with a multiplexing board 22 to provide
a unique simplified and reliable logic control of the response
to the playing field of the game apparatus. The device 23 es-
sentially has a data input port connected to a switch input
means for receiving the signals from the several switch means, a
second input port to receive a monitor or test line 37 which
continuously monitors significant conditions such as the tilt
respon`se means 35 and the operation of the coin units 20. In
addition, a plurality of output ports are connected to transmit
control and operating data from the computer memory and pro-
cessing means to board 22 for transmission to the various ele-
ments of units 5, 16, 21, and 24.
-12-
~0~3~;~33
j .. ~;
The system is particularly described in connection
with a preferred embodiment such as shown in Fig. 4 and 5.
Generally, in accordance with the present invention, the inter-
facing board 22 employs a time scanned multiplexing connection
to directly and separately interface the input from the playing
field 5 and the input to the back panel and to the playing field
to isolate the contacts from the inputs which inherently include
"noise" signals and thereby provides a reliable control system
to respond to the movement and action of the playing ball 7 and
associated elements. Referring particularly to Fig. 4, a time
division multiplexing system is diagrammatically shown including
sixteen multiplexing drive lines 40 coupled to and driven from `!
the logic array device 23 for the sequential stepped operation
of the multiplexing circuit on a repetitive sequential and
cyclical basis. The sixteen drive lines 40 may be identified
conventionally for example in a hexidecimal system by the iden-
tifying digits zero through nine and identifying letters A
through F. Each of the lines 40 are connected in a matrix to a
plurality of input-output ports 41 connected to the several in-
put switches, lamps and controls of the playing apparatus as
shown in labeled block diagram in Fig. 4. A separate output
unit 42 is activated during each cycle of the logic unit 23 to
control and energize a plurality of individually powered elements
such as the chimes 32, the bumper solenoids 30, ball-hole reject
solenoids and the like which require continuous, non-multiplexed
activation, as noted in the labeled blocks. In the embodiment
- of Fig. 5 the output bank or unit 42 includes 16 possible outputs
and thus is conveniently shown in Fig. 4 with the matrix or
multiplexing unit 41.
In Fig. 4, the several elements of the matrix system
or unit 41 have been shown in labeled blocks and grouped generally
in accordance with the port connections for interfacing with the
-13-
10~3~3
programmed logic unit 23. Thus, the several indicating lamps
and solenoid controls are grouped and connected to a first set of
output ports 43 connected in circuit through similar port con-
figuration. A separate output unit 42 is activated during each
cycle of the logic unit 23 to control and energize a plurality
of individually powered unit elements such as the chimes 32, the
bumper solenoids 30, ball-hole reject solenoids and the like which
require continuous, non-multiplexed activation, as noted in the
labeled blocks. A set of input ports 44 are connected to the
switch means of play field 5 as well as certain feedback signals
for updating the memory unit during any given game or interrelated
series of games. A test line port 45 is coupled to continuously
monitor the state of the identified selected switch means and
provide a direct input to the computer means to interrupt and
transfer vital information at any point in the game process.
Thus, if a coin is introduced into the unit, credit must be given
therefore. If the game apparatus is tilted, the condition must
be monitored and the signal essentially immediately transmitted
to terminate game play directly to computer means. The test line
port 45 provides the means for continuously sensing certain
selected priority switches and providing interrupt at any time
in each scan cycle to immediately process and properly update
the machine memory for appropriate play of the game. A final
port 46 is connected to drive the scoring display means for the
respective players as well as to indicate to the control any ad-
ditional games established in the credit system.
In the system the multiplexing lines 40 are sequen-
tially activated fromthe MUX line 0 and through the MUX line F
and at each activation, the several ports 43-46 are thus acti-
vated to appropriately drive the several indicating lamps orother elements and to transmit game condition information to the
computing Means for processing in the conventional manner.
-14-
1~3~t33
As more fully shown in Fig. 5, the interfacing between
the multiplexing circuit means of Fig. 4 and the logic array or
means 23 permits the use of any desired sequential logic micro-
processor which has suitable read only memory chips for operating
of the elements and a suitable random access memory for appro-
priately processing the information received, and activating the
multiplexing lines 40 and the separate driver or output unit 42.
Thus, as shown in Fig. 4 and more fully shown in
Fig. 5, the apparatus is adapted to be driven from any suitable
sequential logic unit and is preferably a microprocessor includ-
ing a read only memory which is preset to operate the various
elements in accordance with the actuation of the response means
and a random access memory interconnected by a processing unit
to process the game information.
In the illustrated embodiment of the invention, the
sequential logic unit is shown in block diagram as a suitable
microprocessor 50 such as that manufactured and sold by the
Intel Corporation of Santa Barbara, California and particularly
identified in their "Intel MCS-40 User's Manual For Logic
Designers" and identified by their number MCS-335A-175/15K, which
was published and copyrighted 1974. Generally, as more fully
disclosed in the Intel bulletin, the microprocessor 50 includes
a central processing unit 51 coupled to a random access memory
unit 52 and to a read-only memory unit 53 via an I/0 cable 54.
The memory units 52 and 53 are activated from control lines 55
and 56 from unit 51 to produce a predetermined programmed se-
quence proceeding through the various functions required to con-
trol and play the game apparatus with appropriate subroutines for
selected portions such as those responsive to an interrupt input.
In the actual construction, the read-only memory 53 is formed on
individual chips each of which also includes individual input-
output ports for interfacing of the microprocessor with the game
-15-
369~3
apparatus. An I/O circuit 57 interfaces the microprocessor
system 50 and peripheral coupling registers 58 - 60. More
particularly, a lamp driver register 58, a digital display
driver register 59 and a response input register 60 are connected
to the microprocessor system 51 via an input-output circuit 57
and coupled to the ports 42, 46, and 44 of the multiplexing cir-
cuit through appropriate interfacing means, as presently
described.
The game apparatus, as more fully developed herein-
after, basically comprises a plurality of response means provid-
ing input information for selectively driving a plurality of
lamp loads and digital display means which may be relatively low
level direct current loads as well as main power loads such as
the solenoids for chimes, coin counter main game controls and
the like.
The interfacing between the microprocessor and the
game apparatus in the illustrated embodiment of the present in-
vention includes a suitable decoder 61 to develop the necessary
sequential and repetitive activation of the multiplexing input
lines 40 and sequentially within a processing cycle, the activa-
tion of a second decoder 62 for controlling unit 42 and particu-
larly, the high level power drivers.
More particularly, in the illustrated embodiment of
the invention, the central processing unit 51 is connected to
the random access memory unit 52 and to the read-only memories
in the usual configuration. The output of the random access
memory unit 52 is connected to the pair of decoders 61 and 62
sho~n as one to sixteen decoders. The first decoder 61 includes
sixteen outputs connected as the input to the multiplex lines 40
for sequentially and repetitively conditioning of the multiplex-
ing channels 41 for response. The second decoder 62 includes a
plurality of outputs connected to the multiplex port 42 to selec-
-16-
1~36~3
tively supply po~er for driving of the heavy AC load such as the
chimes, coin acceptor and the like on a continuous, non-multi-
plexed basis. The two decoders 61 and 62 are strobed by indivi-
dual command or control signal lines 63 and 64 from the central
processing unit 51 which will, of course, transmit appropriate
information from the random access memory unit 52 to the appro-
priate decoder prior to the strobing thereof. In addition, the
processing unit 51 includes an interrupt unit 65 which is con-
nected directly to the test port 45 of the multiplex circuit and
monitors the corresponding points during each activation of the
related multiplexing input lines 40. The computer processing
unit 51 in accordance with the usual functioning responds dir-
ectly to any condition requiring immediate attention such as
the tilting of the apparatus, the accepting of coins in order
to ensure the appropriate crediting of such input to the apparatus.
Generally, the interfacing to the game elements includes
a lamp driver decoder 66 which provides four output lines, one
for each of the lamp driving ports 43 of Fig. 3. Lamp drive 66
is coupled to register 58 via an output bus 67 and is strobed
from the decoder control line 63. In the illustrated embodiment
of the invention, the interfacing is completed by a seven line
segment decoder 69 provided for driving of the several digit dis-
play units or locations coupled to port 46. The output register
59 provides a four bit signal to the segment decoder 69 having
seven output lines 70 to couplers 71 for selectively energizing
the appropriate segments of the several units. The couplers 71
are connected to the multiplex lines 40 for sequential enabling
and displaying of the particular digit in the seve~al units.
The segment drive register 69 is simultaneously strobed
with the lamp drive register 66 from strobe line 63 which
strobes the multiplexing line decoder 61 such that the corres-
ponding output lines are activated in synchronism with the act-
-17-
ivation of the multiplex input lines 40. The devices thus con-
jointly operate to provide a corresponding circuit path through
the input or steering means at the particular intercept point of
the multiplex circuit.
More particularly in the embodiment of Fig. 4, the de-
coders 61 and 62 are shown as one to sixteen decoders with inputs
connected to a common output bus 72 of the random access memory
52 and individually strobed by control lines 63 and 64. The
multiplexing input line decoder 61 providing sixteen outputs con-
nected respectively to the multiplexing input lines 40 which are
individually identified as MUX o through F as shown in Fig. 4.
The one to sixteen decoder 61 for generating of the
multiplexing input signals to line 40 is connected to the output
of the random access memory 52 and provides for the activation
of the decoder in an appropriate manner for activating of the
MUX drive lines O through F. The actual activation of the MUX
line is controlled by the processor sending a strobe signal via
line 63 to the decoder 61. The logic unit thue provides for the
repetitive activation of the lines during each programmed cycle.
Thereafter, the second decoder 62 receives input from
the random access memory 52 in accordance with the response means
for selectively activating of load solenoids for the several com-
ponents connected to the power port 42 on a continuous non-
multiplex basis.
The second decoder 62 is coupled to directly drive
load elements via the port 42 through outputs activated during
the cycle and in practice after the first decoder 61 has com-
pleted the scan of the matrix by activation of line o through F.
In the illustrated embodiment of the invention, decoder 62 in-
cludes eleven output ports or lines 73 for selectively control-
ling of the several elements coupled to port 42, which as shown
in Fig. 4 includes a first "O" or vent portion and thereafter
-18-
~3~;~33
three chime solenoids, left and right ~umper and pot solenoids,
ball ejection solenoids for the "out" hole and the 3,000 hole as
well as the solenoids for the door-knocker, the coin counter,
and the coin accepter. Each of the circuits is essentially the
same with a couple of circuits shown in Fig. 5 and the circuit
described for the ten chime unit 74 which is connected to the one
decoder output line 70. The chime unit 74 includes an operating
solenoid 75 having one side connected directly to a 50 volt AC
bus 76. The other side of the solenoid 75 is returned to ground
through a gates switch device, shown as a triac 77. The gate of
the triac 77 is connected to the decoder line l of lines 73, the
"O" line providing a "rest" or off position when no unit is to be
energized, of the one to sixteen decoders 62. In operation, if
a signal has been received, as hereinafter discussed, to activate
the ten chime unit 74, the processing unit 51 will have encoded
the decoder 62 for establishing a control signal at the appro-
~ priate decoder line 73. The control line 64 will simultaneously
- activate the decoder 62 to energize the number ten chime 74.
The triac 77 may, of course, respond on either half of the alter-
nating current signal and will maintain energization until the
decoder is latched or reset to "O" or "rest" by the microproces-
sor. The solenoids for the several other elements with the ex-
ce~;o~ of the coin acceptor are connected via port 42 to the
several individual lines 73 and activated in a corresponding
manner in accordance with the information provided to the pro-
cessing unit and thus placed in memory unit 52.
The coin acceptor unit 78 is driven from the eleventh
output 73 of the triac drive port 42, and is coupled into the
circuit through the lamp driver 66 to insert a memory to posi-
tively maintain the acceptor operational during and betweeneach cycle. Thus, the coin acceptor 78 includes a solenoid 79,
the one side of which is connected to the fifty volt AC bus 76
--19--
~(~936~3
with the other side returned to ground through a triac 80. The
triac 80 in turn is controlled by the gate signal from the line
73 of the triac driving decoder 62, with the connection coupled
to the lamp driver 66 through an opto-isolator unit 81. The
gate of the triac 80 is connected to a suitable low voltage
source, such as 12 volt source in series with a current dropping
resistor 82 and a sensing resistor 83 of the opto-isolator unit
81. The resistance of sensing resistor 83 is normally of such a
level as to hold the triac off. A lamp element 84 of the opto-
isolator unit 81 has one side connected to line 73 of decoder 62
via port 43 and the opposite side connected in series with a
steering diode 85 to the one output of lamp driver 66. If the
lamp driver 66 is simultaneously energized with the decoder out-
put, the lamp 84 is illuminated and the resistance of resistor
83 reduced. The gate current will increase and the triac 80 will
turn on. The opto-isolator unit 81 will inherently maintain en-
ergization as a result of the illuminating characteristic and
thus provide for continued operation of the coin acceptor 78.
The lamp driver 66 is shown as including four outputs
connected to port 43, and is coupled to the processor input-out-
put unit 57 via register 58 to provide for selective energi2ation
of the ports in accordance with the random logic control. The
processor will selectively activate the ports 43 in synchronism
with the activation of the corresponding MUX lines 40 in accord-
ance with the activation of the response means. Thus as shown in
Fig. 4, the lamp driver controls various lamp circuits for indi-
cating various scoring lamps, target lamps, the flipper lights
and the like. Each output port 43 is similarly connected and
one circuit is schematically shown in detail in Fig. 4.
In the illustrated embodiment, the output of the lamp
driver 66 produces a logic signal to a transistorized switch unit
86 shown including a control transistor 87 having its base con-
-20-
~93~93
nected to the lamp drive output line of port 43 and its emitter
connected to ground. The collector is connected to control a
pair of Darlington connected power transistors 88 having the em-
itter connected to a suitable power supply, such as a twenty-four
volt supply, and the collector connected as the lamp driver "O"
input of the output ports 43 to the multiplexing network. The
"O" driver is also connected to and is part of port 42 via
diode 85 to energize the opto-isolator 81. The lamp driver 66
otherwise controls the several visual display lamps as shown in
Fig. 4. For example, when the MUX "O" line 40 is activated,
the lamp zero drive line will not be activated, or if activated
inoperative, as there is no load connection at such point. When
the MUX "1" line 40 is activated, the lamp driver "O" port 43
will be activated if the "A" lamp is to be energized. The pro-
cessor in turn will determine whether or not the "A" lamp is tobe energized in accordance with the the input signal indicating
whether the "A" target has been activated, as hereinafter des-
cribed. The several MUX lines O - F each are similarly connected
to ground by a transistor 88 which is turned on by the operation
of decoder 61. Transistor 88 is shown in a grounded emitter con-
figuration with the collector connected to the MUX lines.
` At the MUX "1" line of input lines 40, the "O" port
43 is connected by a diode 89 in series with the "A" lamp 90 to
the MUX `'1" line 40. When both the MUX "1" line 40 and the lamp
driver "O" line 42 are simultaneously activated, the circuit will
be completed and the lamp 90 energized, visually displaying the
operative engagement of target "A". In accordance with a unique
and particularly practical aspect of the illustrated embodiment
of the invention, the lamp 90, and other similar lamps, are low
voltage incandescent lamps having a rating significantly below
the supply. Thus, where a 24 volt supply is employed, conven-
tional 6 volt incandescent lamps, which are readily available
1093~93
and very inexpensive, are employed. Each lamp is thus driven
significantly above the rating and will draw significantly greater
current. For example, the current and voltage will both be four
fold and the power will increase sixteen fold. However, the
lamp is only momentarily energized during each scan cycle and
with the sixteen line matrix for a period of 1/16 the cycle
time. Thus the average current is reduced to 1/4. This duty
cycle is readily accepted by the lamps to produce the desired il-
lumination without adversely affecting the practical life there-
of. However, the effective reduction in the average currentplaces a significantly smaller load on the connectors and the
like and will in fact improve the life of the unit and minimize
maintenance and service.
Further, in this system, the transistor 88 is delib-
erately selected as an inexpensive, relatively low Beta transis-
tor. For example, the power Darlington transistor may have a
Beta of 1,000. The transistor 88 then acts as a current limit--
ing element for the lamp 90 during the initial turn-on thereof.
Thus, the cold lamp would tend to draw an abnormally high current,
which, of course, would adversely affect the connectors and
other components as well as the lamp. The low Beta and low cost
transistor limits such current. The transistor can readily
absorb the voltage which, of course, appears across the emitter
to collector, once again because of the very short duration of
time.
The system may, therefore, advantageously be con-
structed withstandardized and commercially available parts which
can also be readily and conveniently serviced.
The operation of the multiplexing decoder 61 thus
moves down the matrix, indicating the corresponding activation
for the not "A" lamp, the left extra ball, the zero hundreds,
the four hundreds, the eight hundred, the zero thousands, four
1~9~ 3
thousand and eight thousand lamps, as shown in Fig. 4, such units
are connected directly to the lamp drive as illustrated.
The "1", "2", and "3" output ports 43 similarly provide
for activation of related lamps as identified in Fig. 4 with each
5 of them being connected in circuit in the same manner as that
described for the "O" port and as schematically shown in Fig. 5.
In addition, the flipper control switch means 91,
coupled to the side mounted buttons 15 of the game apparatus 1,
are connected in circuit via the lamp ports 43 and particularly
10 the "2" port. The flipper control switch means 91 are connected
in series with the gate circuit of triac switches 90 and to the
low voltage power supply by an opto-isolator unit 93. The flip-
per solenoid 94 is series with the triac 90 to the 50 volt A.C.
bus 76. The lamp input of the opto-isolator unit 93 has one side
connected to the lamp driver switch 92 of the "2" port 43 and the
opposite side connected to the MUX "O" line 40 via a load 95.
The flippers 15 are thus continuously enabled as long as the game
apparatus is conditioned for play.
The input ports 44, on the other hand, are connected
to the input network 68 which as shown in Fig. 4 includes indi-
vidual passive resistive branches 96 to scale the signal to an
appropriate level for input to a computer input register 60. In
the illustrated embodiment of the invention, four input lines 44
are illustrated, each of which is connected by a corresponding
branch 96 to the computer input register 60. Each input line 44
in turn is connected in common to one side of individual response
switches 97 for the various respons,ive elements and connected
incircuit through the several multiplexing input lines 40. Thus,
the "O" input port 44 and MUX "O" line 40 are coupled to a left-
lane target as shown in Fig. 4, and a left-lane target switch 97
in Fig. 5. If the ball 7 engages the left- lane target 9,
it will close the switch 97, thereby completing a
--23--
1C)S~3~J3
circuit through a steering diode 98 between the MUX "O" line 40
and the input register network 68, efEecting a grounding and
thereby developing a signal at the input line to the register
60. When the MUX"OI~line is activated, the signal is transferred
to the computing processing unit 51 for storage in the random
access 52 and subsequent processing resulting in automatic acti-
vation of the appropriate score as the unit sequences through
each processing cycle. The several input switches 97 are con-
nected to ground through the same transistors 88 which return
the several lamps 90 to ground. As previously described, with
the lamp cold, the tran~istor 88 functions to limit the current
until the lamp becomes hot and is turned fully on. This voltage
also holds the switch 97 above ground for a corresponding period.
This functioning introduces a practical degree of noise immunity
into the system such that the switch can be driven from a noisy
source. Thus, the transient or noise components generated with-
in the source or the switch will settle out before the switch
drops to ground and signals the input register. This again con-
tributes to an inexpensive and reliable interfacing to the pro-
grammed logic unit and thus provides for practical implementa-
tion of a programmed game apparatus.
The scoring displaying is accomplished through the
scanning of the input line 40 and port 46. Each target and the
like is preassigned a predetermined score such that each engage-
ment effectively increases the player score by a selected amount.In the illustrated embodiment of the invention, the inclusive
MUX "3"-"8", and "A" - "F" lines 40 drive the scoring display
lights. The final port 46 is an input-output port which actuates
the digital display coupler 71 for indicating each of the player's
scores as well as the credit status of the system. The segment
driver 69 is encoded via register 59 and activated in synchronism
with the decoder 61 to correspondingly set the digit display
-24-
3~i~33
coupler 71. Each digit is displayed bythe well known 7 segment
display having 7 individually energized segments with the digits
0 - 9 selectively presented by energization of one or more of the
appropriate segments. Each connector coupler 71 drives an as-
S signed LED display in accordance with the 7 segment input asshown by the coupling cable 99 with the MUX line inputs providing
proper selection of the outputs. Thus, the first coupler may be
scanned with MUX lines 0 - 7, the second with lines 4 - 8, and
the final 8 - F inclusive. The displays will be related sequen-
tially however, to the scanning with the cross-wiring providing
a convenient and inexpensive internal wiring and coupling. The
individual interconnecting cables 99 may be suitably tapped to
select particular outputs in accordance with the MUX line assign-
ments.
In summary, the game apparatus of this invention may
employ conventional, standardized switches, lamps and the like
mounted in the usual manner within a pinball housing and uniquely
interconnected and interfaced witI~ a programmed logic means to
monitor the game and create outputs displays in accordance with
the game play. The multiplexing concept and interfacing with
the illustrated features and constructions establish significant
economy in construction as well as ease and cost of maintenance.
The player enters the coinsand operates the game in
the identical manner as heretofore, with the game apparatus res-
ponding in essentially the same manner with a continuous monitor-
ing of essential functions at port 45 with an immediate and prior-
ity response as well as the sequential monitoring of the several
inputs via the activation of the scan lines 40 in combination with
the sequential monitoring of the input and outputs appearing at
ports 43 - 46 via the programmed logic unit 23. The separate de-
coder 62 provides for direct driving of the several heavy duty
solenoids independently of the multiplex system and, also, where
-25-
1~3~93
desired, continuous energization such as for example the energi-
zation of the bumper solenoids without necessity of the use of
memory or storage devices such as opto-isolators. This provides
further economy in overall construction without reducing the ef-
fectiveness or reliability of the game apparatus.
Various modes of carrying out the invention are con-
templated as being within the scope of the following claims, par-
ticularly pointing out and distinctly claiming the subject matter
which is regarded as the invention.
: :.
10~3~j~3~
1 0: FIM lP 1 // MAIN PROGRAM; BALLY FLICKER PINBALL
2: FIM 2P 241 // PROGRAMMER: J.E.FREDERIKSEN; 10/22/74
4. JMS CLEAR+4
6- FIM 2P 58 / SET GAME OVER
8: JMS BIT
10:MAIN, JMS MUX
12: JCN 12 *+4
14: JMS SCORE
16: JMS INTER
18: JMS SWITCH
20: JCN 12 *-10
22: LD 0
10 23: KBP
24: XCH 0
25: LDM 10
26: ADD 0
27: JCN 10 INTER+5
29: JUN MAIN
31:SWITCH,LDM 2 // SWITCH SUBROUTINE
32: XCH 0
33: SRC 0P
34: RDR
35: XCH 0
36: RDR
37: SUB 0
38: JCN 12 *+13 / IGNORE NOISY SWITCH
40: CLB
41: RDM
42: SUB 0
43: JCN 4 ~+8
45: LD 0
46: WRM
47: JCN 4 *+4 / IGNORE ZERO SWITCH
49: CLB
50: BBL 0
51: BBL 1
52:DECR, FIM lP 224 // DECREMENT CREDIT SUBROUTINE
54: JMS ZERO+l
JMS PREP
58: SRC 0P
59: TCS
- 27 -
1~3~j~3
160: ADM
61: DAA
62: WRM
63: INC 1
64: ISZ 9 *-6
66: JMS SUPPR
68: FIM 2P~ 32 / SET OR CLEAR CREDIT LAMP
70: JCN 4 *+3
72: INC 4
73: JMS BIT
75: FIM 2P 29 / SOUND CHIMES
77: JMS MUS
lO79: JCN 12 *-2
81: LD 4
82: WRO
83: FIM 6P 205
85: INC 4
86: ISZ 5 *-9
88: BBL 0
89:MUX, CLB // MULTIPLEX SUBROUTINE; 9/14/74
90: XCH 14 / WRITE DIGIT
91: SRC 7P
92: RDM
93: WRR
94: INC 14 / WRITE LAMPS
2095: SRC 7P
96: RDM
97: WRR
98: LD L5 / WRITE MUX LINE
g 9 WMR
100: XCH 1 / IR(l) = MUX LINE
101: LDM 1
102: DCL / STROBE OUTPUT LATCHES
103 CLB
104: DCL
105: RD0 / SOLENOID OUTPUT
106: WMR
107: LDM 2
30 108: DCL / STROBE SOLENOID LATCHES
109: CLB
- 28 -
. . , .
1053~;~3
1 110: DCL
lll:TIMER, ISZ 15 *+14 / SOLENOID TIMER
113: LD 13
114: JCN 4 *+8
116: ISZ 12 *+8
118: CLB
119: WRO
120: ISZ 13 *+3
122: BBL 0 / TIMER INACTIVE
123: BBL 1 / OFF TIME IN PROGRESS
124: BBL 2 / ON TIME IN PROGRESS
125: BBL 3 / MUX IN PROGRESS
126:0VFLW, ISZ 11 *+13 // OVERFLOW SUBROUTINE
128: LDM 15
129: XCH 11
130: FIM 2P 112 / SET SPECIAL
132: JMS BIT
134: FIM 2P 19 / SET LEFT EXTRA BALL
136: JMS BIT
138: BBL 1
139: LD 11
140: RAR
141: LDM 0
142: RAL
143: XCH 4
144: LDM 3
145: XCH 5
146: JMS BIT
148: LD 11
149: RAR
150: CMC
151: LDM 3
` 152: RAL
153: XCH 4
154; JMS BIT
156: LD 11
157: FIM 2P 23
159:SEQ, DAA // SEQUENTIAL LAMP SUBROUTINE
160: JCN 10 *+17
162: JCN 12 *+15
164: XCH 9 / CARRY ROUTINE
- 29 -
1~3t~3
1 165: SRC 2P
166: LDM 1
167: WRM
168: INC 5
169: SRC 2P
170: CLB
171: WRM
172: INC 5
173: SRC 2P
174: LDM 4
17S: WRM
176: BBL 1
10 177: STC / SET NEXT SEQUENTIAL LAMP
178: RAL
179: JCN 10 *+4
181: INC 5
I82: CLC
183: RAR
184: XCH 4
18S: JMS BIT
-187: BBL 0
188:WAIT, JMS INTER // WAIT SUBROUTINE
` 190: JMS MUX
192: JCN 12 *-4
194:SCORE, FIM 2P 170 / CHECK GAME OVER
20 196: JMS BIT
198: JCN 12 *+8
200: FIM 2P 202 / CEIECK TILT
202: JMS BIT
204: JCN 4 *+3
206: BBL 2
207: FIM 2P 139 / CHECK FIRST PLAYER
209: JMS BIT
211: FIM lP 187
213: JCN 2 *+4
215: FIM lP 180
217: LD 6
218: JCN 4 *+8
220: DAC
221: XCH 6 '!
222: LDM 1
- 30 -
3~13
1 223: WR0
224: JUN *~22
226: LD 7
227: JCN 4 *+8
229: DAC
230: XCH 7
231: LDM 2
232: WR0
233: JUN *+11
235: LD 8
236: JCN 4 *+19
238: DAC
lO 239: XCH 8
240: LDM 3
241: WR0
242: INC 4
243: INC 5
244: INC 4
245: INC 5
246: LDM 1
247: WRl
248: JMS ZERO
250: JMS ADD
252: FIM 6P 222
2S4: BBL 1
255: BBL 0
:- 256:INTER, JCN 9 *+9 // INTERRUPT SWITCH SURBOUTINE; 9/11/74
258: JCN 9 *+7
260: LDM 15
261: XCH 0
262: CLB
263: FIM lP
264: JIN lP
265: BBL 0
266:COIN, LDM 12 // COIN ROUTINE
267: ADD 1
268: XCH 4
269: LD 4
270: FIM lP 224
272: JMS ZERO
274: JMS ADD
10~3~
1 276: LD 4 / SOUND KNC)CKER
277: CMA
278: XCH 4
279: INC 4
280: JMS MUX
282: JCN 12 *-2
284: . LDM 9
285: FIM 6P 140
287: FIM lP 16
289: SRC lP
290: ~R0
291: ISZ 4 *-11
lO 293: JUN ~IN
295:EXTRA, FIM 2P 131 // EXTRA BALL ROUTINE
297: JUN *+4
299: FIM 2P 227
301: CLB
302: LDM 5
303: ADD 7
304: XCH 7
305: JMS BIT
307: JCN 4 *+10
309: FIM 2P 83 / SET SHOOT AGAIN
311: JMS BIT
313: FIM 2P 122 / SET SAME PLAYER
20 315: JMS BIT
317: JUN MAIN
319:TARGET,LDM 5 // TARGET ROUTINE ,
320: A~D 8
321: XCH 8
322: FIM 2P 224
324: JMS BIT / CHECK SPECIAL
326: JCN 4 EXTRA+22
328: FIM lP 42 / CHECK STRAIGHT
330: SRC lP
331: RDM
332: RAR
333: JCN 2 EXTRA+22
335: RAR / CHECK ADD-A-BALL
336: JCN 2 EXTRA+14
338: . LDM 1 / REPLAY
- 32 - .
~.t)5~3~S.33
1 339: JUN COIN+2
341:SPIN, INC 10 // SPINNER ROUTINE; 9/15/74
342: LD 10
343: FIM lP 20
345: JMS SEQ
347: INC 7
348: JCN 4 MAIN
350: CLB
351: XCH 10
352: JMS OVFLW
354: JUN ~IN
356:BONUS, IAC // 1000 POINT BONUS ROUTINE; 9/11/74
lO 357: IAC
358: IAC
359: CMA
360: XCH 2
361: FIM 0P 17
363: SRC 0P
364: RDM
365: RAR
366: ISZ 2 *-1
368: JCN 10 *+4
370: JMS OVFLW
372: INC 8
373: JUN MAIN
20 375:THOUS, IAC // THOUSAND TARGET ROUTINE
376: IAC
377: IAC
378: CLC
379: RAL-
380: XCH 4
381: LDM 1
382: XCH 5
383: JMS BIT
385: RDM
386: INC 5
387: SRC 2P
388: CMA
389: WRM
390: CMA
391: JCN 4 *+6 / CHECK DOUBLE BONUS
~`'`~'` .
1~9~3tj~3
1 393: FIM 2P 51
395: JMS BIT
397: JUN BONVS+16
399:SLAM, FIM 6P 1 // SLAM ROUTINE
401: JMS CLEAR
403: JMS TIMER
405: JCN 12 *-4
407: JUN M~IN
409:TILT, FIM 2P 106 // TILT ROUTINE
411: JMS BIT / SET TILT
413: FIM 2P 64 / CLEAR FLIPPERS
415: JMS BIT
lO 417: ` JUN MAIN
419:RIGHT, LDM 5 // RIGHT AND LEFT OUT ROUTINE
420: JUN *+3
422: LDM 4
423: INC 6
424: JUN POT+2
426:TENS, INC 6 // TENS ROUTINE; 9/12/74
427: JUN MAIN
429: =512
512:BIT, LDM 1 // BIT TESTER SUBROUTINE
513: CLC
514: XCH 4
515: SRC 2P
516: RAL
517: JCN 2*+26
519: RAR
520: RAR
521: CMA
522: XCH 4
523: LD 4
524: XCH 5
525: RDM
526: JCN 2 *~8
528: RAR / CLEAR SELECTED BIT
529: ISZ 4 *-1
531: CLC
532: JUN *~-6
534: RAR
535: ISZ 4 *-1 / SET SELECTED BIT
- 34 -
t;~3
1 537: STC
538: RAL
539: ISZ 5 *-1
541: W~l
542: BBL O
543: CLC / CHECK SELECTED BIT
544: RAR
545: RAR
546: CMA
547: XCH 4
548: RDM
549: RAR
550: ISZ 4 *-1
552: JCN 10 *-10
554: BBL 1 / ACC=l; LINK=l
555:END, FIM 2P 58 // END OF GAME ROUTINE
557: JMS BIT / SET GAME OVER
559: FIM 2P 64 / CLEAR FLIPPERS
561: JMS BIT
563: FIM lP 42 / CHECK MATCH FEATURE
565: SRC lP
! 566: RDM
567: RAL
568: JCN 2 *+4
570: JUN MAIN
572: FIM 2P 26 / SET MATCH ZERO
574: JMS BIT
576: FIM lP O / CALCULATE MATCH NUMBER
578: SRC lP
579: ADM
580: ISZ 3 *-2
582: DAA
583: FIM lP 2 / DISPLAY MATCH NUMBER
585: SRC lP
586: WRM
587: XCH 5
588: FIM lP 11 / CHECK AGAINST FIRST SCORE
590: SRC lP
591: CLB
592: XCH 4
593: RDM
- 35 -
1~3~ 3
1 594: SUB 5
595: JCN 12 *+3
597: INC 4
598: FIM lP 4 / CHECK AGAINST SECOND SCORE
600: SRC lP
601: CLB
602: RDM
603: SUB 5
604: JCN 12 *~3
606: INC 4
607: LD 4
608: JUN COIN+2 / ADD M~TCH CREDITS
610:CREDIT,FIM 2P 16 // CREDIT ROUTINE
612: JMS BIT / SET GENERAL ILLUMINATION
614: FIM 2P 96 / CHECK CREDIT
616: JMS BIT
618: JCN 4 *+23
620: FIM lP 9 / CHECK FOR FIRST BALL
622: SRC lP
623: RDM
624: DAC
625: JCN 12 *+18
627: FIM 2P 235 / CHECK FOR TWO PLAYERS
629: JMS BIT
631: JCN 12 *+10
~o 633: LDM 9 / TURN ON TWO PLAYER LIGHT
634: WRM
635: FIM lP 163 / TURN ON SECONT PLAYER SCORE
637: JMS ZERO
639: JMS DECR
641: JUN MAIN
643: JMS CLEAR / NEW GAME
645: FIM 2P 153 / TURN ON FIRST PLAYER SCORE AND BALL
647: JMS ZERO
649: FIM 2P 16 / SET GENERAL ILLUMINATION
651: JMS BIT
653: FIM lP 27 / SET ONE PLAYER AND ONE UP
655: SRC lP
656: LDM 5
657: WRM
658: JMS DECR
- 36 -
~0!~3~
1 660: JUN BEGIN
662:0UT, FIM 2P 170 // OUTHOLE ROUTINE
664: JMS BIT
666: JCN 2 BEGIN+30
668: FIM 2P 202 / CHECK GAME OVER AND TILT
670: JMS BIT
672: JCN 12 *+33
674: RDl / CHECK FOR PLAYED BALL
675: JCN 4 BEGIN+26
677: FIM lP 20 / CLEAR BONUS FIELD
679: FIM 2P 10
681: JMS FILL
683: LD 11 / SCORE BONUS.
684: XCH 8
685: CLB
686: XCH 9
687: INC 9
688: LD 9
689: FIM 2P 23`
691: JMS SEQ
693: JMS WAIT
695: JCN 12 *-8
697: FIM lP 18 / CHECK FOR DOUBLE BONUS
699: SRC lP
700: RDM
701: CMA
702: WRM
703: JCN 4 OUT+9
705: FIM 2P 163 / SAME PLAYER SHOOT AGAIN
707: JMS BIT
709: JCN 2 *+35
711: FIM 2P 203 / CHECK FOR TWO PLAYERS
713: JMS BIT
715: JCN 4 *+10
717: RDM
718: RAR
719: LDM 10
720: WRM
721: JCN 2 *+23
723: LDM 9
724: WRM
1~936~3
1 725: FIM lP 41 / INCREMENT BALL COUNTER
727: SRC lP
728: RDM
729: RAR
730: LDM 5
731: JCN 2 *+3
733: LDM 3
734: CLC
735:BEGIN, FIM lP 9
737: SRC lP
738: SBM
739: JCN 4 END
741: RDM
742: IAC
743: WRM
744: FIM 2P 96 / CLEAR SPECIAL :~
746: JMS BIT
748: INC 5 / SET A,B,C,D
749: SRC 2P
- 750: LDM 15
751: WRM
752: FIM lP 18 / CLEAR PLAYFIELD
754: FIM 2P 7
756: JMS FILL
758: WRl / CLEAR SCORE STATUS
759: FIM 5P 0 / CLEAR BONUS
761: FIM 2P 80 / SET FLIPPERS
763: JMS BIT :
765: LDM 7 / KICK BALL
766: JUN HOLE+6
768:FILL, LD 4 // FILL MEMORY SUBROUTINE
769: SRC lP
770: WRM
771: INC 3
772: ISZ 5 *-3
: 774: BBL 0
775:CLEAR, FIM lP 2 // CLEAR MEMORY SUBROUTINE
777: FIM 2P 242 / IR(4)=F; IR(5)=2
30 779 JMS FILL
781: INC 2
782: INC 4
- 38 -
;3~;~3
1 7$3: JMS FILL
-l85: FIM lP 28 / TURN ON COIN ACCEPTOR
787: SRC lP
788: LDM 1
789: WRM
790: BBL 0
791:PREP, FIM 0P 0 // PREPARE SUBROUTINE
793: LD 3
794: XCH 1
795: LD 2
796: XCH 9
797: CLB
798: BBL 0
799:ZERO, XCH 5 // ZERO SUBROUTINE
800: JMS PREP
802: SRC 0P
803: RDM
804: CMA
805: JCN 12 *+3
807: WRM
808: INC 1
809: ISZ 9 *-7
811: BBL 0
812:ADD, JMS PREP // ADD SUBROUTINE
814: LD 5
815: SRC 0P
816: ADM
817: DAA
818: WRM
819: TCC
820: INC 1
821: ISZ 9 *-6
823:SUPPR, LD 1 // SUPPRESS LEADING ZEROS SUBROUTINE
824: DAC
825: XCH 1
826: SRC 0P
827: RDM
828: JCN 12 *+9
830: LDM 15
831: WRM
832: ISZ 5 *-9
- 39 -
i93
1 834: CLB
835: WRM
836: BBL 0
837: BBL 1
838:POT,~% LDM 6 // POT BUMPER ROUTINE
839: INC 7
840: FIM 6P 223 ,
842: FIM lP 16
844: SRC lP ~
845: WR0 ~ ~ -
846: FIM 2P 202 / CHECK TILT
848: JMS BIT
850: JCN 4 *+4
852: FIM 6P 0
854: JUN MAIN
856:HOLE,%~ LDM 3 // 3000 HOLE ROUTINE
857: ADD 8
858: XCH 8
859: JMS WAIT
861: LDM 8
862: FIM 6P 140
864: FIM lP 16
866: SRC lP
867: WR0
868: JUN MAIN
'
- 40 - . .
