Note: Descriptions are shown in the official language in which they were submitted.
~095~25
The present invention relates to an electronic cash register
which includes a time counting function and automatically totalizes
data such as the sale total, the item count and the like within a
predetermined time.
Generally, in the electronic cash register, an amount of each
goods is inputted by an entry key and then a department key of the
department to which the goods sold belongs is operated. The
inputted data is properly processed, assorted and accumulatively
stored in memories allotted for totalizations of the sale amount
and the item count for each department, the gross sale total of the
day and the sale total for each clerk. At the end of the day work,
the cash register is set to a reset mode to successively prin L out
the various data stored in the corresponding memories and then
these memories are cleared. These assorted sale data will be used
for management materials. Therefore, it is preferable that the
saLe data are detailed and correct with brevity.
Since the conventional cash register is not provided with a
clock function, it can totalize only one day's sales so that the
data obtained are insufficient for such the purpose. If we know
the sale condition at specific time zones of a day, for example,
morning, afternoon, and evening, it would be effective and useful
~ for management reference. Further, if the time counting function
-~ is extended to year, month, week and day, an operator can preset
,~
the time period for totalization, for example, a week, a month,
every two days or-the like. Accordingly, the totalization for -~
longer period than a day may be automatically made, resulting in
remarkable improvement of the totalization function of the register.
In t~le conventional register, the operator must key the date
data such as year, month and day at the beginning of the day work,
for receipt issuing.~ This work is troublesome.
Accordingly~ an object of the present invention is to provide
an electronic cash register which can automatically totalize sales
data within a given time zone, with proper time zones preset.
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To achieve the above-mentioned object, there is a provided an
electronic cash register comprising: input means at least including
an entry key for inputting numerical value, registration designatin~
keys for designating the registration of respective goods and
including a plurality of department keys for designating the
departments of respective goods, a totalizing key for setting up a
time zone of the totalization, a time set key and a control switch
for selectively set a desired operation mode such as preset,
registration, reset; first memory means for storing numerical data
inputted from the entry key; second memory means which includes a
plurality of memory regions corresponding to the department keys
and, when one of the department keys is depressed, accumulatively
stores in the memory region corresponding to the depressed depart-
ment key data relating to the department key such as the amount of
items in the numerical data; a clock circuit to set up time in
response to an operation input of the time set switch, the set-up
time being a time start point for succeeding time counting operation;
third memory means for storing time data relating to time zones in
response to an operation input of the totalizing key; judging means
in which the time data stored in the third memory means is compared
with the time counting data in the clock circuit when goods is sold
to judge the time zone to which the time of the sale processing
belongs; calculating means for executing a calculating operation
including a totalization of the amount of goods sold in accordance
with the result of the judgement; fourth memory means which includes
~; ~
a plurality of addresses and is addressed by the result of the
judgement and stores the result of the calculation in the memory
location addressed; and printing means for printing the contents of
~`~ the fourth memory means in the reset mode.
With such a construction, if the time zone for totalization is
preset, the totalization of sales within the preset time zone may
be automatically made. Therefore, the sales condition within
desired time zone may be sized so that more detailed materials
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including change of operators, supplement of goods and the like may
be prepared which are useful for goods control and other managements.
Further, if the time counting function is extended to include
month and day, the date printing may be effected at the receipt
issuing without presetting the date data.
Other objects and features of the present invention will be
apparent from the following description taken in connection with
the accompanying drawings, in which:
Fig. 1 shows a keyboard of an electronic cash register;
Figs. 2A and 2B cooperate to form a block diagram of the
entire cash register;
Fig. 3A is a circuit diagram of a CPU used in the circuit of
Fig. 2;
Fig. 3B is a circuit diagram illustrating a memory circuit and
a clock circuit in the Fig. 2;
Fig. 4 shows a memory map of the memory circuit;
Figs. 5A and 5B show memory maps in the memory in the clock
circuit;
Figs. 6A and 6B show a flow chart for illustrating the
operation of the circuit in time counting;
~; ~ Fig. 7 shows data stored in the memory in the clock circuit;
Figs. 8A to 8C illustrate data stored in the memory and the
register in the time counting; and
~; ~ Figs. 9A and 9B schematically illustrate the printing operation
o~ consecutive number and date.
Reférring now to Fig. 1, there is shown an arrangement of a
~ ` keyboard 10 of an electronic cash register (ECR). In the figure,
`~ reference numeral 11 designates amount keys for entering numeral
; values such as cost/ quantity, and the like of goods, 12 a depart-
ment key for registering goods in group, 13 a clear entry key for
erasing numerals inputted by the amount key 11. A function key
designated by reference numeral 11 is comprised of keys representing
non-add (#) for setting up the present time, void (Vo),
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multiplication (@), percentage (~) and (+) and (-) for indicating
increase and decrease of the percentage. Reference numeral 15
designates a clerk key for entering a responsible person. A trans-
action key 16 is comprised of keys representing receipt (Rc), paid
out (Pd), net total (NT), balance (BL), no sale (NS), credit (Cr),
and charges (Ch). Reference numeral 17 designates a subtotal key
for obtaining the interim result of a course of calculation. A
cash/amount tender key (Ca/TETD) 10 is used for issuing a receipt
for obtaining total or change. A time key 19 is used to set up
time. l9a designates is a service key for setting up a service
time zone. l9b sets up a time zone of totalization. l9c designates
an alarm key (AL) for setting up an alarm time. The x keys l9a to
l9c constitute the time key 19. A control lock 20 switches to
select modes (OFF), (Pr), (REG), (X) and (Z). The (OFF) mode is
used when the ECR is not used; the (Pr) mode for presetting data;
the REG mode for normal registering operation; the (X) mode for
reading operation without destroying data stored; (Z) mode for
executing reset to clear data after the stored data is read out.
Explanation to follow is elaboration of the internal construc-
tion of the electronic cash register according to the present
; invention. Reference numeral 31 is an I/O (input/output) controller
which controls the keyboard 10 and a printing section 33. The I/O
':
~ controller 31 applies a sampling signal to a ]ceyboard 10. When a
lcey is actuated on the keyboard 10, the sampling signal is selected
responsive to the key actuation and is applied as a key input
signal to the I/O controller 31. U~on receipt of the key input
signal from the keyboard, the I/O controller 31 loads the key input
signal into an input buffer register (not shown) for temporarily
storing therein. The I/O controller 31 is coupled with a central
processing unit (CPU) 34. When the CPU issues a control signal of
an input instruction to the I/O controller 31, the key input signal
.
in the input buffer is read into the CPU 34. When receiving
printing data from the CPU 34, the I/O contrGller 31 loads the
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printing data into an output buffer (not shown) where it is
temporarily stored therein. The printing section 33 is comprised
Of a receipt paper printer 36 and a detail paper printer 37. The
printers 36 and 37 are provided with printing drums 38 and 39 which
are coaxially arranged and have numerical characters on the surfaces,
respectively. A receipt paper 41 and a detail paper 42 are disposed
close to the printing drums 38 and 39, respectively. Printing
hammers are disposed against the printing drums 38 and 39 with the
receipt paper 41, the detail paper 42 and ink ribbons (not shown)
therebetween, respectively. A printing position detecting device 44
is provided at one of the ends of the printing drum 38 and detects
the printing positions of the printing drums 38 and 39 every
specified rotational angles of the drums to produce detection
signals. The detection signals are applied to the I/O controller 31
through an amplifier 45. When the printing position detection
signal and the printing data coincide, the I/O controller 31 supplies
a drive signal via a driver 35 to the printing hammer confronting
the printing type at that time, thereby to drive the hammer. When
the printing drums 38 and 39 revolve by one revolution, one line
20 printing operation completes and the receipt paper 41 and the
detail paper 42 are fed by one line. As the printing operation
progresses, the receipt paper 41 is guided out to exterior to
permit the printed portion of it to be tore off, after the printing
~ .
is completed. "YOUR RECEIPT THANK YOU", for example, is printed on
the receipt paper 41. The same contents of printing as on the
; receipt paper 41 is recorded on the detail paper 42 for recording
the net total which is taken up by a shaft 42.
A memory device 47 and a clock circuit 48 are coupled with the
cPU 34. A power source 49 is coupled with both the memory device 47
and clock circuit 48 to place them to always be ready for their
operations- The clock circuit 48 also is coupled with a reference
frequency oscillator, for example, a crystal oscillator 50. mhe
memory 47 and the clock circuit 48 are fabricated by a single chip.
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The CPU 34 produces a chip enable signal OEl to specify the memory
circuit ~7 and another chip enable signal CE2 to specify the clock
circuit 48. A read/write signal R/W from the memory 47 specifies
the reading or the writing operation of the memory device 47. The
clock circuit provides time data and day data which are read out by
the CPU 34, if necessary. When the receipt is issued, the CPU
reads out day information from the clock circuit 48 to cause the
printing section to print the day of the receipt issued. The time
data is used a time marking data when totalizing is performed in a
given time. The CPU 34 executes receipt issuing operation in
response to the key input signal from the keyboard. The processing
data at that time is transferred as printing data to the I/O
controller 31 and to a display section 24 through a display driver
51 where it is visualized.
Fi~s. 3A and 3B cooperate to illustrate the details of the
CPU 34, the memory device 47, and the clock circuit 48. The CPU 34
is first given. In the figure, an address circuit 61 specifies the
address of a control section 62. The control section 62 includes a
microprogram to control the operations of the respective circuits
which is stored in a read only memory (ROM). The control section
~;~ includes output lines 63 to 66. The output line 63 provides a code
generation instruction; the output line 64 a given timing signal;
the output line 65 various instructions, for example, a register
specifying signal, a transfer instruction, a digit shift instruction;
the output line 66 the next address of itself. The code generating
instruction from the output line 63 is transferred to a code
generating circuit 67. A timing signal from the output line 6~ is
transferred to a timing specifying circuit 68. The instructions
from the output line 65 is transferred to an instruction decoder 69.
, ~
The next address outputted to the output line 66 is transferred to
an address circuit 61 for specifying the next address. A timing
signal from a timing generating circuit 80 provided in the CPU 34
is applied to the code generating circuit 67, the timing instruction
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~95625
circuit 68, and the instruction decoder 69. The code generatin~
circuit 67 converts parallel data of 4 bits, for example, given
frorn the control section 62 at given timing into a serial code
signal. The output of the code generating circuit 67 is transferred
to an addition/subtraction circuit 71 through a gate circuit 70.
The timing specifying circuit 68 specifies the operation timing of
the register such as digit specifying of it in accordance with the
timing signal fed through the output line 64 from the control
section 62. The output signal of it is applied as enabling and
1~ disabling signals to the respective gate circuits in the CPU 34
such as a gate circuit 70, and AND circuits 72 to 75. The outputs
of the AND circuits 72 to 75 are applied through the OR circuit 76
to an input/output register 78a in the register group 77. The
instruction decoder 69 decodes the instruction given from the
control section 62 to control the operations in the respective
portions in the CPU 34 such designation of the register in the
register group 77 and gives a read/write instruction to the memory
47 and the clock circuit 48. The outputs of the timing designating
circuit 68 and the instruction register 69 are applied as control
signals to the display driver 51 and the I/O controller 31. The
~: register group 77 includes the X register for input/output register
78ai and other registers 78b to 78n denoted as Y to N. The output
of the register group 77 is coupled with an adder/subtractox 71,
through the OR gate 70. The output of the X register 78a is applied
to the AND circuit 73, through circuit 79a with one digit memory
capacity. The output signal of the adder/subtractor 74 is applied
to the AND circuit 74. The key input signal from the keyboard 10
is applied via the I/O controller 31 to the AND circuit 74. Data
~ decoded from the memory device 47 and the clock circuit 48 is
: ~ 30 applied to the AND circuit 75. The output signals of the X to N
: . registers 78b to 78n:are applied to gate circuits 81b to 81n,
through registers 79b to 79n each wlth one digit memory capacity.
The output signal of the adder/subtractor 71 is also applied to the
:
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gate circuits 81b to 81n. The outputs of the gate circuits 81b to
81n are applied to the X to N registers ,8b to 78n, respectively.
The output of the X register 8a is applied as display data or
printing data to the display driver 51 and the I/O controller 31
and to a chip designating circuit 82. In accordance with an
instruction from the control section 62, the chip designating
circuit 82 reads out the chip designating data in the X register 8a
and produces the chip enable signals CEl and OE 2 in accordance with
the contents of it thereby to designate the memory 47 or the clock
circuit 48. The output of the adder/subtraction circuit 71 is
loaded into an A register 83 for addressing. Data decoded by the A
register 83 is inputted to the adder/subtraction circuit 71 through
a gate circuit 70 and is divided into two addresses; an address RA
of row and an address CA of column. These addresses are applied to
the memory 47 and the clock circuit 48, respectively. Data and
carry signals outputted from the adder/subtraction circuit 71 are
transferred to a judging circuit 84. The judging circuit 84 judges
whether the data or the carry from the circuit 71 presents or not
and produces the result of the judgement towards the address
circuit 61. At this time, the succeeding address outputted onto
the output line 66 and the detection signal are logically summed so
that the ne~t address is changed.
The memory circuit 47 includes a memory unit 91, an address
designating circuit 92 into which the read/write R/W instruction
from the instruction decoder 69, the row and column addresses from
the A register 83 are loaded. The address designating circuit 92
and the gate circuit 93 are enabled by the chip enabling signal CEl
given from the chip designating circuit 82. Data read out from the
memory body 91 through the gate circuit 93 is applied to the AND
30 circuit 75 of the CPU 34, as previously stated. The output signal
of the X register 78a in the CPU 34 is applied as write data to the
memory unit 91, through the gate circuit 93. The memory unit 91
has a capacity of nX8, as shown in Fig. 4. The columns Bl to B8
;
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are designated by the column address CA and the rows 1 to n are
designated by the column address RA. The memory body 91 is divided
into three regions; a first region 91A ranging from Bl to B4
columns, a second region 91B ranging from B5 and B6 columns, and a
third region 91C ranging from B7 to B8 columns. In the first
region 91A, the 1st to 16th addresses store the department total
corresponding to the department key 12. The 17th address stores
the sale total between the designating times Tl to T2. The 18th
address stored the sale total between the specified time zone T2 to
T3. The l9th address stores the sale total within the time range
between the specified time zone T2 to T4. The 20th address stores
the receipt total. Such the memory region will be called a time
designating sale total memory region. In the second region, the
item count is stored in addresses 1st to 16th. The sale count
between the specified time zones Tl to T2, T2 to T3, and T3 to T4
are stored in the memory region 17th to l9th, respectively. The -
receipt count is stored in the 20th address. Preset unit prices in
the respective departments are stored in the 1st to 16th addresses
of the third region 91C.
In Fig. 3B, the clock circuit 48 is provided with a memory 100
for storing the date of the day, the present time data, the preset
time data and the like. The memory 100 is specified by the
addresses RA and CA of row and column set in the address designating
.
circuit 101 through the A register 83 in the CPU 34 and its read
and write operations are specified by the R/W instruction fed from
the instruction decoder 69. A control section 110 in the clock
circuit 48 feeds an address code signal and the R/W instruction to
the address designating circuit 101 for addressing the memory 100.
The data outputted from the memory 100 is applied to a buffer
register 103 via through a gate circuit 102 and to the gate
circuit 104. The output of a buffer register 103 and a l-second
pulse for clocking from a pulse generating circuit 105 are applied
to the gate circuit 104. The pulse generating circuit lG5 operates
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~gS625
in response to a reference signal from a crystal oscillator 50 and,
in addition to the l-second pulse, generates a timing signal
defining the timings for the operations at the respective portions
to be directed to the control section 110. The gate circuit 104
selects an input signal in accordance with a control signal from
the clock control section llO and feeds it to the adder/subtraction
circuit 106. The adder/subtraction circuit 106 executes addition
or subtraction in accordance with an instruction from the clock
control section llO, and feeds the result of the calculation as
write data to the memory 100 through a gate circuit 107. The data
and carry of the calculation result outputted from the
adder/subtraction circuit 106 are applied to the judging circuit 108
for judging the memory mode of 60 or 24 scale and time coincidence,
for example. The result of the judgement of the judging circuit 108
is transferred to the clock control section 110 which in turn
produces a control signal for the next processing, on the basis of
the judging result. The data read out from the memory 100 is
applied to the AND circuit 75 in the CPU through a gate circuit lO9.
; The gate circuits 107 and lO9, and the addressing circuit lOl are
enabled by the chip enable signal CE2 from the chip designating
circuit 82. The gate circuits 102, 104, 107 and the
adder/subtraction circuit 106, and the judging circuit 108 are
controlled by a signal ~rom the clock control section llO. The
., ~
gate circuit 107 is controlled by the chip enable signal CE2 and
signal from the cIock control section 110. The memory 100 has a
memory capacity 4 rows x 8 columns as shown in Fig. SA, for e~ample.
The respective columns Bl to B8 are specified by the column address
CA and the respective rows are specified by the row address RA.
:
The lst to 3rd rows store time data such as hour and minute for
each two columns, i.e. B8-B7, B6-B5, B4-B3 and B2-Bl. Additionally,
time data for timed totalization Tol to To4 are stored in the 1st
~ row; time data ALl to AL4 in the 2nd row; and time data for service
;~ time SVl~to SV4 in the third row. The time data Tl to T4 define
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the net total time range; the time data ALl to AL4 alarm time; the
time data SVl to SV4 the service time of discount and the like. In
the 4th row, the columns B8 to B7 store ~lag 1 and Flag 2 to
indicate the coincidence between the present time and the designated
time; the columns s6 to B4 store "year", "month" and "day" o~ the
day; the columns B3 to Bl "hour", "minute" and "second" of the
present time. In the memory location at the 4th row and the 37
column of the memory 100, for storing the Flag 2, a binary "1" is
stored in the first bit bl when the present time is between Tl to
T2, in the second binary bit b2 when it is between T2 to T3, and
in the third bit b3 when it is between T3 to T4.
In operation, the clock circuit 48 operates in accordance with
the reference signal fed from the crystal oscillator 50. The
reference signal outputted from the crystal oscillator 50 is applied
to the pulse generating circuit 105 which produces the l-second
pulse and various timing pulses. The l-second pulse produced from
the pulse generating circuit ~05 is applied to the adder/subtraction
circuit through the gate circuit 104. The control section 110 sets
the row address RA=4 to specifying the 4th row of the memory 100
and reads out the contents of the address from the memory 100
through a gate circuit 102 and loads it into the buffer register 103.
The gate 104 selects the output of the buffer register 103 and the
l-second pulse from the pulse generator 105 and applies them to the
adder/subtraction circuit 106 thereby to add the l-second pulse to
the second data on the Bl column. The output signal of the
adder/subtractor 106 is transferred to the memory 100 through the
gate circuit 107, and written into the 4th row. In this manner,
the contents of the 4th row of the memory 100 is always refreshed.
The output of the adder/subtractor 106 is transferred to the judging
circuit 108 where it is judged whether the result of the addition
reaches a predetermined value or not and the result of the judgement
determines the control operation in the clock control section.
More specifically, when addition of the second pulse reaches the B
l(~9S62S
row of the 4th column, i.e. the second data reaches 60 seconds,
this condition is judged by the judging circuit 108 and the clock
control section adds "l" to the CGntentS of the B2 column of tlle
4th row, i.e. the minute data, while at the same time the second
data is cleared. Succeedingly, a similar operation of carry
control will be repeated in the order of minute -- hour -- month
-- year. Thus, clock operation will be executed for the time and
date. At the initiation of the clock circuit 48, date and time
must be correctly set. In the setting operation, the control
switch 20 in Fig. 1, 20 set to the Pr mode and, under this condi-
tion, the amount key 11 is actuated in the order of year --
month -- day -- hour -- minute -- second. In this case, the non-
add key "#" is depressed every time unit data is entered into the
ECR. The input data inputted through the respective key operations,
i.e. from the keyboard 10, is transferred to the CPU 34 through the
I/O controller 31 where it is entered into the X register 78a via
the AND circuit 74 and the OR circuit 76 shown in Fig. 3. The
input data stored in the X register 78a is transfer~ed into the
clock circuit 48 where it is loaded into the intersections of the
4th row and B6 to Bl columns through the gate circuit 107. In this
manner, the aate and time data are loaded into the memory 100 of
the clock circuit 4~ and, after finally the second data loading is
; completed, the above-mentioned clock operation will be performed.
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; When the time data for time totalization, the time data for
service time, and time data for alarm time are written into the
::
memory l00, it is performed by using the amount key ll, the To
key l9b, the SV key l9a, and the AL key l9c. For example~ after
the time data of hour is inputted by the amount key 11, the minute
time data is inputted by the To key l9b. After the operation of
the To key l9b, the time sequence specifying data "1" is inputted
by the amount key 11, to specify the intersection of the 1st row
and the B7 and B8 columns so that "hour" and "minute" of the time
data Tl are loaded thereinto. When the operation like the
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above-mentioned one is made by using the SV key 19a instead of the
To key l9b, the time data for service time is loaded into the
memory 100 at the intersections of the 3rd row and the rows B7 and
B8. Use of the AL key l9c writes the time data for alarm into the
intersections of the 2nd row and the B7 and B8 columns.
For loading the preset data of department, the amount key 11
and the department key 12 are depressed under a condition that the
control switch 20 is switched to the Pr position. In this operation,
the key input data is transferred into the memory device 47 by way
of the X register 78a. In the memory 47, the key input data is
written into the 1st to 16th addresses in the 3rd region of the
memory unit 91, through the gate circuit 93.
In processing the sales of goods, the control switch 20 is set
to the REG mode and the unit prices of the goods sold are entered
by the amount key 11. Then, the department key 12 to which the
printing section 33 where it is printed on the receipt paper 41 and
the detail paper 42. At the same time, the input data is displayed
in the display 24 to which the input data is applied by way of the
CPU 34 and the display driver 51 and is accumulated in the CPU 34.
Further, data of the memory circuit 47 corresponding to the address
specified by the department key 12 is read out into the CPU 34
where it is added to the data inputted and the result of the
,
addition is written into the address of the memory device 47
specified. At this time, the price is added to a predetermined row
of the first region 91A, and the item count is added to a pre-
determined row of the second region 91B. In this manner, the
operation like the above- mentioned one will be repeated by
Operating the amount key 11 and the department key 12 every goods
sold. When the prices of all of the goods sold are entered and the
department are specified, the key 18 of Ca/~ND is operated to
issue a receipt, ~ith totalization or change. mhe total amount
thus obtained by the CPU 3~ is displayed in the display section 24
and applied through the I/O controller 31 to the printing section 33
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109562S
where it is printed on the detail paper 42 and the receipt paper 41.
When it is processed by using the department preset key preset for
each department as mentioned above, and without inputting the
prices of goods the process like the above-mentioned one will be
performed with the input data of the preset data of the address
corresponding to the department key 12, through a mere operation of
the department key 12.
The operation of the timed totalization will be described with
reference to Figs. 1 to 8. When data relating to the goods sold is
inputted, the key input signal is applied to the CPU 34 through the
I/O controller 31 and set in the register 78a. Then, the Ca/~T~NTD
key 18 is actuated so that the data in the X register 78a is trans-
ferred to the X register 78b, as shown in a step a in Fig. 6A. The
data flow at this time is such that the data emanating from the X
register 78a flows through the gate circuit 70, the adder/subtraction
circuit 71, and the gate circuit 81b to the Y register 78b. At the
next step b, the control section 62 reads out the chip specifying
data to specify the memory 100 in the clock circuit 48 and the
loads it into given digits in the X register 78a. The control
section 62 issues an operation instruction to the chip specifying
circuit 82. Upon receipt of the operation instruction, the chip
designating circuit 82 reads out the chip designating data from a
given digit of the X register 78a and produces the chip enabling
signal CE2 to specify the memory 100. Then, the control section 62
produces addresses RA=4 and CA=B7 to specify the intersection of
the 4th row and the column B7 of the memory 100. The addresses are
converted into serial codes by the code generating circuit 67 and
then the converted one is transferred to the adder/subtraction
circuit 71 through the gate circuii 70. The addresses RA and CA
outputted from the adder/subtractor 71 are inputted to the A
register 83 where it is converted into parallel data which in turn
transferred to the addressing circuit 101 in the clock circuit 48.
A read instruction from the control section 62 is set in the
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instruction decoder 69, through the instruction decoder 69. That
is, the chip enabling signal CE2 specifies the clock circuit 48 and
the Flag 2 addresses the memory 100. Through the acldressing in the
step b, the Flag 2 stored in the location of the 4th row and the B7
column M(4, B7) of the memory 100 is read out and the read-out
signal is transferred to the X register 78a, through the AND gate 75
and the OR circuit 76. When the present time is read out from the
memory 100 into the buffer register 103, the clock circuit 78
successively reads out the time data of time totalization T1 to T4
from the memory 100 and applies them through the gate circuit 104
to the adder/subtraction circuit 106 to compare it with the present
time stored in the buffer register 103. The result of the com-
parison is applied to the judging circuit 108. In the judging
circuit 108, the service time, i.e. Tl to T2, T2 to T3, or T3 to
T4, to which the present time belongs is searched and the binary
"1" is loaded into the corresponding bit of the Flag 2 memory
location bl to b3 of the memory 100.
Assuming now that the time Tl is preset to be 10:00; T2
12:00; T3 14:00; T4 17:00, and that, under this condition, the
receipt paper is issued at 10:30 by depression of the key 18. As
described above, M(4, B7) memory location of the memory 100 is
addressed and the content of the Flag 2 is read out from the memory
~` 100 into the output register 78a. The present time 10:30 resides
in the time zone Tl to T2, i.e. 10:00 to 12:00, the binary "1" is
set in the first bit bl of the Flag 2 so that the Flag 2 is "0001".
` As shown in the step c of Fig. 6, the contents "0001" of the Flag 2
read out into the register 78a is transferred into the judging
circuit 84, through the gate circuit 70 and the adder/subtractor 71.
The judging circuit judges whether any one of the bits of the
Flag 2 includes "1" or not, as shown in a step _. When the result
of the judgement is NO, i.e. the present time does not belong to
the time zones, the timed totalization is not performed and the
` receipt is immediately issued. When the judgement is YES, i.e. the
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present time belongs to any one of the time zones, the process
progresses to the step e in Fig. 6. In this step, the control
section 62 causes the chip designating circuit 82 to produce the
chip enable signal CEl and addresses the memory device 47 to specify
one of the 17th to l9th row addresses in accordance with the
contents of the Flag 2. In this case, the present time resides in
the time zone Tl to T2 so that the 17th row address of the memory
device 47 is specified. Then, it progresses to a step f in Fig. 6A.
In this step, the contents of M(RA, CA), e.g, the article number
"20" in the time zone Tl to T2 and the subtotal "~13,200" in the
same zone is read out into the X register 78a. The contents of
"~13,200" in the X register 78a and the sales data, e.g. "~700",
stored in the Y register 78b are transferred to the adder/subtraction
circuit 71, through the gate circuit 70. In the circuit 70, these
are added. The article number "20" in the time zone T1 to T2 is
also applied to the adder/subtraction circuit 71 where it is sub-
jected to "+1'l operation. Then, the total amount "Y13,900" in the
time zone Tl to T2 and the article number "21" in the same time
zone are loaded into the 17th address of the memory device 47.
The detailed flow in the step e in Fig. 6A is shown in Fig. 6B.
In a step -1' it is judged whether "1" is set in the first bit bl
or not, i.e. the contents of the Flag 2 is 0001 or not. If the "1"
is set in the bit bl, a step e2 loads the chip enable signal CEl
into the X register 78a and further the row address RA=17 and the
column address CA=B1 are loaded into the A register 83. When the
"l" is not set in the bl in the step el, a step e3 is executed to
see if the binary "1" is set in the second bit b2 or not. If the
"1" is set in the b2, a step e4 loads the chip enable signal CEl
into the X register 78a and sets the row address RA=17 and the
column address CA=Bl in the A register 83. If the "1" is not
stored in the b2 in the step e3, a next step e5 is executed. This
step loads the chip enable signal CEl into the X register 78a and
the row address RA=l9 and the column address CA=Bl into the A
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address register 83.
Fig. 8B illustrates the case when the sales processing is made
at 11:50.
When the sale processing is made after 12:00, for example, at
12:01 as shown in Fig. 8C, totalized and the receipt is issued, the
locations of the 18th row and the columns B6 to sl of the memory 100
are specified since, at this time, the second bit b2 of the Flag 2
is set at "1" and therefore the contents of it is "0010". If this
sale is the first one after 12:00, the contents of the 18th row and
the columns B6 to Bl are all "0". Accordingly, the article number
"1" in the time zone T2 to T3 is loaded into the memory locations
the columns B6 to Bl and the 18th row with the total amount in the
same time zone, for example, "~450" of the sale amount at this
time. After this, data totalization will be continued with respect
to the memory locations of the 18th row and the columns B5 to B1 of
the memory 100 till time T3, i.e. 14:00.
Aftet 14:00, data will be totalized with respect to the memory
locations of the l9th row and the columns s6 to Bl till T4, i.e.
17:00 in this example. In this manner, the amount of money and the
article number are totalized and then the operation advances to a
step g. In this stepj this sales data (the above-mentioned total -
amount) stored in the Y register 78b in the register group 77 is
transferred to the X register 78a and then to the I/O controller 31,
where it is stored in the output buffer register (not shown). The
I/O controller controls the printing section 33 on the basis of
the data stored in the output buffer register and prints the data
as shown in step _ of Fig. 6. In the step h, the printing shown in
Figs. 9A and 9B is made in addition to the data printing. Upon end
of the data printing, the consecutive number is printed as shown in
the step hl of ~ig. 9A. At this time, the microprogram read out
from the control section 62 sets the chip designating data to
specify the memory device 47 in the X register 78a. Thenr the
microprogram of the control section 62 transfers an operation
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1~9S62~
instruction to the chip designating circuit 82. Upon receipt
of the operation program, the chip designating circuit 82 reads out
the chip designating data from the S register 78a to produce the
chip enable signal CEl and to specify the memory device 47. lhen,
the control section produces an address code to specify the memory
locations of the 17th row and the columns B8 and B7 of the memory
unit 91. The address code then is converted into a serial code by
the code generating circuit 67. The serial code converted is then
transferred to the adder/subtraction circuit 71, through the gate
circuit 70. The address data outputted from the adder/subtraction
circuit 71 is loaded into the A register 83 where it is converted
into parallel data to be fed to the address designating circuit 92.
A read instruction fed from the control section 62 through the
instruction decoder 69 is set in the addressing circuit 92. As a
result, the contents of the memory locations of the 17th row and or
columns B8 and B7, i.e. the consecutive number, for example, "3400",
is read out from the memory unit 91 and the consecutive number is
then applied to the X register 78a through the AND gate 75 and the
OR circuit 76. The consecutive number read out from the X re~ister
78a is transferred to the output buffer register in the I/O
controller 31, together with "NO" shown in Fig. 9A. The data set
in the output buffer register controls the operation of the printing
.
section 33, to print the consecutive number "NA3400" on the receipt.
The consecutive number "3400" read out into the X register 78a is
applied to the adder/subtraction circuit 71 where it is subjected
to the "~1" operation. Through this addition, the consecutive
.
number becomes "3401" which in turn loaded into the memory locations
of the 17th row and the columns B8 and ~7 of the memory unit 91.
When the printing operation of the consecutive number is
completed, the CPU 34 issues a paper feed instruction to the I/O
controller 31. As a result, the paper feed of N columns is executed
of the receipt, as ~hown in a step h2 in Fig. 9A.
Then, the CPU 34 transfers a stamp printing instruction to
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the I/O controller 31 so that "YOUR RECEIPT THANK YOU" is printed,
as shown in a step h3 in Fig. 9A.
When the stamp printiny is completed, the operation shifts to
the date printing mode so that the CPU 34 performs a chip designa-
tion to the clock circuit 48 and an addressing of the date to the
memory 100. That is, the CPU 34 transfers a code designating the
chip of the clock circuit 48, e.g. "0010" to the X register 78a,
and at the same time issues an operation instruction to the chip
designating circuit 82, through the control section 62. Upon
receipt of the operation instruction, the chip designating circuit
82 reads out the chip designating code "0010" from the X register
78a, and produces the chip enable signal CE2 to designate the chip
of the clock circuit 48. Then, the control section 62 transfers
the address data to the address register 83, through the gate
circuit 70 and adder/subtraction circuit 71. The address data
specifies the memory locations of 4th row and the columns B6, B5
and B4. The adaress data is transferred from the address register
83 the address designating circuit 101 in the clock circuit 48. In
the address designating circuit 101, a read instruction is set
which is fed from the control section through the instruction
decoder 69. As a result, the date data, for example, if it is
November 20, 1976, 'l76 11 20", is read out from the memory locations
of 4th row and of columns B6, B5 and B4 of the memory 100 as shown
in a step h5 of Fig. 9B. The date data read out is transferred to
the X register 78a/ through the gate circuit 109, the AND circuit 75
and the OR circuit 76. The date data read out into the X register
78a is transferred to the output buffer register in the I/O
controller, together with the segment code, as shown in a step h6
of Fig. 9B. The I/O controller 31 controls the printing section 33
in accor~ance with the data stored in the output buffer register to
print the date, as shown in a step h7 in Fig. 9B. The receipt
issuing operation is made in the above-mentioned manner. The stamp
printing "YOUR ~ECEIPT THANK YOU" and the printing of data are made
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for the succeeding receipt. As shown in Fig. 9s, the receipt is
torn off between the consecutive number printing with N rows space
and the stamp printing. Therefore, the stamp printing and the date
printing are positioned at the upper portion of the receipt issued.
In the above-mentioned embodiment, the time and date are set
up by setting the control switch 20 to the Pr mode and alternately
depressing the amount key 11 and the non-add key "#". However,
year, month, day, hour, minute, and second may be consecutively
inputted by using the amount key and finally actuating the non-add
key "#", for the same pulse. When the totalizing time is set up,
ho~r and minute may be continuously inputted by the amount key 11
and then operating the totalizing key To l9b, unlike the above-
mentioned example. Since the totalizing key To 19b is separately
~rovided, it may be placed to always be settable irrespective of
the mode of the control switch 20. If the totalizing key To l9b
is desired to be substituted by another key, the ST key 17 or the
like may be used under a condition that the control switch 20 is
switched to the Pr mode, for example.
In the abo~e-mentioned example, the sale amount and the sale
:
count within a predetermined time are totalized each operation of
the Ca,/TEND key~18. However, if the memory location for storing
the total and the count is provided for each department and these
; may be totalized for each department. In this case, the totali-
zatlon is made each operation of the department key. Additionally,
the memory location for storing total and count are provided for
each transaction, and the transaction total and count may be
,
totalized for each transaction. In this case, the totalization is
made each time the transaction key 16 is operated. Further, if the
memory location for storing the total and count is provided for
;30 each clerk key, the sale total and count within a given time may be
totalized ~or each clerk. In this case, the totalization is made
` each time the registration key such as the transaction key 16, the
department key 12 or the subtotal key 17 is operated.
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The total and count may be totalized not only within time but
also within the date. In this case, the memory location for storing
the total and count of the preset date is provided and every time
the registration is made, the preset date is compared with the date
of that registration to accumulately store the total and count in
the given memory location.
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