Note: Descriptions are shown in the official language in which they were submitted.
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This invention relates to an inverter in an integrated
injection loyic (,I L) structure which includes a bipolar lateral
transistor and a vertical transistor. Inyerters of this type
are kno~n. For example, in the publication of "N.C. Troye
Integrated Injection Logic - Present and Future", IEEE ISSCC,
1974, an arrangement of this type is. described. An integrated
injection logic of this type is a saturated logic. This means
that the storage time i.n the determination of its speed is a
decisive factor. The lessening o~ the storage time has the
highest significance attached to it ins.ofar as it implies a :
higher speed which has: great.signi.fi.cance in large scale
integxation (LSI).
A principal object of the present inYention consists
accordingly in providing an inverte:r stage in ~hich the storage
time is considerabl~ reduced as compared ~ith the inverter
stages of the prior art.
Thi:s objecti.ve i.s accompli,shed by an inverter stage .:
structure h.erei,nafte~ to be des.cribed. In parti.cular, the
inverter stage of the present inventiQn compri.ses a substrate, .
an epitaxial layer on the substrate, a lateral transi,stor
h.aying emittexr base and collector regions and a yertical
transistor formed s~ide b~ side in the epitaxial layer having an ~.
emitter region, a base region and at least two collector
regions, a pair of supply voltage source terminals, the
collector regi,on of the lateral transistor b.eing connected to
the base region of the vertical transistor, the emitter region
of the vertical transistor and the base region of the lateral
transistor being connected to one of the terminals. of the supply
voltage source, the emitter of the lateral transistor being
connected to the other of the terminals of said supply voltage
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source, and a diode connected in parallel to each base-
collector junction of the vertical transistor, the diode being
poled the same as the base-collector junctions.
An essential advantage of the invention consists in
the fact that, as a result of the production of the base region
of the vertical npn transistor of the inverter stage by means
of ion implantation, a drift field is simultaneously produced
which reduces the switching time of the inverter.
Advantageously the inverse current amplification is
further increased by the greater collector surface of the
additional collector area.
Advantageousl~r, no substantially greater surface
requirement is necessary for the construction of the inventive
inverter than for the construction of the in~erter of the prior
art.
A further advantage of the invention consists in the
fact that the production process need only be substantially
altered by an add~tional standard process, and it is thus
largely compatible with other circuits.
Advantageously, the inverter of this inyention can be
applied in an~ desired logic circuit for inyersely operated
transistors.
According to a broad aspect of the invention there is
provided an inverter comprising a first transistor having an
emitter, a base and a collector, a second transistor having an
emitter, a base and at least two collectors, a pair of supply
voltage terminals, said collector of said first transistor
being connected to said base of said second transistor, said
emitter of said second transis-tor being connected to the base
of said first transistor and to one of said terminals, said
--2
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emitter of said first transistor bein~ connected to the other
of said terminals, and diodes connected i.n parallel to the
junctions between the bas-e and the collectors of said second
transistor, said diodes being poled the same as said collector-
base junctions.
The invention is explained in the following with the
help of the Figures and the specification.
Figure 1 is a cireuit diagram of one preferred
embodiment of an inverter stage having the features of the
present invention; ~-~
Figure 2 is a partial secti.onal vie~ diagrammatically .
illustrating an inverter stage whose circuit diagram is formed
in Figure l; and
Figure 3 shows the transmi.ssion eharaeteri.stie of a
eonventional inverter and also the transmission eharaeteristics ;
of an inverter aeeording to this invention.
The eleetrieal eireuit of an inverter stage in an
integrated injeetion logie of this invention is shown in
Figure 1. Th~s includes a lateral bipolar pnp junction
transistor 1 and a verti.eal bipolar npn junction transistor 2.
Voltage supply source terminals 111 and 131 are provided, the
: terminal 13I being the reference potential such as ground.
The emitter 11 of the lateral transistor 1 is connected
to the voltage terminal 111, while the base 13 of this
transistor is connected to the reference voltage terminal 131.
The collector 12 o~ the transistor 1 is directly connected to
the base 24 of the vertical transistor 2. The emitter ~ of
the transistor 2 is connected to the reference voltage terminal
131. The transistor 2 is provided with two or more collectors
~, 23, which are connected to output terminals 25. Schottky
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diodes 31 and 33 are connected parallel to the base-collector
junction of the transistor 2 and are poled the same as the
base-collector junction. The output of the preceding stage is
connected to terminal 241, which is connected to the base 24 of
transistor 2.
The following considerations are attributed to the
invention. A lowering of the storage time of the inverter can
be achieved in that the over-excitation of the vertical npn-
transistor 2, located in the saturation region, is either
lessened or prevented. The over-excitation can be inventively
reduced with the aid of a Schottky diode 31 to 33, which is,
in each case, arranged parallel to a collector-base junction
-~, 24, and 23, 24, respectively.
In Figure 2, the substrate on which the inventive
circuit is constructed is des'ignated as 10. Pre~erably, the
substrate involved here is a p doped silicon substrate. The
inventive circuit can, however, be constructed in a ESFI ~ -
(,SOS)-technique. ESFI stands for Epitaxial Silicon Films
- on Insulators and SOS stands for Silicon on Sapphire. In this
case, the substrate 10 would consist of sapphire or spinel.
On the substrate 10, an n~ conductive layer 132 ~hich will
later become a buried layer, is arranged by means of diffusion.
On the layer 132, a layer 22 of n type conductivity is
epitaxially deposited. By up diffusion, the thickness of the
layer 132 is enlarged by causing the adjacent portion of the
layer 22 to be changed from n type doping to n~ type doping.
With the aid of an ion implantation step, the p conductive
areas 11 and 12, 24 are formed in the surface of layer 22 in
the manner to be seen from Figure 2.
The zone 11 forms the emitter region 11 of the lateral
J.lD974~l!3
pnp transistor 1, and the zone 12 forms the collector. The ;
base 13 of this transistor is a part of the epitaxial layer 22,
which is left between the emitter 11 and the collector 12.
As seen in Figure 2, it will be noted that the collector 12 is,
in effect, part of the diffused zone 24, which becomes the
base of the vertical transistor 2, while the portion 22 lying
below the base 24 forms the emitter of the transistor 2. Into
the upper surface of the portion 24 of p type conductivity, an
n type conductivity diffused zone 21/23 is formed to provide
the collector 21 and 23 of the vertical transistor 2. In order
to form an ohmic contact to the emitter 11, a p+ electrode 110
is formed in the upper surface of the emitter 11. In order to
form an ohmic contact with -the collector 12 of transistor 1, a
p+ zone 2~2 extends down from the outer surface into contact
with the diffused region 24 which includes the upwardly rising
n portion 12, which forms the collec:tor of the transistor 1.
n~ regions 250 provide ohmic contact.s to the diffused region 22,
which provides the collectors of the vertical transistor 2.
An insulating layer 20 is applied to the device around
the two transistors to provide isolation. This insulation may,
for example, be silicon dioxide. The huried layer 132 extends
out to one side of the vertical transistor 2, and then rises
: to the surface where a metal contact, preferably aluminum is
in contact wi.th. it. Aluminum contacts are also pro~ided for
the areas 110, 250 and 242. Electrodes 110, 250 and 242 are
connected, respectively, to terminals 111, 25 and 241.
The n type conductive layer or region 22 may also be
produced by ion implantation.
Seen electrically, it will be noted that the base 13
is part of the layer 22, and is hence electrically connected to
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the buried layer 132. Thus, the buried layer 132 represents
the base connection regi.on for the lateral transistor 1, and
i.s connected to the reference potential terminal 131. The
collector area 12 of the lateral transistor 1 is, at the same
time, connected to the base area 24 of the verti.cal transistor
2. Beneath the p doped base area 24, the n doped emitter area
22 i.s interfaced therewith, and thus provides the emitter of
the inversely operated yerti.cal transistor 2. As hereinbefore
stated, the emitter area ~ is connected directly to the buried
layer 132, s~ince it is interfaced th:erewith..
It will also be observed that during the process of
construction of the disclosed device, the p~ areas 110 and 242
may be produced at the same time.
. In the place of oxide insulation ~eing used for
isolation, pn isolation may be used.
In arrangements in which only pure integrated injection
logic structures are arranged on a substrate, the isolating
~ provided by insulation 20 may be dispensed w;.th, since there
i the layer 132 is al~ays connected to the reference potential.
In this situation, it ~s preferable that the reference potential
be ground.
Since only yerX small voltages occur with integrated
injection loglcs, p doped protective rings, which, in Schottky
junctions- in other logic arrangements, are provided in a
blocking direction for improving the diode characteristics, are
unnecessary-in th.e $chottky junctions.
In Figure 2, for the sake of simplicity, only the
collector regions 21 and 23 are represented. In reality, many
more collector regi.ons may be provided which together form the
output 25.
740~ .
By means of the arrangement of the base connection
electrode region 242 depicted in the Figure, it is achieved
that areas 21 and 23 are insulated from one another.
The manner of functioning of the vertical npn trans-
istor 2 with a Schottky clamp diode does not change statically
in the active and in the blocking regions, since the Schottky
diode is also biased in blocking direction. Then, only the
capacitance of the diode is paralleI to the collector-base
capacitance, and only has a disad~antageous influence on the
rise times and deIa~ times as long as the charge exchange of
the capacitances is decisive. In the saturation region, on the `~
other hand, not only the collector-base junction, but also the
Schottky diode is biased in the flow direction. I~ the
threshold voltage of the Schottky diode is smaller than that
across the collector-base junction, then the back injection
current flows for the most part through the Schottky diode.
Since the effect of the charge storage in the Schottky diode
is smaller by several orders of magnitude, the storage time
is considerabl~ reduced. The Schottk~ dioae has the further
effect that, because of its smaller threshold voltage, the
collector-emitter saturation voltage is increased. In this
way, the yoltage difference between the logical states is
reduced.
In Figure 3, this is depicted on th~ basis of the
characteristic curves of an inverter of the prior art and of
the inverter of the present invention, i.e. output voltage
(at 25 in Figure l~ vs. input voltage (at 241 in Figure 1).
Therein, the characteristic curve of the prior art inverter is
represented b~ a broken line, and the characteristic curve of
the inventive inverter by an unbroken line. The voltage rise
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change referred to amounts to U~SO-U~so~ The smaller voltage
rise with the inventi~e circuit does: not h.ave a disadvantageous
effect on the noise margin of the circuit, since, in this
circuit, only the greater noise margin U'SO is reduced and not
the critical s~aller noise margin Usl. This noise margin
corresponds exactly to tl~e noise margin of the prior art
circuits. The smaller voltage rise, on the other hand, has an
advantageous effect on the decay and rise times, since the
capacitances in the collector-base junction of the transistor 2
and other line capacitances having more rapid charge exchange.
Advantageously, the smaller voltage rise which has
the above described effect on the rise and decay time,
compensates against the effect, described further above, of the
. additional capacitance of the Schottky diode.
By means of the inventive arran~ement of the base
connection region 242, which connects directly to the collector
regions 21 and 23, it is achieved that the ratio between the
collector-base junction surface to the base-emitter junction
surface becomes more favourable than this ratio is in the prior
art arrangements. This ratio is more favourable there, since
there the collector areas are separately diffused-in, whereas,
in the present invention, they are ini.tiall~ diffused-in as
one area, which i.s subsequently separated by the base connection
area 242.
It will be apparent to those ski.lled in the art that
many modifications and variati.ons may be effected without
departing from the spirit and scope of the novel concepts of
the present invention.
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