Note: Descriptions are shown in the official language in which they were submitted.
10~7737
BACKGROUND OF THE INVENTION
This invention relates to a control system for a pulse width con-
trol type inverter.
One example of an application of the pulse width control type in-
verter involves providing voltage regulation for an available source of
electric current. Since such a source is connected to a load such as a com-
puter, electric communication apparatus or the like, it is desirable to have
apparatus for providing a fast transient response when an external disturb-
ance such as the variations in DC voltage and load are expeTienced.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
Figure 1 shows a basic construction of a pulse width control type
inverter;
Figure 2 is a block diagram showing one example of a prior art con-
trol system for an inverter of the pulse width control type;
Figure 3A are waveforms useful to explain the operation of the con-
trol system shown in Figure 2 ;
Figure 3B shows enlarged views of portions of the waveforms shown
in Figure 3A for explaining the operation of the control system shown in
Figure 2 when the DC voltage varies;
Figure 4 is a block diagram showing one embodiment of the control
system of a digital pulse width control type inverter;
Figure 5A shows waveforms useful to explain the operation of the
control system shown in Figure 4;
Figure 5B shows enlarged views of certain portions of the waveforms
shown in Figure 5;
Figure 6 is a block diagram showing a modified embodiment of this
invention;
Figure 7A shows waveforms helpful to explain the operation of the
modified embodiment shown in Figure 6;
Figure 7B shows enlarged views of certain portions of the waveforms
shown in Figure 7A;
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Figure 8 is a block diagram showing another modification of this
invention;
Figure 9 show waveforms useful to explain the operation of the
modification shown in Figure 8; and
Figure 10 is a block diagram showing still further embodiment of
this invention.
As diagrammatically shown in Figure 1, a conventional pulse width
control type inverter comprises four semiconductor switching elements 1
through 4, such as power transistors and thyristors, which are ON-OFF con-
trolled in a predetermined sequence for converting the power of a DC sourceE into alternating current which is applied to an AC load 5. In order to
maintain the voltage across load 5 at a constant value irrespective of
variations in the DC voltage E, the conduction periods of the switching ele-
ments 1-4 are controlled in accordance with the magnitude of the DC voltage,
or the conduction periods of switching elements 2 and 4 alone are controlled
while the conduction periods of the switching elements 1 and 3 are maintained
fixed
Figure 2 shows one example of a control system which controls the
conduction periods of the switching elements 1-4 and comprises a reference
pulse generator 11 generating pulses having a frequency which is an integer
multiple (in this example, twice) of the output frequency of the
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inverter for determining the frequency thereof a sawtooth wave generator for
generating a signal synchronously with the generation of the reference
pulse, a constant voltage control circuit 13 for producing an analogue sig-
nal having a level corresponding to the DC voltage for the purpose of ob-
tainlng a desired output voltage, an analogue comparator 14 which compares
the output of the sawtooth wave generator with the output of the constant
voltage control circuit 13, a ring counter 15 which in response to the out-
put of the comparator 14 forms a pulse signal adapted to ON-OFF control the
switching elements 1 - 4 shown in Figure 1 in a predetermined sequence, and
a pulse amplifier 16 which amplifies the output of the ring counter 15 to a
level that can directly ON-OFF control the switching elements 1 to 4.
Figure 3A shows waveforms useful to explain the operation of the
control system shown in Figure 2 in which A, B and C show the waveforms at
corresponding portions of the system shown in Figure 2. The dotted line
level of curve B corresponds to the output of the constant voltage control
circuit 13. While this level is higher than that of the output of the saw-
tooth wave generator 12 the output C of the analogue computer 14 becomes "1"
whereas while the output level of the sawtooth wave generator 12 is higher
than the former, the output C becomes "0". During an interval in which the
output C of the analogue comparator 14 is "1" a control signal is applied to
the inverter through ring counter 15 and pulse amplifier 16 for rendering ON
the switching elements 1 - 4 in a predetermined sequence thus producing an
alternating currents output as shown by curve D. In this manner, the conduc-
tion period ~ of the switching elements 1 to 4 vary dependent upon the out-
put level of the constant voltage control circuit 13. Accordingly, the out-
put voltage shown by curve D is controlled such that the product EX~ of the
DC voltage ~ and the conduction period ~ would be always constant. Then, it
is possible to always obtain a constant output voltage regardless of the vari-
ation in the DC voltage E.
The control system descri~ed above, however, can not provide an
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efficient control by following up the output of the constant voltage control
circuit where the DC voltage varies rapidly which occurs when switching is
made between a commercial source and a battery source. Figure 3B shows en- !
larged views of portions of curves B and D shown in Figure 3A and useful to
explain the operation of the control system when the DC voltage varies rapid-
ly. In Figure 3B, lines a, b and c of curve B show the output of the con-
stant voltage control circuit 13. Since lines a, b and c intersect the out-
put of the sawtooth wave generator 12 at the same level, the conduction
periods ~ are the same. Even when the constant voltage control circuit 13
has no internal delay and is provided with DC voltage detecting means for
the purpose of improving its control ability, where the DC voltage varies as
shown by curve D-b, Figure 3B, the output of the constant voltage control
circuit 13 varies as shown by curve B-b, Figure 3B, whereas when the DC volt-
age varies as shown by curve D-c, the output of the constant voltage control
circuit varies as shown by curve B-c. In each case, however, the conduction
period G is equal to that when the DC voltage is constant as shown by curve
D-a. Accordingly, where the DC voltage is constant, product EX~ is also con-
stant, but when the DC voltage varies as shown by curve D-b, a deficiency
shown by hatched portion 1 and having an area of ~ ~ appears as an error,
whereas when the DC voltage varies as shown by curve D-c, a surplus shown by
hatched portion 2 and having an area of ~ C also appears as an error.
Thus, with the control system described above where the rate of variation of
the output of the constant voltage control circuit is large, it is difficult
to obtain high response speed. While the foregoing description was made with
respect to the variation of the DC voltage, the same difficulty also arises
when the output voltage varies due to rapid variation of the load.
Where the control system is constructed by using analogue technique,
the sawtooth wave generator 12 is usually constituted by an integrator in
the form of an operational amplifier, and it is necessary to use consider-
ably complicated circuit for the purpose of compensating for the errors of
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the characteristics of electronic circuit components such as diodes and tran-
sistors, and the off-set voltage of the operation amplifier as well as tem-
perature drift. Moreover, it is not easy to adjust the inclination and lin-
earity of the sawtooth wave. Also, the analogue comparator 14 is generally
constructed by an operational amplifier but this circuit is also difficult
to adjust due to error of the characteristics of the circuit components.
Furthermore, the operation of the comparator is affected by a noise signal
superposed upon the input signal. Accordingly, it is necessary to use a com-
plicated circuit for overcoming these defects.
SUMMARY OF THE INVENTION
It is, therefore, an object of this invention to provide an im-
proved control system for a pulse width control type inverter having excel-
lent transient response for such external disturbances as the variations in
the DC voltage and load and a simplified circuit construction and need not
be adjusted.
Another object of this invention is to provide a control system for
a pulse width control type inverter which can operate accurately without
being affected by the errors of electronic circuit components that comprise
the control sys~em.
A further object of this invention is to provide an improved con-
trol system for a pulse width control type inverter provided with an over-
current protective device.
According to one embodiment of this invention there is provided a
control system for a pulse width control type inverter made up of a plurality
of switching elements, comprising a constant voltage control circuit for pro-
ducing an analogue output, an A-D converter for converting ~he analogue out-
put into a digital signal, a reference pulse generator which generates a
reference pulse that determines the output frequency of the inverter, a clock
pulse generator which generates a clock pulse in synchronism with the refer-
ence pulse and having a frequency of an integer multiple of that the refer-
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ence pulse, a binary up-counter having a predetermined number of steps and
connected to be cleared by the reference pulse and counts up the clock
pulses generated by the clock pulse generator, a digital comparator for com-
paring the output of the binary up-counter with the output of the A-D con-
verter, a m step ~m represents an integer) up-counter for counting the build-
ing up edge of the output of the digital comparator, means responsive to the
- building up edge of the output of the digital comparator for clearing the
binary up-counter thereby repeating m times the counting up and clearing
operations of the binary up-counter until the up-counter produces a carry
signal so as to use an interval between the generation of the reference sig-
nal and the generation of the carry signal as a signal for determining the
conduction period of the switching elements.
According to another embodiment of this invention the control sys-
tem comprises a control voltage control circuit for producing an analogue
output, an A-D converter for converting the analogue output into a digital
signal, a reference pulse generator which generates a reference pulse that
determines the output frequency of the inverter, a clock pulse generator
which generates a clock pulse in synchronism with the reference pulse and
having a frequency of an integer multiple of that of the reference pulses,
a presettable down counter responsive to the generation of the reference
pulses for presetting the output of the A-D converter to an initial value
and then counts down the same in response to the clock pulses generated by
the clock pulse generator until a shift down pulse is produced, a m step ~m
represents an iteger) up-counter connected to count the shift down pulse, and
means responsive to the output of the up-counter for clearing the down coun-
ter when it generates the shift down pulse to preset again the output of the
A-D counter thereby repeating m times the counting down and the clearing op-
erations of the down counter until the up-counter produces a carry signal,
the interval between the generation of the reference pulse and the generation
of the carry signal being used as a signal for determining the conduction
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period of the switching elements.
In accordance with the invention there is provided a control system
of a pulse width control type inverter made up of a plurality of switching
elements, comprising a constant voltage control circuit for generating an
analogue signal; an A-D converter for converting said analogue signal into
a digital signal; a reference pulse generator for generating a reference
pulse which determines the output frequency of said inverter; a clock pulse
generator for generating a clock pulse having a frequency of an integer
~ultiple of that of said reference pulse in synchronism therewith; a preset-
table up down counter in which the output of said A-D converter 12 is preset
as an initial value at the time of generating of said reference pulse and
clock pulse is counted up starting from said initial value, means responsive
to a carry signal generated by said up down counter for presetting again the
output of said A-D converter in said up down counter as another initial value
and for causing said up down counter to count up starting from said another
initial value thereby repeating m (an integer) times said counting up oper-
ations, means for switching the operation of said up down counter to down
counting operation after said m counting operations have been repeated until
a shift down pulse is generated by said up down counter, means responsive
to said shift down pulse for presetting again the output of said A-D convert-
er in said up down counter for causing said up down counter to repeat (Q-m)
(Q is an integer) times of counting down operation until a (Q-m)th shift down
pulse is generated, means for determining the conduction period of said
switching elements to be equal to an interval between the m th carry pulse
and the (Q-m)th shift down pulse, and means responsive to the output of said
up down counter for controlling said conduction period such that the phase
of the output voltage of said inverter would be constant by setting Q=3m.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
.
In a preferred embodiment of this invention as shown in Figure 4,
circuit elements corresponding to those shown in Figure 2 are designated by
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the same reference characters. In addition to those shown in Figure 2 there
are provided clock pulses generator 21 which generates a clock pulse having
a frequency of an integer multiple of the frequency of the pulse generated
by the reference pulses generator 11 in synchronism therewith, a n (an inte-
ger) bit binary up-counter 22 which counts the number of the clock pulses
generated by the clock pulse generator 21 for producing n bit binary code
outputs, an A-D converter 23 which converts an analogue output signal of the
constant voltage control circuit 13 into a digital signal in the form of a
n bit binary code, a digital comparator 24 which compares the output of the
up-counter 22 with the digital output of the A-D converter 23 for producing
an output "1" or "0" in accordance with the relative magnitude of the inputs,
a m ~integer) step up-counter 25 which counts the change of the output of the
digital comparator 24 from "O" to "1", that is the building up edge of the
output and a R.S flip-flop circuit 26.
In Pigure 5A, curves A through F show waveforms at points A through
F shown in Figure 4. As above described the prior art control system com-
prises a sawtooth wave generator and an analogue comparator, whereas the con-
trol system of this invention is constituted by an A-D converter which con-
verts the analogue output of the constant voltage control circuit into a n
bit digital signal, a n bit binary up-counter, a digital comparator and a m
step up-counter. The A-D converter 23 which produces n bit outputs can re-
present 2n type states and it is constructed to produce (2n-1) codes of the
digital output when the output of the constant voltage control circuit 13
is at a maximum where n and m are integers. At this time, the clock frequen-
cy of the clock pulse generator 13 is selected to be 2nxm times of the fre-
quency of the referencr pulse. The binary up-counter 22 is cleared by the
output of an OR gate circuit 50 when a reference pulse is generated and then
starts to count the number of clock pulses. The output of the up-counter 22
and the output of the A-D converter 23 which produces 2n types of digital
signals are compared with each other by digital comparator 24. Where the
lQ~737
output of the up-counter is larger than the output of the A-D converter the
digital comparator 24 produces an "1" output, whereas where the output of
the up-counter is smaller than the output of the A-D converter, the compara-
tor produces a "0" output, and the output of the comparator 24 changes from
"0" to "1" when the output of the counter 22 becomes larger than the output
of the A-D converter 23 so that the OR gate circuit 50 is enabled to clear
again the up-counter 22. At the same time, the building up edge which oc-
curs when the output of comparator 24 changes from "0" to "1" is counted by
m step up-counter 25. At the same time, when counter 22 is cleared the out-
put of digital comparator 24 returns to "0" from "1" as shown by curve D inFigure 5 whereby the counter 22 begins to count up in a manner as above de-
scribed. When the m step up-counter 25 counts m building up edges of the
output of the digital comparator 24, the carry output of the counter 25
becomes "1" as shown by curve E. When the R.S flip-flop circuit 26 which
has been set by the output of the reference pulse generator 11 is reset by
the carry output, the conduction period ~ is determined by the Q output of
the flip-flop circuit as shown by curve F whereby an alternating current s
shown by curve G is produced. At this time, the counter 25 is cleared
simultaneously with the reversal or reset of the flip-flop circuit so that
the counter will not count until next reference pulse is applied. Denoting
the number of outputs of the A-D converter 23 by P, the conduction period Q
would correspond to PXm clock pulses and the output voltage E shown by curve
G would be controlled such that EX~ is constant in the same manner as in the
prior art.
By constructing the control system of the pulse width control type
inverter with digital technique it is possible to improve the transient
response of the control system for such external disturbance as variations
in the DC voltage and load.
Figure 5B is an enlarged view of certain portions of curves C and
G shown in Figure 5A where the DC voltage varies rapidly in the embodiment
shown in Figure 4. In Figure 5B when the DC voltage varies according to
g _
lQ97737
curve G in a manner as has been already described in connection with Figure
3B, the output of the A-D converter 23 which converts the analogue output
of the constant voltage control circuit 13 into a digital signal varies as
shown by dotted lines of curve C and in response to this variation the con-
trol system produces a conduction period of ~ = ~1 + ~2 + ........ + ~m. Ac-
cordingly, the error in this case corresponds to the error caused by the
deficient portion of the inclined portion of curve G
~El X 31 2 2 ~Em ~m
+ + ............. +
2 2 2
However, the error is far smaller than the error shown by D-l of Figure 3B
of the conventional control system, and can be reduced to a negligible value
by increasing m. In other words, the control system of this invention can
respond at a high speed to a rapid variation in the output of the constant
voltage control circuit 13.
Since the control system of this invention utilizing digital tech-
nique is required to merely budge "0" or "1" state of the signal it is not
necessary to consider such factors as the offset voltage of the operational
amplifier, and the errors of such electronic circuit components as diodes
and transistors which caused troubles in the prior art control system utiliz-
ing an analogue circuit. Moreover, since the inclination angle of the curvepassing through respective counts of the binary up-counter is determined by
the frequency of the clock pulse it is not necessary to adjust the inclina-
tion angle and linearity of the sawtooth wave shown in Figure 3A and also
the digital comparator does not require any level adjustment as in an analogue
comparator. Since the accuracy of the linearity of the counts of the binary
up-counter is determined to be l/12nxm~ by the ratio of the clock pulse fre-
quency to the reference pulse frequency, it is possible to improve the accu-
racy by increasing the bit number n of the binary up-counter and the A-D con-
verter or the step number m of the up-counter. Accordingly, it is possible
to obtain sufficiently high accuracies by selecting 2nxm to be about several
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hundreds. With recent development of data transmission technique, the cost
of the A-D convertor has been greatly decreased and it becomes possible to
fabricate a binary up-counter, a digital comparator and a multi-step up
counter with one or two in~egrated circuits without using resistors, capaci-
tors and diodes, thus obtaining an inexpensive control system having a simple
construction yet extremely reliable.
Figure 6 shows a modified embodiment of this invention in which
elements corresponding to those shown in Figure 4 are designated by the same
reference characters. In this modification, there is provided a 2n step
presettable down counter 31 in which the output of the A-D converter 23 is
preset by the output of OR gate circuit 50 having inputs connected to receive
the output of the reference pulse generator 11 and the shift down signal pro-
duced by the counter 31 and the initial value thus preset is counted down by
the clock pulse generated by clock pulse generator 21. The operation of this
modification can be understood from Figure 7A in which curve C shows the pro-
gress of counting of the down counter 31, the dotted lines thereof showing
the output of the A-D converter 23. In this modification, the n bit binary
up-counter and the digital comparator shown in Figure 4 were substituted by
the 2n step presettable down counter 31. More particularly, at the same
time when the R.S flip-flop circuit 26 is set by the reference pulse A, the
output of the A-D converter 23 is preset in the down counter 31 by the refer-
ence pulse and the initial value thus set is counted down by the clock pulse
generated by the clock pulse generator as shown by curve C. Denoting the
output of the A-D converter 23 by P, the initial value is sequentially count-
ed down as P, P-l, P-2 ...., and when the count reaches zero, a shift down
pulse is generated as shown by curve D which is counted by m step up-counter
25. In response to this shift down pulse and the reference pulse A, the OR
gate circuit 50 applies a preset instruction to the down counter 31 thus caus-
ing it to preset again the output of the A-D converter 23 and then count
down. Above described cycle of operation is repeated m times until m shift
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down pulses produced by the down counter 31 has been counted at which time
a carry signal produced by the up-counter 25 becomes "1" as shown by curve
E. This carry signal resets flip-flop circuit 26 so that the conduction
period ~ becomes equal to (Pxm) clock pulses. In this modification too high
transient rasponse can be obtained for such external disturbances as the
variations in the DC voltage and the load. Figure 7B is an enlarged view of
certain portions of curves C and G shown in Figure 7A. The error in this
case is the error caused by surplus portions
QEl X ~1 QE2 X ~2 m ~m
+ ..... +
2 2 2
As has already been described with reference to Figure 5B this error can be
decreased by increasing m.
With the construction shown in Figure 6, the down counter 31 too
can be fabricated with only one or two down counters thus simplifying the
circuit construction and increasing the reliability of the control system.
Although the foregoing description refer5 to a pulse width control
type inverter as shown in Figure 1, the inverter may be of single phase or
poly phase type and the invention is applicable to any type of inverter that
can produce an AC output having a waveform close to a sinusoidal wave.
It should be understood that the combination of the constant volt-
age control circuit and the A-D converter can be substituted by such opera-
tion device as a microcomputer that produces digital signals.
In a modified embodiment shown in Figure 8, there are provided a
reference pulse generator 121 which produces a reference pulse AS having a
frequency of an integer multiple (in this embodiment twice) of the output
frequency of the inverter, a clock pulse generator 122 which generates a
clock pulse DS having a frequency of an integer multiple of the frequency of
the reference pulse AS in synchronism therewith, R.S flip-flop circuits 123
and 124, an OR gate circuit 125, a constant voltage control circuit 126 which
generates an analogue signal having a level corresponding to the DC voltage,
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an A-D converter 127 which converts this analogue signal into a digital sig-
nal comprising a n (an integer~ bit binary code, and a binary presettable up
down counter 128 in which the output of the A-D converter 127 is preset by a
preset signal produced by the OR gate circuit 125. The Q output of the flip-
flop circuit 123 is applied to the up down counter 128 to cause it to count
up or down the clock pulse DS generated by the clock pulse generator 122
starting from said preset initial value. The up down counter produces a car-
ry signal during its counting up operation and a shift down signal during its
counting down operation. Counter 129 counts up the output FS of the up down
counter 128 to produce decimal code outputs 1, 2, ... m .... 1 .... An AND
gate circuit 130 is provided having its inputs connected to receive the Q
output of flip-flop circuit 123 and the Q output of flip-flop circuit 124.
The output GS of AND gate circuit 130 is applied to a ring counter 131 which
produces a pulse signal adapted to ON-OFF control the switching elements of
the inverter according to a predetermined sequence. The output of the ring
counter is applied to the inverter through an amplifier 132. An overcurrent
detector 33 is provided to detect the overcurrent condition on the output
side of the inverter caused by a short circuit, for example, for supplying
an instruction signal HS to the constant voltage control circuit 126 so as
to rapidly decrease the output level thereofO
The operation of the control system shown in Figure 8 will now be
described with reference to Figure 9 which shows various waveforms, in which
curves AS through HS correspond to those shown in Figure 8. In curve ES, Ec
shows the count of the up down counter 125 while dotted lines the levels of
the digital outputs of the A-D converter 127. The n bit output of this con-
verter can represent 2n types of the states. When the output of the constant
voltage control circuit 126 is at a maximum, the digital output thereof has
a code of (2n-1) and the frequency of the clock pulse DS is selected to be
(2n x Q) times of the frequency of the reference pulse AS. The outputs of
the counter 129 are applied to flip-flop circuits 123 and 124 to act as reset
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pulses at counts m and Q respectively, where Q = 3m. The up down counter
128 switches between counting up and counting down operations in response
to the Q output of flip-flop circuit 123 and performs its counting opera-
tion only when the output of counter 129 and the Q output of flip-flop cir-
cuit 24 are "1" and is cleared when these outputs are "0".
In response to the reference pulse AS (Figure 9A) produced by the
reference pulse generator 121, both flip-flop circuits 123 and 124 are set.
At the same time, the reference pulse AS is applied as a preset instruction
to the up down counter 128 through the OR gate circuit 125 for presetting
outputs El, E2 ....... of the A-D converter 127 as initial values which are
counted up by the clock pulse DS as shown in curve E, Figure 9. It is now
assumed that the output of the A-D converter 127 is El, then the clock pulse
is counted up as El, (El+l), (El+2) .... . When the count reaches 2n a car-
ry pulse FS is produced as shown by curve F. The carry pulse FS is counted
by counter 129 while at the same time is applied to the up down counter 128
via OR gate circuit 125 to act as a preset instruction. In this manner, the
output of the A-D converter 127 is preset again in the counter 128 to begin
the counting up operation. When this operation is repeated m times so that
the counter 129 counts m carry signals FS produced by the up down counter
128 the counter 129 applies a reset pulse to the flip-flop circuit 123. At
this time, the up down counter 128 is again preset with the output of the
A-D converter A-D by being applied with a carry signal FS as a preset instruc-
tion. At this time, however, since the output of flip-flop circuit 123 is
reversed to "0" from "1" as shown by curve B, whereby the up down counter
begins to count down from the preset count as El, (El-l) (El-2) ... until
the count is reduced to zero at which time a shift down pulse is produced as
shown by curve F. This shift down pulse is counted by the counter 129 suc-
ceeding to the counting of the carry pulse FS produced at the time of count-
ing up. This shift down pulse is applied to the up down counter 128 via the
OR gate circuit to preset again the output of the A-D converter 127 and to
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begin the counting down operation of this preset value. When above described
operation is repeated (Q-m) times the up down counter 128 produces (Q-m)
shift down pulses which are counted by the counter 129 together with m carry
signals. In other words the counter 129 counts Q pulses for applying a reset
pulse to flip-flop circuit 124. Concurrently with the reversal of the Q out-
put of the flip-flop circuit 124 from "1" to "0" (see curve C, Figure 9),
the up down counter 128 and counter 129 are cleared and they do not count
until next reference pulse AS is applied. The conduction period ~ (curve G)
is determined by the output of AND gate circuit 130 which is applied with
the ~ output of flip-flop 134 and the Q output of flip-flop circuit 124
whereby the inverter produces an alternating current output as shown by curve
J in Figure 9. This conduction period ~ corresponds to El x (Q-m) clock
pulses where El represents the output of the A-D converter 127, and the out-
put voltage E shown in Figure 9 is controlled such that EX~ is constant in
the same manner as in the previous embodiments. Since the interval Tl be-
tween the first reference impulse AS and the leading edge of the output pulse
GS of the AND gate circuit 130 is equal to (2n - Fl)Xm clock pulses, and the
interval between the first reference pulse AS and the trailing edge of the
output pulse GS is equal to Tl + ~ = [(2n - El) m + El (Q - m)] clock pulses,
0 the interval T3 representing the phase is expressed by
Tl + T2 2n 4 m + El (Q - 3m)
T = = 2
Since it is selected that Q = 3m
T3 = 1 2 = 2n m
which is constant independently of the output El, of the A--D converter 127.
In other words, since at the end of T3, mth shift down pulse is generated
and since this instant is always constant independently of the output of the
A-D converter 127, the phase is maintained always at a constant value even
when the conduction period ~ varies in response to the output of the A-D con-
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lQ~7~37
verter 127.
When the output current of the inverter becomes excessive due to
short circuiting or the like, the overcurrent detector 133 rapidly lowers
the output level of the constant voltage control circuit 126 thus rapidly
decreasing the output of the A-D converter 127 to level E4 as shown by curve
E, Figure 9 with the result that the period of producing the shift down
pulse by the up down counter 128 which has been counting in accordance with
output E3 of the A-D converter 127 is decreased greatly as shown by curve F.
Accordingly, the conduction period ~ is greatly reduced as shown by curve J
thus greatly decreasing the output voltage, and the output current which has
been increasing is quickly limited below overload capacity Kl of the inverter
as shown by curve K. The time at which the up down counter 128 produces m th
carry pulse FS for determining the leading edge of the output as shown in
Figure 9E varies in a range equal to the fore one half (in this example 90)
of the period of the reference pulse AS in response to the output of the A-D
converter 127, whereas the time at which the counter 129 produces (Q-m)th
shift down pulse for the purpose of determining the trailing edge of the out-
put pulse GS can be freely varied within the period (in this example 180) of
the reference pulse AS so that it is possible to quickly limit the overcurrent.
The error in the conduction period can be made negligibly small as in the
preceeding embodiments.
In the circuit shown in Figure 8, although the output of the over-
current detector 133 is applied to the constant voltage control circuit 126,
this output is also applicable to a clearable buffer circuit, not shown,
provided on the digital output side of the A-D converter for decreasing the
digital output or to an A-D converter which can be cleared by the output of
the overcurrent detector for decreasing the digital output level of such A-D
converter.
In a modified circuit shown in Figure 10 instead of applying the
output of the overcurrent detector 133 to A-D converter 127, the output is
. - 16 -
7~37
applied to the clock terminal of counter 129 via OR gate circuit 142. It
is also possible to apply the output of the overcurrent detector to clear-
able buffer circuit not shown, to act as a clear signal to lower the level
of the digital output or to use an A-D converter capable of clearing its
digital output or to the A-D converter as a clear signal for lowering the
level of its digital output.
