Note: Descriptions are shown in the official language in which they were submitted.
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This invention is directed to an improvement
over the video signal processor disclosed and claimed
in our United States patent 3,900,885 issued August 19,
1975.
The above U.S. patent is directed to a video
signal processor for removing time base errors from
input video signals supplied by a video recording device,
e.g. a video tape recorder, or other video signal sources.
Incoming video signals are converted from analog to digital
form and temporarily stored in a memory unit. Time
base errors are removed from the video signals by storing
the digitized video signals at a clocking rate which varies
in a manner generally proportional to the time base errors,
and fetching these stored signals at a second clocking rate.
The clock signals for storing the digitized information
are derived from an input phase lock loop which includes
a voltage controlled oscillator whose frequency is depen-
dent upon the frequency content of the instantaneous
line of video information being stored. After storage,
the digitized time base corrected video information is
clocked out from the memory unit, reconverted to analog
form, processed and furnished to an output terminal for
use with appropriate follow-on devices.
The above-noted video signal processor is com-
patible with a wide variety of types of video signals and
with a wide variety of signal input devices. When oper-
ating on signals from a generator locked source, e.g.
a capstan servo recorder,
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-- termed V-LOCK mode-- this system is capable of producing
broadcast quality monochromatic or color video signals from
monochromatic, direct color or processed color input video
signals. Direct color video signals are defined as color
video signals in which successive lines of information
contain color burst portions having a phase difference of
180, with a color frequency fc= 455 H, where H is the
horizontal frequency (NTSC definition). Processed color
signals, also known as heterodyned or non-phased color
signals, are color signals having fc and H which do not
comply with the frequency and phase requirements of direct
color. In an alternate mode of operation, termed LINE LOCK
mode, the processor is capable of producing monochromatic or
color video signals which have a substantially reduced time
base error from monochromatic color video signals supplied
; by an internally synchronized, i.e., a non-generator locked,
signal source, such as a non-capstan servo video tape
recorder. In still another mode of operation, termed
INTERLACE mode, the processor is capable of producing from
processed color video signals supplied by an internally
synchronized signal source time base corrected quasi-direct
color video signals, defined as color video signals which
are properly phased in accordance with the definition of
direct color given above but which do not comply with the
frequency requirements of NTSC direct color. However, the
time base corrected quasi-direct color video signals from
the processor can be converted to broadcast quality direct
color video signals by merely dubbing the signals up to a
quadraplex video tape recorder or other type of capstan
servo video tape recorder and reproducing the recorded
signals.
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The input phase lock loop of the above-referenced
processor includes a first coarse loop controlled by the
frequency of successive horizontal sync pulses in the
incoming video signal, and a second fine phase lock loop
controlled by the color burst frequency of the burst portion
of successive lines of video information when the input
video signals are direct color video signals. Frequency
deviations in the incoming signals are converted to error
voltages, which are summed and used to control the frequency
of the voltage controlled oscillator.
The memory unit comprises a plurality of indivi-
dual memories, each capable of storing a plurality of
horizontal lines of video information. A sequence control
unit controls the selection of each memory for writing and
reading in such a manner that double clocking of a single
memory which marginally occurs at the extreme boundaries of
the correction range of the system is quickly relieved,
The signals for clocking the digitized information
out from the memory unit are generated by an output phase
lock loop which is driven by an output subcarrier signal fsc
obtained from either an internal or an external color fre-
quency standard when the system is operating in V-LOCK mode;
and which generates clocking signals which are phase locked
to the vertical sync portions of the uncorrected input video
signals when the system is operating in LINE LOCK mod~.
Various sync signals obtained from either the internal sync
generator or an associated studio sync generator are coupled
to an output processor amplifier in which the sync signals
are added to the time base corrected video information
signals.
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An output color processor unit is provided for
removing hue phase variations from processed color video
signals by decoding the color component of the video signals
after time base correction, using the instantaneous fre-
quency of the burst portion of successive lines of processedcolor video information; and by re-encoding these signals
using the above-noted output subcarrier frequency fsc when
the system is operating in process color mode, or using a
variable subcarrier frequency when the system is operating
in INTERLACE mode.
While the above system has been found to provide
~`excellent results for a wide range of applications, in some
marginal cases, e.g. when the uncorrected input video signals
are supplied from extremely low-quality pre-recorded video
- 15 tapes, occasional noise and jitter lying in the range below
about 20 nanoseconds is still evident in the output video
signals after time base correction has been effected.
The invention comprises a video signal processor
having the flexibility and operational capability of the
above referenced processor, but which has an improved correc-
tion capability for removing time base errors down to the
lower range of about four nanoseconds and which produces
color video output signals having an improved signal to
noise ratio. An input color processor is provided upstream
of an input video amplifier for processing input color video
signals of the processed color type to synchronize the color
components of each incoming line of video information with
the input clock reference signal train generated by the
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voltage controlled oscillator in the input phase lock loop.
The input color processor comprises means for separating the
incoming processed color video signals into chroma and
! luminance portions, means for converting the chroma signals
into equivalent chroma signals which are phase locked to the
input clock reference signal train, means for delaying the
separating luminance portion by a period equivalent to the
delay of the chroma portion of the corresponding line in
passing through the converting means, and means for com-
bining the delayed luminance portion with the phase lockedchroma signals. The converting means includes means for
mixing the separated chroma portion with a first modulation
signal train derived from the input clock reference signal
train at a first multiple thereof, second means for mixing a
reference signal train derived from the burst portion of
successive lines of the incoming color video signals with a
second modulation signal train also derived from the input
clock reference signal train at a different multiple there-
of, and third means for mixing the intermediate signals
produced by the first and second mixing means to generate
chroma signals containing the original chroma information
but phase locked to the input clock reference signal train.
Also included is an output color processor for
correcting hue phase variations in processed color video
signals supplied by a non-capstan servo recorder or the like
in LINE ~OCK mode of operation.
For a fuller understanding of the nature and
advantages of the invention, reference should be had to the
ensuing detailed description taken in conjunction with the
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accompanying drawings. In the drawings:
Figure 1 is a schematic block diagram of a system
embodying the invention;
Figure 2 is a schematic diagram illustrating the
phase lock loop of the Figure 1 system;
Figure 3 is a waveform diagram illustrating the
operation of a portion of the input phase lock loop of
Figure 2;
Figure 4 is a schematic diagram illustrating the
analog-to-digital converter;
Figure 5 is a schematic diagram illustrating the
; sequence control unit;
Figure 6 is a waveform diagram illustrating the
operation of the sequence control unit of Figure 5;
Figure 7 is a schematic diagram illustrating the
data multiplexer;
Figure 8 is a schematic diagram illustrating the
subcarrier processor;
~ lQ~77~5
Fig. 9 is a schematic diagram illustrating the
output phase lock loop;
Fig. 10 is a diagram illustrating the operation
of the lock detector portion of the output phase lock loop
of Fig. 9;
Fig. 11 is a schematic diagram of the digital-
to-analog converter unit;
Fig. 12 is a schematic diagram of the output
color processor unit;
Fig. 13 is a schematic diagram of the processor
amplifier unit;
Fig. 14 is a schematic diagram of the first
specific embodiment of the input color processor unit; and
Fig. 15 is a schematic diagram of a second
lS specific embodiment of the input color processor unit.
Turning now to the drawings, Fig. 1 is a system
diagram of the preferred embodiment of thè invention.
Before proceeding with a detailed description
of the Fig. 1 embodiment, brief consideration of the general
operating principles of the invention will facilitate an
understanding of the manner in which the various types of
input video signals described below are processed according
to the invention. All incoming video signals are converted
line by line from analog to digital form, temporarily
stored in a memory unit, reconverted from digital to analog
form and processed to improve the information content of
the reconverted analog signals. Time base correction is
achieved by sampling and storing each line of video at a
first rate, and reading the
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digital signal out from memory at a second rate. The sam-
pling and storing rate varies in accordance with the fre-
quency content of the uncorrected video signals; the reading
rate is either constant or varies at a rate determined by
low frequency variations in the uncorrected input signal,
depending on whether the incoming video signals are received
from a V-LO~K or a LINE LOCK source.
This may best be illustrated by the following
examples. Incoming uncorrected video signals obtained from a
V-LOCK source are sampled and stored at a variable rate and
read out from memory at a constant rate. The incoming
uncorrected video signals from a LINE LOCK source are
sampled and stored at a first variable rate and read out
from memory at a second variable rate. For V-LOCK source
lS generated signals, the variable sample and store rate is
controlled by both the repetition rate of the horizontal
sync pulses and also the burst frequency of successive lines
of color video, if the input video signals are of the direct
color type. If the input video signals are of the processed
color type or are monochromatic, the sample and store rate
is controlled by the repetition rate of the horizontal sync
pulses alone. For LINE LOCK source signals, the variable
sample and store rate is controlled by the repetition rate
of horizontal sync pulses, regardless of whether the signals
are color or monochromatic, while the variable reading rate
is controlled by the repetition rate of vertical sync pulse
portions of the incoming signals. The system configuration
and operation of the Figure l embodiment will now be described.
Video input signals are coupled from an associated
video tape recorder or other source of video signals via an
input terminal 10 to a first blade 11 of a double-pole double-
throw switch 12. A first contact, labeled DIRECT, of the
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upper portion of switch 12 is coupled directly to the
input of a conventional input video amplifier 14. A second
contact, labeled PROCESS, is coupled to the signal input
of an input color processor unit 15, described below in
detail. Input video amplifier 14 is a conventional circuit
having a video detector/separator, a sync stripper, a burst
separator and a chroma detector. The video signals output
from amplifier 14 are coupled to the input of analog-to-
digital converter 23 shown in detail in Fig. 4. The
composite sync, burst and chroma detect signals from input
video amplifier 14 are coupled to individual input terminals
of an input phase lock loop 27 shown in detail in Fig. 2.
Input phase lock loop 27 generates high frequency
sample and store signals from the signals input thereto,
corrected in accordance with the frequency deviations in
the input video signals in the manner described below.
The sample signals are coupled to analog-to-digital con-
verter 23 for controlling the rate at which incoming video
signals are sampled. The store signals are coupled to
sequence control unit 28 for use as a reference clock
rate signal for storing the sampled portions of the video
signals in the memory unit described below. In the
preferred embodiment, the frequency of the sample and store
signals generated by input phase lock loop 27 is approximately
3fc where fc is the standard color burst frequency, it
being remembered that the instantaneous frequency of the
sample and store signals is a function of the time base
M
errors in the video signals. Other multiples - (M, N both
integers) fc may be employed for this purpose, if desired.
Input phase lock loop 27 also generates several reference
signals designated PROCESSED H, 2~, PROCESSED V, V SHUTOFF
and CO~OR MODE, which
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are coupled respectively to input video amplifier 14, se-
quence control unit 28, an output phase lock loop 33, a
digital-to-analog converter 38 and a processor amplifier 39,
all for purposes to be described below.
Input phase lock loop 27 also generates a re-
ference signal train having a frequency 4f which is coupled
along with the high frequency sample and store signal train
3f to a pair of input terminals of the first embodiment of
input color processor 15 shown in Figure 14.
The digitized video signals are coupled via a data
bus 29 from analog-to-digital converter 23 to three separate
memory units 30, 31, 32 and also directly to a data multi-
plexer 37. Memory units 30-32 are controlled by sequence
control unit 28 by a plurality of mode control signals
ENABLE A, ENABLE B, ENABLE C and clock signals CLOCK A,
CLOCK B, CLOC~ C.
Multiplexer 37 is controlled by SELECT signals
generated by sequence control unit 28 which conditions
multiplexer 37 to accept information at one of the four
possible data inputs, viz. from one of memory units 30-32 or
directly from analog-to-digital converter 23. In the
preferred embodiment, each memory unit 30-32 comprises an 8-
bit by 2,048 word serial shift register with separate clock
and enable inputs capable of operation at high frequencies.
Each memory unit i5 clocked at approximately 3fc (10.7 MHZ),
which provides a storage capacity of about three complete
lines of video information per unit. If desired, other
memory configurations may be employed without departing from
the spirit of the invention. In addition, shift registers
having different line storage capacities may be similarly
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employed.
Sampled video information is sequentially stored
by cyclically enabling memory units 30-32 and serially
storing three lines of digitized video information in each
selected memory unit. For example, assuming the three most
recently sampled lines of digitized video information were
serially written into memory unit 30, sequence control unit
28 next enables memory unit 31 for storage of the next
succeeding three lines of information, after which memory
unit 32 is enabled, then memory unit 30, etc~
Contemporaneously with the storage of sampled
video information into a selected memory unit, sequence
control unit 28 enables the video information stored in a
different memory unit to be sequentially fetched to data
multiplexer 37. Stored information is sequentially fetched
in a manner similar to the store operation, viz. by cycli-
cally enabling memory units 30-32 and sequentially fetching
the three lines of video information from each enabled
memory unit. Sequence control unit 28 is additionally
provided with means for resetting the contemporaneous read
and write operation whenever the time base error in the
incoming video signals is so gross as to require simultan-
eous reading and writing from the same memory unit.
As noted above, during the write operation the
clock signals supplied by sequence control unit 28 to memory
units 30-32 are derived from the 3f signals generated by
input phase lock loop 27. During the read operation, the
clock signals supplied by sequence control unit 28 are
derived from a different reference signal 3fsc, generated by
an output phase lock loop 33 illustrated in detail in Figure
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9. Output phase lock loop 33 generates the 3fsc signals
derived from either (a) a reference signal fsc supplied
thereto, or (b) vertical sync portions of the uncorrected
input video signals, depending on the selected mode of
operation.
A conventional high frequency crystal controlled
oscillator 34 generates a frequency standard signal Nfc (N
an integer), which in the preferred embodiment is 4fc.
This clock signal is coupled via a switch X (shown in an
alternate INTERLACE position) to the color subcarrier
reference frequency input of a conventional video sync
generator 35, which in the preferred embodiment is a Fair-
child Type 3261 TV Sync Generator. Sync generator 35 has
three additional reference signal inputs coupled respect-
ively to the blade of a switch Y, for a purpose describedbelow, and to composite sync and composite blanking signals
obtained from an external sync generator, such as a conven-
tional studio sync generator. Sync generator 35 is also
provided with a mode control input coupled to the moveable
blade of a switch Z for selecting sync or external sync.
Sync generator 35 provides a plurality of re-
ference signals which are coupled to several sub-units of
the preferred embodiment in the following manner. A refe-
rence signal H', which is a periodic signal having a fre-
quency equal to or close to the frequency of standardhorizontal sync pulses, is coupled to an input terminal of
sequence contro~ unit 28 for providing a reference signal
for switching memories 30-32 during the read portion of the
system operation. A color frequency standard termed INTERNAL
fsc is coupled to a first input terminal of a subcarrier
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processor unit 36, illustrated in detail in Figure 8, for a
purpose to be described. A FIELD START reference signal,
which is a signal having a frequency of about 60 HZ, is
coupled to an input terminal of output phase lock loop 33.
COMPOSITE SYNC, BURST FLAG, and COMPOSITE BLANKING signals ~-
are all coupled to individual input terminals of processor
amplifier 39. In addition, COMPOSITE BLANKING signals are
coupled to an input terminal of input phase lock loop 27.
Subcarrier processor unit 36 has an additional
reference signal input to which an external subcarrier EXT
fsc is supplied, and a pair of phase control inputs coupled
to a pair of manually adjustable controls labeled SYSTEM
PHASE and HUE PHASE, all for a purpose to be described. The
output of switch Z is also coupled to a mode control input
of subcarrier processor unit 36. Subcarrier processor unit
36 generates a pair of output reference signals: a first,
labeled fsc, is coupled to a first reference frequency input
terminal of output phase lock loop 33 and also to an input
of a color processor unit 40; a second labeled f'sc is
coupled to a separate input terminal of processor amplifier
39.
Output phase lock loop 33 is provided with a mode
control input which is coupled to a second blade of switch Y
for a purpose to be described. Output phase lock loop 33
generates the following reference signals: a first, termed
3fsc is coupled to the read clock input of sequence control
unit 28, a sample input of multiplexer 37 and a sample input
of a digital-to-analog converter unit 38 shown in detail in
Figure 11. A second, labeled Nf'Sc is coupled to the LINE
LOCK terminal of switch Y for a purpose to be described. A
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third, termed f''sc, is coupled to the color subcarrier
demodulation signal input of an output color processor unit
40 shown in detail in Figure 12.
The digital video information signals fetched
line-by-line from memory units 30-32, or coupled directly
from analog-to-digital converter 23 to data multiplexer 37,
are processed
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therein in the manner noted below and coupled to the input
of digital-to-analog converter unit 38. Digital-to-analog
converter unit 38 is provided with a mode control input
coupled to the second blade of a switch Y which controls
the operation of this unit in the manner described below.
Digital-to-analog converter 38 furnishes three output signals,
OUTPUT BURST FLAG, OUTPUT COMPOSITE SYNC and VIDEO, here-
inafter abbreviated as OBF, OCS, and DAC VIDEO, which are
coupled to individual input terminals of processor amplifier
39. The OCS signals are additionally coupled to individual
input terminals of output color processor unit 40. In
addition, digital-to-analog converter unit 38 furnishes an
additional signal, termed DAC CHROMA, to a separate input
terminal of color processor unit 40. Output color processor
unit 40 generates an output signal, termed PROCESSED CHROMA,
which is coupled back to digital-to-analog converter unit
38.
SYSTEM COMPONENTS
The system components illustrated in Figs. 2-13
are substantially identical to the corresponding units in the
above U.S. patent 3,900,885. Accordingly, reference should
be had to the disclosure contained therein for a detailed
discussion of the construction and operation of these
components. For convenience, a brief summary of the opera-
tion of each of the components is given in the ensuingdiscussion.
INPVT PHASE LOCK LOOP 27
With reference to Figs. 2 and 3, input phase lock
loop 27 includes elements 42, 44, 45, 46, 47 and 49 which
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generate a pulse train designated PROCESSED H from valid
horizontal sync pulses and alternate equalizer pulses
present in the composite sync portion of the input video
signals. PROCESSED H is a pulse train having pulses of a
uniform width of 3 microseconds and serves as a reference
signal for the coarse phase lock loop described below.
Elements 51 and 52 generate a pulse train signal termed
PROCESSED V in response to vertical sync portions of the
composite sync in the incoming video signal and serves as a
reference signal for output phase lock loop 33 during LINE
LOCK mode operation as described below.
Elements 53, 54, 55, 57, 58 and 60 comprise phase
lock loop in which input voltage controlled oscillator 54
generates a high frequency reference signal train 12f, the
15 frequency of which is controlled by the frequency of PROCES- !
SED H relative to a RAMP reference signal when the input
video signals are monochromatic or comprise processed color
signals. A fine phase lock loop comprising common loop
elements 60, 54, 55, and elements 50, 56, 59, 61 provides a
second control signal for additionally controlling the
frequency of the 12f reference signal train from input VCO
54 in accordance with the frequency of burst in each line of
incoming video relative to an f reference signal. Elements
50, 62, 63 and 64 limit the operation of the fine phase lock
loop to input video signals of the DIRECT color type,
element 63 being a conventional single shot having a period
of about 1 msec ~i.e. about 15 lines of video) and element
64 being a re-triggerable single shot having a period of
about 90 microsecs (i.e. about 1.5 lines of video). The
master reference signal from input VCO 54 is divided down by
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a conventional divider 55 to provide the 3f sample and store
signals, the 4f reference signal train for the Figure 14
embodiment of the color processor unit 15 and the f re-
ference signal train for the Figure 15 embodiment of the
input color processor unit 15.
ANALOG-TO-DIGITAL CONVERTER 23
With reference to Figure 4, analog-to-digital
converter 23 is a parallel-serial converter which converts
each sampled portion of the incoming analog video infor-
mation into an 8-bit Grey code digital character. Each
sampled portion is converted to a digital character in two
4-bit parallel conversions which occur serially. The analog
video input signals are sampled at the rate 3f in response
to the receipt of each sample pulse from input phase lock
loop 27.
SEQUENCE CONTROL UNIT 28
With reference to Figure 5, sequence control unit
2~ controls the selection and clocking of memory units 3032
during reading and writing.
With reference to Figures 5 and 6, in operation
VCO 2H signals (waveform A) are divided down by counters 90
and 91 to sequentially generate the W SEQ A, W SEQ B and SEQ
C signals (waveforms B-D). These signals are coupled via OR
gates 98-100 to sequentially enable a different one of
memory units 30-32 for writing data therein. The 3f clock
signals are coupled during any given wxite interval through
one of AND gates 92-94 and OR gates 95-97 (waveforms E-G) to
a selected one of memory units 30-32 in order to write
successive lines of digital information from analog-to-
digital converter 23 into the selected memory unit. After
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three lines have been written into a specified memory, the
adjacent memory is specified by the output of counter 91 and
the next three lines of information are written therein.
Contemporaneously with the write operation,
counters 101 and 102 divide down the H' timing pulses
(waveform H) and sequentially generate the R SEQ A, R SEQ B
and R SEQ C signal (waveforms K-M). These signals are
coupled via OR gates 98-100 to sequentially enable a diffe-
rent one of memory units 30-32 for fetching data therefrom.
The 3fsc read clock signals are coupled during any given
read interval through one of AND gates 103-105 and OR gates
95-97 (waveforms N-P) to a selected one of memory units 30-
32. The combined ENABLE and CLOCK signals coupled to memory
unit 30 via OR gates 95, 98, respectively, are illustrated
by waveforms Q and R. As shown, memory unit 30 is cycli-
cally enabled for writing of data therein and fetching of
data therefrom by the ENABLE signals (waveform Q) generated
from successive W SEQ A and R SEQ A signals. When enabled,
memory unit 30 is alternately clocked by 3f write clock
signals and 3fsc read clock signals. As will be evident to
those skilled in the art, the separate write and read clock
signals are not mutually synchronous. Since the combined
ENABLE and CLOCK signals coupled to memory units 31 and 32
are substantially similar to the memory unit 30 ENABLE and
CLOCK signals, they are omitted from Figure 6 to avoid
prolixity~
The R SEQ A, R SEQ B and R SEQ C signals are also
individually decoded by select decoder 106 to 2-bit SELECT
signals for synchronizing the operation of data multiplexer
37 with the fetching of data from one of memory units 30-32.
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For economy of space, the SELECT signals are omitted from
Figure 6.
Elements 107-112 comprise a special preset circuit
for alleviating double clocking of a single one of memory
units 30-32 when the time base errors in the input video
exceed the maximum correctable deviation. Waveforms S-Z
illustrate the operation of this preset circuit in response
to an overlap between W SEQ C and R SEQ C write and read
enable signals. As illustrated in this figure, W SEQ A, W
SEQ B and W SEQ C write enable signals are represented by
waveforms S-U. R SEQ A, R SEQ B, and R SEQ C read enable
signals are represented by waveforms V-X. For illustrative
purposes, the write enable signals are all depicted as
having a uniform period which is approximately 10 percent
shorter than the uniformly depicted period of the read
enable intervals. Thus as operation of the sequence control
unit proceeds, the phase difference between the write enable
intervals and the read enable intervals accumulates until
the W SEQ C write enable signal overlaps the R SEQ C read
enable signal at the point indicated by lead line 114. When
this overlapping condition obtains, counters 101, 102 are
preset at the end of the W SEQ C write enable intervals to a
combined count representing one third of the total length of
the R SEQ B interval.
DATA MULTIPLEXER 37
With reference to Figure 7, data multiplexer 37
comprises a switching network 115 for routing data from
memory units 30-32 or directly from analog-to-digital
converter 23, to a conventional 8-bit Grey code converter
117, and a conventional deskewing register 119 clocked by
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the 3fsc output clock signals from output phase lock loop 33
in order to remove any skew between the eight digital
character bits which may be introduced during code conversion.
SUBCARRIER PROCESSOR UNIT 36
With reference to Figure 8, subcarrier processor
unit 36 comprises a selector circuit 121 controlled by the
setting of switch Z for coupling either INT fsc or EXT fsc
subcarrier reference signals to a first phase shifter 122.
First phase shifter 122 includes a manually adjustable
control element 123 for permitting adjustment of the phase
f fsc reference signal train before application of this
signal train to output color processor 40. Unit 36 also
includes a second phase shifter 124 having a manually
adjustable control element 125 for permitting adjustment of
the phase of f'sc reference signal train before application
of the signal train to processor amplifier 39.
OUTPUT PHASE LOCK LOOP 33
_ .
With reference to Figure 9, output phase lock loop
33 includes an upper loop comprising elements 126-129 and a
lower loop comprising elements 130-134 and that portion of
sync generator 35 (Figure 1) which generates the field start
signal train from the Nf'sc signals input thereto via
control switch Y. When switch Y is placed in the V-LOCK
mode position, the upper loop is active and the 3fsc output
signal train is derived from fsc reference signals input to
phase comparator 126 from subcarrier processor 36. When
switch Y is in the LINE LOCK mode, the lower loop is active
and the 3fsc signal train obtained from the output of
voltage controlled oscillator 133 is employed as the output
signal train. In this mode, the frequency of the signal
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output from voltage controlled oscillator 133 is controlled
by the phase difference between the FIELD START signals
obtained from sync generator 35 and the PROCESSED V signals
derived from the input video signals by input phase lock
loop 27. Thus, the 3fsc signal train is phase locked to the
vertical sync portions of the input video signals and
provides a slowly varying reference clock signal which
averages out variations in the input signal. In either mode
of operation, the 3fsc output signal train is divided down
by divider 129 to provide the fsc'' color demodulation
reference signal train, which is coupled to output color
processor 40. Dual bandwidth filter 131 and lock detector
132 provide rapid initial phase lock of the lower loop onto
the input vertical sync. As shown in Figure 10, if the
magnitude of the control signal output from phase comparator
130 lies within the unshaded range, filter 131 operates in a
first narrow band mode. However, when the magnitude of the
control voltage lies outside the lock range, lock detector
132 switches filter 131 to a wide band mode so that the
lower loop can quickly lock to the input vertical sync.
Once locked, the control voltage swings into the locked
range so that filter 131 operates in the narrow bandwidth
range.
DIGITAL-TO-ANALOG CONVERTER UNIT 38
With reference to Figure 11, digital-to-analog
converter unit 38 has a digital-to-analog converter 140,
which converts incoming digital video to analog form, a
sample and hold circuit 141 and a clock driver 142 which
function as a deskewing circuit to stabilize the converted
signals, and three vertically arranged signal paths. The
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first path comprises elements 144-149 and functions to
extract composite sync from the video and to generate
successive output burst flag signals which are inhibited
during vertical sync portions by burst flag inhibit circuit
149. The second and third branches, respectively termed the
V-LOCK and LINE LOCK video paths, provide alternate paths
for the analog video signals and comprise elements 152-154
and 158-163, respectively. A video switch 155 permits video
signals from the V-LOCK signal path to be coupled to the DAC
VIDEO output terminal whenever switch Y is placed in the V-
LOCK position, and video signals from the LINE LOCK signal
path to be coupled to the DAC VIDEO output terminal whenever
switch Y is in the LINE LOCK position. PROCESSED color
video signals are also coupled from the output of emitter
follower 157 to output color processor 40 and are returned
after processing from unit 40 to a summing.
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junction 162 where they are combined with the corresponding
luminance portion before being output to the DAC VIDEO
terminal.
OUTPUT COLOR PROCESSOR UNIT 4 0
With reference to Fig. 12, output color processor
unit 40 comprises a conventional color demodulator and re-
encoder which demodulates processed color video signals
from digital to analog converter unit 38 with fsc'' reference
signal train from output phase lock loop 33, and re-encodes
the demodulated signals with fsc color subcarrier reference
signal from subcarrier processor unit 36.
PROCESSOR AMPLIFIER UNIT 39
With reference to Fig. 13, processor amplifier
unit 39 includes elements 216-219 which generate color
burst for combination with the DAC VIDEO signals in a
summing network 213, elements 210-212, 214 and 215 for re-
setting the ~C level of the DAC VIDEO signals and removing
undesired original sync portions of the signal remaining
in the DAC VIDEO signals prior to combination with color
burst in summing junction 213, and elements 220-223 for
combining the summed DAC VIDEO and burst signals with com-
posite sync from sync generator 3~.
INPUT COLOR PROCESSOR UNIT 15
Fig. 14 illustrates a first specific embodiment
of input color processor 15. Incoming cGlor video signals
are contemporaneously coupled to the respective inputs of
a chroma filter 230, a sync separator 231 and a low-pass
filter 232. Chroma filter 230, is a conventional filter
for separating the color components of each line of video
information from the luminance components and preferably
comprises a 1 MHZ wide band pass filter centered about
3.58 MHZ. The output of chroma
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filter 230 is coupled to a first input of a conventional
burst gate 233 and also to a first signal input of a balanced
modulator 234. The remaining input to balanced modulator
234 is the 4f reference signal train obtained from input
phase lock loop 27. The output of balanced modulator 234
is coupled to the input of an amplifier 235. Amplifier 235
is a conventional band pass amplifier having a band pass
range centered about 5fc. The signal train output from
amplifier 25 is coupled to a first input of a second
balanced modulator 236.
As noted above, incoming video color signals are
also coupled to the input of a conventional sync separator
231, the output of which is coupled to the input of a pulse
generator 238. Pulse generator 238 is a conventional device
for generating a pulse in the nature of a burst flag having
a width substantially equal to the width of the burst
portion of each line of incoming video information. The
output of pulse generator 23~ is coupled to the control
input of a burst gate 233 to permit the passage there-
through of only the burst portion of each line of videoinformation.
The output of burst gate 233 is coupled to a
first input of a phase comparator 240. The output of phase
comparator 240 is coupled via a limiter amplifier 241 to
the control voltage input of a voltage controlled oscillator
242 having a center frequency fc. The output of voltage
controlled oscillator 242 is coupled via a limiter amplifier
243 to the remaining input of phase comparator 240.
The output of limiter amplifier 243, which is a
reference signal train having a frequency controlled by the
frequency of the burst portions of successive lines of video
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information, is also coupled to the first input of a conven-
tional mixer 245. The remaining input to mixer 245 is the
3f signal train obtained from input phase lock loop 27,
described above. The output of mixer 245 is coupled through
a conventional band pass amplifier 246 having a pass band
centered about 4fc to the remaining input of balanced modulator
236. The output of modulator 236 is coupled through a con-
ventional chroma filter 247 to a first input of a summing
network 248. The remaining input to summing network 248
is the luminance portion of the corresponding line of video
information furnished by low pass filter 232 and a delay
unit 249 which provides a delay equal to the transit time
of the chroma information through the above-described elements.
Input color processor 15 functions to phase lock
the color portion of processed color video signals input
thereto to the 3f input clock storage signals generated by
input phase lock loop 27. In operation of the Fig. 14
embodiment, the chroma portion of the incoming video signal
is stripped by chroma filter 230 and coupled to balanced
modulator 234 along with the 4f modulation signal train
from input phase lock loop 27 to produce a reference signal
whose instantaneous frequency is given by 4f+c, where c is
the instantaneous color reference frequency in the incoming
color signal. In addition, the color burst portion of the
same line of information is coupled to phase comparator 240
to cause the frequency of voltage controlled oscillator 242
to approach the instantaneous color frequency c. This
reference signal c is coupled along with 3f reference signal
from input phase lock loop 27 to mixer 245, the output of
which comprises a signal whose instantaneous frequency is
3f+c. The two reference signal trains are then combined in
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modulator 246 in the manner (4f+c)-(3f+c) = f and subse-
quently passed through chroma filter 247 to produce a chroma
signal whose instantaneous frequency is equal to f and which
is now phase locked to the 3f input clock reference signals
generated by input phase lock loop 27. This phase corrected
chroma signal is recombined in summing network 248 with the
luminance portion of the now-processed video signal and
coupled to the input of input video amplifier 14.
Figure 15 illustrates a second specific embodiment
of input color processor 15 which uses different means to
achieve the same result. Elements of the Figure 15 em-
bodiment which are common to the Figure 14 embodiment are
designated with like reference numerals. Incoming color
video signals are contemporaneously coupled to the res-
pective inputs of chroma filter 230, sync separator 231 and
low pass filter 232. The output of chroma filter 230 is
coupled to a first input of burst gate 233 and also via a
gain controlled amplifier 251 to the chroma signal input of
a conventional color decoder 252. The output of sync gene-
rator 231 is coupled to the input of pulse generator 238.
The output of pulse generator 238 is coupled to the control
input of burst gate 233 to permit the passage therethrough
of the burst portion of each line of video information.
The output of burst gate 233 is coupled to a first
input of phase comparator 240, the output of which is
coupled via limiter amplifier 241 to the control voltage
input of voltage controlled oscillator 242. The output of
voltage controlled oscillator 242 is coupled via limiter
amplifier 243 to the remaining input of phase comparator
240. The c reference signal train present at the output of
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limiter amplifier 243 is coupled via a limiter amplifier 253
directly to the B-Y carrier input of color decoder 252 and
also through a conventional 90 phase shifter 254 and
limiter amplifier 255 to the R-Y carrier input of color
decoder 252. The demodulated B-Y and R-Y components of the
chroma portion are coupled to a pair of conventional color
encoder units 258, 259 via parallel branches comprising a
low pass filter 260, a buffer amplifier 261, a DC restore
amplifier 262; and a low pass filter 263, a buffer amplifier
264, and a DC restore amplifier 265, respectively.
The modulation carrier signals for encoders 258,
259 are obtained from the f clock signal train generated by
input phase lock loop 27. This signal is coupled to the
modulation input of encoder 258 via a buffer amplifier 267,
a delay compensation circuit 268, a buffer amplifier 269,
and a limiter amplifier 270. The modulation carrier for
encoder 259 is derived from the f clock signal train by a
conventional 90 phase shifter 271 and coupled via a limiter
amplifier 272 to the input of encoder 259. The respective
outputs of encoders 258, 259 are coupled via buffer ampli-
fiers 274, 275 to a summing junction 276, the output of
which is coupled via chroma filter 247 to summing network
248. The remaining input to summing network 248 is the
luminance portion of the corresponding line of video infor-
mation furnished by low pass filter 232 and delay unit 249.
The embodiment of Figure 15 functions in an
equivalent manner to the Figure 14 embodiment described
above to phase lock the color portion of processed color
video signals input thereto to the 3f input clock storage
signals generated by input phase lock loop 27. In opera-
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tion, the chroma portion of the incoming video signal is
stripped by chroma filter 230 and coupled via limiter
amplifier 251 to the input of color decoder 252. In addi-
tion, the color burst portion of the same line of infor-
mation is coupled to phase comparator 240 to cause thefrequency of voltage controlled oscillator 242 to approach
the instantaneous color frequency c. The variable frequency
output carrier modulator signal from voltage controlled
oscillator 242 is then used to decode the chroma signals
into the B-Y and R-Y quadrature components. After decoding,
the quadrature components are re-encoded with the f clock
signal train obtained from input phase lock loop 27, are
summed, filtered and combined with the corresponding lumin-
ance portion in summing network 248. The re-encoded signal
contains the same color information present in the original
chroma signals before demodulation but is now at a frequency
f which is phase locked to the input clock reference signal
train. The composite video signals are then coupled to the
video input terminal of input video amplifier 14.
Both the Figure 14 and Figure 15 embodiments of
input color processor 15 are used to operate on processed
color input video signals to phase lock the color components
of each incoming line of video information with the input
clock reference signal train f before time base corrections
are applied. To insert input co1or processor 15 into the
video path, switch 11 (Figure 1) is placed in the PROCESS
position. Input color processor unit 15 is intentionally
~ypassed when the input video signals are of the DIRECT
color type, since by definition the color components of
successive lines o~ a DIRECT color type video signal have a
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precisely defined phase relationship and thus can be used to
phase lock the voltage controlled oscillator 54 in input
phase lock loop 27 so that the 3f input clock reference
signal train is phase locked exactly to successively appear-
ing burst portions.
SYSTEM OPERATION
The system is capable of operation in severaldistinct modes, depending on the nature of the upstream
equipment furnishing the raw composite video input signals,
the chromatic nature of the input video signals, i.e.,
whether monochromatic or color, ~nd, if color, the type of
color, i.e., whether direct or processed. In addition, the
system has a special operational mode termed INTERLACE which
is employed to convert processed color signals to quasi-
direct color signals. The various operational modes aredescribed in detail below.
Signal Source Mode
The invention is capable of processing video
signals obtained from V-LOCK video signal sources, such as a
capstan servo recorder, and LINE LOCK video signal sources,
such as a non-capstan servo recorder. Control switch Y is
used to condition the system with respect to the type of
signal source from which the uncorrected video signals are
obtained. For processing signals obtained from generator
locked sources, such as a capstan servo recorder, switch Y
is placed in the V-LOCK position; for processing signals
obtained from non-generator locked sources, such as a non-
capstan servo recorder, switch Y is placed in the LINE LOCK
position. In V-LOCK mode, the upper loop of output phase
lock loop 33 generates clocking signals for sequence control
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unit 28, multiplexer 37 and digital-to-analog converter unit
38. Depending on the position of switch Z, sync generator
35 and subcarrier processor 36 are either driven by external
composite sync, composite blanking and color subcarrier fc
reference signals, or sync generator 35 is used as the
master timing generator to drive the associated generator
locked video signal source and to provide INT fsc reference
signals to subcarrier processor unit 36. In addition, the
direct video path in digital-to-analog converter unit 38 is
selected to furnish the DAC VIDEO signals to processor
amplifier 39 which serves to bypass the output color pro-
cessor unit 40. In the LINE LOCK mode, the lower loop in
output phase lock loop 33 is used to generate the 3fsc
clock signal train for units 28, 37 and 38 and the Nf'Sc
signals output phase lock loop 33 are coupled to the sync
generator 35 via switch Y to control the frequency of the
FIELD START reference signals generated thereby, which in
turn are coupled back to output phase lock loop 33 to phase
lock both output reference signal trains from this unit to
the frequency of the input video signals (PROCESSED V). INT
fsc reference signals are derived from either ~FSc oscillator
34 or the Nf'Sc signals from output phase lock loop 33
depending on the position of interlace switch X. In addi-
tion, the processed color video path in digital-to-analog
converter unit 38 is selected for operation so that the
chroma portion of the signals, after passing through the
memory units 30-32, multiplexer 37 and a portion of digital-
- to-analog converter unit 38 are coupled to color processor
unit 40, where they are decoded with f''sc signals from
output phase lock loop 33 to remove hue phase variations,
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re-encoded with fsc signals from subcarrier processoer 36
and coupled as processed chroma back to digital-to-analog
converter unit 38 where they are recombined with the lumi-
nance portion thereof.
Color Mode
If the uncorrected video signals input to the
system are color video signals, the system may be controlled
in accordance with the nature of the input color signals,
i.e., direct color or processed color. This control func-
tion is directed by control switch 11, which controls theoperation of input color processor 15 and input phase lock
loop 27. If the uncorrected color input video signals are
direct color, input color processor 15 is bypassed and both
the coarse and fine loops of the input phase lock loop 27
are enabled for operation.
Interlace Mode
This special mode of operation is employed in
combination with LINE LOCK and PROCESS modes. In LINE LOCK
mode, it will be remembered, the 3fsc signal train for units
28, 37 and 38 is phase locked to the vertical sync portions
of the incoming video signals, and the chroma portion of the
time base corrected video signals are demodulated with f''sc
reference signals from output phase lock loop 33. In the
special INTERLACE mode, switch X is thrown to the position
illustrated in Figure 1 so that the variable frequency NF'Sc
reference signals from output phase lock loop 33 are not
only used to control the generator of FIELD START signals by
sync generator 35 but also used to serve as a reference
standard for generating the INT fsc which in turn furnishes
the color encoding reference frequency standard fsc for
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lQ"7795
color processor unit 40 and output phase lock loop 33 which
generates the 3fsc clocking signals for units 28, 37 and 38
and the color decoding reference frequency standard f''sc
for output color processor unit 40. Thus, the INTERLACE
mode, processed color signals are first time base corrected
in accordance with the frequency deviations present in the
input video signals, are fetched and converted to analog
form at a sampling rate which follows the long term (PROCES-
SED V) variations in the input signals and are decoded and
re-encoded by carrier reference signals f''sc~ fsc also
derived from the long term (PROCESSED V) variations. The
resulting time base corrected video output signals are
signals which are properly phased in accordance with the
NTSC definition o~ direct color but which have color frequen-
cies which are not identical with NTSC defined color subcar-
rier. Such signals are hereinafter designated as quasi-
direct color signals.
The following examples illustrate the various
combined modes of operation of which the invention is
capable.
Mono-V-Lock Mode
In this mode of operation, monochromatic video
information signals from a capstan servo recorder are time
base corrected to broadcast quality monochromatic signals.
Input phase loc~ loop 27 operates on the coarse loop only.
The 3fsc clocking signals, the H' sequencing signals and the
composite sync and composite blanking signals are fully
phase locked to the associated video tape recorder either
internally with the sync generator 35 serving as the master
timing generator or externally by a studio generator.
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lQ~7795
Direct-Color-V-Lock Mode
_ .
In this mode of operation, direct color signals
from a capstan servo recorder are time base corrected and
furnished to the output as broadcast quality direct color
video signals. Input phase lock loop 27 operates on both the
coarse and fine loops, and the 3fsc clocking signals, the H'
sequencing signals and the composite sync, composite blank-
ing and burst flag signals are fully phase locked to the
recorder, either externally or internally. The video
signals input to digital-to-analog converter unit 38 are
coupled to processor amplifier 39 via the V-LOCK signal
path, bypassing the output color processsr 40.
Process-Color-V-Lock Mode
In this mode of operation, processed color signals
from a capstan servo recorder or the like are phase locked
to in the input clock reference signal train 3f, are time
base corrected and furnished to the output as broadcast
quality direct color video signals. Input phase lock loop
27 operates on the coarse loop only. The 3fsc clocking
signals, H' sequencing signals, and the composite sync,
composite blanking and burst flag signals are fully phase
locked to the recorder, either internally or externally.
The video signals input to digital-to-analog converter unit
38 are coupled to processor amplifier 39 via the V-LOCK
signal path, bypassing the output color processor 40.
Mono-Line-Lock Mode
In ~his mode of operation, monochromatic video
signals from a non-capstan servo recorder ar~ time base
corrected and furnished to the output terminal as mono-
chromatic video signals having substantially reduced time
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base errors. Input phase lock loop 27 operates on the
coarse loop only. The 3fsc clocking signals follow the long
term variations of the vertical sync portions of the input
video.
Process-Color-Line-Lock Mode
In this mode of operation, processed color input
video signals are phase locked to the input clock signal
train 3f, time base corrected and furnished to the output as
processed color video signals having substantially reduced
time base errors. The input phase lock loop 27 operates on
the coarse loop only. The 3fsc clocking signals and f''sc
color demodulation reference signals follow the long term
variations in the input video signals. The chroma portions
of the time base corrected video signals are demodulated by
color processor unit 40 and re-encoded with standard fsc
obtained from frequency standard oscillator 34.
Interlace Mode
In this mode of operation, processed color video
signals from a non-capstan servo recorder are phase locked
to the input clock signal train 3f, time base corrected and
converted to quasi-direct color video output signals in
which the color burst portions of each line are properly
phased but in which the absolute color frequency may deviate
beyond acceptable limits for broadcast purposes. Input
phase lock loop 27 operates on the coarse loop only. The
3fsc clocking signals, H' sequencing signals, composite
sync, composite blanking and burst flag signals and the
color subcarrier signals fsc and f''sc are all phase locked
to the long term variations in the input video signals.
The invention described above provides a video
lQ~7795
signal processor for removing time base errors with un-
paralleled flexibility. The exceedingly wide correction
range of +1.5 lines of video information enables relatively
low cost video tape recorders to be used as a video signal
source. In addition, broadcast quality monochromatic and
color video signals can be provided by the invention from
relatively low cost capstan servo video tape recorders.
When used with non-capstan servo video tape recorders, the
invention is capable of providing high quality time base
corrected monochromatic and color video signals for use in
closed circuit TV installations. Perhaps most importantly,
however, when operated in the INTERLACE mode with processed
color video from a non-capstan servo recorder, the system
generates quasi-direct color video signals which can be
simply converted to broadcast quality direct color video
signals by dubbing the output of the system up to a capstan
servo recorder or a quadra-plex color video tape recorder,
recording the signals, and reproducing them in the con-
ventional manner.
A wide variety of possible combinations of the
invention with conventional television equipment is possi-
ble. The following lists just a few of these possibilities.
Using sync generator 35 as a studio generator, the input of
the system of Figure 1 can be coupled to the output of a
capstan servo recorder and the output of the system of
Figure 1 can be coupled to a video mixer along with the
output of one or more television cameras locked to sync
generator 35 to enable wipes, fades and other editing
techniques among the video signals from the several cameras
and the program content of the video tape reproduced by the
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lQ~7795
recorder. The same results can be obtained by coupling the
Figure 1 system to a studio generator, placing control
switch Z in the EXT position. In interlace mode, a non-
capstan servo recorder can be coupled to the input of a
system and the system output can be coupled to a video mixeralong with the output of one or more studio cameras using
sync generator 35 as the master timing generator. The
output of the mixer can be coupled to the input of a quadra-
plex or capstan servo recorder operating in the record mode.
After recording, the capstan servo recorder can be operated
in the play back mode under control of a studio generator or
sync generator 35 to generate broadcast quality direct color
video signals. If desired, the output of the recorder may
be coupled through the Figure 1 system during play back for
further processing to improve the quality of the color video
signals. Other adaptations of the invention will occur to
those skilled in the art.
By employing the special input color processor 15
in the overall system, the lower range on the time base
correction capability has been found to be about four
nanoseconds for processed color input video signals. In
addition, the signal
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to noise ratio of composite video output signals when
operating in the LINE LOCK mode is greatly improved over the
video signal processor disclosed in the referenced patent by
eliminating the necessity for an independent fast phase lock
loop in the output color processor unit ao. As a consequence,
the utility of the video signal processor has been extended
to an even wider variety of applications.
While the above provides a full and complete dis-
closure of the preferred embodiment of the invention,
various modifications alternate constructions, and e~uiva-
lents may be employed without departing from the true spirit
and scope of the invention. Therefore, the above descrip-
tion and illustration should not be construed as limiting
the scope of 'he invention, which is defined by the appended
claims.
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.
