Note: Descriptions are shown in the official language in which they were submitted.
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This application is a divisional of copending Canadian patent appli-
cation serial number 271,615 filed February 11, 1977, in the name of The
Magnavox Company.
This invention relates to a remote control system of the type parti-
cularly but not exclusively suitable for controlling television receivers.
The great majority of prior art television receiver remote control
systems have utilized an ultrasonic link between the remote transmitter and
the remote receiver located at the television receiver. In early ultrasonic
systems, a discrete ultrasonic frequency was assigned to each function to be
controlled. Such systems, however, are useful for controlling only a small
number of functions. This is due to the limited bandwidth in the ultrasonic
frequency range, the difficulty of maintaining frequency stability, and the
difficulty in economically building a remote receiver that is sufficiently
selective to distinguish among more than a few ultrasonic frequencies. Many
of the same limitations apply to remote control systems utilizing an optical
link between the remote transmitter and receiver wherein a transmitted light
signal ~usually in the infrared range) is modulated by a discrete ultrasonic
frequency for each function to be controlled.
Other ultrasonic systems have utilized pairs of ultrasonic fre-
quencies to increase the number of functions that can be remotely controlled.Thus, for each function to be controlled, two frequencies are transmitted,
either simultaneously or serially for predetermined time periods. In this
manner, five ultrasonic frequencies utilized two at a time will produce ten
unique frequency pairs. Six frequencies will produce 15 unique pairs; seven
frequencies will produce 21 unique pairs, and so on. Because of the limi-
tations mentioned earlier, it becomes economically prohibitive to build a
system having more than five or six discrete ultrasonic frequencies.
There has developed a need to provide for a r,uch larger data capa-
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city between the remote transmitter and the television receiver. This is
because it has become desirable not only to remotely control a larger number
of receiver functions, but also to randomly select any desired channel for
viewing.
An obvious way to increase the data capacity of the system was to
use digital techniques. Thus, a single ultrasonic frequency could be pulsed
to transmit a serial data stream. However, attempts to build such a system
that was economical and reliable were met with many difficulties. Because of
the limited bandwidth in the ultrasonic frequency range, the bit rate was
necessarily low. Reflected signals caused interference with the direct sig-
nal. It was difficult to synchronize the receiver with the transmitter.
Digital techniques have also been applied to remote control systems
utilizing an optical link. Such systems overcome the problem of reflected
signals and the wider available bandwidth permitted adequate bit rates. How-
ever, the problem of reliably synchronizing the receiver with the transmitter
remained unsolved.
It is an object of the present invention to provide an improved ap-
paratus for converting serial to parallel digital codes.
According to the invention there is provided apparatus for receiving
serial digital coded signals and converting them to parallel digital coded
signals, wherein said received signals are of the form having a predetermined
number of equal time data periods, the first data period contains a sync
pulse having a duration equal to a data period, and at least one subsequent
data period contains a data pulse, the duration of each data pulse being less
than the duration of a data period, said apparatus comprising a digital clock
for producing first and second clock signals, said two clock signals being
substantially identical in waveform and frequency and phase displaced from
each other by 90 electrical degrees; a digital counter for sequentially pro-
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ducing a plurality of enabling signals in response to said first clock signal,each enabling signal having a duration equal to one full cycle of said first
clock signal; means for detecting a received Sync pulse and for enabling said
first and second clock signals and said counter upon the termination of said
received sync pulse; sequential gating means having a common data input and a
plurality of data outputs for sequentially gating the received signal to first
and subsequent outputs during second and subsequent data periods of the re-
ceived signal~ saidsequential gating means being under the control of said
enabling signals from said counter and said second clock signal.
The present invention and that of above-mentioned Canadian appli-
cation serial number 271,615 will now be described in greater detail.
Figure 1 is a logic block diagram of the apparatus as used in a
remote transmitter for controlling a television receiver.
Figure 2 is a graphical representation of several signal waveforms
appearing at selected locations in the transmitter of Figure 1.
Figure 3 is a logic block diagram of the apparatus of the present
invention as used on a remote receiver for controlling a television receiver.
Figure 4 is a graphical representation of several signal waveforms
appearing at selected locations in the receiver of Figure 3.
Figure 5, appearing on the same drawing sheet as Figure 3, is a
logic block diagram of a digital clock suitable for use in either the trans-
mitter of Figure 1 or the receiver of Figure 3.
Figure 6, appearing on the same drawing sheet as Figure 3, is a
logic block diagram of a pulse width discriminator used in the present in-
vention.
Referring now to Figure 1, there is shown a key-board 11 which may
be of the kind commonly used with hand calculators. Each key switch of the
key board has at least one pair of contacts. One contact of each pair is
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connected to one side of a dc source, indicated as +V. The other contact of
each pair is connected to one input line of a diode matrix 12.
Diode matrix 12 has a plurality of input lines 13 equal in number
at least to the number of key switches in key board 11. Diode matrix 12 has
a plurality of output lines 14 equal in number to at least the number of
binary digits (bits) required to uniquely identify each of the input lines.
The input lines 13 are connected to the output lines through a plurality of
diodes to provide a unique binary coded signal on the output lines for each
input line. Such constructions are well known in the art and need not be
further described herein.
Each of the output lines is connected to the other side of the dc
source, indicated by the common or ground symbol, through a resistor 15.
Hereafter a voltage at or near +V will be referred to as high and a voltage
at or near common or ground potential will be referred to as low.
In operation, all the output lines 14 are low when no key switch is
closed. ~pon closure of a key switch, at least one output line will go high.
This is because binary zero is not utilized. It should be noted at this
point that only fifteen input lines 13 and four output lines 14 are shown.
However this showing is merely illustrative for sake of simplicity and ease
of understanding, the use of more inputs and a sufficient number of outputs
to provide unique binary coding for each input exclusive of binary zero being
contemplated.
The output lines 14 provide the data inputs to an n-bit latch 21.
The strobe input to latch 21 is taken from the Q output of a monostable
multivibrator or "one shot" 22 connected to be triggered by a positive going
signal at its input. This device may be an integrated circuit type SCL4528,
which is readily available from a number of suppliers and is fully described
in their respective catalogs and manuals.
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The input to one shot 22 is taken from the output of an n-input OR
gate 23 which receives its inputs from the output lines 14 of diode matrix 12.
Thus, whenever a key switch of key board 11 is depressed, at least one of the
output lines 14 will go high and trigger one shot 22 through OR gate 23.
Investigation has shown that even when a key switch of key board 11
is operated as rapidly as possible, its contacts remain closed for a minimum
of several milliseconds, during which time the proper binary code for the
depressed key switch is presented at the data inputs of latch 21. The astable
time period of one shot 22 is selected to be only a few microseconds. There-
fore, latch 21 is assured of being strobed while valid signals are present atits data inputs.
A one shot 24 connected to be triggered by a negative going signal
also receives its input from OR gate 23. The Q output of one shot 24 is con-
nected to the set input ~S) of a flip flop 25. The astable time period of
one shot 24 is selected to be a few microseconds as required to set flip flop
25. Thus, upon release of a depressed key switch, one shot 24 will be trig-
gered to set flip flop 25.
The Q output of flip flop 25 is connected to the reset-enable (RE)
input of a digital biphase clock 31. Clock 31 produces two digital clock sig-
nals identified as CK and CK + 90. These two signals are substantially sym-
metrical square waves of the same frequency and phase displaced from one
another by 90 electrical degrees. Clock 31 will be described in more detail
subsequently, it being sufficient here to note that when its RE input is held
high, clock 31 is maintained in a reset and disabled condition wherein CK and
CK + 90 are held low. When the RE input goes low, clock 31 is enabled and
produces CK and CK + 90 signals as illustrated in Figure 2.
The CK signals provide the clock input to a Johnson or ring type
counter 32. Counter 32 has ten outputs numbered O through 9. In the reset
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state, output O is high and all other outputs are low. Counter 32 will be held
in the reset condition and disabled from counting so long as its reset-enable
(RE) input is high. When the reset-enable signal goes low, counter 32 is en-
abled to count clock pulses at its C input. Only one output of counter 32 is
high at a time. Thus, upon counting a first clock pulse, the O output goes low
and the 1 output goes high. On counting the next clock pulse, output 1 returns
low and output 2 goes high. This sequence continues and repeats until clock
pulses are stopped or the counter reset.
The outputs 0-6 of counter 32 are identified as TO-T6 in Figure 1 and
the waveforms of these outputs are illustrated graphically in Figure 2. Output
6 ~T6) is connected to the reset input (R) of flip flop 25. Thus, upon count-
ing a sixth clock pulse after being enabled, T6 goes high and resets flip flop
25, the Q output of which resets and disables clock 31 and counter 32. The
resulting signal waveforms are shown in Figure 2.
Four three-input AND gates 41, 42, 43, and 44, each receive one input
from T2, T3, T4, and T5, respectively, and a second input from CK + 90. The
third input of each AND gate 41-44 is taken from latch 21. In the 4-bit system
illustrated, the four outputs of latch 21 are identified as A, B, C, and D. As
shown, A is gated by T2 and CK + 90 through AND gate 41; B is gated by T3 and
CK + 90 through AND gate 42; C is gated by T4 and CK + 90 through AND gate 43;
and D is gated by T5 and CK + 90 through AND gate 44.
The outputs of AND gates 41-44 provide four inputs to a five-input OR
gate 46, the fifth input of which is provided by Tl. The output of OR gate 46
is identified as TS. Figure 2 shows the waveform of TS when the binary number
1111 is transmitted. It will be noted that the data periods are defined by
T2-T5, but the duration of the data pulses within the data periods is limited
by CK + 90.
The signal TS is amplified by an oscillator/amplifier 47 to drive a
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light emitting diode 48, which transmits the signal TS in the form of modu-
lated light pulses to the remote receiver.
Referring now to Figure 3, there is shown a light detector and amp-
lifier 51 for receiving and amplifying the transmitted light signals from the
remote transmitter. Signal processing circuits 52 demodulate the received
signal and wave shape it to produce a signal RS which is substantially iden--
tica. to the signal TS that is generated in the transmitter.
The signal RS provides the input to a pulse width detector 53.
Pulse width detector 53 provides an output signal upon the termination of a
pulse at its input if the pulse has a duration greater than a predetermined
duration. In the present invention, pulse width detector 53 is selected to
provide an output only for pulses having a duration somewhat greater than the
data pulses. Thus, only sync pulses will cause detector 53 to produce an
output signal. A preferred embodiment of detector 53 will be described sub-
sequently.
The Q output of detector 53, which is normally low and makes a mo-
mentary high excursion at the trailing edge of a pulse of sufficient duration,
is connected to the set input ~S) of a flip flop 55. The Q output of flip
flop 55 is connected to one input of a two-input AND gate 54, the other input
of which is provided by the signal RS. It will be seen that gate 54 blocks
signals from processing circuits 52 when the Q output of flip flop 55 is low
and passes signals from processing circuits 52 when the Q output of flip flop
55 is high.
The Q output of flip flop 55 is connected to the reset-enable (RE)
input of a digital biphase clock 56 that is substantially identical to clock
31 of the transmitter. When its RE input is high, clock 56 is held reset and
disabled and the CK and CK ~ 90 clock signals are held low. When its RE input
is low, clock 56 is enabled to produce clock signals CK and CK ~ 90.
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A counter 57, substantially identical to previously described coun-
ter 32, has its reset-enable (RE) input connected to the Q output of flip flop
55. The clock input to counter 57 is provided by the CK clock signal from
clock 56. Outputs 0-5 of counter 57 are identified as R0, Rl, R2, R3, R4, and
R5.
A plurality of three-input AND gates 61, 62, 63, and 64 each receive
one input from Rl, R2, R3, and R4, respectively; and a second input from the
output of AND gate 54. The third input of each AND gate 61-64 is provided by
the CK + 90 signal from clock 56. The outputs of AND gates 61-64 are con-
nected to the inputs of buffer storage 65, which may comprise a plurality of
flip flops, one for each input.
The operation of the receiver will be clearly understood with refe-
rence to Figure 4 which graphically shows the waveforms of several signals.
The output RS of signal processing circuits 52 is shown for the data word 1111.
The four data bits A, B, C, and D follow a valid sync pulse SYNC.
Upon termination of the sync pulse SYNC the Q output of detector 53,
indicated as 53Q goes momentarily high, and operates to set flip flop 55. The
Q output of flip flop 55, indicated as 55Q, goes low, enabling clock 56 and
counter 57. The CK and CK + 90 outputs of clock 56 are also shown.
When clock 56 and counter 57 are enabled, counter 57 begins to count
CK clock pulses causing R0 to go low and each of the other outputs Rl-R5 to go
high sequentially as shown in Figure 4. When R5 goes high, it resets flip
flop 55, causing 55Q to return high and reset clock 56 and counter 57. Thus,
R5 will not remain high for a full cycle of CK as do Rl-R4, but will return
low as soon as 55Q goes high. Simultaneously, R0 will return high and remain
there until another sync pulse is detected and the above described cycle is
repeated.
AND gates 61-64 are sequentially enabled by Rl-R4, but only during
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so much of each data period when CK + 90 is high. The time periods during
which gates 61-64 are enabled are identified respectively as Rl (CK + 90), R2
~CK + 90), R3 (CK + 90), and R4 (CK + 90).
If clock 56 is running at the same frequency as the transmitter
clock, the time periods during which each gate 61-64 is enabled will coincide
exactly with the time periods during which data pulses representing binary
ones are present to be gated. However, exact synchronism between the trans-
mitter and receiver clocks is not required for the system of the present in-
vention to function properly. To the contrary, the system of the present in-
vention will function reliably even when a considerable frequency difference
exists between the transmitter and receiver clocks.
This feature is illustrated by Figure 4, which shows a received sig-
nal waveform RS' from a transmitter having a clock running between 6 and 7
percent slower than the receiver clock. It will be seen that there is suf-
ficient overlap between each data pulse of the signal RS' and the times each
gate 61-64 is enabled to properly enter the correct number in buffer storage
65. rt should be noted that false data will not be entered in buffer 65
because there is no improper time overlap between the received data and the
periods during which each gate 61-64 is enabled.
The system of the present invention, utilizing four data bits, will
operate reliably with a frequency difference between the transmitter and re-
ceiver clocks that is as great as plus or minus 12 percent. As the bit size
is increased, less variation can be tolerated. However, even with an eight-
bit data wordJ the system will tolerate a plus or minus 6 percent frequency
variation, and this is well within the range of manufacturing tolerance for
the master oscillators used in the transmitter and receiver clocks.
Referring now to Figure 5, there is shown a block diagram represen-
tative of the digital clocks used in the present invention. A master oscil-
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lator 71 operates in the ultrasonic or low radio frequency range, say about
34KHz. Frequency dividar circuits 72, which may comprise a plurality of tog-
gle flip flops connected in series, divide the pulses from master oscillator
71 by an integral number, say 40. This may be achieved by a .10 circuit and
a .4 circuit, both of which are readily available from a number of integrated
circuit manufacturers.
A toggle flip flop 73 further divides the frequency by two, and al-
ternately triggers JK flip flops 74 and 75 from its Q and Q outputs. It will
be understood by persons skilled in the art that the outputs of flip flops 74
and 75 identified as CK and CK ~ 90, respectivelyJ will provide another 2
function, and will also be phase displaced from each other by one-quarter
cycle or 90 electrical degrees as shown in Figures 2 and 4. These signals
have a frequency of approximately 34KHz ~ 160, or about 212Hz.
Pulse width detector 53 may take the form shown in Figure 6. A
retriggerable monostable multivibrator 81, connected to trigger on positive
going transitions of the received signal RS has an astable time period
slightly shorter than the duration of sync pulses SYNC. The Q output of mono-
stable multivibrator 81 provides one input to an AND gate 82, the other input
of which is provided by the received signal RS.
Upon receipt of a positive going transition, indicating the begin-
ning of a received pulse (sync, data, noise, etc.), the Q output of monostable
multivibrator 81 will go low and remain there for the astable time period. If
the received pulse is of sufficient duration, indicating a valid sync signal,
the pulsc will still be present when Q returns high. This will cause the out-
put of AND gate 82 to go high and remain there until the received pulse ends.
A second monostable multivibrator 83 is connected to trigger on neg-
ative going transitions. Thus, monostable circuit 83 will not be triggered
when the output of AND gate 82 goes high, but will be triggered when it re-
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turns low, which occurs at the end of a valid sync pulse. The Q output ofmonostable circuit 83 is the output of pulse width detector 53, indicated as
53Q in Figure 4. The astable time period of monostable circuit 83 is selected
to be long enough to reliably trigger flip flop 55.
The master oscillator of the receiver clock is free running, and
therefore may be in either state at the instant an incoming sync pulse termi-
nates and the receiver clock counter chain is enabled. However, the resultant
CK and CK ~ 90 signals can never be off in time by more than one cycle of the
master oscillator, or one part in 160 of a data period, too small an amount
to be of significance.
Buffer storage 65 is provided with a reset terminal (R) for reset-
ting or erasing the data stored therein. Buffer 65 is reset prior to receipt
of each new data word. The Q output of pulse width detector 53 may be used
for this purpose. Also, it is desirable to perform decoding operations on the
received data. Such operations may be initiated by the R5 output of counter
57.
It should be understood that the foregoing has described and illus-
trated a presently preferred embodiment of the present invention, and that
many variations of the basic invention may suggest themselves to persons
skilled in the art. Therefore, the foregoing description and drawing should
be considered to be illustrative and not restrictive in character, reference
being made to the appended claims.
