Note: Descriptions are shown in the official language in which they were submitted.
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BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
This invention relates to improvements in heart pacers,
and more particularly to an improved heart pacer controlled by
a digital computer, and still more partieularly to an implant-
able heart pacer controlled by a microprocessor circuit in
conjunction with a memory.
2. DESCRIPTION OF THE PRIOR ART
Heart pacers have been recently proposed which employ
digital circuitry, for example, J K flip-flops, clock pulse
generators, shift registers, and the like. More recently,
heart pacers have been proposed which include digital control
eireuits for enabling a fully implanted heart pacer to be con-
trolled from a location external to the patient to vary, for
example, the operating parameters of the pacer.
None of the pacers advanced to date, however, include
digital computer means for controlling the operation of the
pacer.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to pro-
vide an improved heart pacer.
It is another object of the invention to provide a
heart pacer which is controlled by a digital computer which
can be fully implanted within the patient's body.
It is still another object of the invention to pro-
vide a heart pacer which includes a microprocessor and memory
circuit used in conjunction therewith to control a stimulation
pulse generator to pace the patient's heart.
These and other objects, features and advantages will
become apparent to those skilled in the art from the following
detailed description when read in conjunction with the accom-
panying drawings and appended claims.
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The invention, in its broad aspect, presents a fully
implantable heart pacer adapted to be connected by electrodes
to a patient's heart. The pacer includes a triggerable circuit
for generating an electrical heart stimulation pulse, and a
digital computer operable to trigger the circuit to pace the
patient's heart. In a more specific embodiment of the invention,
the digital computer comprises a microprocessor and a memory
connected thereto to trigger a stimulation pulse generator.
The microprocessor computes the period between stimulation
pulses and the width of the stimulation pulse produced by the
stimulation pulse generator.
In another aspect of the invention, a program having a
predetermined number of steps to be executed is loaded into a
memory connected to a microprocessor. The microprocessor pro-
duces an output after the execution of the predetermined num-
ber of steps. A microprocessor is controlled by a clock, the
frequency of which controls the speed at which the microprocessor
executes the instructions applied thereto. The time of execut-
ion of the instructions is thereby determined by the micro-
processor to determine the width of the stimulation pulse pro-
duced and the time between stimulation pulses produced by a
stimulation pulse generator.
BRIEF DESCRIPTION OF THE DRAWING
The invention as illustrated in the sole accompanying
drawing, wherein;
FIG. 1 is an electrical schematic diagram of the heart
pacer, in accordance with the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
AS shown in the sole accompanying drawing, the heart
pacer, in accordance with a preferred embodiment of the invent-
ion, includes a microprocessor circuit 10 connected to a read
only memory (ROM)ll. The microprocessor 10 in combination with
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the ROM 11 produces an output to trigger a stimulation pulse
generator circuit 12 to produce an output to electrodes (not
shown) upon output line 13.
In simplest terms, a microprocessor is a monolithic
(one-chip) processor, a processor being a device which fetches
and executes instructions. The microprocessor 10 described
hereinbelow is a COSMAC processor of the type RCA-CDP 1802,
although it will be apparent to those skilled in the art that
other microprocessors can be equally advantageously employed.
The microprocessor 10 includes eight memory address outputs
designated MAO-MA7 and eight data input/output lines designated
BUSO-BUS7.
The ROM 11 hereinbelow described is of the type RCA-CDP
1831, although, again, any ROM compatible with the particular
microprocessor employed can be used, as will be apparent to
those skilled in the art.
The RCA-CDP 1802 and CDP 1831 are particularly advant-
ageously employed in conjuction with use in a heart pacer be-
cause of the low current requirements of the CMOS devices their
circuits comprise.
The microprocessor 10 includes an internal digital
clock (not shown), the frequency of which is determined by a
crystal 20 connected between the clock and the XTAL input
terminals to the microprocessor 10. The crystal 20 may, for
example, provide a frequency of 2 MHz. A resistor 21 is
connected in parallel with the crystal 20.
The internal clock produces clock pulses at various
times, one train of which appears at the terminal TPA. The
TPA terminal of the microprocessor 10 is connected to the clock
terminal of the ROM 11.
A resistor 47 is connected in series with a capacitor
48, the series being interconnected between the negative terminal
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33 and ground (VDD). The junction between the resistor 47 and
capacitor 48 is connected to the CLEAR terminal to insure that
the microprocessor is initialized properly when first connected
to the batteries. Thus, the program will begin at memory loca-
tion zero. Initially the capacitor has no charge, so that the
CLEAR signal is low (asserted). Then it charges up to make
CLEAR high (not asserted) and the system begins to run.
In one aspect of the invention, the frequency of the
clock pulses is of importance since the time the microprocessor
utilizes in executing the instructions is directly dependent
on the clock frequency. AS Will become apparent below, the
time of execution of the various steps of the program loaded
into the ROM 11 controls the width and period of the stimulation
pulses generated by the pacer.
The output signal at the MRD terminal of the micropro-
cessor 10 is connected to the ROM 11 to enable a memory read
cycle whenever required by the microprocessor. The ROM 11, as
mentioned above, has its address terminals connected to the
memory address terminals of the microprocessor 10. Likewise,
the various data terminals are connected to the BUS terminals
of the microprocessor 10.
The various flag, wait, interrupt and clear terminals
are tied high. The output of the microprocessor is derived at
the Q output, which is connected to trigger or control the
stimulation pulse generator 12.
The stimulation pulse generator 12 includes two n-p-n
transistors 30 and 31. The transistor 30 has its emitter con-
nected to a negative potential at terminal 33 and its collector
connected via series resistor 34 to a ground terminal 35. The
collector of the transistor 30 is connected to the emitter of
the transistor 31. The transistor 31 has its base connected by
a resistor 39 to a negative terminal 33, and its emitter con-
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nected by a resistor 41 to the negative terminal 33. Thecollector of the transistor 31 is connected by a resistor 43
to the ground terminal 35. A capacitor 44 is connected bet-
ween the collector of the transistor 31 and the output terminal
13.
A zener diode 45 is connected between the output term-
inal 33 and the ground terminal 35 to protect the circuit
against defibrillation voltages which may appear at the term-
inal 13.
The stimulation pulse generator 12, as mentioned above,
is triggered by a pulse appearing on the Q output line of the
microprocessor 10 applied via resistor 46 to the base of the
transistor 30~ When, however, the transistor 30 is triggered
into conduction, the transistor 31 additionally conducts.
The voltage built up upon the capacitor 38 between pulses is
connected. in series with the voltage of the power supply,
thereby producing at the output terminal 13 a stimulation pulse
of voltage determined by the sum of the voltage on the capaci-
tor 38 and the supply voltage.
In order for the microprocessor 10 to control the
stimulation pulse generator 12, electrical instruction signals
are introduced into preselected address locations of the ROM 11.
Thus, electrical signals are introduced in accordance with the
following table.
ROM Address ROM Contents Symbolic Instructions
(hexadecimal) (hexadecimal)
00 7B Begin: SEQ
01 F8 19 LDI 25
03 A3 PLO R3
04 23 Delay 1: DEC R3
05 C4 NOP
06 83 GLO R3
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S~30
07 3A 04 BNZ Delay 1
09 7A REQ
OA F8 65 LDI 101
0C B3 PHI R3
OD 23 Delay 2: DEC R3
OE C4 NOP
OF 93 GHI R3
3 A OD BNZ Delay 2
12 30 00 BR Begin
14 on Not Applicable
The microprocessor 10 operates on and in response to
the particular electrical signals within the ROM, in accord-
ance with the predetermined instruction responses provided
by the microprocessor manufacturer, substantially as follows.
The first instruction at address 00 is 7s, which sets the Q
output of the microprocessor to 1 tor high state3. This
triggers the transistor 30 of the stimulation pulse generator
12 into conduction, thereby producing an output pulse, in
the manner above described. The transistor 30 will remain in
the conducting state so long as the output on the Q terminal
remains high.
The next instruction at address 01 loads the number at
the ROM address 02 into the D accumulator (not shown) of the
microprocessor 10. ~The number 19 in hexadecimal notation
corresponds to the decimal number 25.)
The instruction at the ROM address 03 then transfers
the number in the D accumulator into the low order byte of
scratch pad register R(3) (not shown). The instruction at
address 04 decrements the number in the low order byte of the
R(3) scratch pad register by 1. Then, the instruction at the
ROM address 06 ~etches the number then existent in the low
order byte of the scratch page register R(3), and inserts it
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into the D register. The instruction at the address 07 in the
ROM then dictates that if the number obtained from the R(3)
scratch pad register is not zero, the program will return to
address 04, which will decrement the R(3) contents by 1. The
process continues until a zero is found during the execution
of the instruction at ROM address 07. Then, in accordance
with the instruction at ROM address 09, the Q output is set
to zero.
The setting of the Q output to zero will cause the trans-
istor 30 to discontinue conduction, and remain in a nonconduct-
ing state until the Q output again becomes high. Thus, the
decrementing loop set forth by the instructions in the ROM ad-
dresses 01-07 essentially count the clock pulses produced by
the clock until a sufficient time corresponding to the width of
the pulse has been counted.
Then, the instruction contained in the ROM address OA
is executed. That instruction dictates that the number con-
tained in the ROM address OB be loaded into the D register~
The number in the ROM address OB is the hexadecimal number 65,
corresponding to the decimal number 101.
The operation dictated by the instruction at ROM address
0C moves the number in the D register to the high order byte of
the scratch pad register R(3) (not shown). The instruction at
the ROM address OD decrements the number in the scratch pad re-
gister R (3) by one~ The instruction in the ROM address OF then
brings the number in the upper byte of the scratch pad register
R (3) back to the D register. Instruction at ROM address 10
then determines whether the number fetched is zero, and, if not,
mo~es back to ROM address 0D to repeat the decrementing process
until the number in the upper byte of scratch pad register R(3)
becomes zero. At that time, the program pointer points to the
ROM address 12, which reinitiates the program moving back
to ROM address 00~ setting the Q output of the
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microprocessor 10 to a high state to again initiate conduction
of the transistor 30.
Thus, the second portion of the instructions in the
ROM addresses OA-12 repeats for a time corresponding to the
period between the stimulation pulses desired. (Since the
pulse width is initially counted in sequence with the time
between the pulses, the time that the program is executing the
second loop [instructions at ROM address OA-12] is not strictly
the period of the pulses, but, rather the time at which the Q
output is at a low state.) The period, strictly speaking, is
the time for execution of the entire program, including the
repetitive looping within instructions 01-07 and OA-12.
It should be noted that the scratch pad register R(3)
is two bytes (16 bits) long. The DEC R3 instruction's execut-
ion decrements the entire 16-bit quantity. In the first pro-
gram section (locations 01-08), it is unimportant what is in
the upper byte of R3. The lower byte is merely initialized
and continually decremented and tested until it reaches zero.
However, in the second program section (locations OA-13), the
upper byte of R(3) is initialized, the lower byte now being
zero~. The upper byte decrements by 1 for every 256 executions
of the DEC R3 instruction (i.e., eve~y time the lower byte
decrements from 00 to FF). This, along with the initialization
value of 101, provides the long 819 MSEC delay.
Thus, the stimulation pulse generator 12 produces out-
put pulses upon the terminal 13 in accordance with the instruc-
tions in the ROM 11 as read and executed by the microprocessor
10. It should be additionally pointed out that the instructions
in the ROM 11 addresses illustrated serve two purposes. First,
they provide instructions and data to the microprocessor 10, in
a fashion ordinarily employed in microprocessor operations.
Additionally, the execution of the various instructions, data
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fetches, and the like, in conjunction with the clock pulses,
provides the timing of the output produced at the Q terminal
of the microprocessor 10. That is, the time of execution of
the instructions in the ROM addresses 01-07 defines the width
of the stimulation pulse produced at the output terminal 13.
And, in like fashion, the time of execution of the instructions
in the ROM addresses 09-12 defines the time period between the
stimulation pulses. Consequently, the pulse timing of the
stimulation pulses is controlled not only by the particular
instructions in the ROM, but by the fact of the existence of
the instructions and their execution as well. The importance
of the clock frequency employed can therefore be appreciated.
With a clock frequency of 2 MHz the instruction time for the
RCA-CDP 1802 is 8 microseconds (using 16 clock cycles per
instruction). Therefore, the stimulation pulses generated
will be about 816 microseconds in width and be spaced about
819 milliseconds apart.
Although the invention has been described and illustrat-
ed with a certain degree of particularity, it is understood
that the present disclosure has been made only by way of ex-
ample, and that numerous changes in the details of construction
and the combination and arrangement of parts may be resorted
to without departing from the spirit and scope of the invention
as hereinafter claimed.
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