Note: Descriptions are shown in the official language in which they were submitted.
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1 The present invention is directed to an improved
charge coupled device (~n) and particularly to the input
circuit for such a device.
A charge coupled device, accordin~ to the prior
art, comprises a substrate and electrodes insulated
from the substrate. Multiple phase volta~es applied to
the electrodes form potential wells in the substrate for
the storage and propagate charge signals along the
length of the channel. The charge coupled device also
; 10 includes a source electrode in the substrate. F.lectrode
means insulated from the substrate and located between
the source electrode and the CCD channel are responsive
to an input signal, for controlling the introduction
of charge from the source electrode to the CCD channel.
According to the invention, the electrode means
; includes storage electrode means for for~ing an input
potential well in the substrate in response to an applied
voltage which input potential well is substantially
larger than the capacity of the potential wells in the
CCD channel. The input potential well has a signal voltage
versus number-of-charge-carriers-introduced transfer
function, which is relatively non-linear at lower input
signal levels and relatively linear at higher input
signal levels. In order to overcome the problem presented
by this nonlinear transfer function, there is proved ~ ;
means responsive to the input signal and to a control
voltage manifestation for introducing into the input
potential well a charge which includes a bias component
at a level which corresponds to the non-linear region of
said transfer characteristic and further includes a
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l signal component. Also provided is means for removin~
from said input potential well beneath the stora~e
electrode the signal component of the charge stored
therein and for propagating that signal component to
the CCD channel, while retaining in the input potential
well beneath the storage electrode the bias component
of the charge.
In the drawings:
FIGURE 1 is a graph of input signal voltage-versus-
charge carriers produced, in a conventionally onerated
buried channel CCD input stage;
FI~UR~ 2 is a plan view of a CC~ input circuit
embodying the present invention;
FIGURE 3 is a section taken along line 3-3 of
FIGURE 2;
PIGURE 4 is a drawing of substrate potential
profiles to help explain the operation of the circuit of
FIGURES 2 and 3;
FIGllRE ~ is a drawing of waveform ti~ing
employed in the operation of the circuit of FIGURES 2 and
3; and
FIGURES 6a and 6b are ~raphs to help explain the
operation of the circuits of PI~IlR~S 2 and 3.
U.S. Patent No. 3,986,198 issued October 12, 197fi
to Walter P. Kosonocky describes relatively noise-free
circuits for introducing a charge signal into a CCD
register. The technique employed has become known as the
"fill and spill" mode of operation. Charge signals is
, introduced from a source electrode to a first potential
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1 well, this being the fill portion of the cycle. Then,
the potential well is partially emptied, for example
by operating the source electrode as a drain. nuring the
emptying process, an input signal potential is
maintained between the electrode under which the potential
. well is formed and a second electrode between that
electrode and the source electrode. The char~e which
remains in the first potential well is a function
of the amplitude of this --~
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RCA 71,287
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I input signal and is relatively noise free.
It has been found that when the CCD is a buried
channel CCD, the operation described above, while relatively
noise free, results in relatively non-linear translation of
the input signal to charge (as compared to the signal
translation which occurs in a surface channel CCD). The
transfer characteristic of signal voltage versus number of
charge carriers produced for a typical buried N-channel CCD,
is shown in FIGURE 1. The flat region 11 at the top represents
the charge capacity of the input potential well and it may be
slightly greater than that of each transfer potential well
along the major part of the CCD channel. The capacity of
such a transfer potential well is represented by dashed line
13.
The curve includes a relatively non-linear region
at relatively low signal levels (between Vz volts and Vx) and
a relatively linear region at relatively high signal levels
(between Vx and Vy). A change in signal level ~VINl at a
relatively low input ~ignal level i8 translated non-linearly
to a charge signal in the input potential well; a change in
input signal ~VIN2 at a relatively high input signal level
is translated linearly to a charge signal in the input
potential well. The non-linear region results, for example,
from the characteristic of a buried channel device that the
capacitance of the buried channel varies more as a function
of charge level at lower value~ of charge than at higher
values of charge. There are also more complex effects which
influence the degree of non-linearity.
In certain applications as, for example, in CCD
delay lines employed to delay analog signals such as the
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I video signals of television, operation as discussed above is,
of course, highly disadvantageous. It is desirable that the
CCD delay line introduce as little distortion as possible to
the analog signal and to do this, the input circuit to the
CCD should operate in linear fashion.
It is also important that a CCD delay line as
described above not occupy excessive area on the semiconductor
substrate. The CCD is designed to have a channel width and
electrode areas such that the potential wells which are
formed in response to the multiple phase voltages can store
only as much charge as can be produced by the greatest amplitude
input signal expected (assuming some practical value such as
10-12 volts or so of multiple phase voltage). If the CCD
; electrode areas are ~ade larger, it means that each CCD delay
line is larger and this, in turn, means that fewer such CCD
delay lines can be obtained from a single wafer~n practice,
many delay lines are,fabricated at the same time on the same
uae~ and are then cleaved or separated in some other way from
one another). This is wasteful and adds to the expense of
20 each line. In addition, larger area delay linee exhibit -'
greater capacitance and this makes operating them at high
frequencie~ (high fre~uency multiple phase voltages) more
difficult and reauires greater power dissipation in the CCD
driver circuits.
FIGURÉS 2 and 3 illustrate a circuit embodying the
invention which solves the problems above. The CCD includes
a P-type silicon substrate 10 and a source electrode S at the
substrate surface. This source electrode may comprise an N-type
diffusion in the P-type substrate. The layer B comprises a
thin layer of N-type silicon at the substrat~ surface and
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1 forming a PN junction 12 with the substrate. Layer B, as is
well understood in the art, is less highly doped than the
source diffusion S. The CCD input electrodes comprise three
gate electrodes Gl, G2 and G3, in that order, followed by
multiple phase electrodes 14, 16, 18, 20 and so on. By way
of illustration, these electrodes may all be formed of
polysilicon and may be the overlapped, two-layer type. Of
course other materials and other forms of construction are
possible and within the scope of the present invention. The
CCD channel, which may be defined by channel stop diffusions
~not shown), is r~latively wide beneath the input electrodes
Gl, G2 and G3 and tapers down to a narrower width for the
major part of the CCD as illustrated by dashed lines. This
major part of the CCD (not shown) may include several hundred
CCD stages (over 500 in one practical design, with four
electrodes, per stage). In the embodiment illustrated, the
wider portion of the CCD channel may have a width double that
of the major portion of the CCD channel as indicated by the
widths 2w and w, respectively, in FIGURE 2.
The operation of the CCD is depicted in FIGURES 4
and 5. It iB assumed for purposes of illustration that at
time to~ no charge is present in the potential well 26 beneath
electrode G2 as indicated at a of FIGURE 4. At this time, ~1 ;
~ is low so that there is a potential barrier 20 beneath the
',~ 25 first ~1 electrode 14 and a shallow potential well 22 beneath
the electrode 16. The shallow well occurs because electrode
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16 is maintained at a direct voltage offset which is relatively
; positive compared to the voltage at electrode 14. This is
indicated schematically by the battery 15. V3 is at a
relatively low level at this time so there is a potential
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1 barrier 24 beneath electrode G3. V~ continuously is maintained
at a relatively high dc level so that a potential well 26
is present beneath storage electrode G2. This well may be
considered the "input" potential well. Vl also is a dc
level but it is less positive than V2. This voltage and the
signal ~oltage VIN are applied to electrode Gl. Accordingly,
there is continuous~y present beneath electrode Gl a potential
barrier whose height is a function of the dc level Vl plus
the oignal level VIN. The voltage V~ is relatively positive
at time to so that diffusion ~ acts as a drain for charge
carriers.
At time tl, the voltage Vs i3 relatively negative
; so that the diffusion S operates as a source of charge
carriers. These charge carriers ~electrons) now fill the
potential well 26 to the level 30.
At time t2, the voltage Vs is at its more positive
value, causing the diffusion S to operate as a drain. Now
some of the charge pre~ent in well 26 spill8 back over the
barrier 28 and into region ~. The charge remaining in
potential well 26 includes one component proportional to
- signal and another proportional to the difference in dc
levels between Vl and V2. In the drawing, the charge in well
26 i~ cros8-hatched in two different ways. One part 32 of
this charge will continuously remain in this well and it is
legended "bias." The remainder 34 of the charge, legended
"signal" will be "skimmed" from the well and propagated down
the CCD register as will be explained shortly.
At time t3, V3 is relatively positive so that the
height of barrier 24 is substantially lower than it was at
time t2. The voltage V2 applied to the storage electrode G2
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1 remains the same, as already mentioned. At time t3 also, the
PHASE 1 voltage ~1 is high so that potential wells 36 and 38
are present beneath, the ~l electrodes 14 and 16, respectively.
As electrode 16 is biased more positively than electrode 14,
the well 38 beneath electrode 16 is deeper than the well
36 beneath electrod,e 14.' (While for purposes of the present
discussion a means 15 providing a voltage offset between two
electrodes is shown for producing an asymmetrical potential
well, alternative structures are possible. One is to employ
a single electrode in place of the two such as 14, 16 and
to employ a suitable ion implant under one of them.) The
~1 voltage is of substa~tially greater amplitude than the V3
voltage at time t3 so that well potential 20 is higher than
(appears as a potential well relative to) well potential 24.
In responoe to these co~ditions, a portion of the charge
~, in potential well 26 is skimmed from this well and propagated
'~ to well 38. The remainder of the charge, the bias charge 32,
', continues to remain in potential well 26. The portion 34
of the charge formerly in well 26 and now in well 38
subs'equently is propagated down the CCD register by the two
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";,, phase voltages ~ 2 i~ conventional fashion.
;;',l The significance of the operation in the way
',l described may be better appreciated by referring to FIGURE
~ 6a. This graph is drawn to smaller scale than FIGURE 1
,'j 25 tassuming dashed line 13 represents the same charge level
, in both figures, note that this dashed line is roughly twice
'~ as far from the zero charge level than the same line in
FIGUR~ 6a) but the same reference numerals are employed to
describe similar parts of the graph. The potential well 26
30 (FIG . 4) continuously
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1 retains a bias charge (32 of FIGURE 4) which is represented
by the dashed line 15 of FIGURE 6. Thi~ dashed line defines
the start of the relatively linear region of the transfer
curve. Any charge added to this potential well in response
to an input signal VIN results in substantially linear
translation of this input signal to charge (34 of FIGURE 4)
because the opera~ion is in the linear region of the
characteristic. Moreover, the structure is such that full
dynamic range is obtained. In other word~, because the input
potential well (the well beneath electrode G2) is in a region
where the channel is wide, its capacity is relatively large--
approximately double that of the CCD transfer wells in the
major part of the'CCD (the input well beneath electrode G2
has approximately double the capacity of a well beneath
an electrode s,uch as 42 of FIGURES 2 and 3). This means that
, even though the potential well 26 beneath storage electrode
', G2 is available to accept signal charge up to only a fraction
of its capacity (assume that when the input signal is at its
maximum value, it occupies only one half the well, the bias
charge occupying the remainder of the well), the charge
8ignal skimmed from this potential well 26 still can fill the
well beneath electrode 42 to substantially its entire
capacity, at maximum input signal level, Thus, the CCD
~ described operates linearly over substantially the full
'~ 25 capacity of the transfer potential wells in the body of the
CCD and therefore has wider useful dynamic range.
The tranRfer function of a typical transfer potential
well such as one beneath electrode 42 of FIGS. 2 and 3 as
~' related to the input signal VIN applied to electrode G, is
illustrated -in FIGURE 6b. The full transfer well capacity
is illustrated at 13. Note that the operation is quite linear
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1 over almost the entire characteristic. (It is found, in
practice, that at extremely low input signal VIN levels, some
minor non-linearity is introduced as shown at 17, but the
reason is not yet fully understood.)
The substantially linear operation described above
is achieved without requiring ex~essive substrate area. In
one practical design, the major part of the CCD comprises over
500 stages (over 2,000 electrodes) and the channel width,
electrode areas and substrate areas of all except the first
of these stages remain unchanged. The electrodes 14, 16, 18,
20 of this first stage are increased in area, one additional
gate eleatrode G3 is employed an~ the source electrode and
first two gate electrodes are increased in area. The total
! . increase in size required of the CCD is not significant--only
i 15 a fraction of a percent.
, While for purposes of illustration two phase operation
~l ~ is assumed, it is of course to be appreciated that the
;~ invention is equally applicable to three, four or higher phase
operation. It is also to be understood that while the CCD
illustrated employs a P-type sub8trate, it is equally applicable
; to N-type substrate devices employing P-type surface layers
and a P-type source region. Of course, appropriate changes
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in operating voltages are re~uired. Further, while typical
~- waveforms are illustrated, modifications are possible. For
example, the voltage V3 is shown to have the same shape as
the wave ~1 ~owever, proper operation can still be obtained
with V3 of different shape than Vl. V3 should be low at the
time Vs is low, however, V3 can go high before ~1 goes hig~.
~hile not illustrated, the system disclosed can
employ the technique illustrated in either of two copcnding-
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l United States patents identified below for insuring that the
source electrode operates at proper potentials during the
fill and spill operation. These are United States Patent
No. 4,191,895 granted to Peter A. Levine and Donald J. Sauer
for "Low Noise CCD Input Circuit" and United States Patent
No. 4,191,896 granted to Donald J. Sauer and Peter A. Levine
for "Low Noise CCD Input Circuit." Both of these patents
are assigned to the same assignee as the present application.
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