Note: Descriptions are shown in the official language in which they were submitted.
~ACKGROUND OF THE INVENTION
.
Field of the Invention
This invention relates to semiconductor integrated
circuits and more particularly to the layout of integrated
circuits on a semiconductor chip.
. .
~ Description of the Prior Art
,
There are two principal design techniques used in
the semiconductor industry: masterslice or custom design.
The masterslice design involves forming the transistors,
diodes, resistors, etc. of a particular circuit family into
a plurality of repetltive cell6 within the semiconductor
chip. Each of the cells contains a sufficient number of
;
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1 transistor, resistors, etc. to form a selected type
2 of circuit and the cells are arranged in arrays,
3 withln the chip. The circuits within the chip are
4 then "personalized" to form a particular logic function
or functions by selectively wiring the circuits with
6 a first level of metallization on the surface of the
7 chip. This type of design is most suitable for a design
8 automation system in which the wiring is accomplished
9 more or less automatically. The turn-around time or
the design and release to manufacturing of masterslice
11 chips is substantially less than that required for chips
12 which are custom designed.
13 In custom design techniques, the cells are laid
14 out to perform a specific function, usually in a specific
system. Wiring is less of a problem because it is fully
16 considered when the circuits are laid out within the
17 chip. Custom design chips are mostly one-of-a-kind
18 and manufactured in large q-~antities. Changes in logic
19 functions are extremely difficult and rarely undertaken.
With either of these designs, a relatively large
21 proportion of the chip area must be provided for the
22 wiring of the circuits. The utilization of this wiring
23 for its intended purpose is not very efficient. As a
24 result, the circuit densities available on large scale
integrated circuit chips has been limited by the area
26 which must be provided for the wiring - an area which
27 might he otherwise used for the devices within the -
28 semiconductor.
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1 The wiring on the surface of the semiconductor includes
2 connections between devices, power buses and signal dis-
3 tribution buses. The wiring w~ich is used to interconnect
4 different functional circuits, termed Macros, within the
semiconductor and to interconnect the circuits between
6 chips are commonly termed global wiring. The area of the
7 chip which is occupied by this global wiring varies, depending
8 on the type of chip, such as logic or memory, the rules
9 which must be followed during the fabrication process and
t~e number of metallization levels available on the surface
11 of the semiconductor for performing the wiring.
12 Very little information exists on the efficiency of
13 this wiring. We have found that with two levels of metal-
14 lization available to perform global wiring, roughly 30~
of the chip area is utilized for the active circuits within
16 the substrate and the remaining 70% is reserved for the
17 global wiring. Even with sophisticated design automation
18 systems for performing the wiring only 60% of the area
19 which is reserved for global wiring is àctually utilized.
Thus, around 40% of the chip area is unused.
21 The problem lies in the design of the circuit cells
22 used to populate the chip. Typically, each cell comprises
23 both an active area as well as space for several wiring
24 channels to handle both the intra-cell and intra-Macro
wiring as well as the global wiring. The cells are
26 disposed in closely-spaced columnar arrays to maximize
27 the number per chip. This design, however, is too rigid.
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1 In particular, the density of well-designed wiring
2 patterns tends to vary by location on the chip; more
3 wires are usually needed near ~he center than at the
4 periphery, for example. However, when this number
exceeds the wiring channels available within a cell,
6 the cell cannot be used. This has resulted in the
7 aforementioned inefficiency of cell and wiring space
8 utilization.
9 One semiconductor integrated circuit layout for
i~mproving the efficiency of the wiring utilization is
11 illustrated in U. S. Patent 4,032,962 issued in the names
12 of Balyoz et al and assigned to the same assignee as the
13 present application. In that patent the semiconductor
14 circuits are provided in columnar arrays within the
substrate, with each circuit including an elongated
16 impurity region and a set of other impurity regions
17 disposed contiguous to it to form diode junctions. The
18 elongated region is capable of containing a predetermined
19 maximum number of the other regions. A second device
is located adjacent the narrow side of the first device.
21 A first set of first level conductors, extending over
22 the elongated region orthogonally with respect to the
23 elongated direction, are interconnected to selected ones
24 of said other impurity regions. Another conductor on
a second level of metallization atop the substrate is
26 connected to an impurity region of the second device
27 and extends substantially parallel to the elongated
28 direction. In this way numerous conductors, whether
FI9-77-002 -4-
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1 used or unused by a particular circuit nonetheless are
2 allowed to cross over the active area within the substrate
3 utilized by the semiconductor cells. This type of layout
4 has been effective in increasing the circuit density
within the chip. However, it is not directed to the
6 problem of optimizing the utilization of the semiconductor
7 surface area required for the wiring alone.
8 Summary of the Invention
9 It is therefore the primary object of our invention
to improve the utilization of the semiconductor chip area.
11 It is another object of our invention to reduce the
12 amount of area on the semiconductor chip which must be
13 reserved for global wiring.
14 These and other objects of our invention are achieved
by separating the areas of the semiconductor which are
16 reserved for global wiring channels from the chip areas
17 which are reserved for the active circuits and their
18 wiring. Each of these areas ls subdivided into smaller
19 portions, termed active cells and wiring cells. The former
are utilized for the active circuits and the latter are
21 utilized for primarily global wiring channels. These
22 cells are designed with dimensions which have predetermined
23 relationships to each other in a prefixed manner prior
24 to fabrication of the physical wiring on the chip.
In one aspect of our layout process, the semiconductor
26 wiring designer initially lays out groups of circuits
27 providing particular functions. The designer, prior to
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1 the fabrication process, is allowed to use portions
2 of the regions within one or more Macros for wiring
3 only. He may form the Macro with sufficient numbers
4 of wiring cells so that the wiring channels pass
completely through it, thereby minimizing the distance
6 which the wiring needs to travel between Macros. In the
7 prior art, the wiring would have to travel a circuitous
8 route completely around a Macro.
9 In general, the layout comprises a plurality of
spaced-apart circuits or cells and first and second sets
11 of substantially parallel, elongated conductors disposed
12 atop;a first insulating layer. The first set of conductors
13 is disposed directly above the active circuits; and the
14 second set is disposed in areas between the circuits
reserved for wiring. Selected terminations of the first
16 set of conductors are connected to selected regions of
17 the active circuits through apertu~es made in the first
18 insulator. In the preferred embodiment, a third set of
19 conductors extending orthogonally with respect to the
first and ~econd sets is disposed atop a second insulating
21 layer.
More particularly, there is provided:
~n the method for fabricating a semiconductor
substrate integrated circuit layout including:
forming a plurality cf spaced-apart circuit
cells in columnar arrays within said substrate;
forming a first insulating layer above said
substrate, said layer having apertures therein to expose
selected active regions of said selected cells;
the improvement comprising:
depositing first and second sets of elongated
conductors in substantially parallel relationship atop
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said first insulating layer in said columnar direction;
said first set being disposed directly atop said
exposed cells to make selected contact with selected ones
of said exposed active regions through said apertures
in said first insulating layer;
said second set being disposed in areas between
said exposed cells;
forming a second insulating layer above said
first and second sets of conductors, said second insulating
layer having apertures therein to expose selected ones of
said first and second sets; and
depositing a third set of substantially parallel,
elongated conductors atop said second insulating layer,
orthogonally with respect to said columnar direction, to
make selected contact with said exposed ones of said first
and second sets through said apertures in said second
insulating layer.
There is also provided:
In a semiconductor substrate integrated circuit
layout including:
a plurality of spaced-apart circuit cells in
columnar arrays within said substrate;
a first insulating layer overlying said substrate,
said layer having apertures therein to expose selected
active regions of selected cells;
the improvement comprising:
first and second sets of elongated conductors
i~ substantially parallel relationship atop said first
insulating layer in said columnar direction;
said first set being disposed directly atop
said exposed cells;
means for making selected contacts with selected
ones of said exposed active regions through said apertures;
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said ~econd set being disposed in areas between
said exposed cells;
a second insulating layer above said first and
second sets of conductors, said second insulating layer
having apertures therein to expose selected ones of said
first and second sets;
a third set of substantially parallel, elongated
conductors atop said second insulating layer and extending
in a direction which is substantially orthogonal with
respect to the direction of said first and second sets
of conductors; and
means for making selected contacts with said
exposed ones of said first and second sets through said
apertures in said second insulating layer.
Brief Description of the Drawing
Figure 1 illustrates a prior art diode transistor
logic tDTL) type circuit which performs the NAND logic
function.
Figures 2 and 2A are plan and cross-sectional views,
respectlvely, of a set of cells in semiconductor form
of the circuit illustrated in Figure 1.
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1 Figure 3 illustrates a partial layout on a semi-
2 conductor chip of a plurality of cells shown in Figures
3 2 and 2A.
4 Figure 4 i8 a top view of a portion of a complex
integrated circuit array, whish performs a Macro function,
6 and with the first and second levels of metallization
7 applied thereto.
8 Figure 5 is a schematic representation of Figure 4
9 showing the active and wiring cells.
Figure 6 is a top view of a portion of a complex
11 integrated circuit array, which performs another Macro
12 function, and with the first and second levels of metal-
13 lization applied thereto.
14 Figure 7 is a schematic representation of Figure 6
showing the active and wiring cells.
16 Figure 8 is a schematic representation of a Macro
17 performing an ALU function showing the active and wiring
18 cells used to form the Macro.
19 Figures 9 and 10 are schematic representations of an
entire semiconductor chip wherein the wiring cells are
21 greater in number at the center of the chip than at the
22 periphery.
23 Description of the Preferred Embodiments
24 Turning now to the drawings, the prior art DTL circuit
in Figure 1 performs a NAND function. This circuit forms
26 no part of our invention per se and is well known to those
27 of skill in the semiconductor design art. It will also be
FI9-77-002 -7-
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1 understood that our invention is no way limited to
2 this particular circuit or layout in a chip. In fact,
3 our invention is applicable to layouts of various
4 circuits such as TTL, standard DTL, emitter-coupled
logic, etc.
6 The circuit per se and its variations are described
7 in the paper by Peltier entitled "A New Approach to Bipolar
8 LSI: C3L", 1975 IEEE International Solid-State Clrcuits
9 Conference, Digest of Technical Papers, pages 168-169.
The circuit comprises a single transistor Tl, a pair of
11 biasing resistors, denoted RB and RC, and connected to
12 the base and collector of transistor Tl, respectively.
13 The gate has six connectable outputs, preferably in the
14 form of Schottky barrier diodes, denoted Dl, D2, D3, D4,
D5 and D6 as well as an ohmic contact to the collector
16 denoted C.
17 Logic operation of the circuit is by steering the
18 current from resistor RB, which alternatively may be a
19 transistor. If all of the input signals to transistor
Tl are at a down level, Tl is non-conductive, and the
21 output signals at the Schottky barrier diodes is at an
22 up level. Conversely, if one of the input signals at
23 Tl is at an up level, Tl is conductive from +V to ground
24 and the output Schottky barrier diodes are on.
Figures 2 and 2A are plan and cross-sectional views,
26 respectively, of four cells, denoted All, A12, A21 and
27 A22. Each cell is substantially the same and a description
28 of one will suffice to describe the others.
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1 Each cell is a DTL-type circuit, as shown in
2 Figure 1, in semiconductor form which comprises a
3 plurality of regions of different conductivity types
4 extending into the chip to provide transistors, diodes
and resistors. These regions are interconnected at
6 a first metallization level atop a first insulating
7 layer 31 on the semiconductor chip to form the basic
8 DTL-type circuit. Some of the surface wiring has been
9 omitted for ease and clarity of illustration. For
example, the connections between resistors RB and RC
11 to the base and collector, respectively, are not
12 illustrated in Figure 2 and will not be illustrated
13 ~n the remaining figures of the drawing. The symbol ~
14 indicates regions where second level wiring is permitted
to cross over first level wiring atop a second insulating
16 layer 34. This will be explained in greater detail in
17 later sections of this specification. It is noted at
18 this point that the cell layout configuration in Figure
19 2, 2A and 3 are not our invention. However, they do show
the best mode of operation of our invention.
21 Transistor Tl comprises an elongated subcollector
22 region 10 formed in substrate 8, base region 11 and
23 emitter region 12 formed in epitaxial layer 26. Schottky
24 barrier diodes Dl, D2..., D6 are formed symmetrically on
each side of transistor Tl in epitaxial layer 26. A
26 collector contact 14 completes transistor Tl. Isolation
27 between circuits is provided by P+ region 14a and recessed
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1 oxide region 15, as is known in the art. Isolation
2 region 18 isolates reach-through region 14 from base
3 11 and emitter 12. As illustrated in Flgure 2A, only
4 those diodes which are actually connected in the circuit
have metallization 32 which is necessary to actually
6 form the diodes. Thus, the number of impurity regions
7 actually interconnected to conductive lines 32 is less
8 than the maximum number of diodes which could be so
9 connected. This cell structure, which is not our invention,
is similar to that shown in the aforementioned U. S.
11 Patent 4,032,962 in the names of Balyoz et al. Conductors,
12 denoted ~V and GND, comprise supply reference potentials
13 to each circuit and are disposed orthogonally with respect
14 to the elongated direction of the cell atop insulating
layer 31. Resistors RB and RC are formed in elongated
16 fashion adjacent the elongated side of each cell. The
17 conductors for interconnecting the cells are fabricated
18 on first and second levels of metallization into functional
19 circuits, termed Macros, and the global wiring which
interconnects different Macros. The conductors are
21 not shown in Figure 2 for clarity and ease of illustra~ion.
22 The second level conductors are insulated from the first
23 level conductors by second insulating layer 34. The
24 crossovers of the first and second level conductors are
denoted in Figure 2 by the numeral 36. Thus, in the
26 preferred embodiment, each cell also contains spaces
27 for second level elongated conductive channels which
28 extend in parallel with the length of the cell and the
29 resistors.
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1 As previously discussed, contact is made to regions
2 within the substrate for the Schottky barrier diodes by
3 means of first level conductiv~ channels which run
4 orthogonally with respect to the second level conductors
and the elongated direction of the cells.
6 Figure 3 shows a partial layout on a semiconductor
7 chip of a plurality of cells illustrated in Figures 2
8 and 2A. As shown, the cells are in columnar arrays and
9 repeated over the entire chip, with the exception of
peripheral areas required for external cells (not shown)
11 which typically include drivers, receivers and power
12 buses. A circuit cell unit is outlined in Figure 3.
13 Each of the cells is repeated hundreds of times in columnar
14 arrays on the chip. At the present time, more than 1900
such cells are typically fabricated on a single chip which
16 is around 150 mils square. Each cell is typically 4-5
17 mils in length and 1-2 mils in width. In Figure 3 the
18 cells are not wired and hence are not yet capable of
19 functioning as active circuits.
For wiring purposes each said circuit cell may be
21 considered as a whole or as two cells which are divided
22 into an active and a wiring cell. The utilization of
23 this concept will be described in more detail in succeeding
24 sections of this specification.
As previously noted, resistor RB is connected ohmically
26 to both the base of its associated transistor as well as
27 the source of potential +V. In the same fashion, resistor
28 RC is ohmically connected to both its associated collector
FI9-77-002 -11-
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1 as well as +V. Similarly, the emitter of each transistor
2 is connected to GND potential.
3 Figure 4 illustrates a p~.rtion of a semiconductor
4 chi~ which is wired in accordance with our invention.
The layout of 5 columns, Cl C5, and 11 rows, Rl-Rll
6 illustrates a portion of a semiconductor chip which
7 performs the logic Macro function of an input bus
8 selector, similar to a decoder. In operation, this
9 Macro receives signals from the chip receiver and.decodes
the signals and transmits them to various other Macros
11 within the chip.
12 Integrated circuit layouts of circuits which perform
13 Macro functions are known in the prior art. See, e.g.,
14 U. S. Patent 4,006,492 in the names of Eichelberger et al
for layouts of various Macros. See also U. S. Patent
16 3,558,992 in the names of Heuner et al.
17 Returning now to Figure 4, the dashed lines, which
18 are orthogonal with respect to the elongated direction
19 of the cells and parallel to the columnar array direction,
are conductors which are formed on the first insulating
21 layer 31 atop the active regions of the chip. The solid
22 parallel lines, which extend generally along the elongated
23 direction of the cells, and orthogonally with respect to
24 the first level conductors, are conductors which are
formed on the second insulating layer 34 disposed over
26 the first level conductors. Contacts from first level
27 conductors to selected active semiconductor regions
28 within the cells through apertures in the first insulating
29 layer are shown as filled-in rectangles~-, as for example,
at region 100.
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1 The "active" regions in these examples are the base
2 and collector of the transistor and the diodes in each
3 of the cells. Clearly, where ells performing other
4 circuit functions such as TTL, emitter-coupled logic,
etc., are used, the active r~gions may be other types
6 of device impurity regions. Because the emitters of
7 the transistors and both of the resistors in our preferred
8 circuit cell are wired for each active cell, these
9 contacts are not illustrated for the sake of clarity.
. Contacts between the second level of metallization
11 through the second insulating layer by means of via holes
12 to the first level are illustrated as circles, O, as for
13 example, at region 101 in Figure 4.
14 Contacts are not made directly from the second level
conductors to said active regions due to processing
16 considerations. Where such a connection is made, the
17 second level conductor first is connected through a via
18 hole, 0, in the second insulating layer to a first level
19 conductor. This first level conductor then contacts
the active region through an aperture for the contact,~
21 , in the first insulating layer. This is shown by
22 way of example at region 102.
23 At locations where the second level of metallization
24 is connected to a first level conductor which is in
turn connected to an active region, and the-second level
26 conductor crosses over that contact, the conductor is
27 shown by means of an oblique line, as at region 103.
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1 This i8 done for clarity. In practice, the second level
2 conductor lies directly atop the first level conductor
3 but is separated therefrom by the second level insulator.
4 At other locations where a second level conductor
crosses over a first level contact, ~ , the second level
6 ~nsulator separates the two, as at region 104.
7 In the metallization process, the first insulation
8 layer 31 generally comprises a composite layer of silicon
9 dioxide and a layer of silicon nitride. As will be
understood by those of skill in the art, other dielectric
11 layers could be substituted for the first insulating
12 layer with good results. The first level of metallization
13 for forming both the ohmic contacts to the transistor
14 impurity regions as well as the non-ohmic contacts to
the Schottky barrier diodes comprises a first layer of
16 chrome of around 0.1 micron thickness, a layer of platinum
17 deposited thereon, followed by aluminum or alloys of
18 aluminum-copper and silicon. Other types of metallization
19 may also be used. Preferably, for Schottky barrier diodes
having a barrier height of around 0.5 electron volts,
21 the Schottky barrier diode contact comprises a layer
22 of tantalum and a layer of chrome, atop which is said
23 aluminum metallurgy.
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1 The aluminum comprises the first level conductive lines,
2 which are formed in accordanc:e with conventional masking
3 and etching techniques.
4 After the first layer of metallization has been
formed, a layer of insulating material 34 such as quartz
6 is deposited to provide the insulation between the second
7 level of metallization to be formed and the first level
8 of metallization. Apertures, O, commonly termed via
9 holes, are formed in glass layer 34 where connections
are to be made from the second level of metallization
11 to the first level of metallization.
12 The noteworthy aspect of the Macro in Figure 4 is
13 that the entire last row, Rll, is devoted solely to the
14 second level wiring, which provides global wiring between
the Macro illustrated and other Macros not shown. No
16 active regions of any cell within the substrate in row
17 Rll, column C1-C5 have been contacted by any first or
18 second level wires along that row. On the other hand,
19 all of the other cells within that Macro, except in
location R10/C3, are utilized as active circuits; i.e.,
21 connections are made from the first level wiring to at
22 least one active region of each of the cells not utilized
23 for wiring only.
24 Each of the second level lines in row Rll is connected
to the collector of an associated transistor in the cells
26 in row R10 by means of a first level conductive line as,
27 for example, at region 105. Thus, the first and second
28 level wires in Rll form part of the 5 x 11 cell Macro,
FI9-77-002 -15-
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1 but they are disposed in areas not including exposed,
2 active cells. This represents an efficient wiring
3 system, because otherwise the ~iring would be interrupted
4 by other wiring connected to active regions, thereby
requiring a circuitous routing of the wiring.
6 It i8 convenient to consider unexposed areas having
7 wiring passing over them to be wiring (W) cells, as
8 compared to active (A) cells, in which the active regions
9 are contacted by the wiring through apertures in first
fnsulating layer 31.
11 A simplified illustration of this layout is shown
12 in Figure 5, wherein each cell area is designated as
13 either 'A' designating an active cell, or 'W', designating
14 a wiring cell.
Figure 6 illustrates a more complex Macro which requires
16 an area of 6 x 15 circuit cells for a total of 90 such
17 cells. This Macro performs a four-bit address register
18 function with true-complement and parity generators. The
19 significant aspect of this layout is the use of single
cells as both active cells and wiring cells. For example,
21 the left-hand side of the cell in column Cl, row R14,
22 enumerated 106, is used for first level wiring only.
23 Thus, this set of wires is disposed in an area of the
24 cells in column Cl which are not exposed. None of the
Schottky diode inputs on the left-hand side of the circuit
26 cells in locations Cl/R13 and R14 are contacted by the
27 wiring, although the right-hand sides only of these cells
28 are used as active cells. The remainder of the cells in
FI9-77-002 -16-
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1 that column are utilized for wiring only. There is,
2 then, a complete first level wiring path through the
3 Macro in column Cl. A similar path exists in column
4 C6.
Figure 7 illustrates that the layout, in addition
6 to containing continuous wiring cells at the periphery
7 of the Macro, many also contain individual wiring cells
8 within the Macro, as at locations C3/R6, C3/R7 and C3/R8.
9 Turning now to Figure 8, there is shown a schematic
layout of a Macro wherein second level wiring in an entire
11 row, R9, traverses the Macro. Wiring channels provided
12 for signal buses pass straight through the Macro between
13 the active cells of the Macro. In addition, first level
14 wiring in column C5 provides similar passage for columnar
connected signal buses through the Macro. All of the
16 active cells are fully utilized and the global wiring
17 is unable to pass through the active cells. By allowing
18 the interconnections to pass through the Macro, rather
19 than around it, the wiring lengths are reduced, with
concomitant advantages in reduced silicon area and potential
21 drops.
22 As discussed in the Summary of the Invention, the
23 circuit density on modern semiconductor chips is limited
24 by the wiring required to interconnect the circuit cells.
In particular, most designs require that there be a greater
26 density of conductors near the center of the chip than at
27 the periphery. Our invention allows for a greater wiring
28 density at the center of the chip than at the periphery
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1 and lends itself to alternate approaches for the layout
2 of an entire chip. In Figure 9, the wiring cells are
3 designed to have the same area ~s the active cells, as
4 in the previous embodiments with respect to Macros, and
more wiring cells of the same area are allocated at the
6 center of the chip than at the periphery. This allows
7 a greater number of conductors to be provided near the
8 center of the chip.
9 In Figure lO,the relative areas of each wiring cell
are varied so that the area of an individual wiring cell
11 at the center of the chip is greater than the area of
12 the wiring cell at the periphery. Clearly, various modi-
13 f ications of these layouts are possible which would also
14 come within the purview of our invention. For example,
the wiring cells in Figures 9 and 10 are for first level
16 wiring, but the same concepts apply for second level,
17 orthogonal wiring.
18 ~hile the invention has been particularly shown
19 and described with reference to preferred embodiments
thereof, it would be understood by those skilled in
21 the art that the foregoing and other changes in form
22 and details may be made therein without departing from
23 the spirit and scope of the invention.
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