Note: Descriptions are shown in the official language in which they were submitted.
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HIGH SPEED PE~EDICTIVE ENCODIl\IG ANI) DEC012ING SYSTEM
FOR
TELEVISIOM VIDE~O SIGNAL,S
The present invention relates to a high speed predictive
encoding and decoding system for the frequency band compression
of television video signals .
A television video signal produced through the horizontal
and vertical scanning of an optical image has a high degree of
correlation between neighboring scanning lines, neighboring
picture elements and successive frames. To reduce the amount
of information to be transmitted for frequency band compression,
the so-called predictive encoding system has been proposed .
` ~ 10 One example of the predictive ènccding system is of the intraf3 ame
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type, in which the correlation is taken between the neighboring
scanning lines or neighboring picture elements by subtracti~g
from the present video signal level a predicted signal level
corresponding to the level taken one scanning period or one
picture element period earlier~ Another exampie is of the
interframe type, in which the predicted signal level corresponds
to the level taken one frame period earlier.
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~or tlle cletails of the intrafrclme and interframe
predictive encoclillg system, reference is made to PROCEEDINGS OF
TilE IEEE" Vol. 60, No. 7, pp. 779 - 799, July issue, 1972 (Liter-
ature 1).
~ more sophisticated version of the predictive encoding
system based on the combination of the intraframe and interframe
predictive encoding system has been proposed in the United States
Patent No. ~,133,006 issuecl on Jaunary 2, 1979.
ilowever, these conventional systems require high speed
logic and memory circuits, because the subtraction oE the digitized
prediction signal from -the incoming encoded video signal, and the
quantization of the result of subtraction must be completed in one
video sampling period, e.g., 10 second. This tends to make
the system as a ~lole very costly to manufacture.
An object of the present invention is therefore to pro-
vide a high speed predictive encoding and decoding system for the
; frequency band compression of television video signals without
resorting to high-speed circuit elements otherwise required in
conventional systems.
The present system has a transmitting unit and a receiving
unit coupled by a transmission link for transmitting a video signal
produced through a repeated horizontal and vertical scanning of
an optical image, wherein said transmitting unit comprises:
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an A/D converter for digiti~lng said video signal to provide a.
series of d;gitized video codewords at the rate of the sarnpling of
said video signal for digiti~ing; means, including a pair of memory
. ¦ means for temporarily storing two successive segments of said
codeword series segment by segment, for interleaving said
codewords of one segment with those of immediately neighboring
segment; and means for predictive encoding of the output of said
interleaYing means, to provide a series of codewords representative
of the predictive encoding output alternately of the neighboring
segments; and wherein said receiving unit comprises: means for
:
predictive decoding of the output of said predictive encoding means;
means, including a pair of memory means having a capacity equal
`~ to that of the memory means at the transmitting unit, for sepa~ating
~ ¦ the predictive encoding output for one of the segments from that of
: ~ 15 the other of the segments through a signal processing inverse to
that performed at said interleaving means; and means for converting
into an analog signal the output of said separating means.
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~, The present invention gives two video sampling periods for
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every cycle of logic operations needed for the predictive encoding.
~- 20 Those high-speed circuit elements required for conventional
systems may therefore be replaced with low-speed, less e~pensive
elements to achieve a performance comparable to that of the
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conventional systems . Similarly, the present illvention ~nakes it
possible to incrcase the video sampling frecluency and associated
clock pulse repetition frequency if such increase is required.
Now the present invention will be described in greater detail
in conjunction with the accompanying drawings, in which:
Fig. 1 is a block diagram of one embodiment of the present
' inventlon;
Fig . 2 shows in blocks details of a part of the embodiment;
Fig . 3 sho~vs in blocks another part of the embodiment;
Fig. 4 shows in blocks still another part of the embodiment;
and
Fig. S is a time chart for describing the operation of the
embodiment .
Referring to Fig. 1, the embodiment shown therein has a
transmitter unit T and a receiver unit R. The transmitter unit
T has an A/D converter 1 for digitizing a television signal supplied
through an input terminal 16 with a sampling frequency fs ~
The digitized video signal; which is a PCM signal with 8 digits
assigned to every sampled picture element, is then supplied to
an interleaving means 2 to be described later. The output of
the interleaving means 2 is subjected to the correlation-taking
process at a predictive encoding means 3 for the frequency band
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colnpr~ssion. Th~ hori~ontal synchroni~ing pulse is separated
from the input video signal at sync separating circuit 11 and
supplied to a clock pulse generator 12 and the interleaving means 2.
The clock pulse of the sampling frequency fs~ e.g., 10.74 MHz
is supplied to the A/D converter 1, the interleaving means 2 and
the predictive encoding means 3. Another clock pulse synchronized
with the sampling-frequency c:Lock pulse (frequency being equal to
: 8 fs) is generated within the AJD converter 1 for the PCM encoding.
Of the structural elements of the units T and R, those except
the interleaving means 2 and-reverse-interleaving means S may be
made of well~known circuits . The description hereunder will
therefore be concentrated on these means 2 and 5.
Referring further to Fig. 1, the receiver unit R has a
~, predictive decoding means 4 for prediction-decoding the incoming
digital signal supplied through a transrnission line (shown in dotted
¦ line) and an input terminal 14, a reverse-interleaving means 5,
and a D/A converter 6. A clock pulse generator 15 is provided
for supplying sampling-frequency clock pulses to the ~neans 4, 5
and 6. A timing signal separating circuit 13 connected to the
-~ 20 input terminal 14 separates a synchronizing signaI for setting the
time base of the operation of the receiver unit R and supplies it
to the ~everse-interleaving means 5.
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E~eferring to Fig. 2, the interleaving rneans 2 has an input
t~rmin~l 25 for receiving the digitized vicleo signal in a series of
8-digit parallel codewords representative respectively of the signal
levels of the picture elements successively sampled at the sampling
frequency clock pulse. The digitized video signal is supplied to
a pair of random-access me~ories 21 and Z2 through a first
switching means 23, which is driven by a first switch driver
means 23d to connect the input terminal 25 to the memories 21 and
; 22 alternatively in response to the output of a bistable circuit 9
driven by the horizontal synchronizing signal supplied at sync input
; terminal 29 from the sync separating circuit 11 (Fig. 1). Each of
the memories 21 and 22 has a capacity for picture elements lying
in one horizontal scanning period, each of the picture elements
being represented by 8 bit parallel codeword, i.e., 8 bit x 684 --
54~Z bits . Also, the switching means 23 is driven upward and
¦ downward at an interval of the horizontal sync signal, i.e., the
horizontal scanning period. Thus, a first one-horizontal-line
long segment of the digitized video signal is stored in the memory 21,
a second one in the memory 22, a third one in the memory 21 and
ZO fourth one in the memory 22 and so forth. To enable the write-in
at memories 21 and 22 in the above-mentioned fashion, a write
address counter 7 supplies a ~}bit parallel write address codes
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at a rate of the sampling frequency clock pulse in synchronism with
the horizontal sync pulse. The write address codes are decoded
at the respective mernories Zl and 22 to effect the scanning-li3ce
. actuations of the 8-bit parallel memory cell arrays from one end
to the other.
¦ The read-out of the memories 21 and 22 is controlled by a
read address counter 8 which is identical in circuit construction
to the write address counter 7 and generates read-out address to
effect the scanning of the 8-bit parallel memory cell arrays.
The i~bit parallel read address codes are timed with the write
~- address codes so that the read-out follows the write-in one video
codeword period behind the write-in. The storage contents at
the respective 8-bit parallel cell arrays accessed successively
- appear at the output of the memories 21 and 22, and are selected
by a second switch 24, which is driven by a second switch driver
means 24d to derive the read-out outputs of the memories 21 and
22 alternatingly in response to a second bistable circuit 10.
In contrast to the first bistable circuit 9 drivsn by the hori~ontal
sync pulse, the second bistable circuit 10 is driven by the
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~; ZO sampling-frequency clock pulse supplied through terIninal 27.
The alternate upward and downward switching of the movable
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contact o~ the second switching means Z4 is therefore at the rate
of the sampling pulse.
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Now the operation of the interleaving means 2 will be described
in more detail referring also to the time chart shown in Fia. 5, in
which ~vaveforms (a) to (j) represent those of the signals obs0rved
at the points denoted in Fig. 2 by the corresponding reference
characters ~ It is assumed that in the first horizontal scanning
period Hl, the switch 23 selects the memory 21 in response to the
binary "0" state of the switch control input (c) to the switch
driver 23d. During this period, the first one-horiz;ontal-line long
segment (d) Al ~ Am of the digitized video signal is successively
written in the corresponding addresses in the memory Zl in response
to the write addresses (e) given from the write address counter 7 at
¦ -the same rate as the sampling frequency fs (b). The read addresses
are fed from the read address counter 8 to the memory 21 and 23
after a delay of one horizontal scanning period, so that no codeword
is read out from the memory 21 nor from the memory 22 during
this period Hl.
Xn the second horizontal scanning period H2, the switch 23
k selects the ~nemory 22 in response to the binary "1" state of the
switch- control input (c) . For thi~3 reason, in the first clock
period 1 among the second horizontal scanning period H2, the
first codeword Bl of the second one-horizontal-line long digitized
video signal segment is written in at the first address of the
memory Z2.
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On the other ha~d; in this clock period, the first codeword Al
stored in the memory 21 and the first codeword el just stored
- in the memory ~2 in the first cloclc period i are respective1y read
out to allow only the first codeword Al to be outputed to the output
S terminal 26 because of the movable contac-t of the switch 24 connected
to the memory 21 under the binary "0" state of the switch control
- input (i~. In the second clock: period 2, the second codeword B2 is
written in the memory ZZ while the first codeword B 1 is outputed
because of the movable contact of the switch 24 now turned to the
memory 22 in response to the binary "l" state of the switch control
input (i). In the third clock period 3, the third codeword B3 is
written in the memory 22 ~,vhile the second codewords A2 and Bz
are respectively read out from the memories 21 and Z2 to allow
only the second codeword A2 to be outputed. In the fourth clock
: ~ 15 period 4, the fourth codeword B4 is written in memory 22 while
the remaining second codeword B2 is outputed. In this way, in
k
`~ the second horizontal scanning period HZ, the respective first
~ codewords Al - Am and Bl - B~ of the first and second
.-~ digitized video signal segments storèd in the memories Zl and 22,
: Z0 respectively, are read out from the corresponding addresses
according to the read addresses (f) and are interleaved as shown
Fig . 5 (j ) .
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In the third hori~.onta1 scannin~ period H3 in l~hich the
switch 23 select~ the rnemory 21 agairl, the third digitized video
signal segment (d) Cl ~ Cm is written in the line rnemor~ 21,
,` and at the same time the remaining latter codewords Am -. 1 ~ Am
S and B m -~ 1 ~ Bm f the first and second digiti~ed video signal
segments stored in the memo:ries 21 and Z2 are read out alternately.
Then, in the fourth hori~ontal scanning period H4 (not-sho~,vn),
the fourth digitized video signal segment (d) written in the memory 22,
and the respective first codewords of the third and fourth digitized
video signal segments stored in the memories 21 and 22 are read
out. In the fifth horizontal scanning period H5 (not shown), the
fifth digiti~ed video signal segment is written in the memory 21,
~r while the rem.aining latter half of the third and fourth digitized
video signal segments are read out. In the above-described
manner, the two horizontal-line-long digiti~ed video signal
:segmsnts are arranged interleaved in two successive horizontal
scanning period pairs (H2)--(H3) and (H4)-(H5) as shown at (j)
in Fig. 5.
Referring to Fig, 3, the predictive encoding means 3 has
a subtractor 31 for providing a digital signal representative of
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the difference between digital video signal (j) supplied through an
input terminal 38 and the prediction reference signal fed from a
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- multiplier to be described later. The output of the subtractor 31
is delayed by one clock period at a first register 33, which serves
as a delay rlleans . The delayed difference signal is then quantized
at a quantizer 36 to provide a digital signal representative of the
1 5 difference for transrnission through an output terrninal 39.
An adder 32 is also provided fox providing the sum of the output
of the quanti~er 36 and the prediction reference signal supplied
through a second delay means 35. The output of the adder 32 is
delayed by a third delay means 34 for giving a delay of one cloclc
period to the output signal of the adder 32, and multiplied by a
multiplier 37 for multiplication of the output signal by a factor
(O ~ 1) to form the prediction reference signal.
To describe the opera,tion of the predictive encoding means 3
of Fig. 3, it is assumed that the first codeword Bl of the second
I S horizontal scanning period H2 is supplied for the interleaving
means 2 and followed by the second codeword B2. When the
latter arrives at the input terminal 38, the first codeword Bl
~' has been already processed into a prediction reference code by
the circuit elements 31, 32, 33, 34, 35, 36 and 37. Due to the
` ~-~ 20 delay given at the delay means 33, 34, and 35, the prediction
reference signal fed to the subtractor 31 is in synchronism with
the second codeword B2. For details of the predictive encoding
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means 3, reference i9 made to Fig. 4 oE Literature 1. It will be
noted that, the incoming code~,rords Bl, B2, etc. are supplied at
an interval t~,vice as longJ as the sampling period. This allows the
rate of the incoming data to be one half of the write operation,
relaxing the speed requirement for the circuit elements included
in those structural ele~nents 31, 32, 33, 349 35, 36 and 37.
The same applies to other structural element 4 included in the
r e c eiving uni t R .
Referring to Fig. 4, an exa}nple of the predictive decoding
means 4 has a decoder 41 for decoding the prediction-encoded
~ ~ codewords supplied at an input terminal 4b from the encoding
? means 3 through a transmission line shown in dotted line.
The output from the decoder 41 is supplied to an adder 4Z for
summation with the output of a multiplier 45, which is supplied
' 15 ~,vith the output of the adder 42 through delay means 43 and 4~,
: which respectively, give a delay of one clock period. The factor
'~ of multiplication at a multiplier 45 for multiplying the output signal
'~ of the register 44 is o~. This predictive decoding means 4 has
such a construction that the register 43 corresponding to the
- , ~ 20 register 33 or 35 used in the encoding means 3 of Fig. 3 is
added to the predictive decoding means shown in Fig. 4 on page
782 of the Literature 1.
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In tlle reCeiVir1g unit R, the reverse-interlea~ing rneans 5
~' supplied with the output of the predictive decoding means 4 has
exactly the same circuit construction as the interleaving means 2
except that the input digitized difference signal sequence is given
to the output terminal 26 rather than to the terminal 25, so that
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the alternate write-in into the memories 21 and 2Z is switched by
the switching means 24 at an interval of the sampling pulses while
the alternate read-out from the memories 21 and 22 is switched
at an interva1 of the horizontal sync pulses, thereby to restore
the digitized video codeword sequence line by line.
. The restored digitized video codeword sequence is converted
~: ~ into an analogue signal at the D/A converter 6.` ~ The intraframe prediction encoding/decoding described with: ~` respect to the encoding means 3 and decoding means 4 in the
embodiment may be the so-called composite interfra~ne predictive
. encoding/decoding, which is a combination of the simple intraframe
prediction encoding and the interframe predictive encoding/decoding
j~ as shown in Fig 3(a) and 3(b), respectiv~ly of Conference Record,
pp. 6.4-1 to 6.4-5 of the "National Telecommunication Conference"
held in 1976. Stated simply, the composite interframe predictive
encoding/decoding is identical to the simple intraframe prediction
encoding/decoding except that an additional delay means of one
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frame period is provided to take the aclditional frarne-to-frame
c o r re lation .
Also the capacity of the memories 21 ancl 22 which is for
one horizontal-scanning-line-long digitized video signal segment
in the embodiment, may be chosen arbitrarily depending on the video
signal to be handled.
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