Note: Descriptions are shown in the official language in which they were submitted.
7~
~ gro~ing cl~ss of disp]ay devices employs
pllosphor coatecl segmented anodes excited by low energy
thermoelectrons emitted by a dull red filament controlled
by a control grid either interposed therebetween or on
the outside of the filament. These devices are enclosed
in enclosures in which a hard vacuum is drawn. A
transparent window in the enclosure enables viewing of
the excited anode segments usually through the control
grid. The segmented anodes may be in any configuration
such as 7-segment numeric or multiple-segment alphabetic
as illustrated in U.S. Patent 3,986,760, issued October
19~ 1976 to Kishino, or they may be in a sequentially
illuminated linear indicator such as disclosed in
applicant's U.S. Patent 4,100,455, issued July 11, 197~.
The prior art and the present invention will be
described in conjunction with the accompanying drawings,
in which:
Fig. 1 shows one example of the prior art
employing a 7-segment alphanumeric display controlled
by an integrated circuit
~ ig. 2 shows another example of the prior art
employing a linear scale indicator.
Fig. 3 shows one embodiment of the present ~`
invention.
Fig. 4 shows another embodiment of the present
invention.
Vacuum fluorescent display devices are being widely
chosen for display purposes because of their brightness,
reliability, color and compatibility for drive by solid
state descrete or integrated circuits. In the typical
application, the value to be displayed is an analog or
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digital signal which must then be processed to yield one
binary signal per anode segment to command each anode
segment to be either illuminated or extinguished. More
sophisticated sytems can~ in addition, incrementally
control the brightness o the anode segments between
full oEf and ull on.
Fig. 1 shows the method used in the prior art to
perform the simple ~unction of driving a 7-segment numeric
display lO ~rom a 4-Iine binary-coded-decimal input 12.
An evacuated enclosure 14 of the display 10 is mounted
on a suitable support such as a circuit board 16. An
integrated circuit 18 in its evacuated enclosure 20 is
also mounted on the circuit board 16. One signal line 22
per segment,~a total o 7 lines in the illustrated example,
is connected between the evacuated enclosure 20 and the
evacuated enclosure 14 to connect the 7 binary signals
~; ~ between them. Thus, exclusive of DC power inpues7 the
integrated circuit evacuated enclosure 20 has 11 hermetically
sealed leads 24 piercing it and the dispIay evacuated
enclosare 14 has 7 hermetically sealed leads 24 piercing ~ -
it. Furthermore, the leads 24 are connected to the signal
lines 22 by interconnections 26 at each of the two ends
of each signal line 22. Thus there are 14 interconnections
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26 for the 7 signal lines 22. In the electronics industry,
faulty interconnections 22 account for a large part o~
both assembly labor and device failures. An even more
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exaggerated example of interconnect requirements is to
be :~ound in the linear scale indicator of the referenced
U.S. patent application. A 40-segmenk linear scale
indicator as illustrated at 28 in Fig. 2 requires 40
signal lines 22, 80 hermetic seals and 80 interconnections
to con~rol the 40 segments from a driver inte~rated
circuit 30. In a typical application, only a single
analog input signal line 32 is required into the integrated
circuit 30. The integrated circuit 30 generates a
contiguous set of binary.ones on the signal lines 2~ to
the linear scale indicator 28 in proportion to the amplitude
of the analog signal on the signal line 32.
. Summary of the Invention
The applicant has discovered that many of the
mechanical, chemical and sealing operations incident
to manufacturing a vacuum fluorescent di9play and an
integrated circuit are t~e same. For.example, both
: devices require cleaning, metallizing, application of
:photoresist, etching and removal of photoresist. In
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addition, the working environment of both devices is
preferably a hard vacuum. The bonding of the~integrated
circuit. t~ the substrat is per~ormecl using a low
: temperature glass preform which fuses at a~low:temperature
of~approximately 525C. This temperature is low enough
to have negligible effect on the:integrated circuit~
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; Furthermore, the cover of the enclosure~is bonded to
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the ~u~stra~ at tl-e samc temp~rature. ConsequeQtly7
the app]icnnt con~emp]ates perforrning the e]ectrLcal
interconnections between electrical leads formed on
the substrate and integrated cLrcuit, then placing the
cover in place and bonding the lntegrated circuit to
the substrate in the same heating operation used to
seal the perimeter of the cover to the substrate.
The present invention is used in a method of
producing an integrated display device having a substrate
and a cover bonded thereto to form a hermetically sealed
enclosure having an integrated circuit mounted therein.
This method includes the steps of forming a plurality
of anodes on the substrate~ forming electric leads on
the substrate, with the electric leads interconnecting
with the anodes. The anodes have at least a part thereof
coated with a phosphor. Further steps are affixing
at least one control grid and one filament to the
substrate, mounting the integrated circuit on the
substrate and interconnecting the integrated circuit with
the electric leads. The invention relates to the
improvement comprising the steps of., (a) positioning
a low-temperature glass preform on the substrate between
the integrated circuit and the substrate prior to inter-
connection of the integrated circuit with the electrical
leads; (b) placing the cover on the substrate for
covering the anodes, control grid, filament and integrated
circuit; and (c3 heating the cover and substrate for
heat bonding the cover to the substrate, the cover and
substrate forming thereby a single sealed enclosure,
the low-temperature glass preform fusing during the
operation of heating the cover and substrate whereby
the integrated circuit is bonded to the substrate as
the cover is heat bonded to the substrate.
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ThC! app l :Lc~l~t dlscLoses a (levLce in whlch the
integra~ecl c;rc~sit and vacllum fluorescent dlsplay are
botll fabricate(l on a single subs~rate wlth dlrect
interconnections between devices. Both devices are
sealed within a single evacuated envelope. Thus, 14
of the hermetic seals for leads 24 shown in Fig. 1
and the 14 interconnects 26 are eliminated. In Fig. 2,
80 leads and interconnects are eliminated leaving only
the analog signal line 32 piercing the vacuum enclosure.
In all cases, certain dc connections, such as ~ilament
voltages must still be supplied through the vacuu
envelope.
In one application contemplated by the applicant,
a complete digital clock, including a plurality of
numeric display devices and the timing and control
electronics are all fabricated on a single substrate,
interconnected and enclosed in a single evacuated
enclosure. Gettering may be employed to improve the
vacuum.
The very great reduction in assembly labor as
well as the improvement in reliability, stemming from
the sharply reduced number of hermetic seals and
interconnects, gives the present invention significantly
improved practicability.
Detailed DescriPtion of the Preferred Embodiment
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Referring to Fig. 3, there is shown generally
at 34 an integrated display according to the present
invention. A substrate 36, suitably of glass or ceramic
has a display device 37 applied thereto consisting of
a conductive pattern of segmented anodes 38 and integral
interconnect lines 40 formed by conventional methods
well known in the art. At least part of the anodes 38
are covered by electron-excitable phosphor material.
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An :Lnte~rrlt(LI c:Lrcu:Lt :].~3 i.s nff:Lxed ~:o ~-he same
substrnte 36 conta:Ln:lllg ~:hc di.sp:Lny device 37 and
:Lnterconnect lines ~0 w:i.th:Ln the same evacuated
enclosure 42. The evacuated enclosure i9 formed by
a concave cover plate being placed over the substrate
36 and sealed thereto about their abutting perimeters.
In this way, only internal connections between the
display device 37 and the lntegrated
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circui~ 18 are required. ~3 iS readily e-vident, the device
in Fig. 3 eliminated 14 interconnects and 14 hermetic æeals
as compared to the prior art device shown in Fig, 1.
Even more dramatic reductions in interconnects and
hermetic seals occur when a prior art deyice o~ the type
shown in Fig. 2 is integrated into a single evacuated en-
closure. Eighty of 81 hermetic seals and 80 interconnects
are eliminated in the 40-segment device and replaced by high-
reliability machine-made interconnect lines which are sealed
and protected within the slngle evacuated enclosure.
Certain types of devices made according to the present
invention require no signal inputs or outputs except for
power and alignment signals. A complete digital clock is
shown at 44 in Fig. 4. A digital clock integrated circui~ 46
is affixed to the same substrate 48 as the four-digit display
elements 50 and the hours/minutes delimiter 52. According
to the operation of vacuum fIuorescent dîsplay devices
disclosed in the references, a control grid 54 over each display
element 50 de~ermines whether it is illuminated or extinguished.
Each control grid 54 i6 connected to the digital clock integrated
circuit 46 by a control line 58 at least partly integrally
formed on the substrate 48 during the p-reparatlon o~ the d~s-
` play elements 50. The corresponding anodes 56 from each dis-
play element 50 are connected in parallel to outputs of the
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;~ ~ digital clock integrated circuit 46 by signal lines 60 at
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leas-t partly in~egrally forrned on the substrate 48 during
the preparation of tlle di.splav elements 50. It will be
evident to one skilled in the ar-t, that the control lines
58 and signal lines 60 may be on the ront or rear face of
the substrate or they may be sandwiched between one or more
layers of insulating material. Furthermore, some parts o
the control lines 58 and signal lines 60 may be on one sur-
ace and other parts on other surfaces. Interconnections
between display elements 50, integrated circuit 46 and parts
o the control and signal lines 58, 60 may be direct or
through holes in the insula.ting layers or by other means
known or to become known in the' a.rt. The displa,y elements
50, the integrated circuit 46 and at least part of the con-
trol and signal lines 58, 60 are enclosed within a single
evacuated enclosure 62.
The digital clock 44 illuminates each o the display
elements 50 i~ turn at a high rate to create the visual
impression that all display elements 50 are continuously
illuminated with their selected numerals~ For example, the
control lines 58 may ena.ble the illumination of one display
element 50 at a time at the rate o 400 per second. Thus
each o the ~ display elements 50 is illuminated 100 times per
second. At the time a particular,display element 50 is enabled
by its control line 58, all signaL lines 60 assume the digital
code required to display the.decimal digit required or that
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position. A8 the next display element 50 is enabled by its
control line 58, the digital code on ali signal lines 60
changes to display the decimal digit required for that
position.
In all devices discussed, dc power input leads are
required through hermetic seals. These have been omitted
for simplicity.
It will be understood that the claims are intended to
cover all changes and modiications of the preferred embodi-
ments o~ the invention, herein chosen for the purpose o
illustration which do not constitute departures from the
spirit and scope of the invention.
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