Note: Descriptions are shown in the official language in which they were submitted.
6z
,
j, , ~1
: lo~i~
. .
1 METHOD AND APPAR~TUS FOR READING AND .
: DECODING A HIGH ~ENSITY LINEAR BAR CODE . :.
. .. ~ .^~-`
Prior Art and Summary of the~Invention
26 ~ ~ This inventlon relates to a~method and apparatus for ¦ -
27 ;:readlng and aecoding a hlgh denslty, linear bar code of the j
28 type of the Un~ersal Product Code standara symbol and : !
~ 31 ~ va~latl 1Is thore~F
~2 :
. . , .
, ' .
1 .
;
-' ' ~:
'
, ,
,
362
1 The grocery industry has adopted a linear bar code that
2 is known as ~he Universal Product Bar Code (UPC~ for identifying
3 the items sold in the grocery trade~ This Universal
4 Product Code symbGl is widely used in the grocery industry
by marking it on packages, containers, cans or the like in
6 which ~he items are packaged and sola. The standard s~ ~ol
7 comprises a series of parallel light and dark bars of different.
8 widths with an optical character recognition (OCR-B~ numeric
9 font equivalent of the symbol printed along with the bar code
t0 symbol. The standar~ ~PC symbol is also employed on shelf
11¦ labels for identifying the items stored on the shelves
12 for use in inventory control purposes and the like. Various
14 ¦ prior art publications disclose the standard UPC symbol and
151 its characteristics as utilized in the grocery industry and
I the various versions for use in other industries~ i~e.~ for
16 use on drug and health related items and general merchandise
18 or department store items~ In ad~ition, special versions that
have been developed such as ~he zero-suppression version ~o
facilitate marking the symbol on packages that are too small
to include the UPC symbol and the distribution symbol (DCI) .
22 and which DCI symbol is designed for printing on shipping
23 containers. The primary advantage in utilizing the UPC
symbol is automatic item identification at the check stand in
24 conjunction with automatic, electronie check-out systems. .
26 In present day check-out systems, the UPC bar code symbol
~7 is interpreted by a high speed laser beam scanner.
28 Ther~ is also a need for a portable data acquisition
device to scan the UPC symbol and its descendant, the DCI
29
symbol. This is most easily satisfied with a hand-held wand
3~ . . . .
31 scanner. A wand scanner need not have the depth of field
32 that the check stand scanner requires since it is scanned
~ 111036Z
~j in contact with the label. It does not require the speed of
2~1 the laser beam sincP it is hand propelled. Also, the laser . .
3 I scanner must reject ~he majority of its input as extraneous
4 ¦ graphics but a wand scanner would "see" little extraneous
51 input. However, a portable scanner would be battery powered
61 and therefore low power consu~.?tion is important~ Also, while
71 the velocity of the laser beam is known, hand movement
81 velocities vary ovex a wide range and exhibit significant
9¦ accelerations.
10~ Prior art methods of readi~g the UPC symb~l consist of
111 decoding the symbol through the use of delta distances to .
12¦ eliminate printing tolerances due to ink spread resulting from
13 printing the symbol on a surface~ Ink spread is the major .
14 printing error to be considered in decoding bar coded data.
Delta distance measurements are the distances between the
16 leading edges and the trailing edges of a combinatîon of
17 successive bars and spaces in the bar coded symb51. The delta
1B distance measurements are utilized to obtain ratios of the
~9 selected delta distances for decoding the symbol. I~ the ink
spread is uniform in the r~corded ~ymbol, these decoding ratios.
22 do not change as a result of the ink spread. There ~re sixteen
combinations of ratios~ ~ut when the forward and reverse .
23 sequences are considered, twenty ratios are required.
24 Accordingly, some further measurement must be made to
2 resolve the ambiguities that result when a distinct delta .
6 distance ratio cannot be solely used for decoding purposes.
28 These other measurements do not have the advantage wi$h respect .
to printing tolerances that the delta distance measurements
29 have. Some early prior art decoding techniques required that
31
~2 . . .
362
1I the decodin~ circuitry distinguish between a larye numbex of
2 1 ratios and very close ratios thereby requiring very good
31 resolution for decoding purposes. Such resolution is not
41 readily obtainable, particularly in a hand-held wand scanner
51 or a portable decoding unit. More recently, decoding techniques
61 have been developed so as to reduce the number of ratios to
71 be discriminated between to four ratios having relatively .
8 good separation between them so that they may be readily
distinguished. In this type of decoding arrangement, the
ratios are selected so ~at the numerator and denominator have
11 one bar and one space so that the ink spread is not a factor
13 in the resulting ratio. Since in ~e UPC sym~ol each coded
digit has a forward and a reverse sequence~ there are still
14 combinations that produce ambiguities when these prior art
15 techniques are resorted toO These digits cannot be .
16 una~biguously decoded solely on the basis of the aforementioned.
: delta distance ratios and some other means or rati~s must be 18 utilized to eliminate the printing tolerance problem and .
yet unambiguously decode all of the coded digitsO ~he prior
21 art methods of implementing the aforementioned decoding .
techniques in terms of delta distance measurements are
~2 .
23 generally by means of utilizing the high speed laser beam .
24 scanner and associated circuits for computing the decoding
ratios. In a manual wand scanning technique for reading the :
2 UPC symbol and similar symbols t wide ranges of velocities may
6 result from passing the wand over the recorded symbol whereby .
28 these priox art circuits for computing the delta distance
29 ratios are not practical. Some prior art techniques utilized .
with hand-held wand scanners for reading bar coded data .
31 utilize logarithm time based circuits~ however, ~ese circuits
~2 . .
ll~LO ~ 2
1 are not practical for computing the delta distance ratios for
2 decoding the UPC symbol.
3 The present invention provides an improved, very reliable
4 low cost , low power consuming method and apparatus for reading
and decoding a high density linear bar code of the type of
6 the UPC symbol that may be advantageously employed in a manual
7 wand scanner but may also be used in other decoding apparatus.
8 The invention provides reliable reading and decoding that is
9 highly tolerant to wand acceleration and poorly printed symbols
and symbols having a wide range of printing tolerances, yet
11 permitting a simplified technique for resolving amhiguities.
12 The implementation of the present invention recognizes and
takes advant~ge of the minimum ~nount of graphics rejection
14 required in a hand-held wand, Yis-a-vis~ a high-speed laser
beam scanner. The implementation of the present invention is
76 advantageous over prior art methods and apparatus in that it
17 measures the widths of the successive bars and spaces in a
18 bar coded symbol in real time and stores them in a storage
19 device of the type of a random access memory which permits
22o sophisticated po5t processing techniques to be utilized once
22 the measurements are madeO In addition f certain computations .
may be readily made by use of logarithmic techniques whîch .
23 permit wide dynamic ranges without the need for multiplying
and dividing large numbers. By utilizing th~ coded information
26 from the central portion or a standard portion of coded symbol
27 of the UPC type, ink spread corrections can be readily made
28 and by selecting proper secondary decoding ratios for ambiguity
29 resolution purposes that are dependent upon the primary decoding
ratios whereby the ambiguities may be resolved with con~idence.
31 . .
32
362
1 ¦ These and othex features of the present inve~tion may
2 be more fully appreciated when considered in the light of the
3 followin~ specification and drawings, in which:
4 FIG. 1 is a schematic block diagram of the reader for
manually reading a UPC symbol or a deriva~i~e thereof and
6 embodying the present inventicn;
7 FIG. lA is a representation of the UPC standard symbol;
8 FIG. lB is a representation of the character structure
9 of the symbol illustrated in Fig. lA;
FIG. lC is a xepresentation of the character structure of.
~' .1
11 the symbol of Fig. lA and identifying the primary and ..
secondary decoding ratios;
13 FIG. 2 is a schematic block diagram of the linear time
14 to digital converter utilized in the system of FIG. l;
FIG. 3 is a schematic block diagram of the center bar
16 locator utilized in the system o~ Fig. l;
FIGo 3A is a diagrammatic illustration of the address
18 positions in a memoxy of the center bar pattern for a symbol
19 of the type illustrated in Fig. lA;
FIG. 3B is a representation of the information stored
21 in the read only memory E utilized in the center bar locator
22 of Fig. 3;
23 FIG. 4 is a schematio block diagram of the ratio computer
24 utilized in the system of FigO l; and
2 FIG~ S is a schematic block diagram of the character
6 dec~der utilized in the system of Fig. l.
27 Now referring to the drawings, the invention will be
28
29 examined in detail as the concept may be implemented for
reading and decoding a high density, linear bar code of the
31 type of the grocery industry Univexsal Product Code (UPC)~
~2
~110~62
1 I For ~he purpose of facilitating the understanding of the
2 concept of the present invention, the basic characteristics
3 of the standard UPC symbol as illustrated in Fig. l~ and lB
4 will be first examined. The bas;c characteristics of the
standard Universal Product Code symbol as illustrated in
6 Fig. l includes a series of light and dark parallel bars with
¦ a light margin on each side. As illustrated in Fig. lA, there
81 are 30 dark bars and 29 light baxs for any lO character code.
I The overall shape of the symbol is rectangular. As can be
best appreciated from examining Fig~ lB, each character or
11 digit of the code is represented by ~ da~k bars and two
12 ~ght spaces. Each coded character is made up of seven modules.
13 A module may consist of either a dark bar or a light bar ~or
14 a sequential combination of l, 2, 3 or 4 dark bars or light bars~.
To this end, in Pig. lB the left-hand portion of the character
16 structure illustrated represents the digit 6 wherein the seven
17 moaules are characterized as two bars and ~wo spaces. From this~
18 it will be noted that the right-hand bar consists of a series of
19 four dark modules. The right-hand portion of the character
21 structure is similarly encoded in terms of two bars and two
22 spaces for representing the aeclmal digit 0. It will also be
2 appreciated from examining Fig. lA in particular, that each of
3 the two characters coded in terms of the ~PC symbol is independenl
24 of the other~ The symbol is designed to be recordable or printed
by conventional methods. The UPC symbol is "wandable'which means
27 a simple hand-held device can be used to scan or read the symbol.
Fixed position scanners have been constructed to scan this
8 s~mbol in an o~nidirectional manner. Specifically, the symbol
29 can be automatically read by a scanner, such as a laser beam
31 scanner, when the symbol is drawn past the scanner in any
orientation. Whether the symbol i~ read by means of a hand-held
32 device or by a device having omnidirectional characteristics~
lliO3b:~ ~
1 I there must be some relative motion produced between the recoxded
2 ~ symbol and the scanning device.
4 ¦ The UPC symbvl as repxesented in Fig. lA al50 includes a
l standard pattern comprising a group of coding modules having
5 ¦ known width ratios between successive coding m~dules. As
61 utilized in the standard VPC symbol~ the standard patterns
~¦ illustrated in Fig. lA include three such patterns having a l:l
91 width ratio and which patterns are identified as the left-hand
101 guard bar pattern, the right-hand guard bar pattern and the tall .
11¦ center bar pattern. The right-hand and left-hand guard patterns
12 are defined to represent a dark - light - dark pattern or
13 l 0 1, The tall center bar pattern represents the pattern of
informatioD 0 l 0 l 0 or a light har - dark bar - light bar
t4
pattern. The central bar patt~xn separates the forward and
t6 reverse digits that are encoded by means of the symbol. To the
17 left of the center bar pattern ~ere are five characters of the
18 code which represent the "forward" encoded characters/ while to
19 the right o the tall center bar pattern there are fiYe
characters that are encoded in the "reverse~' ~irection. The
. .
21 forward, or left characters, and the reverse, or right characters .
22 refex to the fact that the right-hand characters represent the
23 binary complement of the left-hand characters. For the decimal
24 digit zero, for example/ the left-hand encoding is OOOllOl~ while
the right hand encoding for zero is lllO010. ~he let-hand
26 characters are considered to have an ~dd parity and the right-
27 hand characters an even parity. The left~hand character will
Z8 comprise 3 or 5 dark modules and always begin with a light space.
29 The right-hand characters will comprise 2 or 4 dark modules and
always begin with a dark module~
31 As illustrated in Fig. lA3 the standard symbol also includes;
32 a modulo check character encoded between the right-hand guard
34 bar pattern and the last module o~ the reverse character field. .
In addition to the left-hand gua~d pattern and to thP right of
~ : ~
llS~36 ~
1 I the left- and guard bar pattern, inf~rmation is recorded
2 which may be utilized to identify the number system of the
characters encoded by means of the symbol and having a
4 preselected widtho In reading any bar coded symbol, the
symbol is not only read as recorded but the peripheral
: 6 recorded information ad~acent the desired information bar
7 coded pattern is gener~ly detected whether it is related to
. 8 the symbol or not. In the laser scanner techniques, for
: example, the majority of the extraneous graphics must be
rejected while in a hand-held wand scanner very little
11 extraneous graphics are sensed by the scanner.
12 As indicated hereinabove and illustrated in Fig~ lB,
13 the UPC symbol comprises two bars and two spaces for represent-
14 in~ a single characterO The order of the bars and spaces
. may be space ~ bar - space - bar~ or the reverse sequence
18 in accordance with the direction of the scan and the field
17 of the recorded character. For the purposes of examinin~
18 the present invention the sequencing assumed is A, B, C, D
wherein the spaces and the bars are identified in accordance
with F~g. lC for both the forward and the reverse directions.
22 Stated di~ferently, each character, whether recorded in the
. forward direction or the reverse dixection will be represented
24 by the sequence A, B, C and D. Wi~h this se~uence.. the two
primarv decodin~ ratios utilized herein are defined as2
~A + B~ ~A + D\
26 ~ DJ and l B + C~
27 In examining Fig. lC, it will be noted that each of these .
28 primary decoding ratios contain in both the numerator and
29 denominator one bar and one space so that any ink spread that
3 may be present does not affect the ratio. ~hese primary
~2
I 9 ,
1~ 36Z
1 I decoding ratios produce the numerical ratios 2/5, 3/4, 4/3
2 and S/2. A pair of these primary ratios are utilized to .
3 decode a sinyle character. Howe~er, it shoud be recognized
4 that in any delta d.istance method utilizing the aforementioned .
decoding ratios, an am~iguity occurs and certain characters
6 cannot be unambiguously decoded solely on the basis of ~he
7 primary decoding ratios. The present invention utilizes
9 selected and simplified secondary decoding ratios fox resolving .
the am~iguity and also corrects any print tolerances rendering
the decoding of a character sy~bol on the basis of a primary
and secondary ratio very reliable~ The sPcondary ratios, .
12 which are utilized in accordance with the present invention,
are dependent upon values resulting from developing the two
14 primary ratios. As indicated in Fig. lC, if-the two primary
15¦ ratios produc~ the ratios 3/4, 4/3 or 4/3, 3/4, then the .
7 1 secondary ratios must be ~ ~ in accordance with the values
~81 of the primary ratios. If the selected primary ratio upon .
,91 which thesecondary decoding ratios are dependent is 3/4 then .
2~1 the ratio of the widths of the modules A and B (A) is examined .
211 while if the primary ratio i8 4~3, then the secondary ratio
221 f ~hP wid~ of the modules C and D (D) is examined. T.he
231 secondary ratios are examined to determine if they are l or l. .
24 . In any event, for those digits thzt do produce an ambigui.ty r
such as l and 7 and 2 and 8, they are decoded on the basi~ of .
26 the two primary decodin~ ratios and the selected secondary
27 decoding ratio. All of the other digits may be unambigously .
28 decoded on the basis of primary decoding ratios alone. .
29 The improved scannex and decoder of the present invention . .
is implemented by means of a microproce~or~ The widths of
. .
31 each bar and each space o~ a scanned symbol are measured and .
32 . . .
~ 111~)362
1 stored in a counter that is driven by a linear time base.
2 These measured distances or widths are then transferred to a
3 memory, once a measurement is completed and the successi~e
4 measurements are stored in successive storage locations in
5 the memory until all of the measurements are completed. As .
fi indicated hereinabove, in the scanning of a recorded symbol
7 there is extraneous graphics on the label with the UPC symbol. .
8 that may be sensed and this extraneous data is also stored
9 in the memory along with the desired information. Accordingly,
the information scanned before scanning the symbol itself
11 as well as the information detected after the symbol is stored
12 in the memory~ There is no decoding while the label i5 being
13 scanned. This procedure requires that the l'label" having the
14 desired encoded information be.located or "framed" in the
memory before it ca~ be decoded. As indicatedhereinabove~ the
16 standard UPC symbol has a standard central bar pattern wherein .
17 characters are encoded to the left and to the right of the
18 centex bar patternO The data in the memory is examined so .
19 that the encoded data may be located th~rein by examining and
locating ~he stored data representing the standard center bar .
l pattern~ Once this center bar pattern is located, i~ i5 .
2~1 utilized in accordance with the present invention for identi~yin .
24 the locations in stoxage of the encoded characters to the .
l left and to the right thereof. Stated diferently~ once the .
Z5 center bar pattern position in memory is located, the locations
2B of the modules A, B, C and D will be known for each character
27 of the symbol. Qnce these modules are located in the memory, .
28 then the sums of the modules may be computed to determine the .
29 values of the two primary decoding ratios~ Once the primary .
31 decoding ratios are computed, the secondary decoding ratios
. . .
32 . ;
36Z
1 may be computed and the s~nbol decoded~ If the two pximary
2 ratios produce any combination of 3/4 and 4/3, an ambiguity
3 exists which is resolved by means of the aforementioned
4 secondary decoding ra~ios O see Table ï..
6 TABLE X
Primary Ratios
7~ ~ B :~ ~ D
. 8~ I: B + C ~;econdary Ratio Resultinq Di~it
9~/5 2/5 3 Reverse
10~/5 3/4 4 Forward .
112/S 4/3 0 R~verse
2~5 S/2 . 6 Forward
12 . .
133/4 2/5 S Forward
143/4 3/4 A ~ 7 Reverse
153~4 3~4 B 2 l Reverse
163/~ 4j3 B l 2 Forward .
18~f 4 4~3 ~ = 1 8 Forward
1g3/4 5/2 - 9 F~everse
204/3 2/5 - 5 Reverse
214/3 3/4 D ~ 1 1 F~rward .
234 j3 3/4 D 2 7 Forwar~
244/3 4/3 D ~ I 8 Reverse
264/3 4/3 D 2 2 Reverse
274/3 5/2 -- 9 Forward
28S/~ 2/5 -- 3 Forward
295/2 3/4 -- 4 Reverse .
305/2 4/3 -- O Forward .
315/2 5/~ - 6 Re~erse
~2
.. : . . .
~ ~' 111036Z
1 I The secondary ratios A/B and C/D do not contain delta
2 ¦ distance properties and so exhibit a wide range of values.
3 ¦ While they do not overlap according ~o the sym~ol specification,
4 ¦ other errors or out-of-~olerance symbols can cause readi~g
5 ¦ errors.
6 ¦ Included in the standard UPC symbol are guard bars and .
71 center bars with a l:l ratio. If the logarithm of the ratio
81 of a cen~.er bar to a center space is other than zeroO the
9¦ ratio is not l:l and the degree of deviation therefrom is
10 indicated by the magnitude of the log. This provides .
11 infonnation on the direction and magnitude of print tolerance .
12 which can be used to correct the secondary ratio measurements.
13 For example, if the ratio of a center bar to a center space
14 i5 measured a~ 2:l, it can be inferred that the symbol is .
15 overprinted. In that case~ a nominal 20.1, A/B ratio would be
16 measured as close to 4: l O I:E the measured A/B ratis~ i~ .
17 divided by the measur d ;::en~.er bar to c:enter space ratio ) .
18 the nominal va1.ue of 2: ~ wouldl resul~:................... .
19 . .
'21 :
2Z ~
23 . .
2q . .
. .
28
29 . . .
31
~2 . . .
lllQ36Z ~ I
1¦ The computations are simplified by utilizing logarithms. The
2 ¦ division results by subtracting the logs. If the A/B (or C/D)
31 ratio i5 a space-to-bar ratio, then the logarithm of the center bar
41 to centQr space ratio is added to the A/B ratio to effect .
51 multiplication. In reading from left to right, the correction
~¦ factor is logarithmically added to the measured widths of the
71 first half of the symbol while it is subtracted from the right
81 hand chara~ters. In a reverse read, the first hal~ is the
9¦ right half.
10¦ A l:l ratio does not change proportionately to a 2.l
t1 under conditions of ink spreadO But a correction can be made
12 if the only nominal ratios are 1:2 and 2:10 If all other .
13 ratios were to be encounteredt in a middle bar to middle bar
14 space ratio.~ for example~ the accuracy of the correction would .
be le~s accurate.
16 With the above structurP and the general philosophy for .
17 decoding the symbol discussed above in mind, the general
18 organization of the decoding system will now be examinea as
19 it is represented in th~ block diagram of Fig~ l. The UPC .
symbol is illustrated in Fig~ 1 as it may be recorded or printed
on a label lO~ The label lO is read by passing ~he optical
22 wand ll over the symbol for detecting and signalling the bars . .
24 and spaces representing the data in terms of the UPC symbol. .
The optical wand ll provides signals indicating the transition .
25 between a white bar and a white space and vice versa. Such . .
27 optical wands are well known in the art and such a wand reading .
28 system is exemplified by the dis~losure in U~ S. patent .
29 3,925,639 owned by the same assignee as the pxesert invention.
These wand signals or raw data are applied to a linear time to :
311 . .
32 1 :
: .
IL11036;~
1 digital converter 12. The converter 12 measures the amount .
2 of time spent by the wand 11 in traversing each bar and each . .
3 space and these width measurements are stored in a read/writé
4 memory 13. The width measurements are stored in sequence in
storage locationsi in the memory 13~ The read/write memory 13
6 may conveniently be a random access memory (RAM)~ When the
7 transitions siensed by the wand 11 terminate,control of the
8 system isi passed from the linear time to digital converter
9 12 to a center bar locator 14. The center bar locator 14 - .
searches the memory 13 for xatios that ~iatisfy the pattern
11 for the center bar of the UPC symbol or the center bar pattern
12 O 1 0 1 00 The center ~ar pattern locator 14 utilizes a
13 ratio computer 15 for this purpose~ The ratio computer 15
14 is utilized also by a character decod~r 16.
~hen the ratio computer 15 is under the control of the
16 center bar locator, it recieives the linear values of the width
17 measurements for the modules A, B~ C and D from the memory 13 .
18 and adds a selected pair of these values and ~omputes .
19 preselected ratios to determiine if a valid center bar pa~tern
is present~ The center bar locator 14 determines the position. .
22 of the center bar pattern in the memoxy by determining that
a preselected pair of ratios are both vneO The center bar
23 pattern representsi the patterA O 1 0 l O.and in reading from
24 lPft to xight these can be çonsid,ered a$ ~he A~ BJ C. D and
E modules, To de~ermine that a valid center bar is loeated
26 :in the mem~ry,l3t,the center bar ratios ~C + D)and(B + C) are .
developed and exa~ined.; I~ both of these ratio5 are oneO
28 then the cen~ex bar,pattern has ~ee~ ço~rectly located in
the memory 130 BY exami~i~g,bot~,~f,~h~ aforementioned ratios lnd
31 ~nthe correct re$ult i~ ~ro~uced, thQ i~ystem will.be assured
32 , ... .
, ~ ", ~ ,
I , , I i I ~ .
/. . . ,; ~41 1l
~1 111036Z
1 that the center bar pattern was begurl with a space and is
2 correctly located. If either of the above ratios do not
3 ¦ compute to one, the process must ~e repeated until two successi~ e
4 ¦ ratios of unity are detected. It shoula be noted in the -
5 ¦ calculations for locating the center bar pattern that the delta
6 ¦ distances are utilized and therefore if the ink ~pread is
71 uniform it will not effect the determination of the correct
81 location of the center bar pattern. If after the preselected
91 numb~r of tryst the desired ratios ar~ not~detected, then
10¦ the read is abortPd.
11¦ Once the conditions for a valid center bar are satisfied,
12 a recording or print tolerance correction character is computed~
13 The print tolerance correction is computed on the ~asis of the .
14 sensed widths of the modules comprising the center bar pattern~
lS The magnitude of the correction is obtained by measuring the .
16 ratio of the standard bars to the guard spacesO Accordingly,
17 to determine the value of the print tolerance correction, the .
18 ratio ( A + C) is computed. In this ratio,~A + C~represents
19 the widths of the bars while~B ~ D)represents the widths o~ .
the ~paces and if the center bar pattern is correctly located~ .
21 the ratio should be one as that was the basic logic of the
22 symbol prior to recbrding or printing ito Once this print .
23 tolerance correction value i~ computed~ the memory address of .
24 the memory 13 i~ set to the location of the start of the first .
26 character to be decodea~ At this point in the decoding process~ .
the control is passed to the character decoder 160 .
27 The character decoder 16 utilizes the ratio computer 15 .
B for executing its function in decoding the pattern of module~
29 to the left and the right of the center bar pattern~ As in .
the ca~e of the valid center bar pattexn recognition~ the .
31 . . . .
~2 .
1~ 36Z
1 characters are decoded by a sequence of ratios produced by
2 the ratio computer 15 under the control of the character
3 decoder 16. The character decoder 16 then steps through the
4 sequence of 12 oharacters plus the centex bar pattern as
~ stored in the memory 13 starting from the location noted by
6 the center bar locatvr~ Once each of the pximary ratios are .
7 computed, the secondary ratios are computed to resolve any
8 possible ambiguity. Before the secondary decoding ratios are
9 computed, the printing tolerance correction character i~
combined with the data representing the width of the modules .
2 as stored in the memory 13 and then these corrected value~ .
1 are utilized in computing the secondary decoding ratios~ If
13 any o the 12 characters fail to properly decode, control i~
14 retuxned to the center bar loeator 14~ Once all of the
1 characters axe properly d~coded by the chc~racter decoder 16 .
17 then the control i~ passed ~rom the decoder 16 to the validity .
18 check circuit 17. . . .
~9 The validity check circui~ 17 ~ill not be described in .
detail since it does not constitute a portion of the novel .
21 aspect of the method and apparatus for decoding the UPC symbol.
22 It is merely. included for the sake of the completeness of
23 the read cycle iterative loop~ To this end there is included .
with each character.~a rçad direction indicator~, In order .
24 that the informa~ion decoded be yalid, the read ~irection .
26 indicators must,all be consistent. If the direction of the .
~ reading by thelwand 11 is in the reverse directionO the ..
28 character o~der is.~eversed an~ the c~eck digit verifiea~ .
2g If either of ~hese tests failO contral of the system is returnec .
to the cent~r ~a~,lqca~qr ~4 toi~etçrmi~e th~i correct location
31 of he center,~ar,pattçrn in the memory 13~ T~is process
32 . , , j , , ;,, . . .
. ,,,, ,, ;,j ,"j, ",,1 ,~, I, . , . .
j .., 16j ll ,,, ,
: . ' '
lllV3b2
1 ~ is repeated until a valid read is accomplished or the potential .
2 locations of a valid symbol as stored in the memory 13 are
3 exhausted. In this latter case, the read cycle is aborted. .
4 With the above general organization of the decoding system .
in mind~ the details of the linear time to digital converter 12
6 as illustrated in Fig~ 2 will now be examined in detail.
7 The lineax time to digital converter 12 comprises the circuit .
8 elements for rPceiving the wand raw data information from the
9 wand 11 and processing the data for storage in the read/write .
mem~xy 13. Yor this purpose~ an AND circuit 20 has one input . .
11 terminal coupled to receive the wand raw aata information .
12 at its input~ The other input of the AND circuit 20 is
13 coupled to a start/stop toggle 21~ The output circuit from
14 the AND circuit 20 is coupled tc~ a differentiator circuit 22) .
which in turn is coupled to a rectifier 23. A toggle TM .
16 has its set input~ Sl coupled directly to the output of the
17 rectifier 23. The reset output for the toggle TM ~s idPntied .
18 as Ml. The set output o~ the t~ggle TM is coupled to an
1g ~ND circuit 2~. The output of the A~D circui~ 24 is coupled
to a sequencer 25 which provides the se~uential output signals :
21 M2, M3 and M4. The real time,measurements re~ult through the
23 provision of.a count rate oscillator 26 which provides clock .
, pulses at a preselected rate to an AND circuit 27. The other
24 input to the AND circuit 27 is the Ml reset.output from the
toggle T~ ,The clock pulseslfrom the oscillator 26 are also
26 applied as.a.second,inpu$ toithe ~NDIcircuit.24 for co~trolling
?7 the operation ~ thel~equ~ncer,25~ ,Th~ AND circuit 27 has its
28 output connect~;,to the i~creme~in~linput~.an 8-bit counter
, 28. The~8-bit counter may,lb,e preset j~hxoughla signal coupled
31 to its preset ~nput a~d ~hi,ch sig~al i$ identified in Fig~ 2
32 I ........... , ,l .l . .
, ~ I 17
. ~ )36Z
1¦ as the M3 signal fr~m the sequencer 25. The 8-bit cvunter 28
21 also has an overflow output which is identified as a carry
31 output and this output signal is coupled to an OR circuit 29 .
41 as one input thereto. The count output~ for the 8-bit coun1er
5¦ 28 are coupled as one input to an AND circuit 30. The other .
61 input to the AND circuit 30 is the M2 signal from the sequencer .
71 25. The output of the AND circuit 30 enables the data input .
8 terminal for the read/write memory 13 and transfers data into
9 the memory at the successive storage locations~ The read/write .
memory 13 is under the control of an address counter and .
11 register 31~ The address counter and register 31 has an .
12 incrementing input fuxther identified as having the M3 signal .
13 from the sequencer 25 coupled thereto for incrementing the
14 succes~ive addre~ses of the memory 13. The address counter
and register 31 also have an ovel-flow output terminal identified .
16 as a "carry ~ut'9 and this output signal is applied as a second .
18 input signal to the OR circuit 29. The star~ing signal for .
ini~ia~ing the read cycle is coupled to the reset terminal :
19 for the adaress counter 31. The OR circuit 29 will produce .
an overflow output signal identified a~ an M5 signal if either .
of its inputs receive an overflow signal from the counter 28 .
22or the register 31~ The M4 signal from the ~encer 25 is .
Z4 applied to the reset terminal R for the toggle TM for resetting :
the toggle at the completion of readiny a module of the UPC
~6 symbol. The "start" signal is also coupled to the reset .
27 terminal of the toggle 21 for e~abling the A~D gate 20. .:
28The operation of the linear time to digital converter 12 :
may now be appreciated with the above ~tructure in mind. This .
30element 12 may be provided with a switch to function to start
31. .
18 .
. '
1110362 : ~
1 ¦ the reading operation and apply a "start" signal to the reset
2 ¦ terminal for the toggle 21 or the "T" toggle, as well as to the
3 ¦ reset terminal for the address counter and the register 31.
4 ¦ The unit 12 on the other hand may be armed to be automatically
5 ¦ responsive to certain conditions that indicate that an attempt
~¦ is to be made to read the label 10, such as when the wand 11
71 is placed against the white surface or the end of the label 10
81 as disclosed in U~ SO Patent 3,925,639r for exampleD As the
9¦ wand 11 i5 moved over the label 10, it detects the transitions -
~I between the dark bars and the white spaces. When these tran-
11¦ sitions vccur~ they are passed through the AND gate 20 and
12¦ are differentiated in the element 22 and rect~.fied at the
13¦ element 23 for application of the resulting signals to the
14¦ "set" terminal of the toggle TMo The toggle TM is 9~etl~ at
15¦ each transition between the detected modules9 The clock
16¦ pulses provided by the oscillator~ axe accumulated in the
~71 8-bit counter 28 between the time intervals; the toggle TM is
1~¦ reset resulting from the application o th~ ~1 signal to AND
19 gate 27. The setting o~ the toggle TM will cause the sequencer
2 25 to be ena~led and disable the application of the clock
1 pulses to the 8-bit counter 28~ This disabling of the clock .
22 pulses to the counter 28 results ~hrough the change in state
23 of the Ml signal upon the toggle TM being "set"~ At this .
4 point in time~ the information that has been accumulated in
the counter 28 is transferred into the memory 13, the address
26 of the memory for storing the next piece of information is
28 incremented between transitions and then resetting the
toggle TM~ The sequencer 25 is provided to perform
29 these functions by generating the sequentiall signals M2 9
30 M3 and M4 in that sequence. The 3equencing opertions that . .
31 . . . .
32 . .
111~36~:
1 result aftex thie.~tting of the toggle TM are as follows:
2 . .
3 Sequencing Signal Function
M2 Load the count of the counter 28
4 into the memory 13~ :
M3 Increment the memory address of th~
register 31 and preset the count of
6 the counter 28~
M4 Reset the toggle TM and accumulate
the counts for the next detected
81module or next biar or space~ .
1 9¦The Ml signal can be considered as a "stop" æignal while the
l M5 signal transfers control of the system to the center bar
1~1 locator 14O
~¦The memory 13 is preferably defined to have the capacity
12¦ to accumulate the results of 64 measurements to permit the
; 131 wand 11 to traverse any extraneous graphics that may ~e
1 assoi~iated with the UPC symbo1 on the label 10~ The count
interval for the counter 28 is about 40 microseconds and the
16 count capacity is 8 bits ~ or countB~ It will be recognize~
17 that some finite amount of time i5 required~to execute the ;
18 functions iden~ified above after a transition point is ..
de~ected by the wand li~ For this purpose the counter 28 is
21 preset ~o,a,value thiat ~epresie~ts.th~ ,co,unt th~t would hav~ . .
been accumulated during this processing time~ In one .
22 arrangementj the minimum count is preset to 7~to allow .
sufficient tim~ to store the ~ccumulated m~asuremçnts in the
memory 13 a~ter t~e tra~siti~n., Th~ caun~.e~ 28 is preset to .
. count 7 at the begin~in~ o.,e~ch,measu~emen~lby the M3.i~ignal
26 to preserve,t~ç accu~ çy,~f,~e ~ec~ding s~stem~
281 If th~ci~unti~r;28 ~r~the~mçmory,addrçss counter 31 ;
¦ overflows and provides an output signal~ the overflow is
301 i~dicated ~y thq ~ u~pu~ sign~ om the OR ga~e 29~ I~
31¦ . ................. . . i i ;
3i~1 i. . . .., ... ! . , ,
7n
l~LlU36;~
1 ¦ i:he M5 signal occurs, it is assumed that the er~d of the la~el .
2 ¦ 10 has been reached and the M5 signal is effective to transfer
31 control of ~le system from the converter 12 to the center bar
4 1 locator 14 . .
5 ¦ Now referring to Figs~ 3, 3,A and 3B, the block diagram o~E
6 ¦ the circuits fsr recognizing and identifying the location of
71 the center bar pattern of the UPC 9ymbol in the memory 13
. ¦ will be explained. Basically, the center bar locator includes
: 9¦ a center bar ratio detector 14D, a retry counter 14C~ a
10¦ center bar locator sequencer 14;5 and a memory address control
¦ unit 14M~ The center bar locator unit 14 oper~tes in
12 ¦ conjunction with the ratio computer 15 for computing the
13¦ desired ratios that are processed by the cen ~ bar locator 14. :
14 During the time interval that the center bar pattern is being . .
.15 located in memory~ the ratio computer 15 is under the control
17 of ~he center bar locator unit 14. The operation of the ratio .
computer will be described more fully hereinafterO
19 The center bar locator se~uencer 14S as illustrated in .
block form in Fig~ 3 includes a sequenc~ for providing the .
signals identified as ~1~ P2~ P3f etc. and Sl~ S2~ S3, etc~
21 The sequencer functions such that when it is pres~t to a
22 specific state all of the other positions of the sequencer
24 are resetO The preset positions are identified in Fig. 3
at the bottom of the se~uencer as Pl~ Sl, P9, etc~ The input
circuit for the sequencer advances the sequencer as it
27 sequentially receives a signal at its step inputO The sequence
. is controlled and sequentially advanced in response to the
29 clock pulses generated by the ~loc]; pulse oscillator 260
The clock pulses from the oscillator 26 are appli~d as one
input to an AND circuit 35~ The other input to the AND
31 . ~ .
~2
~ ~ ~ Q 36 2
1 ¦ circuit is derived from the "set" output from the toggle 35T. . ..
21 When a clock pulse is applied to the input of the AND cir~uit .
31 35 at th time that the toggle 35T is in its i'set" state,
41 an output signal will be applied to the step input of the .
51 sequencer to advance it to the next successive: position.
61 Accordingly, when the toggle 35T is in the set state, the
71 sequencer will be sequentially advanced in response to the -
81 reception o~ each clock pulse at the AND gate 35. The set
91 input of the toggle 35T is controlled by an OR gating circui~
360 The OR circuit receives the overflow signal M5 from the
11 linear time to d~gital converter 12 in addition to a "retry"
12 signal~ It will be recalled that th~ control of the system .
13 is transferred from the linear time to digital converter 12 .
14 to the center bar locator 14 in response to the M5 signal. .
The output of the OR circuit 36 i~ coupled to the set input
16 o~ the toggle 35T as wellas to the Pl preset position f~r
17 the seguencerO :
18 The memory address control unit 14M of the center bar .
lg locator 14 utilizes and ~ime shares the address counter and
21 register 31 or the memory l3 utilized in the linear time to
digital converter 120 It is illustrated in ~ig. 3 as a ..
23 separate circuit element to simplify the explanation of the
invention~ The memory addr~ss register 31 has a "preset"
24 input ~or setting a desired address into the a~dress register .
26 3l as well a~ an "incrementing" input for sequentially .
27 incrementing the addresses stored in the registerO For the .
purposes o~ the present invention an address may be preset .
28 into the register 31 such as the "star~" address entered into.
the unit 37 and this "start~ ~dres~ is stored in the register
31 to commenc~ a read-out of the memory at that addres~ For
32 .
)36Z ` ~
1 this purpose, the numerical value of a desired address stored
2 in th unit 37 is coupled to an AND circuit 38 in conjunction
3 with the M5 signal (from unit 12~ for initiating the sequential
search in the memory for the center bar pattern location. The .
output circuit of the AND circuit 38 is coupled as one input
61 to the OR circuit 39 . The other input to th OR circuit 39 : .
7 is the output ~f the AND circuit 40 which receives the P13
8 signal from the sequencer in conjunction with the output
signal from the memory address register 31, The output signal
from the OR circuit 39 is coupled to a control network .
11 identified as a pxeset and next start address control unit 41. .
12 The output of the control unit 41 is applied as one input
13 signal to the AND circuit 42 in conjunction with the Pl signal .
14 from the sequencer~ The output aignal from the ~ND circuit
16 42 is in turn applied as one input to the OR circuit 43~ The
output signal from the OR circuit 43 is applied to the preset
~7 input for the address register 31 and thereby may sbore the
address entered at unit 37 in the regist~r~
19 To the right of the memory address register 31 there
illustrated a control network for ~ubtracting preselected
22 numexical values ~rom the address at which the address
regi~ter 31 is set~ This control natwork includes a unit 44
23 for storing a number to be subtracted from the address storçd .
in the address register 31~ As illustrated in Fig~ 3~ the .
subtrahend is identified as the nu~K~ 26 stored in the unit ~.
26 The output of the storage unit 44 is applied as one input
signal to the AND circuit 45 i~ conjunction with the P13 .
28 signal from the sequenceru The output signal from the AND
circuit 45 is applied as one input to ~he OR circuit 46
31
32 . ~ . .
lllU36Z ~ ~ -
¦ The other input to the OR circuit 46 is derived through the
21 control network havin~ a stora~e element 47 for storing other
¦ numerical values (such as the digit 2 illustrated in ~i.g. 3)
41 to be subtracted from the address stored in the register 31O
I The element 47 has an output signal coupled to an input circuit
61 for the AND circuit 48O An OR circuit 49 has its output
I signal coupled to the other input o~ the AND circuit 48~ The
9 input signal to the OR circuit 49 are deri~ed from the
; sequencer and are identi~ied a~ the two signals P6 and Pll~
: 10 The outpu o~ the AND circuit 48 is ooupled as the remaining
2 input to the OR circuit 46~ The output of the OR circuit 46
1 is coupled to the preset input for the subtrahend register SD.
13 The subtrahend register 50 will then store either the number .
stored in the unit 44 or the un:it 47 for further processin~
The nutput signal from the subtrahend register 40 is applied .
as one input signal to the sub~ractor 510 Th~ ~ther input
18 to the subtractor 51 is derived from ~.e output of the aadress
19 register 31. The numerical value of the address provided
from the address register 31 has thé value stored in the
21 subtrahend registsr 50subtracted therefrom and applied a~a
22 stored in a difference register 52. The signal derived from ¦ .
23 th2 difference register 52 is applied as one input signal to .
24 the ~ND circuit 53O The other input signal to the AN~
circuit 53 is derived from ~he output signal of the OR circuit
26 54O The two signals applied to the OR circuit 54 are derived
27 from the center bar locator sequencex 14S and are identified
28 as the two signals ~a and PlSo The vutput signal from the .
29 AND circuit 53 is applied as the remaining input signal to the
30 OR circuit 43 for presetting an addres~ into the memory .
31 . . .
32
1~1036Z 1
~¦ address register 31, i. e., 29-26 = 3.
2 The incrementing input of the memory address register 31
3 is controlled by the output signal from the OR circuit 55~
4 The OR circuit receives the S1~ S2 and S3 signals from the
center bar locator sequencer for se~uentially incrementing
6 the address ~tored in the address register 31~
7 The center bar ratio detector 14D is illustrated on the
~ left-hand ~ide of Fig. 3. The ratio detector 14D recei~es .
9 a signal representative of the logarit~m. of the desired ratio .
from the ratio computer 15~ The logarithmic signal is applied
11 and stored in a log ratio register 56. The numerical value .
~2 of the log ratio is utilized to address a conversion table
73 stored in a read only memory identified as the unit 57, .
14 further identified a~ the ROM E, The read only memory stores
the data from a table for converting the computed logarithmic
16 ratio to numerical value in the decimal number system or any
17 other convenient number system~ It will be assume~ that the .
18 conversion will be to the decimal number system for the
lg purposes of undex~tanding the pre~sent invention. Accordinglyt
21 the logarithmic ratio signals applied to the ROM-E, unit 57
representati~e of the ~ogarithm of the ratio is converted
22 to a numerical signal representative of the computed ratioO
23 The numeric value signal representative of the ratio that i~
24 read out of the read only memory ROM E is applied to a .
pair of AND circuits 58 and 59. The output signal from the .
unit 57 is applied to the AND circuit 59 as one input by means
28 of an inverter 60 while it is applied directly~ in an .
unmodified statet to the AND circuit 58~ ~he remaining input .
29 signal for each of the two input AND circuits 58 and 59 is .
31 the same P2 signal derived from the center bar locator se~uence: .
~2 I . .
l~t}36Z
~¦ oth ~utput signals fr~m the AND circuits sa and 59 are
2 ¦ applied to control a cycle counter 61. The output signal
31 from the AND circuit 58 is applied dixectly to the incrementi~g
4 ¦ input of the cycle counter 61~ The output signal from the
:G 51 AND circuit~ is applied as one input to the OR circuit 62.
6 ¦ The output of the OR circuit 62 is applied directly to a .
71 reset inpu~ or the cycle counter 6l. The remaining input .
8 signal applied to the OR circuit 62 is derive~ fxom the AND .
3 cixcuit 63~ The AND circuit 63 is controlled thr~ugh an OR
circuit 64 that is responsive to the Pl and P8 signals from .
11 the sequencer l45. In addition~ an even/odd bit signal
12 derived from a retry counter unit 14C is applied as the .
13 remaining input to the AND circuit 63.
14 The cycle counter 61 has its output applied to a cycle
counter decoding network 65 for ~ignalling the decimal value
16 of the count of the counter:6l. The output siynal of th2 .
18 network ~5 is applied as one inpu~ to ~he AND circuit 66 .
: in conjunction with the P4 signal from the s~quencer 14S.
The output signal from the AND circuit 66 ls applied directly .. to the P9 preset position of the center bar locator seque~cer
21 14S r a~ illustrated. .
22 The retry count~r 14C comprises a retry binary counter .
23 67 for counting the number of attempt.s the system makes to .
24 locate the center bar pattern in the memory and stores the
result~. The retry counter 67 is reset at its R input by
26 means of the M5 signal from the linear time to digital converte~ .
28 12. The incrementing input to the counter 67 is responsi~e
29 to the P3 signal from ~he center bar seque~cer 145~ The- .
even/odd ~ignal from counter 67 is applied to the AND gate
31 63 for controlling the cycle count2r 61; as discuss2d
~2 .~
I . .,
11.~36Z
1 ¦ hereinabove~ The count stored in the retry counter 67 is
2¦ applied directly to a retry decoding network 68 for decoding
31 the output signals from the counter 67 as the counter is
41 counted up~ The unit 6Ei is also responsi~e to the P5 signal
5¦ from the center bar l~cator sequencer 14So The unit 68 is
61 constructed and defined so that after 10 attempts to locate .
71 the center bar pattern in the memory 13 that after the tenth
8 attempt the xead is aborted andO accordingly, the output
. signal from the unit 68 is so identified~ This value is
selected since a valid symbol would exceed the memoryS 9i ,
11 capacityO
12 In considering the search for the position of the .
13 standard center bar pattern in t.he memory 13, it is initially .
14 assumed that in reading the label lO.that no transitions .
occurred before the guard bars provided.on the UPC sym~ol on .
16 the label 1~ so ! that,the center bar patternlwould be stored .
17 in the memory.l3iat ~ddresses.27r31... The first memory location
18 (~), al~aysi contains,the mqasu~em~nt; for a moaule that :
19 ix a bar anq there~4re! alll e~re~ .aldd,resses in, ~he memory
store bar measurements~ This storage arrangement is
22 illustrated in Fig.j 3A wher~in ~he ~,din~ m,odu~e of the center
23 bar pattern ~arç ~dentifie~,,a~ ,,B~IC~andlD a~Qng with th~
! . decoding ratio~ orldç,t,e~inin~ ~ y~ , ce~tje~ ~ar pat~ern. .
24 Accordinglyq ~hej~iearc,h,fo~ the ! positi~n,,ojf,~hejjcenterjbar ~
26 pattern inl~he mç~o~y;l,3 isi,al~ays,sta~e~,wit~lad~ress 27~j .
2 It will;bei ~a~rst~od,that if extr~neous da~a is,stored ! in ~ .
j7 the memoryll~ durinjy,a"sc~n, the memor~,p~sitions !will; be
2 displacçd~dj~jhe~in~tiallatte~,pt~ o loca~e, t~e pattern will
9 resultjin ~ailu~ "~his ~qrti~ re~ s,i~t~e~ in the
unit 37 for exa~i~ing thej da~a storedla~la~dr,e$s positions
31 . .
32
, ! ! I ' I ~ I . i I I .
! , i i, , I, . ~ ! l .
lllU3a~
1¦ 27 ~ 31 f~r determining if the known center bar width ratio~
21 are satisfied by the stored data for positively locating the
31 position of the center bar pattern in the memoxy 13~ A valid
41 center bar pattern will be located if both of the ratios
6~ ~ ~ ~ B) and ~D ~ C ~ompute to one~
8~ TA~LE II
-Sequence Func-tion . .
~1 ~oad start address to memory address
reoister 31
Sl Load thé ~ register and increment the - .
11 memory address register.31
S2 Load the B register and increment the
12 memory address register 31
13 S3 Load the C register and increment ~he .
14 memory address register 31
S4 - Load the D register
16 S5 Select and add the contents of register A
7 to the contents of ~egister B
1 S6 Load the log (A ~ B) into register E
18 S7 Select and add the contents of re~ister C
19 to the contents of register D
S8 - Load the log (C ~ D) in~o register F .
21 S9 Subtr~ct the contents o~ register F from
22 thè contents of register E
P2 Increment the cycle counter 61 if the
23 resulting log is one; if log is no~ one~
-24 reset counter 61
P3 Increment retry counter 67
P4 If cycle counter 61 signals two~ jump to
26 sequence P9
27 P5 If retry counter 67 signals ten~ abort the
28 the read
P6 Load subtrahend register 50 with the
29 numeral two : .
P7 Subtract the contents of the subtrahend
register 50 from the contents of the
31 memory address register 31 .
~1 ~llQ362 ~
1 TABLE II (continued)
Z Sequence Function
3 P8 Load the contents of the dif~erence
4 register 52 into the memory address
register 31; reset cycle counter 61 if
the retry counter 67 signals an ~evenn
bit; jump to step Sl .
6 P9 Select and add the con~ents of register B
7 to the contents of register C .
8 P10 Load the log (B ~ C) into register E
P11 Select and add the contents of register D
to the contents of register E; load the
10 I subtrahend register 50 with the numeral two
11 ¦ P12 Load the log (D ~ E) into register F; .
I su~tract the contents of the subtrahend
12 ¦ ~ register 50 from the contents of ~he
. I memory address register.31
13 P13 Subtract the contents of register F from the
14 contents of register E: load the ~ubtrahend
register 50 with the number 26
P14 Load correction value register 100 (Fig. 5);
16 subtract the contents of subtrahend register
50 from the content~ of the memory:adares~
17 register 31 :
18 P15 Load the content~ of the dîfference regi~er
52 into the memory address regis~er 31;
19 jump to the decoder 16
Table II delineates the step-by-step sequence to be followed
21 for locating the center bar pattern in the memory. .
22 ~he basic sequence of events khat occur in ~ear~hing ~he
23 memory 13 for the corre~t addresses of the stored center bar
24 data is that at step Pl~ starting with memory address 27, th~
values for the modules A~ B, C and D are read out of the
2~ memory 13. The first ratio~ ~C + ~- -) is computed in the ratio
27 computer 15 and further processed through the center bar ratio .
28 detector 14D. If it is determined that this ratio is one, the .
29 cycle counter 61 will be incremented at P2 time~ At the P3 :
time~ the retry ~ounter 67 i~ incremented to record that a
31 . 29 . .
36Z
1¦ ¦ decode attempt is completed. The next sequence is that the
21 ¦ information stored in the memory 13, beginning with address
3 ¦ 28 through address 31, the new set of data representing the
4 ¦ modules A~ B~ C and D ~re read out o~ the memory 13~ ~his .
5 ¦ results by modifying the start address thrc~ugh sequential step~
61 P6 to P8 and then retrieving the data and computing the ratio .
71 through steps P9 through P13. .
8¦ TABLE III
l .
9 ¦ 5eguence Memory Address Cycle Counter 61 Retry Counter 67
1~1 Pl ~7
12 1Sl 28 . O O
S2 29 0 0
~31 ~;3 / 30 O O
14 S~4 , 30 ~1 0 .
~ 30 0 0 .
16 P2 30 1 0
P~3 30 1 1
18 ~ 30 1 1
P8 2~ 1 ~ -
Sl 2~ ~ 1
21 S2 30 1 1 .
22 S3 31 1
23 S4 31 1 1
24 ~ 31 '1 1
26 P2 31 2 1
P3 31 2 ~ .
27 P4 31 2 2
28 P9 31 2 ~
29 ~ 31 2 2
31 l12 29 2 2 .
P13 29 2 2
~Z ~14 03 2 2 .
1110362
~¦ Table IIIrelates the memory addresses of ~he register 31 to
2 ¦ Table II and indicates the counts of the cycle counter 61 and
31 the retry counter 67 during the sequence of operations detailed
4¦ in Table II when the center bar pattern is located in the
51 memory on the irst attempt.
6 With this new data 7 ~he ratio( ~ + C)is computed and if it
7 is determined that this ratio is onep the cycle counter 61
8 is incrementedD In addition, the retry counter 67 is a~ain :
9 incremented~ The cycle counter 61 now should siynal the count 2
and the decode network will b~ signalling the decimal di~it tw~o
11 This state of condition~ will be recognized at P4 time so that
12 the signal from the AND gate 66 will preset the position of .
13 the sequencer to P9~ At P9 time~ the recording or printing
14 ~orrectio~ character i~ computed a5 will be explained hereinafte~ .
15 The above description of the operation o~ the center bar
16 locator 14 as~umes that only two successi~re trys were required :
18 to locate t~e center bar pattern in the initially identiPie~
address positions 27-31~, If eith~er of the above attempts at
19 locating the center bar position did not 3?rc~duce a ratio o~
21 one, the search muslt be repeated un~il two successive ratios of
22 unity are detected. During each of these attempts the retry .
23 counter 67 is inc!remented and if the num~er o~ attempts reach~s .
24 10, as illustrated in ~ig. 3~ it is assumed that the valid .
label would exceed the capacity of the memory 13 and accordingly
26 the read is aborted. In addition ~ it should be noted that if
27 the cycle counter 61 has not been counted up to 2, and the .
28 retry counter 67 produces an "even'l output signal at AND gate .
29 63, the cycle counter 61 will be rese~ a~ P8 time by ~he signal .
31 from the OR circuit 62~ Thi~ assures that two successive ratios
~2 .
,, 31
, ; "
~ )362 ; I
1 of unity always begin with a ~pace, a requirer:ent for satisfying
2 the conditions for detecting a valid center bar pattern. .
3 At this point, in the detailed step-by-step operation of the
4 center bar locator 14 for locating the position in memory of .
the center bar infQrmation as represented in Table II, it should
6 be recognized that the steps identified as steps Sl - 59 and .
7 P9 - P13 are performed in the ratio computer 15. These steps
8 derive the information in the address positions of the memory
9¦ 13 having the modules A, B~ C; D and E stored therein and compute
~1 the logarithmic ratio signal to be applied to the log register .
11¦ 56 of the center bar ratio detector 14D~ These sequencing .
12¦ opexations will be described in conjunction with the operation .
~31 f the ratio computer 15. .
~41 Table III records the counts in the cycle counter 61 and the .
16 xetry counter 67 during the center bar locating ~rocedures .
when the center bar pattern is identified on the first attempt.
17 Thi~ tablé corresponds to the detailed operation of the sequencer .
18 as represented in Tabl~ In following through the step-by-~te~ .
19 sequence represented in Table IX, it will be nQted that there . .
21 is a correspondence between the operations delineated in
22 Table II and the values represented in Table III~ It should be .
23 noted that in seguence P6 of Table II that the subtra~hend
24 register 50 is loaded with the decimal digit 2 fr~m th2 unit 47~
This value is subtracted from the address of the memory position
2~ from which the la~t piece of information is derived~ It will
27 be recalled that in following the steps for deriving the value .
28 for A~ B, C~ and D from the memory 13 that at the S4 sequence .
29 time the last memory position interrogated was number 30.
30 Accordingly~ when the numeral 2 is subtracted ~rom the memory
31 position 30 at sequence P8 timer the memory aadress ide~tified
~2 . . ..
lllQ36Z : 1
1¦ is 28 which corresponds to that indic~ted in Table III.
21 Address 28 then identifies ~he staxting address for the second
31 cycle in the first attempt for identifying the ce~ter bar
41 pattern and the information is derived from addresses 28-310
51 This information is derived throu~h the sequence of steps pg .
~¦ through P12 r as identified in Table II~ corresponding to
71 sequences P8, Sl-S3 in Table III. After this interval at
8 sequence P13, the numeral 26 stored in unit 44 is entered into
. the subtrahend register 50. At the P14.se~uence~ the numeral
26 is subtracted from the memory address at which the memory
11 is pointing~ namely 29~ so that the new memory address stored .
12 in the register 31 is directed to memory pos;.tion 3 at sequence
13 P14; see Table III. This number 30 o* course~ is the memory
14 position in ~hich the A module ~or the ~irst character to be .
decoded resides~ After this memory position is identified at
16 se~uence P15, see ~able II, the control o~ the system is
17 transfer~ed to the character decoder 160 The character decoder .
18 1~ will s~art to decode the ~tored data beginniny with memoxy
19 position 3 and sequentially forward.
~0 It should be noted that the contents of ~he center bar ratio
1 read only memory 57 is as represented in Fig. 3B. The logarithm l,
22 of the ratio stored in this ROM E are pexmitted to be the value
23 minus ly 0 or plus 1 to allow for any quantization error~ This
24 ROM E is utilized to convext the logarithm ratio si~nal applied ,l
thereto to the decimal number of the ratio~ As defined and
26 recorded in Fig. 3A9 the resulting ratio output ~i~nals represent
27 a ratio of one or a ratio other than oneO .
2~ To complete the understanding of the center bar pattern
2~ search in the memory~ Table~ IV~ V~ and VI are included for
relating the memory addresse~ of the register 31 and counts of
31
~2 . . .
111(~362 -~
1 the cycle counter 61 and retry countex 67 when the center bar .
2 pattern is not located in ~he memory 13 on the first attempt.
3 .
4 TABIæ TV
Sequence lem_y Address C~cle Cou~ter 61 Ret~y Counter 67 .
6 Retry 2 2 .
7 Pl ~9 0 2
Sl 30 ~ 2
SZ 31 0 2
S3 32 0
11)
. S~ 32 0 2
1~ ~ , ..
~2 ~ 32 0 2
~3 P~ / 32 ~ 2
14 P3 l ~2 1 3
~5 ~ ~ 3~ 1 3 .
P~ 30 1 3
~7 Sl 31 1 .3
18 S2 32 1 . 3
S3 33 l 3
19 l
~ 33 1 3
2i P2 33 2 3
22 T 33 2 4
23 ~ 33 2
24 P12 31 2 ~
P13 31 2 4 .
2~ P14 05. 2 ~ .
27 ~able IV relates the register 31 values of a first retry after
28 a decoding failureO This new attempt commence~ with address
29 position 29 in memory and follows the same sequence as noted
30 in Table II~ The counts of the counters 61 and 67 at the
31 . .
32
commencement of the "retry'` procedure are both at count 2. At
Pl time the cycle counter is reset to zero as a result of the
signals applied to the AND gate 63. the Pl signal provides an
output signal from the OR gate 64 to the AND gate 63 along with
the even bit (2) signal from the retry counter 67. The sequence
of operations then commence with the data retrieved from address
positions 2~ through 32 in accordance with the sequential
operations of Table II. The cycle counter 61 is counted up at
P2 time to one during the first search cycle and again at
P2 time during the second cycle. At P3 time during the first
cycle, the retry counter 67 is counted up to three and again
at P3 time during the second cycle to four. As noted hereinabove,
at P12 time two is subtracted from the address register 31
position and after P13 time, twenty-six has ~een subtracted.
Accordingly, the address register 31 is pointing to address 5
for commencing the next decoding attempt at P14 time.
- 35 -
. .-
: ~. .. ,,, . : ,
. . . : . :
- .: . : . . ,
~Q36Z
TABLE V
Sequence Memory Address Cycle Counter 61 Retry Counter 67
Pl 27 a o
Sl 28 0 0
S2 29 0 o
3 30 a o
~ 3a o o
: P2 30 ~ ~ 0 ~ 0
P3 30 0
I
~ 30~ 0
P8 28 : 0
Sl 2~ 0
S2 3Q ~0
S3 31 0
lS I 31 0
P2 31
P3 31 l 2
1 l 2
P8 ~2 a 2
3Q - 35a -
~ ~ 3~Z
1¦ Table V represents the addre~s values of register 31 if
21 during the first attempt, the first cycle results in a center bas
3 pattern thatis not one, ~ut is one :in the second cycle~ Thi~
4 table then corresponds to Table III with the aforementioned
5 exceptio~0 The cycle counter 61 will only be counted up to
6 one at P2 time during the second cycle of the new attempt.
8 By referring to Table II, it will be noted that at ~8 time the
cycle counter 61 will be reset if the retry counter 67 provides .
9 an even bit signal to AND gate 630 Since this i~ true under
these conditions, the counter 61 is reset at P8 time to zeroO
11 Since a valid center bar pattern has not been located in memory,
12 the sequence commences with sequence ~1, see Tabl~ IIo Th~ ;
13 ~earch for a valid center bar pattern will now commence at
14 memory address 29 and retry counter at 2.
16 . TABLE VI :
Sequence MemorY ~dres~ C~cle ~o~nter 61 Retry Counter 67
_ . _ ~ . . . . _ ,
17 Pl ~7 o o
18 Sl 28 0 0
19 S2 29 0 0
20 S3 3~ 0 0
21 1 ~ 0 ~
22
~3 P2 30 1 0
P3 30
24 .
25 ~ 3~ 1 1
P8 ~8 1 ~
26 S~ 2~ 1
28 S2 30
2g 13 31 ~ 1
30 ~ 3~ 1 1
31 P2 31 0 1
~2 03 31 0 2
r 31 ~ 2
P8 29 0 2
.' ,,3~ .
. ~ 1~1036Z
1 Table VI represents the values of the address register ..
2 similar to Table V except the inverse relationship of the cycles,
3 Table VI represents the address locatioDs when an attempt for .
4 locating a valid center bar pattern results in a one during ~he
51 first cycle~ but not during the second cycleO During these
6 assumed conditions, the cycle counter 6l will be counted up
7 at P2 time during the first cycle only. As noted in Table I~
8 duri~g the second cycle at P2, the cycle counter is reset to
9 zero. A~ter completing thi~ at~empt, the search is repeated
starting at memory location 29 and the retry counter registering
1~ two. ,
12 Now referring to Table II~ once again, it will be noted that
13 i~ a valid center bar pattern has been located in memory at -
14 P4 time9 that the sequence skips to P9 timeO At P9 tImey the
recording or printing tolerance co:rrection character computations . 1
16 commenceO The sequencer l4S is preset to P9 since at P4 time . ,1
17 an output ~ignal is applied to the sequencer from AND gate 66.
18 This signal results due to the decoding network 65 applying a . .,
19 l'twol' signal to the AND gate 66 which is read out at P4 time~ .
20 At P9 time,thenj the correction computation commences on :
27 the basis of the width measurement stored at the address position ~ J
22 denoted for step Sl in accordance with the location resulting ; I ,
23 i~ the valid search. If this occurs on the first attempt) .
24 the addres~ location is 27~ ~or example~ The computations
26 continue during steps PlO through Pl2 for the module~ B~ C and
27 D. These computations are performed in the ratio computer 15
and will be described in conjunction therewith. The resulting
28 character correction value is stored in the correction ~alue :
29 register lO0 of the character decoder l6 to be utilized .
30 during the decoding procedures to be described. .
3~1 .
32~ . ..
l 37 . ,~
~ 3~2
1 Now reerring to Fig. 4, the general organization of the
2 ratio computer 15 will be examined~ The ratio computer 15 i5
3 utilized in conjunction with both the center bar locator 14
4 and the character decoder 160 The ratio computer 15 is operative
on the data read out of the memory 13 for providing the necessary
6 ratio computations and providing an output signal that is the
7 logarithmn of the desired ratio to be used in either the center
8 bar locato~ 14 or the character deooder 16. The data that is read
9 out of the memory 13 and processed in the ratio computer 15
are width measurements representing the measured values for the,
11 modules A, B~ C and D of a characterO This A~ B~ C and D .
12 data is read out of the memory 13 and stored in individual .
13 storage registers A~ B~ C and D in the ratio computer 15. The..
14 data module that a register stores is identified in terms t:>~E
the data read out from the registerO Accordingly~ ~he A module
1~ measurement is stored in the A register~ and the B module
17 measurement in the B registerO .The C moau~e measurement is .
18 stored in the C register and the D module measurement in the
1g D registeru Each of the registers A7 B~ C and D have their .
21 inputs controlled by an individual AND circuit identified as ~
22 AND circuits 70, 71~ 72 and 73 respectively and are arranged , .
23 left to .right in FigO 4~ The data ~rom the memory 13 is `
24 coupled in parallel circuit relationship to each of the ~ND
circuits 70 73 as one input to each of these AND circuitsO ~he
AND circuit 70 is activated to store the A module measurement
26 by means of the signal Sl from the center bar sequencer 14S. .
Similarly~ the signals S2~ 53 and S4 individually activate
28 the respective AND gates 710 72 and 730
29 The output circuits for the registers A - D are controlled
31 by means of one or two AND gatesO The A register output circuit
32 `. ,,
:. ~
3~
1~1(1362
1 is controlled by means of the single two input AND gate 74,
2 while the output circuit from the B register is controlled by
3 means of two, two input AND gates 75 and 76. The output from
4 the C register is controlled by a single AND gate 77~ whi~e
5 the D register is controlled by means of a pair of AND gates .
6 78 and 79. The second inpu~ to the AND gate 74 coupled to the
7 A register is the output signal provided from the OR gate 80e
8 The OR gate 80 ~s responsive to the input signals S5 f Sllo S17A
9 and P9 which provlde an output signal from the OR circuit 80
for reading out the data stored in the A register for further .: .
11 processing in the computer 15. Similarly~ an OR gate 81
12 controls one of the input signals to the AND gate 75 for the
13 B registerO The OR ~ate 81 is responsive to the sequencing
14 signals S13t S19B and Pll~ The output signals from the B
register are applied in parallel circuit relationship as one .
16 input to both AND gates 75 and 76. The second input tG the
17 AND gate 76 is the S5 signal from the sequencer 14S. An OR
18 gate 82 provides one of the input ~ignals for the AND gate 77
19 for reading out the information out of the C registerO The OR
gate 82 is responsiYe to the sequencer signals ~77 S13r S17C
21 and P9O The seguencer signal S7 controls the transfer of the . .
23 D register data through the ~ND gate 78. The D register data
is coupled in parallel to bo~h of the AND gates 78 a~d 79. A~ .
24 OR circuit ~3 controls the input signal to the second input to
the AND gate 79O The OR gate 83 ls responsive to the sequencer
2~ signal~ Slly S19D and Pll, The data stored in the registers
~8 A~ B, C and D (and the memory 13) is not aestroyed since a
number of attempts may be required to decode the recorded
2 symbolO The raw measurement data stored in the registers are .
merely read out for processing in the ratio computer 15u The :~
31 data ~tored in the registers Ar B~ C and D is applied to a .
~2 .
. . .
3~2
two input binary adder 84. One of the inputs to the adder 84
is controlled by an OR gate 85 and the other by an OR gate 86.
The OR gate 85 is responsive to the output signals from the
AND circuits 74, 75 and 78. The OR gate 86 is responsive to
the output signals from the AND circuits 76, 77 and 79. The
output signals from the adder 84 represent the linear sum of
the width measurements of the two modules applied thereto or
the sum of the signals presented to it by means of the OR gates
85 and 86.
The signal derived from the adder 84 is utilized to address
a table stored in a read only memory identlfied as ROM A in
Fig. 4. The data stored in ROM A is a conversion table that
converts the linear sum signals to a binary coded decimal number
that is the logarithmic value of the sum signal/ A method for
selecting the base for the logarithms is disclosed in U~S. Patent
Mo. 4,058,708 and assigned to the same assignee as the present
application. The sum signal is utilized as the address signal
for reading out ROM A in accordance therewith. The signals read
out of the ROM A are stores in a log register 87 coupled to
receive the binary coded output signals from ROM A. The
register 87 has an 8-bit capacity and is illustrated in Fig. 4 as
having a left and right half, each storing four bits. The right
half of the register stores the binary bits 2 through 23,
while the left half stores the binary bits 24 through 27.
- 40 -
362
. . .
. . .. :
1 TABLE VII
...... .
. Register 87
Left R<ight
3 ROM A: Address 4 Bits4 ~its . ~
. . !
4 7 F~ ~ . I I
8 1 0 1-
6 ~-10 2 1 ~
7 1~-12 3 2 ;
8 13 4 2 .
:~ 9 - 14 4 3
~0 15-16 5 3 i
11 17 5,
12 18-20 ~ ~
13 21-24 7 5 i
~14 25 8 5
26-29 IB 6
16 30-31 9 6
32-3~1 9 7
18 35~3~ 10 7
19 39_40 10 ~ l
2t) ~1~48 11 8 i
21 ' 49~~;7 ~ 12 9 ~ ~
22 5 8 5 9 1 3 9 r
23 60-68 13 lC~
24 69-7~ ~ 14 10 j
75-80 1~ L;L
26 81-92 15 11
28 g3~95 15 12 ;
29 96-113 )iY 12
114-L15 1 ~2
31
32
.. . -~- 1'
3fJZ
1~ T~LE VII Icontin~ed~ ¦
2 R@igi~Bte~ ~7
~e~t Right
3 ~OM ~ ~ddress 4 Bits 4 Bits .
,..... ,
4 11~-135 1 13
~ ~36-143 ~ ~3
6 14~-~60 2 . 1~ .
~ 161-17g 3 ~4 :
8 180-190 3 ~5 . .
9 191-2~3 4 15 .
~24-225 ~ O . .
11 226-255 5 0 .
12 It will be recalled that the minimum linear value selected : ~
fQr ~he counter 28 was seven and therefore values below seven
14 need not ~e considered in Table VI~O The logarithmic values
represented in Table VII are ar~itrarily initiated at ~ero and : .
16 re~tart with zer~ after the value of lS is reached~ ~hen the .
~71 correction character is calculate~, the ratios A~B or CJD ar~
1B ~ computed as ~) and ~).
~20 The output ~ignals from the two portions o~ the logarithmi : l,
21¦ register 87 are controlled for further processing through the ,
22 pair of AND gates 88 and 89. The 1 t-hand portion of the . .
23 regi~t~r 87 has its output signals applied as an input to the .
24 AND gate 88~ while the right-hand poxtlon of th0 registex 87 :
25 has its output signals applied as an input signal to ~h~ AND ¦
26 gate 890 The four bits comprising the input s;.gnals to the AND. ,
27 gates 88 and 89 represent the decimal value~ recorde~ in
28 Table VII. ~n OR gate 90 controlc the second i~p~t tG the AND
29 gate 880 The OR gate ~0 is respon~ive to th2 signals from the /
sequencer 145 identified as S6, S8, S12, S14, S18 and S20.
31 , .
32 . ,
42
, /;,,
. ,.......... ,, . . . ,,, ,., ,". , ... :
1~L1(~36Z
1 Similarly, an OR gate 91 controls the other input to the AND .
2 gate 89. The OR gate 91 is xesponsive to the sPquencer signal
3 P10 and P12. An OR gate 92 contrsls the application of the
4 output signals from the ~ND gates 88 and 89 and is coupled ..
51 thereto. The output signal from the OR gate 92 is coupled to .
6 a pair of AND gates 93 and 94 in parallel circuit relationship.
71 The other input to the AND gate 93 is controlled by means of
8 an OR circuit 95.. The OR circuit 95 is responsive to t~e
9 sequencer signals S6, S12, S18 ~nd P10. An OR gate 96 contro1s
the other input to the AND circuit 94O The OR gate 96 is
11 responsive to the slgnals S80 S14J S20 and P12~ The AND
12 circuits 93 and 94 control the data that i5 entered into the
13 individual log registers E and F~ respectively~ Each of the
1 registers E and F are 4-bit registers for storing values of
the logarithms of the s~ms of the measured widths r such as the
16 logaxithm of the sum A + B~ for example~ The regi~ters E and F~
17 each have their output circuits coupled for transferring their.
18 contents to a subtractor 97. The subtracter 97 ~ubtracts the
19 logarithm of the two sums stored in the registers E and FD .
the register F value is subtracted from the register E value, ¦
21 and provid~s an output ig~al that is the log of the desired :
22 ratio signal. The subtracter 97 is enabled under the control .
23 of an OR gate 98~ The OR gate 98 is responsive to the
24 sequencex signal~ S9 r S15 r 521 and P13~ The signal from the
subtxacter 97 is coupled to the center bar locator 14 or to the:
26 character decoaer 16 in accordance with the use made of the
ratio computer 15.
28 With the above ~tructure of the ratio computer 15 in mind~:.
29 the operation of the ratio ~omputer will now be further examined.
.-.
31 . . .
32 43 .
~11036Z ~ ~
1 The information from the memory 13 representing the modules ;
2 A, B, C and D are entered into the corresponding module registers
3 in response to the generation of the sequencing signals Sl, S2, .
S3 and S4 as delineated in Table XI hereinabove. Once all of
5 the A, B, C and D data is entered into the registersO the :. .
6 sequencing continues as indicated in Table II 50 ~hat the A
7 data and the B data are appli~d to the adder 84 to obtain the
8 linear sum of these measured widthsu This results due tv the
9 generation of the sequence signal SS appearing as an input to
10 the OR gate 80 ~or reading out the A register through the .
11 ~ND gate 74 and the ~R gate 85. The same sequencing signal S5 :
12 transfers the B register data through the AND gate 76 and the
OR gate 86 to the adder 84~ The linear sum deriv~d from the
14 adder 84 addresses the ROM A to read ~ut the logarithmic value
of the sum and which sum i~ stored in the register 870 As
16 noted in Table II~ this data is txansferred into the E registex
17 upon the generation of the S6 sequencing signalO The 56
18 se~uencin~ signal provides an input signal to the AND ~ate 88
for transferring the da~a from the left half of the register 87
21 through the OR gate 92 and the AND gate 93 to the E register. ; .
22 It will be noted that the AND gate 93 is responsi~e to the .
23 output signal from the OR gate 92 in co~bination with the .
output signal from the OR gate 95 which latter gate produces .
25 the output signal in response to the reception of the S6 :
26 signal at its input.
27 The next sequence as noted in Table II is the generation .
28 of the S-7 signal and that signal is effective through OR gate .
29 820 AND gate 77 and OR gate B6 to apply the 'IC" data to the .
31 adder 84. At the same time~ the S7 signal transfers $he D data .
~ . ' . ',,
44 .`
V3~Z
~ -.
1~ from the D registex to the AND circuit 78 and the OR circuit 86
21 to the other input to the adder 84. In the same ~ashion this
31 data is transferred from the adder 84 by means of the ROM A and
41 the logarithmic register 87 to the ~ regis~erO The S8 sequence .
51 signal, as noted in Table II~ will transfer the logarithmic
61 value of the sum of the C and D data ~y means of the AND gate 88t .
71 the OR gate 92 and the AND gate 940 This results from the .
81 coupling of the S~ signal to ~he OR gate 90 and the OR gate 96 :
91 for activating the AND gates 88 and 940 Accordingly, at S9 .
10¦ time in the sequencing operation9 the subtracter 97 is activated ¦ . .
11 to subtract the data in the ~ register fro~ that in the E :
12 register to provide the desired log of ratio slgnal from the ¦ :
13 subtracter 97. ¦ .
14 Now referring to FigO 5 ~ the g~eneral organization of the ¦ ;
character-decoder 16 will ~e examined. The character decoder 16 :
16 as mentioned hereinabove operates in conjunc~ion with the ...
17 ratio computer 15 and rece~.ve~ the output signal from the ratio
18 computer which is the logarithmn of the ratio computed and is .;
19 stored in the ~og ratio register lOl for the character decoder ¦
20 16. It will be recalled that during t~e operation of the : ,
22 ratio computer lS in locating ~he center bar pattern that the .
23 printing error correction value was al~o calculated and :
transferred to the character decoderO. It will be assumed that
24 this value is stored i~ the correction value register lOO for :
the decoder 16. The correction value registex lOO has the
26 correction value entered therein under the control of the ~ND :;
2 gate 102. ~he AND gate controls the input to the register lOO s
28 and has its input connected to the output of the log ratio
register lOl and the signal Pl4 ~rom the center bar locator
31 sequencer 145 illustrated in Fig~ 3. ..
3~ .
~' .
I lllU3~
I ...
I ..
~ T BLE VIII
1 ¦ Se~uence Function
_ .
2 ¦ Sl Load the A register and increment the memory
31 address in register 31
¦ S2 Load the B register and increment the memory . .
41 addrPss in register 31
51 S3 Load the C regîster and increment the memory
~¦ address in register 31 :
l S4 Load the D register and increment the memory
71 address in registar 31
8¦ S5 Select and add the contentæ of register A to th~
9¦ contents of xegister B with adder 84
10 . S6 Load the log 5A ~ B~ i~to registex E
S7 Select and add the contents of register C to
11 the contents of regi~er D with adder 84
12 S8 Load the log (C + D~ into register F
13 S9 Subtract the contents of register F from th2
14 contents of register E with subtracter 97 .
S10 Translate log ç- ~ D with ROM B and load the : .
result into reglster Rl .. .
16 Sll Select and add thle conten~s of register A to .
17 the contents of register D with adder 84 .
18 S12 Load log (A + D) into register E v
19 S13 Select and add the contents of register B to
the contents of regist~r C .
S14 Load log (B + C) into register F :
1 S15 Subtract the contents of register F from th~
22 contents of register E with subtracter 97 .
23 S16 Translate log ~ + C with ROM B and load the i
24 result into register R2
S17 Select the contents of the A register (Fig. 4) t .
if the Rl regi~ter i~ 1 select the contents of .
26 the C register (Fig~ 4) i the Rl register i~ 2
S18 Load the value of log (A or C) into the E . .
27 register (Fiy. 4)
28 Sl9 Select the contents of the B register (Fig~ 4)iP.
Rl equals 1 t select the contents of the D regist~ r
29 (Fig. 4) if Rl equals 2
S20 Load the value of log (B or D3 into the F regist~
31 S21 Subtract the contents of the F register from th~
~2 contents of the E register by subtracter 97
S22 Combine the tolerance correction value to log
~B or CD by adder 108 or subtractor 112
?36Z
l .~
1 TABLE VIII (continued)
2 Se~uence Function
3 S23 Transmit the decoded character to validity checX4 element 17 .
S24 Incremenlt the character counter 123 and restart
6 the sequence .
8 . .:
12 i . . . . ,.
14 .
16 ~ .
18 . - ~ :
~ o l~ ,
21 ~ :
23
'~
~2 . .
46~
"
~ 36~
1 The table stored in ROM A comprehends the charactex
2 correction resulting from printing the. UPC sy~bol on a label .
3 or the like. Acrordingly~ the corxection value is calculated
4 in the ratio computer 15 after a valid cen~ex bar pattern is
5 located and prior to decoding the characters of the symbol. .
6 The correction ~lue is stored in the register 100 of the .
7 character decodar 16. .
8 The correction value is computed in accordance with the
9 present invention by examining the standard pattern hc.ving the .
10 known 1:1 ratio as to bars and spaces~ For the purposes o~ .
11 decoding the UPC standard symbol the standard pattern that is . .
12 examined is the center bar pattern widthso The correction ' .
13 value i~ obtainea by measuring the actual or printed ratio -` .
14 of the cen~er pattern bars and spacesO The ratio has been : .
selected to include two bars and two spaces for minimizing the ;
16 effects of local printing irregularities r In the standard . .
17 UPC symbol r the ratio is dafined by the two center bars over
18 the two center spaces, or the ratio ~ + C ~ For a nominal . .
19 symbol these ratios w~ll be oneO ~or an over-p~inted symbo~ .
21 or label they will be greater than one and for an under-printed .
22 label they will be less than one~ Stated differently, the
23 ratio is defined by the widths of two dark bars over the widths
of two light barsO Since the known ratio~ or the width of a .
24 bar and space should be the same~ any resulting ratio other .
than one will réquire a correction value to be combined with :.
26 the stored~ measured values of the modules A~ B, C and ~O
28 The correction computation in the ~equence of events :
colTmences at P9 time by the reading out of the data for the
o center bars from register~ A and C. ~hese width measuremen~;¦
~2 47 ~
36Z ~
1 are read out at P9 time by ~he P9 signal appearing at OR gate .
2 80 and OR gate 82. They are applied to adder 84 through AND :'
3 gate 74 and OR gate 85 and AND gate 77 and OR gate 86
4 respectively. The logarithmn of the resulting sum is read out .
5 of ROM A and stored in register 87~ At P10 time, the register
6 87 has its contents trans~erred to the E register. This .
7 resulks from the signal P10 applied to the OR gates 91 and 95 :
8 which correspondingly activate AND gates 890 OR gate 92 and :
9 AND gate 93. Similarly~ the B and D registers are read out at
Pll $ime in the sequence. These width measurements are coupled
11 to the input of adder 84 as a result of the Pll signal being .
12 coupled to the OR gate 81 and the OR gate 83~ At P12 time9
13 the log of the sum signal is transferred from register 87 to
14 the ~ registerO Thi~ results rom the coupling of the P12
signal to OR gate 91 and OR gate 96. At P13 time~ the -.
16 subtracter 97 is enabled as a result of the P13 signal bein~ '
17 coupled to the OR gate 98~ The resulting logarithm of the .
18 correction signal is loaded into the correction value register
19 100 for the decoder 16 to be utilized for decoding by means oiE
the aforementioned secondary ratiosO
21 It shoula now be noted that the decode sequencer 14S
22 illustrated in Fig. 5 is ~he same sequencer that is illustrated
23 in FigO 3 solely for the purpose of the center bar locator .
24 14 and is merely duplicated in Fig. 5 to simpli~y the
2~ consideration o~ the operation of the aecoder 16. It will be
6 recognized by those s~illed in the art that the sequencar coul~
27 be time shared in a decoaing system~
29 The log ratio register 101 output signals are applied ?
to a primary ratio read only memory identified as the RO~ B
3Z . "
' '.'
..
111036Z ~
1 ¦ in Fi~. 5. This ROM B stores a table for converting the
2 ¦ logarithmic value of the ratios for the primary ratios generated
. 3 ¦ during the decoding process or to a numerical ~ve representa~ive
4 ¦ of one of the primaxy ratios 4/3, 5/20 2/5 or 3/4.
5 ¦ T~BLE IX :
6 ¦ Address ~u~put DataData Ratio Value
7 ¦ ~ 4 (Error)
8 ¦ 1-3 ~ 2 Ratio = 4/3
91 4-8 3 Ratio = 5/2
10¦ 9~12 0 Ratio = 2/5
11¦ 13-15 1 Ratio = 3/4
12 ¦ Table IX relates the addresses of the ROM B to the output data .
13 ¦ for representing the primary ratios as indicated~ It should
14 be noted tha~ when the output data of the ROM B is "2" the .
primary ratio is 4/3 and when the output data is ~'1" the
16 primary ratio is 3/4,
17 The output data derived from ROM B is applied in a parallel
18 ~ircuit relationship to a pair of AND circuits 103 and 104~
19 The AND circuit 103 is effecti~e for transferring the ROM B
output data therethr~ugh in response to the S10 signal from th2
22 sequencer 14S~ For this purpose~ the output from the AND
circuit 103 couples this data into the Rl register ~or storing
23 ~he first primary ratioO Similarly, the AND circuit 104 is
controlled by means of the signal S16 to transfer the ~OM B outp t
data to the R2 register~ The R2 register will stoxe the second
25 primary decodin~ ratio~ The output circuits from the AND .
27 cixcuits 103 and 104 are also applied to an OR circuit l05 for.
28 controlling a decoding circuit 106. The decoding circuit 10~ .
29 indicates an error when a primary ratio data ~ignal from ~OM B
is 4~ as noted in Table IX~
31 . . .
~2 . .
~ lllU36Z
7~ The output slgnals ~ the registers Rl and R2 are coupled
21 to a ratio to binary coded decimal ROM C. The data output
31 signal o~ registex Rl is applied to the b2 and b3 ~its of ROM C,
41 while the output signal of the R2 register is applied as the
6~ bo and bl bits of the ROM C~ ';z
71 TABLE ~
81 Secondary Ratio ~0. - 0. (.1/.2) .Secondary Ratio b.~ ) .
l ! - Rl R2 ~ ' Rl R2 ~~ t
9¦ iAddress Value Value Data F/~ Bit IAddress Value Value Data F/R B~
101 0 ~ ~ 3 1 ` . 16 0 ~ 3 1. 1'
~1 1 ~ 1 4 ~ ' , 17 , ~ 1 4 0'1,
12l ~ 2 ~ 2 0 1 1~ 0 ~ 0 1 '
~3 3 ~ 3 ~ ~ . 19 0 3 6 ~ ..
14 4 1 ~ 5 ~ 20 1 ~ . 5 ~ -
~ 21 ~ 1 7 1 ' :
~6 6 1 2 . ~ ~ ' 22 1 2 2 0 .
17 7 1 3 9 1 23 1 3 9
18 8 2 0 S. 1 24 2 ~ 5 1
19 9 ~ 1 7 0~ , 25 2 1 1 0 .
2 2 2 1' 26 2 2 8
21 11 2 3 9 0 27 2 3 9
~2 ,12 3 0 3 0 2~ 3 ~ 3
23 i13 3 1 4 1, .' 29 3 1 4
24 .'14 3 ~ 0 . ~~ ' 30 3 2
lS 3 3 6 11 . 31 3 3 ~ 1
26 ....................... _ ____ _ __ _ __ :
27 The stored contents of ROM C is in accordance wi~h Table X. .
28 This table relates the two primary ratios and the secondary
29 ratios to produce the desired character decoding in terms of .
31 the decoded decimal value as indicated in the data column and .
32 , .
, . .
.
ll~ 36Z ~ ~
l whether the data is a forward or a reverse read bi t. The
2 zero, 0, bit identifies a forward number while a one, 1, bit . .
identifies a reverse number. Forward is utilized in the sense
4 illustrated in Fig. lA of a left tv right scan and reverse is.
a right to lef~ scan. Both right and left characters decode a~ ;
~forward" in a left to right scan and "reverse" in a right to .;
7 left scan~ The binary coded decimal output of the ROM C i~
8 applied to an AND circuit 107 which is controlled by means of ;
9 signal S23 from the sequencer~ The output of the AND circuit .
107 is a binary coded decimal character haYing a direction bit
11 which is coupled to the validity check circuitO
12 As will be recalled prior to generating the secondary ratio:
13 for decoding a character, the correction value character must .
14 be added or substracted to the measured widths for the module~
A, B~ C and D. In the left-hancl portion o~ the la~el 10 the ..
16 correction value is added to the measurement data and in the .
17 right half of the label, it is ~ubtracted from this data, For .
18 this purpose, a binary adder 108 ls provided for adding the '
19 information to the left-hand charac~ersO The operation of ~he
adder 108 iR controlled by an AND gate 109. The AND gate 109
21 activates the adder 108 in response to a "left" signal and
the S22 signal from the sequencerO The adder 108 combines the
23 signals from the log ratio register 101 with the signal from
24 the correction value register 100 and provides the corrected ..
module data signal on the lead wire 110 to an OR circuit 111.
26 Similarly, for the right half of the UPC symbol a subtracter
27 112 is provided~ The subtracter 112 is enabled by means of a~.
28 AND circuit 113 which is respon.ive to a ~Irite~ signal and
29 the S22 signal from the sequencer 14Se The subtracter 112 ::
combines the data rom the log ratio register 101 w~th the data
31 from the correction value register 100 by subtracting the
~'
51 .,
~336;i~ ~
1 corxection signal from the rati~ signal. The corrected module
2 value signal appears on a lead wire 114 t~at is applied as a .
3 second input to the OR circuit 111~ The output signal of the
4 OR circuit 111 is applied for addressing the secondary ratio
ROM D~
6 TABLE XI . .
7 Address Output Data Data Ratio Value
8 ~ 1 2 Error
91 2 - 7 1 Ratio = 2/1
8 2 Error
~¦ 9 ~ 14 0 Ratio = 1/2 .
12¦ 15 2 Error :
13 The contents of the secondary ratio ROM is represented in Table:
14 XI. The output signals of the ROM D define whether the ratio .
AB or D is 1 or 1 for the purposes of resolving the ambiguity O
1& The outputs of the secondary ratios ROM D are identified as bo
17 and bl outpu~s. If the bo output from the RO~ D is 1~ the -
18 ratio is 2/1 and if the b~ output is zero, tbe ratio is 1/2O
19 Other output signals are the bl signals and all have th~ value.
two to denote a decoding Prror; see ~able XI~ The bl output
21 signal from the ROM D is coupled as an input si~nal to an AND
22 circuit 115. A second input ~o the AND circuit 115 is provided ,
23 by the output signal from the element 116A further identified ..
24 as the R2 equals 1 or 2 element~ The input s;.gnal for the
element 116A is coupled from the output of the R2 register~
26 The bo R~M output signal is coupled to the b4 bit of the ROM C~
27 For the purpose of resolving any ambiguityy it is necessa~y
28 to select one of the two desired secondary ratios in accordance . .
29 with whether the first primary ratio, or the ratio stored in
the Ri register is 3/4 or 4/3O To this end~ the output of the
31 Rl register is coupled to a pair of decodincJ elements 116 and
32 117 for storing the Rl value for decoding purposesO
3~2
When khe decoding element 116 signals that the Rl register
equals 1, the primary ratio is 3/4 and the selected secondary
ratio is A/B. When the decode register 117 signals that the
Rl register equals 2, the primary ratio is 4/3 and the selected
ratio is C/D; see Fig. lC. Each of the output circuits for the
decode registers 116 and 117 are applied as input signals to
an O~ gate 118. The output of the OR gate 118 is coupled as
the third input to the AND circuit 115. Accordingly, when ~1
equals 2 or 1 and R2 equals 2 or 1, and the bl signal of two
appears at the AND circuit 115, an error will be signalled from
the AND circuit 115. The output signals from each of the decode
registers 116 and 117 are coupled in a parallel circuit
relationship to an individual pair of AND circuits 119 and 120
and 121 and 122 respectively. The AND circuit 119 is responsive
to the S17 signal and the Rl decode so that it produces a signal
identified as the S17A signal at its output which is coupled
to the ratio computer 15. Similarly, the~other input to the
AND circuit 120 is responsive to the Sl9 input signal for
producing the output signal S19B to the ratio computer 15.
The AND circuit 121 and the AND circuit 122 are each responsive
to the output of th.e decode register 117 in parallel circuit
relationship. The AND circuit 121 is also responsive to the
S17 sequencer signal to produce the output signal S17C.
Similarly, the AND circuit 122 is responsive to the Sl9 signal
to produce the Sl~D signal which i5 coupled to the ratio
computer 15.
Since the character decoding unit 16 decodes both the left-
hand and right-hand UPC symbol ln sequences through the 6 left-
hand ~0-5) characters normally, at character 6 time the center
3Q bar pattern commences and would ~e decoded. To prevent decoding
- 53 -
'''. !:
': ' ' ' . , .' .
1~103fjz
1 the central patternf the memory address is advanced 5 positions.
2 The decoding may then commence at the first right-hand character.
3 For this purpose a character counter 123 i5 provided which cou~ts
4 the characters as they are se~uentially decoded in response to
each of the S24 signals from the sequencer~ The counter .l23
6 provides an output to decode register 124 for indicating that
7 6 character~ have been decoded~ This unit 124 is further
8 identified as the character count = 6 decode. Similarlyy
9 a second register 125 is respon~ive to the 12th~~ount of the
counter 123 to indicate that the symbol has been completely
11 decoded~ The decode register 124 provides a CH6 signal for .
12 resetting the toggle element 126 to produce th~ "rite" signal~
13 The decode register 125 has its output applied to the reset
14 terminal of the toggle 21. The toggle 21 has its set terminal
coupled to be responsive ~o the P15 siynal from the center bar
16 se~uencer 14S illustrated in FigO 3. The setting of the toggl~
17 21 pxovides a signal to the AND circuit 35~ The P15 signal is
18 also applied to reset the character counter 123 and to set the
toggle 126~ The setting o the t~ggle 126 provides the "left"
signal to the AND circuit lO9o The P15 signal is also couple~
27 to the OR circuit 127 for resetting the decode sequencer 14S .
22 (Fig. 5)u The sequencer 14S is controlled as in the previous
23 sequencer by means of the AND ci.rcuit 3~ coupling the clock
24 pulses to the stepping input of the sequencer in response to
the "se$" state of the to~gle 21~ The OR circuit 127 i~ also
27 provided with an input signal from the AND circuit 128 for
resetting the sequencer~ The AND circuit 128 is responsive to
29 the CH6 signal from the decoding register 124 and the S5
sequencing circuit9 The output of the AND circuit 128 is also
31 . .
~Z
l~lU362
1 coupled to the OR circuit 129 for providing a signal M3 for
2 incrementing the memory address. ~he OR circuit 129 for this
3 purpose is also responsive to the Sl, S2, S3 and S4 sequencing
4 signals for incrementing the memory address of the other four
positions.
6 With the above structure of the character decoder 16 in mindO
7 the step-by-step operation can now be examined. ~he ~quential
8 operation will be examined in conjunction with Table VIII.
9 Initially, it will be recalled that during the center bar
locating sequence that the correc~ion value for correcting the
11 measuxed widths of the modules was generated. Accordinglyr at
12 the P14 time in the center bar locating sequence~ the AND gate
13 102 for the character decoder 16 was activated and the
14 logarithm of the tolerance correc~ion character from the
register 101 was transferred into a correcti~on value register
16 100 prior to the actual character decoding operation commencing.
17 At the P15 time in the center bar locating seguence the control
18 of the system was transferred from the center bar locater 14
19 to the character decoder 16 so that the decoding of the charactër B
21 of the UPC symbol will commence; see Table IIo
22 At this point, the logic for making the correction to the
23 measured widths of the modules should be understood. For both
a forwaxd and reverse ~can of the UPC symbol~ the tolerance
24 correction chaxacter or value is added to the measured modules
25 widt~s for those modules in the left-hand field of the symbol
27 and is subtracted from the measured widths in the right-hand
field. In a reverse scanning operation, the correction is
29 made before inverting the reverse scanned characters~ This
logic applies when the correction value has ~een computed from
a bar/space ratio.
31
32
111~362
1 Since the character decoder 16 is dependent upon the ratio ~.
2 computer 1SJ certain operations for the purposes of decoding
3 are identical to those required for locating the center bar ..
4 pattern; see Table VIII. Accordingly, the initial sequencing
5 steps Sl ~ S9 are identical to those disclosed in conjunction
6 with the operation of the center bar locator 14 for producing .
71 the desired logarithm of the decoding ratios that are.stored
8¦ in the register 101. Accordingly, after the S9 sequencing
9¦ step occurred~ the primary ratio computation, lvg ~C + B is
10 transferred from the xatio computer 15 to the decoder 16. .
11 This logarithmic signal addresses the ROM B and provides a
12 numerical output signal representative o~ the primary ratio in
13 accordance with Table IX. At S10 time in the sequence, the
14 data read out of the ROM B is st;ored in the R1 register. -.
Similarly, during the sequence steps Sll - S16, the second
16 primary ratio is generated in the .ratio computer 15 and
17 transferred to the register 101 of the decoder 16, Thi.s .
18 ~econd primary ratio log signal represents the ratio B + D o
At the end of S16 time~ the data read out of ROM B is stored
2 in register R2~ . .
1 With both primary decoding ratios generated and residing .
23 in registers Rl and R2, th~ decision as to which secondary
ratio is to be utilized for the purposes of resolving the
ambiguity must take place, see Fig~ lC~ The ratio AB or D
26 i~ computed during each decoding operation whether or not it
27 is required..... For this purpose0 the contents of decode .
28 registers 116 and 117 are examined to determine if the first
29 primary ratio is 3/4 or 4/3. The data stored in the registers .
116 and 117 is in accordance with Table IX~ It should now be
31 . .
~2 . . .
36z '`
1 I noted that i~ the data si~nal stored in either reyister 116 or
2 1 117 is four (Rl or R2 is four) an . ERROR signal is genex~ted and
3 ¦ the control of the system is returned to the center bar locator
41 14. An ERROR signal is generated by the OR gate 118 sensing
¦ the "four" stored in the register 116 or 117 and providing an
61 input signal to the AND gate 1150 The bl signal from ROM D
71 will be true when it signals a "two" as indicated in Table XI.
81 I there is n~ error at this point~ the selection of the
correct secondary decoding ratio will continue in accordance
10 with seque~ce step S17. If the register 116 signals that Rl `
11 is equal to 1, the ratio is 3/4 ~Table I~) and then the A
12 module is selected or the A register in the ratio computer 15
13 is i~terrogated. For this purpose~ the decoder 16 generates
14 a signal S17A in response to the S17 sequencing step for
reading out the contents of the A register in the ratio
16 computer 15 by means of the OR circuit 80 and the AND circuit
18 74 ; and the OR circuit 85 to the adder 8~ of ~he ratio compute~.
If the register 117 signals that Rl is equal to 2 then the .
19 ratio is 4/3 (~able IX), the ratio computer 15 receives an
21 S17C signal during the S17 sequence and which S17C signal is
22 applied to the OR circuit 82 and enables the AND circuit 121.
23 This will read the data out of the C register in the ratio
24 computer 15 through the OR ci~cuit 82, the AND circuit 77 and
the 9R circuit 86 to the adder 84O At step Sl~; the logarithm :
26 signal of the measured module width A or C0 in accordance with
the previous selection is loaded into the E register of the .
228 ratio computer 15~ The same procedure occurs at sequencing .
time Sl9 to read out ei$her the B register or the D register
29 .
30~ to tho er 84 in accordance with whether ~1 is 1 or ~. At
32
57
362
1 . .
1 ¦ step S20 the resulting logarithm signal for the modules B or
2 ¦ D is loaded into the ~ register of the ratio computer 15.
¦ At S21 time, the contents of register F is subtxacted from the .
4 ¦ contents of register E to provide ~he log of the ratio signal .
6 ¦ in the register 101. At S22 time, the tolerance correction
I value previously stored in register 100 is added or subtracted
7 ¦ in accordance with whether the left-hand or the right-hand
8 ¦ field characters are being decoded.
10 ¦ If the correction value is to be added to the measured width,
the logical conditions ~or this addition must be satisfiedl
21 At P15 time of the center bar locating sequence, the toggle .
l 126 was "set" fox providing a l'~E~T" output signal that is in . .
131 the true state. This "LEFT" signal is coupled to the AND gate .
l 109 and upon the occurrence of the S22 time the adder 108 is .
16 enabled. The contents of ~he log ratio register 101 is added . :
to the contents of the correction value register 100 and the .
18 corrected module width signal appears on the lead wire 110 and
7~ is coupled to the OR gate 111. .
If the correction ~alue is to be subtract~d to the measured
21 module width, the logical conditions or a subtraction must be . .
22 satisfiedO Assuming an initial forward scan, after the left-hand . .
field has been decoded, the character counter 123 has been .
24 counted up to six. This six count is decoded by the character .
2~ six decoding network 124 ~o provide an output signal indicative
Z6 of the six counts~ This output signal is coupled to the reset
27 input of the to~gle 1~6 to produce a "RITE" output signal that :
28 is in the TRUE state~ This RITE signal is coupled to the AND
29 gate 113 and upon the occurrence of the signal S22~ the .
s~btractor 112 is enabled. The contents of the eorrection value .
31 . . .
~2 . . . :
. .
136Z
: 1 register 100 is subtracted from the contents of the log ratio
2 regis~er 101 and the corrected module width signal appears on
3 the lead wire 114 and is coupled to the OR gate 111. .
When a corrected module width siynal for either a left-hand ~:
or a right hand field appears at the input of OR gate 111,
6 the output signal thereof addresses the secondary decoding
7 ratio ROM D. The signals read out of ROM D are in accordance .
with Table XI. With the secondary ratio data xead out of
9 ROM D~ the data signals representative of a valid 2/1 or 1/2
secondary ratio is applied to the bit 4 (b~) position of the
11 ROM C along with the data from the Rl and R2 registersO The .
121 Rl data is applied to the b2 and b3 positions of ROM C and the.
: 13¦ R2 data to the bo and bl positions thereof. The contents of .
14¦ ~he ROM C corresponds to the data represented in Table X. In .
'51 relating this Table data to the circuit operation of the
16 character decoder 16 r it will be noted that since the secondary
17 ratio value is applied to the highest order address bit or
1~ position of ROM C, the characters that do not require a
~9 secondary xatio to be unambiguously decoded appear twice in .
RO~ CO For these characters the secondary ratio is a
22 ndon't care'l bit and can be ignored. .
The values recorded in Table~ I and X can be readily .
~3 translated to reveal the decodi~g of the recorded characters
24 in terms of the primary and secondary ratiosO If the primary . I
26 ratios decode to 2/5 and 3/4, the decoded character is defined
27 solely by these two primary ratios and the character is un-
ambiguously a forward 4, Table I and address l in Table XO : .
28 If the two primary ratios are 3/4, 3/4~ a secondary ratio must
31 be examined as ~ re~erse7 or a reverse 1 may result; Table Io
32 . . .
S9 ,
~ 3~;2
1 If the secondary ratio of A/B results in the ratio 2/1, a
2 reverse 7 is decoded. Similarly, if ~he secondary ratio is
3 1/2, reverse 1 is unambiguously decoded.
4 The Table X contents relate the ~0 - b4 address positions
5 of ROM C for both a forward and reverse scan and the secondary .
6 ratios of 1/~ and 2/1. The "Address" column of Table X
7 represents the decimal equivalent of the hinary coded bits .
8 bo - b4. The bits bo - b3 will have the values 0,1,2 or 3 for
a valid primary ratio as noted in Table IX~ The b4 bit will
11 be either 1 or 0 ~or a valid secondary ratio as noted in .
Table XI. The F/R column of Table X identifie~ whether the .
12 decoded data character is a forward or reverse bito The
14 ~*~1 signifies a forward bit and the 1 a reverse bito
At the S~3 sequence, the addressed memory location in R0~ C
16 is coupled through AND gate 107 to produce ~he binary coded
decimal decoded character having the direction bit as discussed
17 hereinabove~ At this time, the output signal from the AND gate .
19 107 is transmitted to the validity check circuit 17~ The :
remaining step in the decoding proceduxe is S24~ The S24 sig~al
21 increments the character counter 123 to the count of twelve~
22 This 12th character is decoded in the unit 125, which signals a
23 "12" output signal. With the register 125 signalling that the
12th character has been decoded, the toggle 21 is reset to
disable the AND gate circuit 35 and thereby the decoder sequencer
26 14S. The character decode sequence may now be restarted.
~7 The characters that are decoaed in accordance with Table X
28 must be consistent either for a forward or reverse scan. This
29 effectively satisfies the parity check requirements referred to
in the UPC standard symbol specifications. To provide a validi
31 . . . .
~2 . . .
,
36Z
1 ~ decoded o tput there must be twelve valid characters and the
2 ¦ check digit must ~erify. If the read direction indicators are
3 ¦ not consistent and the check digit test fails, control is
4 ¦ retuxned to the center bar.locator 14 to attempt to find another
51 position D
61 In following through thb operation of the sy~tem various
7¦ conditions have been mentioned herein, ~herein an invalid decoding
~¦ operation may re~uxn the control to the center bar locator 14 to .
9¦ reexamine the memory for a valid center bar pattern. In addition~
10¦ it has been noted that ~ read will be aboxted when the retry
11¦ counter 67 has been counted up to ten (~ ~ttempts and 2 Gycles pe~
12¦ attempt)O Other conditions that will abort the read are:
13 (1) If any of the data from the wand ll provides modllle ~iath !,
14 measurements that when added together or summed (A ~ B~ C + Do~~~)
15 overflow 8 bits cause an aborted read. ,
16 C2) I.~ any of the character ratios or ~/B or C/D ratios fall ~
18 into the regions marked l~rror" in Tables IX and XI the read is . . ¦
aborted in addition to the conditions noted in T~ble IIo
It should be appreciated by thbse skilled in the art th~t the.
21 circuit elements described herein are well known in the art and
commercially available thereby permit~ing ~he sys~em to be con-
22 structed on the basis of the above disclosure~ The element
24 functions that have been repeated herein for purposes of explanati~
an be performed by a single element that may be time shared inn operational system. . ,
26 The improvement disclosed herein has advanced the state of the .
28 rt with respect to reading and decodincJ a high density, linear .
291 bar code of the type of the standard Universal Product Code s~mbol: .
l and derivatives thereof that permit decoding ambiguities to be . ',
3,1 simply resolved and is highly tolerant to manual accelerations a~d
of reco~ding or printing tolerancesO The improvement is directly -
~21 applicable to high speed laser scanners as well as portable r
33 ! battery operated hand-held scanners. .
