Note: Descriptions are shown in the official language in which they were submitted.
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SINGLE TRACK AUDIO-DIGITAL RECORDER AND CIRCUIT
FOR USE THEREIN HAVING ERROR CORRECTION
This invention relates to electronic equlpment
~or processing analog signals such as those in the audio
range lnto corresponding digital signals suitable for
recording on a record medium such as magnetic recording
5 tape, and particularly to related systems for correction
of errors when such digitlzed slgnals are played back and
reconverted into an output analog audio signal.
Professional audio recording generally begins at
the point where a number of tracksg such as 4, 8 or 16
lO tracks o~ analog audio signals are recorded onto a master
tape, the master tape is then mixed with other masters to
dub in other sounds and the mixed masters are further
mixed into sub-master tapes having a single monaural
track, two stereo tracks or four quadraphonic tracks. The
15 sub-master tapes are then used as the basis for
manufacture of both record discs and prerecorded tapes,
such that any defects or deficiencies inherent in the
analog signals are embodied in the subsequent generation
master and sub-master recordings and become a part o~ all
20 manufactured copies. In order to greatly reduce3 if not
completely eliminate many such de~iclencies, professional
audio recorders are now wldely considering the adaptation
of digital recorders such as are generally used in
instrumentation and computer data processing fields for
25 audio uses. In such recorders, as for example that
depicted in U.S. Patent No. 3,786,201 (Myers et al), the
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analog slgnals are periodically samplecl and a digital word
is generated corresponding to each sample. Since the
signal to tape inter~ace affects only the fine structure
digit carry~ng signal and not the numerical content per
se, the integrity o~ the digitized audio s:lgnal is
maintained and no degradation in the quality of the
recorded sound occurs, even with repeated re-recordlng,
mixing and the like. Typical decreases in the amplitude
or pulse rise time, etc. of the dlgital pulses may be
recovered by conventional signal processing techniquesO
However, despite the inherent desirability of
such digital audio recorders, general acceptance in the
professional recording industry has not yet been achieved.
It is believed that at least part of the reason for the
lack of acceptance has been the propensity of errors in
the digitized signal as may result fro~ defects in the
record medium such as the familiar drop-out problem in
magnetic recording tape. Rather than merely causing a
momentary loss o~ audio signal as in conventional analog
audio recorders, the loss o~ a digltal bit may, if it
occurs at a most inopportune time, cause the signal to
lose sync entirely such that all subsequent portions of
the digital signal are meaningless. To avoid such total
loss, it is conventional to group the digiti~ed data words
formed ~rom a number of bits into blocks or frames, each
of which is indexed by a sync word. Such systems still do
not prevent the loss of data wlthin a given frame, which
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loss will still result irl an undesirable shi~t in the
ou~put level or other disturbil~g noises as well as the
actual loss in the intended sounds.
In order to prevent the loss o~ computer or
other data processing information, systems have been
developed for detecting the presence of errors in a
playback signal and ror correcting errors so detected.
Such schemes are not known for use in digital audio
recorders per se. Typically, such data processing
recorders enable error correction by providing redundant
information which may then be recovered and played back in
the event an error in a primary track is discerned. ~ost
simply, such systems provide two (or more) totally
redundant data tracks and record the same in~ormation on
each o~ the tracks. Particularly, the data on the two
tracks may be desirably spatially staggered along the
length of the tape such that a single defect spanning both
tracks will not cause the loss o~ the same portion o~ the
signal. While such ~ully redundant systems are
technically ~easible, they obviously require twice as much
record medium as would otherwise be needed. More
sophisticated recorders have also been devised in which
error correction codes are generated and recorded along
with the digital data, such that when an error is
detected, the correction codes are decoded to regenerate a
corrected data portion corresponding to the erroneous
data. Such schemes also generally utilize multiple
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tracks, in which one or more tracks may be exclusively
devoted to storage Or the error correcting code (ÆCC).
See Patel, U.S. Patent No. 3,745,52~. In that patent, the
error detection operation provides error pointers
(pointing to an erroneous block of data) which are
generated by determining the ~uality of the p ayback
signal, i.e.~ overall wave~orms) etc.
However, not all data or recordlng s~ystems are
amenable to multitrack recording, i.e., particularly to
facilitate compatibility with previously accepted recorder
systems, it is desirable to provide a single track
digitized audio recorder in which an error correction
operation is also employed. In U.S. Patent No. 3,913,068
(Patel), a single track recorder is disclosed which
utilizes a data format in which error check codes are
included at the end of' a block of data and in which
external indicators are detected to initiate the need f'or
error correction.
In contrast to the systems discussed above, the
present invention is directed to a circuit for processing
audio signals to be digitized and recorded on a single
track of a suitable record medium. The circuit includes
an error correction feature which enables the
reconstruction of corrected data in frames in place of
erroneous data without the need f'or externally generated
error pointers. The circuit of the present invention is
particularly adapted for use in an audio digital recorder
in which both a record and a playback section are
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provi~e(l. The circuit includes means, such as an analog
to ~igital converter, for converting an lnpllt analog audio
signal into a corresponding digitized audio signal and an
encoding means for partitionLng the digitized audio signa]
into a serialized signal containing a succession of frames
suitable ~or recording on the record medium. Each of the
~rames comprises a preselected number of data words, a
preselected number of parity words, an error check word
corresponding to the frame and a sync word defining the
frame location. The encoding means includes means for
generating the parity words of each frame by an exclusive
combination of data words of at least two other frames
which are preselected according to the expression
pKN = D~+Jn ~ DKN++mk ~ where
PNK is a given parity word located at segment K
of frame N,
DNK++n is a given data word located at segment
J K+J Or frame N+n, and
DK+km is a given data word located at segment
K+k of frame N+m.
In these expressions, K, J, k, m and n are all integers,
and m and n are not equal to each other or to zero. The
thus encoded parity words enable each frame that is
incorrectly played back to be detected~ The circuit
further enables correct data words of the incorrect frame
to be reconstructed from the data words of at least one of
the other preselected frames in combination with the
parity words originally generated from the data words of
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the lncorrect frame and the corrected data words inserted
into a serialized pl~yback signal in place of the data
words of the incorrectly played back frarne.
Preferably~ the preselected frames are in turn
selected to comprise data words spatially located
different predetermined intervals of time frorn the data
words of the given frame such that the intervals of time
are sufficiently long to provide a corresponding
sufficient separation of the given frame frorn the
;~ 10 preselected frames to minimlze the probability that a
single defect in a said record medium on which the
digitized signal is to be recorded will cause the loss of
signal corresponding to both the given frame and the
preselected frames.
The encoding means of the record section
preferably includes means for providing a succession of
frames ln which each frame contains a selected number of
data words and parity words. Desirably~ each parity word
is divided into two components~ each of which are
positioned within a given frame immediately after a data
word. Further, the parity word generating means
preferably includes means ~or generating the parity words
of a given frame from the data words in at least two
predetermined spatial locatlons within different
preselected frames, each of which is located a different
multiple of N frames from the given frame.
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Thus, ~or example, each frarne desirably includes
sixteen data words, each conslsting of s~xteen bits, and
eight parity words, each consisting o~ sixteen bits. Each
sixteen bit data word is indicative of the amplitude o~
the corresponding input analog audio signal during a
sampling period selected to be less than that
corresponding to the highest frequency to be recorded.
I.e., an upper ~requency o~ 20 KHz has a period of
50 ~ sec; accordingly, a sampling period o~ 20 ~ sec is
desirably selectedO Each sixteen bit parity word is
divided into two eight bit portions, each o~ which is
inserted following one data word.
The parity words are pre~erably generated ~rom
data words in two previous frames, one frame being located
15 frames previous and the other 30 frames previous to the
~rame being then formatted. Further, the specific parlty
word within the 16 data word-8 parity word sequence of
each frame is pre~erably generated from the data word in
the N+15 frame at the same relative position within the
~rame (i.e., ~=0) and from the data word in the N+30 frame
at one successive relative position (i.e., k=l).
Generally, the encoding means includes a combination of
shi~t registers and/or random access memories ~or
temporarily storing the received data to enable
construction o~ the parity words from successively
received data words~ The encoding means also includes
means for generating error check word and sync word and
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means for assembling the respective words to complete each
f`rame.
Analogously, the circult desirably also includes
a playbac~ section includlng means for provlding a dlgital
playback signal corresponding to recorded data on a record
medium, means ~or processlng the digital playback signal
to de-termine khe presence of an erroneous frame~ means ~or
reconstructing a corrected data word ln a rrame and ~or
lnserting the corrected data word in place o~ the
erroneous data word and means for converting the processed
and corrected digital playback signal into a corresponding
analog output audio signal. The means ~or determlning the
;~ presence o~ an erroneous ~rame includes means such as
including shift registers and logic circuits for
responding to a received playback signal to generate an
error check code word corresponding to a received frame
and ~or comparing the regenerated error check word with
the corresponding error check code word received at the
end of that frame to provide a frame error signal
indicative o~ a said erroneous frame in the absence o~ a
match between the two. The ~rame reconstruction means
includes means ~or temporarily storing playback signals
corresponding to each ~rame until signals corresponding to
the preselected frames containing the parity and data
25 ~words required ~or reconstruction of data words o~ said
erroneous frame are received. When a ~rame error signal
is received, corrected data words are reconstructed ~rom
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che receiv~d parity and daSa words w~thin said preselected
frames an~ the reconstructed corrected data words are
inserted in the proper spatial locatlon within the
processed digi~al playback signal.
Desirably, means including a FIFO memory and
associated shi~t regis~ers are also provided ~or
correcting ~or "wow" and "flutter" and okher time base
irreglllarities in the received playback signal. Such time
base correcting means may include means responsive to a
fixed clock pulse signal from a playback contol and time
generator network to lock the received signals at that
rate and servo means ~or controlling drive means for the
record medium to ensure that the average periodicity of
the sync words are the same as that of the fixed clock
pulse signals. The error correction means also preferably
includes shift registers and/or random access memories
(RAr~) as well as associated logic gates and the like which
may be controlled by timing signals from the playback
control and time generator network. Successive data words
may thus be received and stored frame by frame in the RA
such that when a frame error signal is received, a data
latch network is activated. Data words from appropriate
successive ~rames are then operated on together with
appropriate parity words in a data reconstruction network
such as a bank of exclusive OR gates. Reconstructed data
words are then fed back to the RArl in the same relative
location within the data stream as the original defective
data words, and the data words corrected as necessary are
coupled out, such as through a parallel to serial data
converter to the digital to analog converting means.
The single track recorder with the error
correction feature as herein clescribed is partlcularly
desirable in that it enables the expense of the record and
playback heads to be rninimized, and the record rnedillm to
be correspondingly narrower, thus facilitating handling
the rnedium. In a preferred embodiment, a recorder having
a one-inch tape moving at 45 ips has been found suitable
for recording 32 parallel tracks in which the data in each
track is protected by the error correction feature. Such
a system is particularly useful in professional audio
recorders where multiple track recording and mixing are
desirable features.
Figure 1 is an overall block diagram of the
audio-digital recorder of the present invention;
Figure 2 shows the format of the data encoded
according to the present invention and as recorded on a
magnetic recording tape;
Figure 3 is a block diagram of the record
encoder within the record section of the recorder of the
present invention;
Figure 4 is a block diagram of the error
detection and time base corrector within the playback
section of the recorder o~ the present invention; and
E~'igure 5 is a block diagram of the error
corrector ~ithirl the playback section.
Referring first to ~igure 1, there is
schernatically s~-lown an overall block diagram of a
preferred e~bodiment for an audio-digital recorder having
an error correction feature. As is there shown, the
recorder 10 comprises a record sec~ion 12 and a playback
section 14. An input analog audio signal received at
terminals 16 is coupled through a low-pass filter 1~ which
removes all frequencies in excess of that desirably
processed within the recorder. Typically, an upper cutoff
frequency of 20 KHz is conveniently provided. A
particularly desirable filter for processing input analog
signals is a Type V87E 20 KHz low-pass filter manufactured
by T.T.E., Inc., Los Angeles, California.
The thus filtered analog signals from the filter
18 are then coupled to an analog to digital converter 20
which converts the analog signal into a corresponding
serial formatted digital e~uivalent. Such an analog to
digital converter is conventional in the art and may
desirably be purchased as a Model MP 8016 from Analegic
Company, or modified as appropriate to provide a suitable
number of digital bits corrsponding to a desired dynamic
range.
The serialized digital signal from the converter
20 is coupled to a record encoder 22. The encoder 22 is
described in detail in con~unction with ~lgure 3, and
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processes the serial digital signal 50 as to partition the
serial digital bits into a succession of frames, each o~
which includes a plurality of da-ta words, parity words,
error correction word and sync word. In so doing, the
serial input is converted to a parallel input which is
then temporarily stored to enable subsequently received
data words to be acted on in order to generate parity
words corresponding to the subsequently received data
words. These ~enerated parity words are then formatted
together with the temporarily stored data words to form a
given frame.
~ 'he record controller and time generator 24 is
coupled to both the A/D converter 20 and to the record
encoder 22 to control the sampling time at which the A/D
converter 20 ~enerates digital bits corresponding to a
given sampling time within the converter 20. In order to
ensure reproduction of the highest frequency present in
the analog signal, i.e., frequencies up to 20 K~z, it is
essential that the sampling period be less than the period
associated with such frequencies. Since a 20 KHz signal
has a period associated therewith of 50 microseconds, a
sampling period of 20 microseconds is desirably provided.
The recorder controller and time generator 24 is further
coupled to the record encoder 22 in order to provide
appropriate timing signals therein to control the length
of each of the data, parity, error correction and sync
words within the formatted digital signal. Preferably,
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t~lc c~ata words and parity ~ords gerlerated theref'rorn are
processed in p.lrallel digital forrn. ~fter the appropriate
~rocessing to ~enerate the parity words is completed, the
parity and d~ta words are couF)led through parallel to
serial converters such as conventional shift registers to
provide a serial output. Serial Olltputs corresponding to
the data words, parity words and corresponding to serial
formatted error code words ancl sync words are then coupled
through a controller output switch to provide the
respective data words in appropriate sequences. The thus
formatted frarnes are preferably coupled throllgh a delay
modulation pulse generator network to provide an output
signal suitable for recording on a suitable record medium
utilizing a minimllm bandwidth requirement. Such an OUtpllt
signal is coupled to a suitable record transducer such as
a magnetic recording head 25.
The playback section 14 of the recorder 10 is
adapted for playing back signals recorAed on a record
medium such as the rnagnetic recording tape 23, ~or
detecting errors in the playback signal and for correcting
such detected signals. The playback section 14 thus
includes a playback transducer 26 such as a conventional
magnetic playback head, the output of which is coupled to
a preamplification and equalization circuit 28. This
network desirably encompasses conventional circuits for
interfacing a conventional magnetic pickup head with
successive arnplification and signal processing circuits.
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T~e circuit 28 provides an additional amplification stage
for ~he receLved signal ~rom the playback head 26 and
provides e~ualiza~ion to com~ensate for amplitude and
phase nonlillearities. The circuit 2~ also includes a
limiter for converting the flux transitions detected by
the head into a digital delay modulatéd signal which
generally corresponds to that recorded onto the record
medium 23. The preamplification and equalization circuit
28 thus preferably may include an impedance matching
transformer which couples the playbàck head 26 to an
integrated circuit amplifier such as Type CA 3095
manufactured by RCA Company. The output frorn the
integrated circuit amplifier may be coupled to a limiter,
such as a zero crossing detectorJ which converts the
~ 15 quasi-digital signal as there amplified into a more
;~ readily processable, standardized delay modulation digital
signal. The standardized signal is coupled to a bit-sync
generator 30 which generates a clock signal corresponding
to the rate of the data being reproduced at a nominal
frequency of 1.25 MHz, and also generates a frame sync
signal corresponding to a nominal frequency of 3.125 KHz,
which signals are subsequently used for controlling the
data processing operations. Further, the delay modulated
digital signal ls there processed through conventlonal
decoding circuits to provide a non-return to zero (NRZ)
digital ~ormatted signal on lead 31.
The NRZ signal is coupled through lead 31 to the
error detector and tir,le base corrector 32, which, in
response -to control signals ~rom the generator 30,
generates the frame error signal in response to the
detection of an erroneous frarne. The corrector 32 is set
forth in more detail in a block diagram o~ Figure 4~ and
may be generally viewed as comprising two basic features,
one dealing with error detection and one with time base
correction. The error detection operation is ef~ected
through a cyclical redundancy code (CRC) check circuit.
The CRC check circuit generates a CRC check word ~rom the
reproduced signals and provides a ~rame error output
signal indicative of the absence o~ a match between the
generated CRC check word and the CRC code word received at
the end o~ each ~rame. The time base correction portion
of the corrector 32 includes input and output timing
networks responsive to signals from the sync generator and
to ~ixed clock signals from the play controller 36. Any
deviation between the signals received from the sync
generator 30 and the ~ixed clock signals are automatically
corrected and any deviation such as that associated with
"wow" or "flutter7' from the playback mechanism are
removed.
The output ~rom the error detector and time base
corrector 32 are coupled to the error corrector 34 as
shown in more detail in the block diagram of Figure 5.
The error corrector 34 responds to that output in order to
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initiate error correction procedures. Data ~rords and
parity WOr(l5 received from the time base corrector 32 are
split within the error corrector 34, and the data words
are tempoarily stored in a cyclically driven data word
memory. Similarly, parity words as received are
temporarily stored in a parity storage circuit. Upon
appropriate instructions from the error detector 32 and
the controller 36 indicative o~ the presence o~ erroneous
words within a given frame, appropriate previou~ly
received data words are operated on together with
appropriate parlty words to reconstuct corrected data
words. The reconstructed and corrected data words are
then reinserted in the data word memory.
The successive frames~ containing corrected data
words as necessary, are coupled through appropriate shift
registers to provide a corrected serialized output~ This
serial output is coupled to a digital to analog converter
38 such as a Type DAC 169-16 converter manu~actured by
Datel Systems, Inc. The resultant analog output signal ls
then desirably coupled through a low-pass ~ilter 40 to
remove any high frequency noises as may be present in the
signal due to the digital processing operationsO The thus
processed analog audio playback signal is then coupled to
an output terminal 42.
Figure 2 shows a recording format ~or the audio
information as presented in dlgital form together with
appropriate codes enabllng the error correction operations
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according to the present invention. As may there be seen,
data within a glven frame (N) is desirably formatted
within a succession o~ positions (K) ranging from 0
through 7. Each Or the positions K in turn includes two
data words Do through D15, and one parity word, each of
~hich is divided into a most significant PKM and least
significant PKL component. Each frame is completed by an
error check code word~ such as a cyclical redundancy code
word and a synchronization code word. Accordlng to the
format there shown, each of the data wordæ Do throùgh D15
comprises a 16 digit analo~ Or the intensity of a given
sample of the input analog signal. As discussed
hereinabove, each of the digital samples consisting of 16
digital bits is repeated every 20 microseconds, thereby
providing a train of digital bits, the duration of each of
which is 1.25 microseconds. Within the record encode
network 22, the digitized data ~ords are compressed into a
~ramework wherein each bit has a duration of 0.8
microseconds~ so as to provide time within each frame for
the associated parity words, error check words, and
synchronization words without expanding the time required
for a given frame to be recorded~ Thus~ in the recorded
format, each of the 16 data words Do through D15
comprising 16 bits each, extends over a duration of 12.8
microseconds. The component of the parity words PoM and
POL through P7M and P7L each comprise 8 bits which also
have a duration of 008 microseconds and thus extend 6.4
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microseconds. ~'inally, the error check word in the form
of a cyclical redundancy check, is generated from the
preceding 16 data words and alternating parity word
components and includes 12 bits, i.e., a duration of 9.6
microseconds. Completing each ~rame is the synchronlzation
word which consists o~ a 4 bit signal, i.e., a duration o~
3.2 rnicroseconds. Accordingl;y, each entire frame (N) has
a total duration of 320 microseconds which is recorded ln
real time in synchronization with the 16 data word samples
within the frame, each of which persists for 20
microseconds for a total sampled period of 320
microseconds.
As is further shown in Figure 2, each of he
parity words P0M and PoL through P7M and P7L within a
frame N is generated from data words of frames which are
spatially located a sufficient distance from the frame N
that a single defect on a record medium will not cause the
loss of both of the frame N and the frames from which the
parity words of the ~rame N are generated. Thus, for
example, in a preferred embodiment, the parity words PKr~
and PKL respec~ively, for each position K within the frame
N will be generated from the data words Dorl and DoL
respectively of ~rame N~15 combined through an exclusive
OR circuit, shown symbolically as ~, with the data words
at the next position, i.e., D1M and D1L respectively~
frame N+30, Such relationships may be shown according to
the following generalized expression:
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Kll L D2Kpl L ~ D~2K~ L
w~ere pr~ is a parity word at position K within frarne N,
PK referring to the parity words generated from the rnost
significant half of the corresponding data words D2Krl and
D(2K-~l )r~ clnd PKL referrin~ to the parity words generated
from the least significarlt ha:L'f of the data words D2KL and
D(2K~l)L; and where n is the offset between the f'rames of'
WiiiC~l the parity words of frarne N are generated.
More specifically, the expressions for the
parity words PK~q and PKL, i.e., corresponding to the rnost
and least significant portions respectively of the data
words D2K and D2K+l from which the parity words are
generated are:
pKN = DN n ~ I)(N22n+l) , and
pKN = D2NKn ~ D72K+1~1
In a pref`erred embodiment, N may be selected to
be 15 such that for a given position K=0 of frame N the
parity words PoM and PoL will be:
P0 = Do+l5 ~ DlN+30 and poN = DoN+l5 ~ Dl+30
Similarly, for position K=1 at frame N:
pM = DN+15 ~ D3+30 and PlL = D2+15 ~ D3L
And, f'or position K=2 at ~rame N:
M M 5M P~L = D~+L15 ~ D5N+30
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It may thus be see~, that ln the preferred
embo~iment Or the present invention, an error correction
scheme is set forth in which a 1/~ savings in required
tape storage space is effected over that required for a
fully redundant recording format by providing a two ovt of
three redundant format. It is similarly within the scope
of the present invention to further utilize encoding
format as M out Or N levels of redundancy. Thus, for
example, a three out of four or four out of five scheme
may similarly be adopted utilizing an encoding scheme
similar to that depicted in ~igure 2. It is further
within the scope of the present invention to provide
formats similar to that shown in Figure 2 but wherein
parity information as well as error checking codes and
synchronization words are differently spatially located
within a given frame. ~or example, a synchronization code
word, which locates a given frame, may be positioned
within the frame at an~ of a variet~ of convenient
locations. In ~igure 2, the sync word is shown to
terminate a given frame N; however, the synchronization
word may be positioned at any given location within the
frame and may further be split apart so as to further
delineate the end of any given position or word within the
frame. Similarly, the error check (CRC) word and the
parity words may be variously positioned within the frame
- or grouped togethe~ toward the termlnal portion of a given
frame.
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'I'he block dia~rarl of ~i~ure 3 sets forth details
of a prercr7rcd ernbodillent of' the record encoder~ 22 of'
~igure l. As May there be seen, seriallzed digital data
rrom the A/D converter 20 received on lead 50 is coupled
to an 8 bit shlft register 52, such as a Type 74LS164
integrated circuit module manufactured by Texas
Instruments~ Inc. (T.I.). The shi~t register 52 converts
the serialized input digital information into a parallel
output signal as denoted on the double leads 54. The
parallel outputs are fed to a random access memory (RAM)
56, such as a bank of eight Type 2102 integrated circuit
RAM memory elements, manufactured by N.E.C., which stores
the data words of successive frames to enable the
generation of parity words from the N~15th and ~+30th
frames. The RAM memory 56 provides a storage capacity of
; 1,024 bits per element, thus providing sufficient capacity
to store the 30 frames, each of which contains 256 bits,
i.e., a required capacity of 960 bi-ts per register. The
locations within the memory 56 in which the individual
parallel signals are stored are controlled by outputs on
lead 58 from the record controller 24. The controller 24
thus provides outputs to generate each address within the
memory 56 at which the respective outputs from the shift
register 52 are stored. The shift register 52 is also
controlled by a signal on lead 64 from the controller 24
to enable the transfer of the serial data words inputed on
lead 50 out on leads 54, In order to generate the parity
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words, the outputs from the RAM memory 56 are coupled to
parity registers 66 ~nd 68, which may pre~erably be IC
circuits such as Type LS165, manufactured by T.I. The
first of the parity registers 66 is controlled by slgnals
5 from the record controller 24 on lead 70 to generate a
parity word based on data words occurring N+15 ~rames
later. I.e., data words loeated 15 x 256 bits or 3840
bits after a given data word is shifted lnto the register
66 by an appropriate command signal from the controller
240
Slmilarly, the parity register 68 is controlled
by timing signals on lead 72 from the record controller 24
to generate a parity word based on data words occuing in
one successive position within the N-~30th successive
frame. Thus, data words located 30 x 272 (i~e., one frame
of 256 bits plus one additional 16 bit data word) or 8,160
bits after a given data word, are shifted into the
register 68 by an appropriate timlng signal from the
controller 24. The output from each of the parity
registers 66 and 68 are the~ serially shifted out in
response to a common clock control signal on lead 74, and
are combined in the exclusive OR gate 76. Similarly, the
undelayed data words ~ithin the memory 56 are outputed in
parallel form on leads 78 to shift reglsters 80 and 82 in
response to control signals on leads 84 and 86 from the
controller 2ll to thereby temporarily store the most
significant and least signiflcant portions of each data
-23- ~3~
word. The serialized e~uivalent to the most significant
and least significant portions of a given data word are
then outputed from the shift registers 80 and 82 and are
coupled with the appropriate parity words frorn the
exclusive OR gate 76 in a serial switch 880 Also coupled
into the switch 88 are sync signals on lead 90 from the
controller 24 as well as a CRC code word ~rom the CRC
generator 92. The CRC generator 92 is preferably an
integrated circuit type such as 9404 manuractured by
Fairchild Semiconductor Corp. Each of the respective four
inputs into the switch 88 are appropriate gated out in
response to control signals on lead 94 frorn the record
controller 24. The serial switch 88 thus provides on
- output lead 96 a fully formatted serialized digital signal
containing the appropriately sequenced data words and
parity words within a given frame followed by the CRC
check word and sync words. The serial signal on lead 96
is coupled to the delay modulation generator 97 together
with timing signals on lead 98 from the controller 24
corresponding to a fundamental frequency (Fo) clock rate
of 1.25 MHz, a 2Fo clock rate and a missing transition
control signal. The thus processed digital signal from
the generator 97~ in delay modulation form, is coupled
through lead 99 to a head driver circuit 100, which
amplifies the digital signal, and applies the amplified
signal to a record head 25, such that the thus processed
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delay r,lodulate(i signal is recorded on a sultable record
medium suc'l as conventional magnetic recording tape.
Details of the manner in which signals are
processed during playback to detect erroneous data and to
provide correction of the time base of the retrieved
sigllals are set ~orth in the block diagram o~ the error
detector and time base corrector shown in F'igure 4. In
this figure, the error detector and time base corrector 32
of Figure 1 is shown to receive the serialized data from
the bit sync generator 30 on lead 31. This input signal
is coupled in parallel to both the time base corrector
portion and to the error detection portion. The error
detection portion includes a CRC check 101 which recodes
the data words of each received frame and regenerates
therefrom a corresponding CRC check word. That check word
is then operated on in con~unction with the subsequently
received CRC check word of that ~rame in a comparator
netword within the CRC checker 101. The synchronization
of the respective comparison operations are controlled by
: 20 a data clock signal on lead 102 from the play controller
36. In the absence of a match between the regenerated CRC
check word and the subsequently received CRC check word, a
frame error signal is provided on lead 104, which signal
is coupled to a switch 106 within an input timing network
shown generally as 108.
The data input on lead 31 is also coupled within
the time base corrector portion to a serial to parallel
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conver~or 110 WhiCIl converts the serial input data into a
corresponding eight channel parallel output on leads 112.
The convertor 110 may conveniently be an integra~ed
circuit such as Type LS164 manufactured by T.I. The
sequencing of s-lgnals outputed from the convertor 110 are
in turn controlled by tape cloc~ signal on lead 114 from
the bit sync generator 30 and from a ~00 bit counter 116
within the input timing circuit 108. The counter llh is
in turn controlled by the tape clock signal on lead llLI
and a frame sync signal on lead 118. and provides outputs
on leads 12Q and 122 corresponding to the end o~ each
respective ~rarne.
Seven of the eight parallel outputs from the
convertor 110 are coupled on leads 112 to a first in-first
out (FIF0) memory 128. The FIF0 memory 128 preferably
comprises a bank of six integrated FIF0 IC chips such as
Type 3341 manufactured by Fairchild Semiconductor Corp.
The eighk parallel input to the ~IF0 memory 128 on lead
130 is from the switch 106, which selects between data on
the eight output leads 113 of the convertor 110 and the
frame error signal on lead 104 from the CRC error checker
101. The FIF0 memory 128 is further controlled by a reset
signal ~rom the AND gate 124 on lead 132 to enable the
data input signals to be temporarily stored and to be
outputed on the parallel output leads 131l modified in time
sequence as appropriate to provide a rigorously controlled
time base.
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The serial to parallel convertor 110 ln
conJunction with the switch 106 is adapted to replace the
CRC check word (12 bits) and the sync word ( 4 bits) of the
incoming data on leacl 31 ~ith a 16 bit FIFO sync code.
This sync code is coupled via leads 112 together Nith the
remaining data and parity words to the FIFO memory 128.
One of the bits of the 16 bit FIFO sync code is coupled
through the switch 106 back into the eighth input to the
FIFO memory 128 via lead 130 :Ln response to appropriate
timing signals on lead 122. All elght parallel blts ~rom
the FIFO memory 128 are then coupled on leads 134 to the
FIFO sync code detector 136 as well as coupled to outputs
138 to the error corrector 34. The FIFO sync code
detector 136 responds to the FIFO syne code on leads 134
and to timing signals from the play controller 36 on lead
140 to provide a feedback control signal on lead 142 in
the event data outputed from the memory 128 is out of
proper spatial position. If the data outputed ~rom the
FIFO memory 128 1~ thus out of sync with timing signals on
lead 140, the data ls automatically reset by signals on
lead 142 inputed into the input enable flip-flop 126 which
~ is then automatically reset through the AND gate 124 to
: control the rate at which data ls processed in the FIFO
memory 128~ resets the FIFO memory 128 and resets the
output enable ~llp-~lop 158.
The 400 bit counter 116 is responsive to the
tape clock pulse on lead 114 and to the frame 3ync signal
~27-
on lead 118 to thus generate a control slgnal on lead 144
whlch is l/8th of the rate at which the tape clock pulses
occur. This signal is coupled together with the output
from the enable data flip-flop 126 through the AND gate
124 and thence via lead 132 to enable the input to the
FIF0 memory.
The error detection and time base corrector 32
also includes an output tirning network 146 which completes
a feedback loop to a phase lock loop servo 148, which in
turn provides Olltputs on lead 150 to control the drlving
speed of a record medium drive mechanism (not shown) to
control the rate at which the data is fed in on lead 31.
The network 146 includes a memory level monitor 152 which
responds to the level of data in the FIFO memory 128, and
provides an output signal when the memory is half full,
i.e., when 75 bits are present at the input to the monitor
152. At that point, the output signal is coupled to the
AND gate 154 together wlth an output frame sync signal
from the play controller 36 on lead 156, which signal is
also coupled to the phase lock loop servo 1483 and whlch
sets the output enable ~lip-flop 158~ The output of
flip-flop 158, when set, allows a crystal clock signal on
lead 164 from the play controller 36 to pass through NAND
gate 162 and thereby provides the flxed clock control
signal on lead 166 to the FIF0 memory 128. The output
timing network 146 thus responds to the fl~ed clock
slgnals and additlonal synchronizatlon signals from the
~ .
play controller 36 to control the rate at which signals
are outputed ~rom the FIFO memory 128 and to en~ure that
the output signals on lead 138 are provided in an absolute
~ixed time relationshipO
The error detection and time base corrector 32
also includes means for generating the error frame signal.
Such a slgnal is triggered by the eighth output lead 168
from the FIFO and is coupled therefrom to an OR gate 170,
which is further controlled by the signal on lead 142 ~rom
the FI~O sync code detector, and provides an output
coupled to the good/bad frame latch circuit 172 to provide
the error frame signal on lead 174.
The details of the error corrector 34 are shown
in the block diagram in Figure 5. In this ~igure, the
eight parallel outputs from the FIFO memory 128 of the
error detection and time base corrector are shown coupled
on leads 138 to a data word select switch 180 and to a
parity storage latch 182. The switch 180 ls in turn
: controlled by a timing signal on lead 184 from the play
controller 36. This signal in turn controls the switch
180 such that the data words on the input leads 138 are
coupled to a cyclically driven data word memory 18~ The
; memory 186 preferably comprises a bank ~f random access
memories ~RAM) such as Type 2102 integrated circuit
manufactured by N.E.C. The RAM 186 is in turn controlled
by a read/write control signal on lead 188, which signal
is provided ~rom the AND and OR gates 190 and 192,
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respectivel,v, in response to write-correction and
write-data signals on leads 194 and 196, which signals are
provided by the play controller 36.
The frarne error signal on lead 174 which
controls the overall error correction process is coupled
to a frame status select switch comprising gates 198 and
200. This switch provides a signal on ]ead 202 to the
frame good/bad memory circuit 204. The output of the
memory 204 is then coupled to a frame status latch 206 to
provide a RArl read/write control signal on lead 20~. The
signal on lead 208 is coupled back to the input Or the AND
gate 200 to further control the frame status swltch and is
also coupled to the AND gate l90 to control the production
-~ of the read/write correct signal on lead 188. As thus
configured, the data word memory 186 is cyclically driven
` by the play controller via leads 210 such that the data
words of successive frames are sequentially entered.
These control signals further cause the data words of each
frame to be successively outputed from the memory 186 as
the data words of a next successive frame N+30 frames
later in time are successively received. The outputed
signals from the memory 186 are coupled to shift registers
212 and 214 to convert the parallel data into serial form.
The registers are preferably integrated circuit types such
as LS 165. The serial output signal is coupled through
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the A~D ~ate onto the output lead 218 J whence the signal
is fed to the digital to analog convertor 3,~ as shown in
~`igure 1.
The output from the data word r~emory 186 is also
coupled to a data storage latch 220~ and in response to a
data store signal from the play controller 36 on lead 222,
couples the data words then present at the data word
memory to a bank of e~clusive 0~ gates 224. The parity
store latch 1~2 is also controlled by signals on lead 226
from the play controller 36. As will be described in
detail hereinafter, the foregoing portion of the error
corrector circuit enables the correction of erroneous data
words within a given frame.
In addition to such correction features, the
error corrector 34 also includes circuits for muting the
output in the event no correction is possible. That
portion of the circuit includes a bad frame output mute
; 228 which is coupled to receive signals from the frame
good/bad memory 204, and which is also controlled by input
signals on lead 230 from the play controller 36. The
output of the bad frame output mute 228 is coupled on lead
232 to the AND gate 216 where it is coupled together with
the output from the shift registers 212 and 214. Thus if
an uncorrectable frame is determined, the signal on lead
232 prevents the AND gate from passing the output from the
shift registers and provides on output lead 218 a series
of digital zeros.
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The operation o~ the error corrector 311 may
generally be described as follows. Making an assumptlon
that a glven prevlous frame (N+l) has Just been processed
and the flrst data word of a :new frame N is arriving lnto
the error corrector, as the first data word of that frame
N is recelved, the ~irst 8 bit group, l.e., the most
signi~icant portion of that dl~ta word, ls entered into the
data word memory 1860 The RA:M memory 186 is then stepped
forward and the next 8 bit ~roup, consiscing of the least
significant portion of the first data word, is entered
into the memory 186. The next data to be received on lead
138 is an 8 bit parity word oiginally generated from data
: words of frames N+15 and N+30. Sinte each frame contains
only 8 parity words of information~ it is readily
appreciated that only half of the data words of frame N
: may be reconstructed from a combination o~ the parity
words of one frame with data words of another frame. The
received parity word is separated from the flow by the
play controller 36, and is entered into the parity store
latch 182. With the now received parity information of
frame N and the data words of frame N+30 already stored in
the RAM 186~ ik is now possible to correct half of the
data words that are presently.in the cyclical RAM memory
186 at position N+15, i.e., that frame whlch is 15 frames
ahead in time of frame N.
The status of the data words of frame N+15 is
outputed from 'che frame good/bad memory 204 into the frame
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~32~ 2
status latch 206. If an indicatlon is received that any
of the data words of frarne 11+15 are bad, a correct:Lon
signal is coupled on lead 208 through the gate 190 and 1~2
onto lead 188 into the memory 186 to allow corrected data
words from the exclusive OR 224 to be inserted into the
right place on the data word rnemory 186, thus deleting the
erroneous data words at that pOSitiOIl. If such an
erroneous ~rame indication is received, once each parity
word of frame N is stored in the parity latch 1~2, khe
play controller 36 provides a signal on lead 222 to enable
the data storage latch 220 to access half of the data
words of ~rame N+30 into the latch 220. The exclusive OR
network 224 operates on the two and provides an output
which will be the possible reconstruction of half of the
data words of frame N+15.
The other half of frame N+15 is reconstructed
when the 8 bit parity words of frame N-15 are received 15
- frames later on, which parity words thus provide the
additional information necessary to complete the
reconstruction. At that time, each parity word of frame
N-15 is successively stored in the parity storage latch
182 and the play controller 36 provides a signal on lead
222 to enable the data storage latch 220 to sequentially
access half of the data words of frame N. The exclusive
OR network 224 operates on these two groups of words and
provides an output to the RAM 186 completing the
reconstruction of the data words of frame N~15.
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Each half of the above descr:Lbed operatlons thus
continues on for the 16 data word portions of a given
frame that arrives. Each respective data word is stripped
o~ and entered into the cycllcal RAM memory 186, while
the successive parity words are stripped off and entered
into the parity storage latch, where they are used to
reconstruct, ln succession,~ha:lf of the data words at
positions 1, 2~ 3, 4, ... 16. At the end of the f'rame,
the f'rame good/bad status of the ~rame in which the parity
words may be used f'inally arrlves, such that thak
information can then be used to determine whether or not
the corrected inf'ormation that has been entered into the
memory 186 is actually a valid or good correction.
Subsequent to the correction o~ the f'irst half
of' f'ame N~15, the f'rarne good/bad memory 204 outputs the
status of f`rame N+15 to the frame status latch 206. The
output o~ latch 206, indlcative of the status o~ frame
N+15, is in turn summed with the good/bad status o~ frame
N in the AND gate 200 as received on lead 174. The play
controller 36 then controls the NOR gate 198 to couple the
summed output of' gate 200 to the frame good/bad memory
204. The summed signal is thus written in memory 204 as
the new good/bad ~rame status of ~rame N~15. When the
second half o~ ~rame N~15 is subsequently reconstructed
from ~rames N and N-15 this sequence is repeated, such
that the output of latch 206, whlch is now indlcati~e of
the status of' N, ls summed in gate 200 with an indlcatlon
~ ~ ~3
_31~_
of frame N-15 to provide a completed summed signal to
memory 204 indicative of the ~inal good/bad status o~
frame N+15.
In the preferred embodiment described above, the
condition ~or correcting data is that only two of the
three ~rames that have been used were good, such that if
the good/bad sta-tus of the frames from which the parity
were constructed was good, and the alternate o~ either the
: frame N+15 or N~30 was good, then a corrected data word
could be constructed and written into the memory 1~6 in
the appropriate position of N+30 or N+15. In an analogous
fashion, similar systems may also be construoted in which
a three out of four or four out of five reconstruction
techniques are utilized.
Since information is being retrieved from the
record medium 23 at a higher rate than is needed to output
;~ it, due to the extra parity in~ormation inserted during
the recording operation, the information is necessarily
temporarily stored in the shift registers 212 and 214.
When a complete data word is received into the shift
:~ registers, a serialized ouput is coupled to the AND gate
; 216. In combination with the final frame good/bad status
on lead 232, that word is then outputed on the OUtpllt lead
218.
The specific circuits provided in the play
controllor 36 are state of the art and are simply those
required to provide the appropriate control signals as
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described to the respective other portlons of the playback
section 14. The controllor 36 thus includes a crystal
clock generator for providing a fixed clock pulse as well
as appropriate counters, such as, for example, a 400 bit
counter which may be preferably an integrated circuit type
such as 74LS393. Oher circuits for generating appropriate
commands at other lntervals throughout a given frame
sequence are sirnilarly constructed o~ conventional
counters, registers and logic gates.
Having thus descrlbed the present invention,
what ls claimed is:
